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From: Chao Hao <chao.hao@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
	"Matthias Brugger" <matthias.bgg@gmail.com>
Cc: Anan Sun <anan.sun@mediatek.com>,
	devicetree@vger.kernel.org, Jun Yan <jun.yan@mediatek.com>,
	wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org,
	Chao Hao <chao.hao@mediatek.com>,
	iommu@lists.linux-foundation.org,
	linux-mediatek@lists.infradead.org,
	Yong Wu <yong.wu@mediatek.com>,
	Cui Zhang <zhang.cui@mediatek.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 06/19] iommu/mediatek: Add new flow to get SUB_COMMON ID in translation fault
Date: Sun, 5 Jan 2020 18:45:10 +0800	[thread overview]
Message-ID: <20200105104523.31006-7-chao.hao@mediatek.com> (raw)
In-Reply-To: <20200105104523.31006-1-chao.hao@mediatek.com>

When the number of smi_larb is more than seven, smi_larb id
will be divided into COMMON_ID(high three bits, bit[11:9]) and
SUB_COMMON_ID(low two bits,bit[8:7]). So we can analyse translation
fault id by SUB_COMMON_ID and COMMON_ID. We can distinguish if
has SUB_COMMON_ID and SUB_COMMON_ID by has_sub_comm variable.

Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
 drivers/iommu/mtk_iommu.c | 16 ++++++++++++----
 drivers/iommu/mtk_iommu.h |  1 +
 2 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index b61785a87764..5de13ab1094e 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -89,6 +89,8 @@
 #define REG_MMU1_INVLD_PA			0x148
 #define REG_MMU0_INT_ID				0x150
 #define REG_MMU1_INT_ID				0x154
+#define F_MMU_INT_ID_COMM_ID(a)			(((a) >> 9) & 0x7)
+#define F_MMU_INT_ID_SUB_COMM_ID(a)		(((a) >> 7) & 0x3)
 #define F_MMU_INT_ID_LARB_ID(a)			(((a) >> 7) & 0x7)
 #define F_MMU_INT_ID_PORT_ID(a)			(((a) >> 2) & 0x1f)
 
@@ -227,7 +229,7 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
 	struct mtk_iommu_data *data = dev_id;
 	struct mtk_iommu_domain *dom = data->m4u_dom;
 	u32 int_state, regval, fault_iova, fault_pa;
-	unsigned int fault_larb, fault_port;
+	unsigned int fault_larb, fault_port, sub_comm = 0;
 	bool layer, write;
 
 	/* Read error info from registers */
@@ -243,8 +245,13 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
 	}
 	layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
 	write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
-	fault_larb = F_MMU_INT_ID_LARB_ID(regval);
 	fault_port = F_MMU_INT_ID_PORT_ID(regval);
+	if (data->plat_data->has_sub_comm[data->m4u_id]) {
+		fault_larb = F_MMU_INT_ID_COMM_ID(regval);
+		sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
+	} else {
+		fault_larb = F_MMU_INT_ID_LARB_ID(regval);
+	}
 
 	fault_larb = data->plat_data->larbid_remap[data->m4u_id][fault_larb];
 
@@ -252,8 +259,9 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
 			       write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
 		dev_err_ratelimited(
 			data->dev,
-			"fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d layer=%d %s\n",
-			int_state, fault_iova, fault_pa, fault_larb, fault_port,
+			"fault type=0x%x iova=0x%x pa=0x%x larb=%d sub_comm=%d port=%d regval=0x%x layer=%d %s\n",
+			int_state, fault_iova, fault_pa, fault_larb,
+			sub_comm, fault_port, regval,
 			layer, write ? "write" : "read");
 	}
 
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index ec3011a50728..d4495230c6e7 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -40,6 +40,7 @@ struct mtk_iommu_plat_data {
 
 	/* HW will use the EMI clock if there isn't the "bclk". */
 	bool                has_bclk;
+	bool                has_sub_comm[2];
 	bool                has_vld_pa_rng;
 	bool                reset_axi;
 	u32                 m4u1_mask;
-- 
2.18.0
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  parent reply	other threads:[~2020-01-05 10:59 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-05 10:45 [PATCH v2 00/19] MT6779 IOMMU SUPPORT Chao Hao
2020-01-05 10:45 ` [PATCH v2 01/19] dt-bindings: mediatek: Add bindings for MT6779 Chao Hao
2020-01-06 21:57   ` Rob Herring
2020-01-07 11:10     ` chao hao
2020-01-05 10:45 ` [PATCH v2 02/19] iommu/mediatek: Add m4u1_mask to distinguish m4u_id Chao Hao
2020-01-05 10:45 ` [PATCH v2 03/19] iommu/mediatek: Extend larb_remap to larb_remap[2] Chao Hao
2020-01-05 10:45 ` [PATCH v2 04/19] iommu/mediatek: Rename offset=0x48 register Chao Hao
2020-01-05 10:45 ` [PATCH v2 05/19] iommu/mediatek: Put inv_sel_reg in the plat_data for preparing add 0x2c support in mt6779 Chao Hao
2020-01-05 10:45 ` Chao Hao [this message]
2020-01-05 10:45 ` [PATCH v2 07/19] iommu/mediatek: Add REG_MMU_WR_LEN reg define prepare for mt6779 Chao Hao
2020-01-05 10:45 ` [PATCH v2 08/19] iommu/mediatek: Add mt6779 basic support Chao Hao
2020-01-05 10:45 ` [PATCH v2 09/19] iommu/mediatek: Add mtk_iommu_pgtable structure Chao Hao
2020-01-05 10:45 ` [PATCH v2 10/19] iommu/mediatek: Remove mtk_iommu_domain_finalise Chao Hao
2020-01-05 10:45 ` [PATCH v2 11/19] iommu/mediatek: Remove pgtable info in mtk_iommu_domain Chao Hao
2020-01-05 10:45 ` [PATCH v2 12/19] iommu/mediatek: Change get the way of m4u_group Chao Hao
2020-01-05 10:45 ` [PATCH v2 13/19] iommu/mediatek: Add smi_larb info about device Chao Hao
2020-01-05 10:45 ` [PATCH v2 14/19] iommu/mediatek: Add mtk_domain_data structure Chao Hao
2020-01-05 10:45 ` [PATCH v2 15/19] iommu/mediatek: Remove the usage of m4u_dom variable Chao Hao
2020-01-05 10:45 ` [PATCH v2 16/19] iommu/mediatek: Remove mtk_iommu_get_m4u_data api Chao Hao
2020-01-05 10:45 ` [PATCH v2 17/19] iommu/mediatek: Add iova reserved function Chao Hao
2020-01-05 10:45 ` [PATCH v2 18/19] iommu/mediatek: Change single domain to multiple domains Chao Hao
2020-01-05 10:45 ` [PATCH v2 19/19] iommu/mediatek: Add multiple mtk_iommu_domain support for mt6779 Chao Hao

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