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From: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
To: <miquel.raynal@bootlin.com>, <broonie@kernel.org>
Cc: <xiangsheng.hou@mediatek.com>, <benliang.zhao@mediatek.com>,
	<dandan.he@mediatek.com>, <guochun.mao@mediatek.com>,
	<bin.zhang@mediatek.com>, <sanny.chen@mediatek.com>,
	<mao.zhong@mediatek.com>, <yingjoe.chen@mediatek.com>,
	<donghunt@amazon.com>,  <rdlee@amazon.com>,
	<linux-mtd@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>,
	<srv_heupstream@mediatek.com>
Subject: [RFC,v4,5/5] arm64: dts: mtk: Add snfi node
Date: Tue, 30 Nov 2021 16:32:02 +0800	[thread overview]
Message-ID: <20211130083202.14228-6-xiangsheng.hou@mediatek.com> (raw)
In-Reply-To: <20211130083202.14228-1-xiangsheng.hou@mediatek.com>

Add snfi node for SPI NAND controller.
Just take MT7622 for example at present.

Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 16 ++++++++++++++++
 arch/arm64/boot/dts/mediatek/mt7622.dtsi     | 13 +++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
index 596c073d8b05..1a5bf553f3a3 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -530,6 +530,22 @@ &spi0 {
 	status = "okay";
 };
 
+&snfi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&snfi_pins>;
+	nand-ecc-engine = <&bch>;
+	status = "disabled";
+
+	spi_nand@0 {
+		compatible = "spi-nand";
+		reg = <0>;
+		spi-max-frequency = <104000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+		nand-ecc-engine = <&snfi>;
+	};
+};
+
 &spi1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&spic1_pins>;
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index 6f8cb3ad1e84..229ec2a3a65e 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -497,6 +497,19 @@ spi0: spi@1100a000 {
 		status = "disabled";
 	};
 
+	snfi: spi@1100d000 {
+		compatible = "mediatek,mt7622-snfi";
+		reg = <0 0x1100d000 0 0x1000>;
+		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&infracfg_ao CLK_INFRA_AO_NFI_BCLK_CK_SET>,
+			 <&infracfg_ao CLK_INFRA_AO_NFI_INFRA_BCLK_CK_SET>,
+			 <&infracfg_ao CLK_INFRA_AO_NFI_HCLK_CK_SET>;
+		clock-names = "nfi_clk", "snfi_clk", "hclk";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	thermal: thermal@1100b000 {
 		#thermal-sensor-cells = <1>;
 		compatible = "mediatek,mt7622-thermal";
-- 
2.25.1


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      parent reply	other threads:[~2021-11-30  8:35 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-30  8:31 [RFC,v4,0/5] Add Mediatek SPI Nand controller and convert ECC driver Xiangsheng Hou
2021-11-30  8:31 ` [RFC,v4,1/5] mtd: nand: ecc: Move mediatek " Xiangsheng Hou
2021-11-30  8:31 ` [RFC,v4,2/5] mtd: nand: ecc: mtk: Convert to the ECC infrastructure Xiangsheng Hou
2021-12-09 10:32   ` Miquel Raynal
2021-12-10  9:09     ` xiangsheng.hou
2021-12-10  9:34       ` Miquel Raynal
2021-12-11  3:25         ` xiangsheng.hou
2021-12-13  9:29           ` Miquel Raynal
2021-12-14  3:32             ` xiangsheng.hou
2021-12-14  9:47               ` Miquel Raynal
2021-11-30  8:32 ` [RFC,v4,3/5] spi: mtk: Add mediatek SPI Nand Flash interface driver Xiangsheng Hou
2021-12-09 10:20   ` Miquel Raynal
2021-12-10  9:09     ` xiangsheng.hou
2021-12-10  9:40       ` Miquel Raynal
2021-11-30  8:32 ` [RFC, v4, 4/5] mtd: spinand: Move set/get OOB databytes to each ECC engines Xiangsheng Hou
2021-12-14 11:41   ` [RFC,v4,4/5] " Miquel Raynal
2021-12-20  7:37     ` xiangsheng.hou
2021-11-30  8:32 ` Xiangsheng Hou [this message]

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