From: bchihi@baylibre.com
To: daniel.lezcano@linaro.org, rafael@kernel.org, amitk@kernel.org,
rui.zhang@intel.com
Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org,
khilman@baylibre.com, linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, james.lo@mediatek.com,
rex-bc.chen@mediatek.com
Subject: [PATCH v10 6/6] arm64/dts/mt8195: Add temperature mitigation threshold
Date: Thu, 12 Jan 2023 16:28:55 +0100 [thread overview]
Message-ID: <20230112152855.216072-7-bchihi@baylibre.com> (raw)
In-Reply-To: <20230112152855.216072-1-bchihi@baylibre.com>
From: Balsam CHIHI <bchihi@baylibre.com>
The mt8195 board has several hotspots around the CPUs. Specify the
targeted temperature threshold when to apply the mitigation and define
the associated cooling devices.
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 153 ++++++++++++++++++++---
1 file changed, 137 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 683e5057d68d..0d6642603095 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -14,6 +14,7 @@
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
#include <dt-bindings/power/mt8195-power.h>
#include <dt-bindings/reset/mt8195-resets.h>
+#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/thermal/mediatek-lvts.h>
/ {
@@ -2413,107 +2414,227 @@ dp_tx: dp-tx@1c600000 {
thermal_zones: thermal-zones {
cpu0-thermal {
- polling-delay = <0>;
- polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT819x_MCU_LITTLE_CPU0>;
trips {
+ cpu0_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
cpu0_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu0_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu1-thermal {
- polling-delay = <0>;
- polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT819x_MCU_LITTLE_CPU1>;
trips {
+ cpu1_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
cpu1_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu1_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu2-thermal {
- polling-delay = <0>;
- polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT819x_MCU_LITTLE_CPU2>;
trips {
+ cpu2_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
cpu2_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu2_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu3-thermal {
- polling-delay = <0>;
- polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT819x_MCU_LITTLE_CPU3>;
trips {
+ cpu3_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
cpu3_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu3_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu4-thermal {
- polling-delay = <0>;
- polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT819x_MCU_BIG_CPU0>;
trips {
+ cpu4_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
cpu4_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu4_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu5-thermal {
- polling-delay = <0>;
- polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT819x_MCU_BIG_CPU1>;
trips {
+ cpu5_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
cpu5_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu5_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu6-thermal {
- polling-delay = <0>;
- polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT819x_MCU_BIG_CPU2>;
trips {
+ cpu6_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
cpu6_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu6_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu7-thermal {
- polling-delay = <0>;
- polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT819x_MCU_BIG_CPU3>;
trips {
+ cpu7_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
cpu7_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu7_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
};
};
--
2.34.1
next prev parent reply other threads:[~2023-01-12 15:31 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-12 15:28 [PATCH v10 0/6] Add LVTS thermal architecture bchihi
2023-01-12 15:28 ` [PATCH v10 1/6] thermal/drivers/mediatek: Relocate driver to mediatek folder bchihi
2023-01-12 20:08 ` kernel test robot
2023-01-13 10:47 ` Daniel Lezcano
2023-01-12 15:28 ` [PATCH v10 2/6] dt-bindings/thermal/mediatek: Add dt-binding document for LVTS thermal controllers bchihi
2023-01-13 8:11 ` Krzysztof Kozlowski
2023-01-13 11:54 ` Matthias Brugger
2023-01-13 14:30 ` Balsam CHIHI
2023-01-16 10:38 ` AngeloGioacchino Del Regno
2023-01-16 11:05 ` Balsam CHIHI
2023-01-12 15:28 ` [PATCH v10 3/6] arm64/dts/mt8195: Add efuse node to mt8195 bchihi
2023-01-13 11:45 ` Matthias Brugger
2023-01-16 10:38 ` AngeloGioacchino Del Regno
2023-01-12 15:28 ` [PATCH v10 4/6] thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver bchihi
2023-01-16 10:50 ` AngeloGioacchino Del Regno
2023-01-16 11:08 ` Daniel Lezcano
2023-01-16 11:52 ` AngeloGioacchino Del Regno
2023-01-18 13:58 ` Balsam CHIHI
2023-01-18 14:30 ` Daniel Lezcano
2023-01-18 14:52 ` Balsam CHIHI
2023-01-18 14:37 ` Balsam CHIHI
2023-01-12 15:28 ` [PATCH v10 5/6] arm64/dts/mt8195: Add thermal zones and thermal nodes bchihi
2023-01-12 15:28 ` bchihi [this message]
2023-01-13 11:49 ` [PATCH v10 6/6] arm64/dts/mt8195: Add temperature mitigation threshold Matthias Brugger
2023-01-13 14:24 ` Balsam CHIHI
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