From: Sunny Shen <sunny.shen@mediatek.com>
To: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>
Cc: "Jason-JH . Lin" <jason-jh.lin@mediatek.com>,
Singo Chang <singo.chang@mediatek.com>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
Project_Global_Chrome_Upstream_Group@mediatek.com,
Pin-yen Lin <treapking@chromium.org>,
Nancy Lin <nancy.lin@mediatek.com>,
linux-mediatek@lists.infradead.org,
"Paul Chen --cc=devicetree @ vger . kernel . org"
<paul-pl.chen@mediatek.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Matthias Brugger <matthias.bgg@gmail.com>,
linux-arm-kernel@lists.infradead.org,
Sunny Shen <sunny.shen@mediatek.com>
Subject: [PATCH 4/5] drm/mediatek: Add MDP-RSZ component support for MT8196
Date: Tue, 11 Feb 2025 10:52:53 +0800 [thread overview]
Message-ID: <20250211025317.399534-5-sunny.shen@mediatek.com> (raw)
In-Reply-To: <20250211025317.399534-1-sunny.shen@mediatek.com>
Add MDP-RSZ component support for MT8196.
Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 24 ++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++
3 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index 7f09a8977965..65878d3fe8a9 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -46,6 +46,10 @@
#define DSC_BYPASS BIT(4)
#define DSC_UFOE_SEL BIT(16)
+#define DISP_REG_MDP_RSZ_EN 0x0000
+#define DISP_REG_MDP_RSZ_INPUT_SIZE 0x0010
+#define DISP_REG_MDP_RSZ_OUTPUT_SIZE 0x0014
+
#define DISP_REG_OD_EN 0x0000
#define DISP_REG_OD_CFG 0x0020
#define OD_RELAYMODE BIT(0)
@@ -235,6 +239,18 @@ static void mtk_od_start(struct device *dev)
writel(1, priv->regs + DISP_REG_OD_EN);
}
+static void mtk_mdp_rsz_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MDP_RSZ_INPUT_SIZE);
+ mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MDP_RSZ_OUTPUT_SIZE);
+}
+
static void mtk_postmask_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -391,6 +407,12 @@ static const struct mtk_ddp_comp_funcs ddp_ovlsys_adaptor = {
.get_num_formats = mtk_ovlsys_adaptor_get_num_formats,
};
+static const struct mtk_ddp_comp_funcs ddp_mdp_rsz = {
+ .clk_enable = mtk_ddp_clk_enable,
+ .clk_disable = mtk_ddp_clk_disable,
+ .config = mtk_mdp_rsz_config,
+};
+
static const struct mtk_ddp_comp_funcs ddp_postmask = {
.clk_enable = mtk_ddp_clk_enable,
.clk_disable = mtk_ddp_clk_disable,
@@ -454,6 +476,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_DITHER] = "dither",
[MTK_DISP_DSC] = "dsc",
[MTK_DISP_GAMMA] = "gamma",
+ [MTK_DISP_MDP_RSZ] = "mdp-rsz",
[MTK_DISP_MERGE] = "merge",
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
@@ -515,6 +538,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
[DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
+ [DDP_COMPONENT_MDP_RSZ0] = { MTK_DISP_MDP_RSZ, 0, &ddp_mdp_rsz},
[DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
[DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
[DDP_COMPONENT_MERGE2] = { MTK_DISP_MERGE, 2, &ddp_merge },
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
index badb42bd4f7c..87f573fcc903 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
@@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_OVLSYS_ADAPTOR,
MTK_DISP_OVL_2L,
MTK_DISP_OVL_ADAPTOR,
+ MTK_DISP_MDP_RSZ,
MTK_DISP_POSTMASK,
MTK_DISP_PWM,
MTK_DISP_RDMA,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 50f5f81a7da1..b810a197f58b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -885,6 +885,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_GAMMA, },
{ .compatible = "mediatek,mt8195-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
+ { .compatible = "mediatek,mt8196-disp-mdp-rsz",
+ .data = (void *)MTK_DISP_MDP_RSZ },
{ .compatible = "mediatek,mt8195-disp-merge",
.data = (void *)MTK_DISP_MERGE },
{ .compatible = "mediatek,mt2701-disp-mutex",
--
2.34.1
next prev parent reply other threads:[~2025-02-11 2:59 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-11 2:52 [PATCH 0/5] Add components to support PQ in display path for MT8196 Sunny Shen
2025-02-11 2:52 ` [PATCH 1/5] dt-bindings: display: mediatek: mdp-rsz: Add rules " Sunny Shen
2025-02-11 17:54 ` Conor Dooley
2025-02-23 17:49 ` Sunny Shen (沈姍姍)
2025-02-24 19:01 ` Conor Dooley
2025-03-18 3:14 ` Sunny Shen (沈姍姍)
2025-03-19 20:00 ` Conor Dooley
2025-03-21 5:45 ` Sunny Shen (沈姍姍)
2025-02-17 6:01 ` CK Hu (胡俊光)
2025-02-23 17:50 ` Sunny Shen (沈姍姍)
2025-02-11 2:52 ` [PATCH 2/5] dt-bindings: display: mediatek: postmask: Modify " Sunny Shen
2025-02-11 17:44 ` Conor Dooley
2025-02-23 17:51 ` Sunny Shen (沈姍姍)
2025-02-11 2:52 ` [PATCH 3/5] soc: mediatek: Add components to support PQ in display path " Sunny Shen
2025-02-11 2:52 ` Sunny Shen [this message]
2025-02-17 6:04 ` [PATCH 4/5] drm/mediatek: Add MDP-RSZ component support " CK Hu (胡俊光)
2025-02-23 17:52 ` Sunny Shen (沈姍姍)
2025-02-24 2:07 ` CK Hu (胡俊光)
2025-02-11 2:52 ` [PATCH 5/5] drm/mediatek: Change main display path to support PQ " Sunny Shen
2025-02-17 6:06 ` CK Hu (胡俊光)
2025-02-17 14:25 ` AngeloGioacchino Del Regno
2025-03-27 5:44 ` Sunny Shen (沈姍姍)
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