* [PATCH] drm/mediatek: mtk_hdmi_v2: fix VID_DOWNSAMPLE_CONFIG register offset
@ 2026-08-28 12:10 Julien Stephan
2026-09-03 9:04 ` Louis-Alexis Eyraud
0 siblings, 1 reply; 2+ messages in thread
From: Julien Stephan @ 2026-08-28 12:10 UTC (permalink / raw)
To: Chun-Kuang Hu, Philipp Zabel, David Airlie, Simona Vetter,
Matthias Brugger, AngeloGioacchino Del Regno, Louis-Alexis Eyraud,
CK Hu
Cc: dri-devel, linux-mediatek, linux-kernel, linux-arm-kernel,
Tommy Chen, Julien Stephan
According to the datasheet, VID_DOWNSAMPLE_CONFIG is at offset 0x8f0;
0x8d0 is the VID_CSC_COEFF_0 register.
Fixes: 8d0f79886273 ("drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188")
Signed-off-by: Julien Stephan <jstephan@baylibre.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h b/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h
index 521b35c7e14d..bf3ebf5492d1 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h
@@ -173,7 +173,7 @@
#define TPI_AUDIO_LOOKUP_EN BIT(2)
/* Video downsampling configuration */
-#define VID_DOWNSAMPLE_CONFIG 0x8d0
+#define VID_DOWNSAMPLE_CONFIG 0x8f0
#define C444_C422_CONFIG_ENABLE BIT(0)
#define C422_C420_CONFIG_ENABLE BIT(4)
#define C422_C420_CONFIG_BYPASS BIT(5)
---
base-commit: 1b78070aaef63512688aebfbc82365ef9d6660f1
change-id: 20260828-mtk-hdmi-v2-fix-register-offset-879afc38cad1
Best regards,
--
Julien Stephan <jstephan@baylibre.com>
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] drm/mediatek: mtk_hdmi_v2: fix VID_DOWNSAMPLE_CONFIG register offset
2026-08-28 12:10 [PATCH] drm/mediatek: mtk_hdmi_v2: fix VID_DOWNSAMPLE_CONFIG register offset Julien Stephan
@ 2026-09-03 9:04 ` Louis-Alexis Eyraud
0 siblings, 0 replies; 2+ messages in thread
From: Louis-Alexis Eyraud @ 2026-09-03 9:04 UTC (permalink / raw)
To: Julien Stephan, Chun-Kuang Hu, Philipp Zabel, David Airlie,
Simona Vetter, Matthias Brugger, AngeloGioacchino Del Regno,
CK Hu
Cc: dri-devel, linux-mediatek, linux-kernel, linux-arm-kernel,
Tommy Chen
Hi Julien,
On Fri, 2026-08-28 at 14:10 +0200, Julien Stephan wrote:
> According to the datasheet, VID_DOWNSAMPLE_CONFIG is at offset 0x8f0;
> 0x8d0 is the VID_CSC_COEFF_0 register.
>
> Fixes: 8d0f79886273 ("drm/mediatek: Introduce HDMI/DDC v2 for
> MT8195/MT8188")
> Signed-off-by: Julien Stephan <jstephan@baylibre.com>
> ---
> drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>
I've checked in the MT8370, MT8390 (MT8188 variants) and MT8395 (MT8195
variants) datasheets and 0x8f0 offset is indeed the correct one.
So,
Reviewed-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
Regards,
Louis-Alexis
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2026-08-28 12:10 [PATCH] drm/mediatek: mtk_hdmi_v2: fix VID_DOWNSAMPLE_CONFIG register offset Julien Stephan
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