Re: [PATCH v3 1/2] dt-bindings: pinctrl: mediatek: Add support for mt8188

[AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>]

Il 28/07/22 10:49, Hui Liu ha scritto:
> From: "Hui.Liu" <hui.liu@mediatek.com>
> 
> Add the pinctrl header file on MediaTek mt8188.
> Add the new binding document for pinctrl on MediaTek mt8188.
> 
> Signed-off-by: Hui.Liu <hui.liu@mediatek.com>
> ---
>   .../pinctrl/mediatek,mt8188-pinctrl.yaml      |  224 +++
>   .../pinctrl/mediatek,mt8188-pinfunc.h         | 1280 +++++++++++++++++
>   2 files changed, 1504 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml
>   create mode 100644 include/dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml
> new file mode 100644
> index 000000000000..87c72b621188
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml
> @@ -0,0 +1,224 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8188-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek MT8188 Pin Controller
> +
> +maintainers:
> +  - Hui Liu <hui.liu@mediatek.com>
> +
> +description: |
> +  The MediaTek's MT8188 Pin controller is used to control SoC pins.
> +
> +properties:
> +  compatible:
> +    const: mediatek,mt8188-pinctrl
> +
> +  gpio-controller: true
> +
> +  '#gpio-cells':
> +    description: |
> +      Number of cells in GPIO specifier, should be two. The first cell
> +      is the pin number, the second cell is used to specify optional
> +      parameters which are defined in <dt-bindings/gpio/gpio.h>.
> +    const: 2
> +
> +  gpio-ranges:
> +    maxItems: 1
> +

Please allow to specify gpio names

   gpio-line-names: true

after which:
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> +  reg:
> +    items:
> +      - description: gpio registers base address
> +      - description: rm group io configuration registers base address
> +      - description: lt group io configuration registers base address
> +      - description: lm group io configuration registers base address
> +      - description: rt group io configuration registers base address
> +      - description: enit registers base address
> +