* [PATCH] arm64: dts: mediatek: add mt8176 device tree
From: Yidi Lin @ 2017-02-07 5:35 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger
Cc: Mark Rutland, Daniel Kurtz, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Yidi Lin
The core configuration is the only difference between mt8173 and mt8176.
Like what arm/juno and marvell/armada-ap806 did, this change splits
mt8173.dtsi into mt817x.dtsi and mt8173.dtsi. mt817x.dtsi defines the
common blocks for mt8173 and mt8176. mt8173.dtsi and mt8176.dtsi
describe mt8173 and mt8176 respectively.
Signed-off-by: Yidi Lin <yidi.lin-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
Documentation/devicetree/bindings/arm/mediatek.txt | 1 +
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 1205 +-------------------
arch/arm64/boot/dts/mediatek/mt8176.dtsi | 125 ++
arch/arm64/boot/dts/mediatek/mt817x.dtsi | 1199 +++++++++++++++++++
4 files changed, 1338 insertions(+), 1192 deletions(-)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8176.dtsi
create mode 100644 arch/arm64/boot/dts/mediatek/mt817x.dtsi
diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
index c860b24..f305149 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -16,6 +16,7 @@ compatible: Must contain one of
"mediatek,mt8127"
"mediatek,mt8135"
"mediatek,mt8173"
+ "mediatek,mt8176"
Supported boards:
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 12e7027..c0a9cfa 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014 MediaTek Inc.
+ * Copyright (c) 2016 MediaTek Inc.
* Author: Eddie Huang <eddie.huang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
*
* This program is free software; you can redistribute it and/or modify
@@ -11,45 +11,10 @@
* GNU General Public License for more details.
*/
-#include <dt-bindings/clock/mt8173-clk.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/memory/mt8173-larb-port.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/power/mt8173-power.h>
-#include <dt-bindings/reset/mt8173-resets.h>
-#include "mt8173-pinfunc.h"
+#include "mt817x.dtsi"
/ {
compatible = "mediatek,mt8173";
- interrupt-parent = <&sysirq>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- ovl0 = &ovl0;
- ovl1 = &ovl1;
- rdma0 = &rdma0;
- rdma1 = &rdma1;
- rdma2 = &rdma2;
- wdma0 = &wdma0;
- wdma1 = &wdma1;
- color0 = &color0;
- color1 = &color1;
- split0 = &split0;
- split1 = &split1;
- dpi0 = &dpi0;
- dsi0 = &dsi0;
- dsi1 = &dsi1;
- mdp_rdma0 = &mdp_rdma0;
- mdp_rdma1 = &mdp_rdma1;
- mdp_rsz0 = &mdp_rsz0;
- mdp_rsz1 = &mdp_rsz1;
- mdp_rsz2 = &mdp_rsz2;
- mdp_wdma0 = &mdp_wdma0;
- mdp_wrot0 = &mdp_wrot0;
- mdp_wrot1 = &mdp_wrot1;
- };
cpus {
#address-cells = <1>;
@@ -120,1163 +85,19 @@
};
};
};
+};
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
- method = "smc";
- cpu_suspend = <0x84000001>;
- cpu_off = <0x84000002>;
- cpu_on = <0x84000003>;
- };
-
- clk26m: oscillator@0 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <26000000>;
- clock-output-names = "clk26m";
- };
-
- clk32k: oscillator@1 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32000>;
- clock-output-names = "clk32k";
- };
-
- cpum_ck: oscillator@2 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- clock-output-names = "cpum_ck";
- };
-
- thermal-zones {
- cpu_thermal: cpu_thermal {
- polling-delay-passive = <1000>; /* milliseconds */
- polling-delay = <1000>; /* milliseconds */
-
- thermal-sensors = <&thermal>;
- sustainable-power = <1500>; /* milliwatts */
-
- trips {
- threshold: trip-point@0 {
- temperature = <68000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- target: trip-point@1 {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- cpu_crit: cpu_crit@0 {
- temperature = <115000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map@0 {
- trip = <&target>;
- cooling-device = <&cpu0 0 0>;
- contribution = <1024>;
- };
- map@1 {
- trip = <&target>;
- cooling-device = <&cpu2 0 0>;
- contribution = <2048>;
- };
- };
- };
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- vpu_dma_reserved: vpu_dma_mem_region {
- compatible = "shared-dma-pool";
- reg = <0 0xb7000000 0 0x500000>;
- alignment = <0x1000>;
- no-map;
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupt-parent = <&gic>;
- interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- soc {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "simple-bus";
- ranges;
-
- topckgen: clock-controller@10000000 {
- compatible = "mediatek,mt8173-topckgen";
- reg = <0 0x10000000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- infracfg: power-controller@10001000 {
- compatible = "mediatek,mt8173-infracfg", "syscon";
- reg = <0 0x10001000 0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- pericfg: power-controller@10003000 {
- compatible = "mediatek,mt8173-pericfg", "syscon";
- reg = <0 0x10003000 0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- syscfg_pctl_a: syscfg_pctl_a@10005000 {
- compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
- reg = <0 0x10005000 0 0x1000>;
- };
-
- pio: pinctrl@0x10005000 {
- compatible = "mediatek,mt8173-pinctrl";
- reg = <0 0x1000b000 0 0x1000>;
- mediatek,pctl-regmap = <&syscfg_pctl_a>;
- pins-are-numbered;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
-
- hdmi_pin: xxx {
-
- /*hdmi htplg pin*/
- pins1 {
- pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
- input-enable;
- bias-pull-down;
- };
- };
-
- i2c0_pins_a: i2c0 {
- pins1 {
- pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
- <MT8173_PIN_46_SCL0__FUNC_SCL0>;
- bias-disable;
- };
- };
-
- i2c1_pins_a: i2c1 {
- pins1 {
- pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
- <MT8173_PIN_126_SCL1__FUNC_SCL1>;
- bias-disable;
- };
- };
-
- i2c2_pins_a: i2c2 {
- pins1 {
- pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
- <MT8173_PIN_44_SCL2__FUNC_SCL2>;
- bias-disable;
- };
- };
-
- i2c3_pins_a: i2c3 {
- pins1 {
- pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
- <MT8173_PIN_107_SCL3__FUNC_SCL3>;
- bias-disable;
- };
- };
-
- i2c4_pins_a: i2c4 {
- pins1 {
- pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
- <MT8173_PIN_134_SCL4__FUNC_SCL4>;
- bias-disable;
- };
- };
-
- i2c6_pins_a: i2c6 {
- pins1 {
- pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
- <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
- bias-disable;
- };
- };
- };
-
- scpsys: scpsys@10006000 {
- compatible = "mediatek,mt8173-scpsys";
- #power-domain-cells = <1>;
- reg = <0 0x10006000 0 0x1000>;
- clocks = <&clk26m>,
- <&topckgen CLK_TOP_MM_SEL>,
- <&topckgen CLK_TOP_VENC_SEL>,
- <&topckgen CLK_TOP_VENC_LT_SEL>;
- clock-names = "mfg", "mm", "venc", "venc_lt";
- infracfg = <&infracfg>;
- };
-
- watchdog: watchdog@10007000 {
- compatible = "mediatek,mt8173-wdt",
- "mediatek,mt6589-wdt";
- reg = <0 0x10007000 0 0x100>;
- };
-
- timer: timer@10008000 {
- compatible = "mediatek,mt8173-timer",
- "mediatek,mt6577-timer";
- reg = <0 0x10008000 0 0x1000>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&infracfg CLK_INFRA_CLK_13M>,
- <&topckgen CLK_TOP_RTC_SEL>;
- };
-
- pwrap: pwrap@1000d000 {
- compatible = "mediatek,mt8173-pwrap";
- reg = <0 0x1000d000 0 0x1000>;
- reg-names = "pwrap";
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
- reset-names = "pwrap";
- clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
- clock-names = "spi", "wrap";
- };
-
- cec: cec@10013000 {
- compatible = "mediatek,mt8173-cec";
- reg = <0 0x10013000 0 0xbc>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&infracfg CLK_INFRA_CEC>;
- status = "disabled";
- };
-
- vpu: vpu@10020000 {
- compatible = "mediatek,mt8173-vpu";
- reg = <0 0x10020000 0 0x30000>,
- <0 0x10050000 0 0x100>;
- reg-names = "tcm", "cfg_reg";
- interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CLK_TOP_SCP_SEL>;
- clock-names = "main";
- memory-region = <&vpu_dma_reserved>;
- };
-
- sysirq: intpol-controller@10200620 {
- compatible = "mediatek,mt8173-sysirq",
- "mediatek,mt6577-sysirq";
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupt-parent = <&gic>;
- reg = <0 0x10200620 0 0x20>;
- };
-
- iommu: iommu@10205000 {
- compatible = "mediatek,mt8173-m4u";
- reg = <0 0x10205000 0 0x1000>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&infracfg CLK_INFRA_M4U>;
- clock-names = "bclk";
- mediatek,larbs = <&larb0 &larb1 &larb2
- &larb3 &larb4 &larb5>;
- #iommu-cells = <1>;
- };
-
- efuse: efuse@10206000 {
- compatible = "mediatek,mt8173-efuse";
- reg = <0 0x10206000 0 0x1000>;
- };
-
- apmixedsys: clock-controller@10209000 {
- compatible = "mediatek,mt8173-apmixedsys";
- reg = <0 0x10209000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- hdmi_phy: hdmi-phy@10209100 {
- compatible = "mediatek,mt8173-hdmi-phy";
- reg = <0 0x10209100 0 0x24>;
- clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
- clock-names = "pll_ref";
- clock-output-names = "hdmitx_dig_cts";
- mediatek,ibias = <0xa>;
- mediatek,ibias_up = <0x1c>;
- #clock-cells = <0>;
- #phy-cells = <0>;
- status = "disabled";
- };
-
- mipi_tx0: mipi-dphy@10215000 {
- compatible = "mediatek,mt8173-mipi-tx";
- reg = <0 0x10215000 0 0x1000>;
- clocks = <&clk26m>;
- clock-output-names = "mipi_tx0_pll";
- #clock-cells = <0>;
- #phy-cells = <0>;
- status = "disabled";
- };
-
- mipi_tx1: mipi-dphy@10216000 {
- compatible = "mediatek,mt8173-mipi-tx";
- reg = <0 0x10216000 0 0x1000>;
- clocks = <&clk26m>;
- clock-output-names = "mipi_tx1_pll";
- #clock-cells = <0>;
- #phy-cells = <0>;
- status = "disabled";
- };
-
- gic: interrupt-controller@10220000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- interrupt-parent = <&gic>;
- interrupt-controller;
- reg = <0 0x10221000 0 0x1000>,
- <0 0x10222000 0 0x2000>,
- <0 0x10224000 0 0x2000>,
- <0 0x10226000 0 0x2000>;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- auxadc: auxadc@11001000 {
- compatible = "mediatek,mt8173-auxadc";
- reg = <0 0x11001000 0 0x1000>;
- clocks = <&pericfg CLK_PERI_AUXADC>;
- clock-names = "main";
- #io-channel-cells = <1>;
- };
-
- uart0: serial@11002000 {
- compatible = "mediatek,mt8173-uart",
- "mediatek,mt6577-uart";
- reg = <0 0x11002000 0 0x400>;
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
- clock-names = "baud", "bus";
- status = "disabled";
- };
-
- uart1: serial@11003000 {
- compatible = "mediatek,mt8173-uart",
- "mediatek,mt6577-uart";
- reg = <0 0x11003000 0 0x400>;
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
- clock-names = "baud", "bus";
- status = "disabled";
- };
-
- uart2: serial@11004000 {
- compatible = "mediatek,mt8173-uart",
- "mediatek,mt6577-uart";
- reg = <0 0x11004000 0 0x400>;
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
- clock-names = "baud", "bus";
- status = "disabled";
- };
-
- uart3: serial@11005000 {
- compatible = "mediatek,mt8173-uart",
- "mediatek,mt6577-uart";
- reg = <0 0x11005000 0 0x400>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
- clock-names = "baud", "bus";
- status = "disabled";
- };
-
- i2c0: i2c@11007000 {
- compatible = "mediatek,mt8173-i2c";
- reg = <0 0x11007000 0 0x70>,
- <0 0x11000100 0 0x80>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
- clock-div = <16>;
- clocks = <&pericfg CLK_PERI_I2C0>,
- <&pericfg CLK_PERI_AP_DMA>;
- clock-names = "main", "dma";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c1: i2c@11008000 {
- compatible = "mediatek,mt8173-i2c";
- reg = <0 0x11008000 0 0x70>,
- <0 0x11000180 0 0x80>;
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
- clock-div = <16>;
- clocks = <&pericfg CLK_PERI_I2C1>,
- <&pericfg CLK_PERI_AP_DMA>;
- clock-names = "main", "dma";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@11009000 {
- compatible = "mediatek,mt8173-i2c";
- reg = <0 0x11009000 0 0x70>,
- <0 0x11000200 0 0x80>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
- clock-div = <16>;
- clocks = <&pericfg CLK_PERI_I2C2>,
- <&pericfg CLK_PERI_AP_DMA>;
- clock-names = "main", "dma";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi: spi@1100a000 {
- compatible = "mediatek,mt8173-spi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0 0x1100a000 0 0x1000>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
- <&topckgen CLK_TOP_SPI_SEL>,
- <&pericfg CLK_PERI_SPI0>;
- clock-names = "parent-clk", "sel-clk", "spi-clk";
- status = "disabled";
- };
-
- thermal: thermal@1100b000 {
- #thermal-sensor-cells = <0>;
- compatible = "mediatek,mt8173-thermal";
- reg = <0 0x1100b000 0 0x1000>;
- interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
- clock-names = "therm", "auxadc";
- resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
- mediatek,auxadc = <&auxadc>;
- mediatek,apmixedsys = <&apmixedsys>;
- };
-
- nor_flash: spi@1100d000 {
- compatible = "mediatek,mt8173-nor";
- reg = <0 0x1100d000 0 0xe0>;
- clocks = <&pericfg CLK_PERI_SPI>,
- <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
- clock-names = "spi", "sf";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@11010000 {
- compatible = "mediatek,mt8173-i2c";
- reg = <0 0x11010000 0 0x70>,
- <0 0x11000280 0 0x80>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
- clock-div = <16>;
- clocks = <&pericfg CLK_PERI_I2C3>,
- <&pericfg CLK_PERI_AP_DMA>;
- clock-names = "main", "dma";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_pins_a>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c4: i2c@11011000 {
- compatible = "mediatek,mt8173-i2c";
- reg = <0 0x11011000 0 0x70>,
- <0 0x11000300 0 0x80>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
- clock-div = <16>;
- clocks = <&pericfg CLK_PERI_I2C4>,
- <&pericfg CLK_PERI_AP_DMA>;
- clock-names = "main", "dma";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4_pins_a>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- hdmiddc0: i2c@11012000 {
- compatible = "mediatek,mt8173-hdmi-ddc";
- interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
- reg = <0 0x11012000 0 0x1C>;
- clocks = <&pericfg CLK_PERI_I2C5>;
- clock-names = "ddc-i2c";
- };
-
- i2c6: i2c@11013000 {
- compatible = "mediatek,mt8173-i2c";
- reg = <0 0x11013000 0 0x70>,
- <0 0x11000080 0 0x80>;
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
- clock-div = <16>;
- clocks = <&pericfg CLK_PERI_I2C6>,
- <&pericfg CLK_PERI_AP_DMA>;
- clock-names = "main", "dma";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c6_pins_a>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- afe: audio-controller@11220000 {
- compatible = "mediatek,mt8173-afe-pcm";
- reg = <0 0x11220000 0 0x1000>;
- interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
- clocks = <&infracfg CLK_INFRA_AUDIO>,
- <&topckgen CLK_TOP_AUDIO_SEL>,
- <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
- <&topckgen CLK_TOP_APLL1_DIV0>,
- <&topckgen CLK_TOP_APLL2_DIV0>,
- <&topckgen CLK_TOP_I2S0_M_SEL>,
- <&topckgen CLK_TOP_I2S1_M_SEL>,
- <&topckgen CLK_TOP_I2S2_M_SEL>,
- <&topckgen CLK_TOP_I2S3_M_SEL>,
- <&topckgen CLK_TOP_I2S3_B_SEL>;
- clock-names = "infra_sys_audio_clk",
- "top_pdn_audio",
- "top_pdn_aud_intbus",
- "bck0",
- "bck1",
- "i2s0_m",
- "i2s1_m",
- "i2s2_m",
- "i2s3_m",
- "i2s3_b";
- assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
- <&topckgen CLK_TOP_AUD_2_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
- <&topckgen CLK_TOP_APLL2>;
- };
-
- mmc0: mmc@11230000 {
- compatible = "mediatek,mt8173-mmc",
- "mediatek,mt8135-mmc";
- reg = <0 0x11230000 0 0x1000>;
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_MSDC30_0>,
- <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
- clock-names = "source", "hclk";
- status = "disabled";
- };
-
- mmc1: mmc@11240000 {
- compatible = "mediatek,mt8173-mmc",
- "mediatek,mt8135-mmc";
- reg = <0 0x11240000 0 0x1000>;
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_MSDC30_1>,
- <&topckgen CLK_TOP_AXI_SEL>;
- clock-names = "source", "hclk";
- status = "disabled";
- };
-
- mmc2: mmc@11250000 {
- compatible = "mediatek,mt8173-mmc",
- "mediatek,mt8135-mmc";
- reg = <0 0x11250000 0 0x1000>;
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_MSDC30_2>,
- <&topckgen CLK_TOP_AXI_SEL>;
- clock-names = "source", "hclk";
- status = "disabled";
- };
-
- mmc3: mmc@11260000 {
- compatible = "mediatek,mt8173-mmc",
- "mediatek,mt8135-mmc";
- reg = <0 0x11260000 0 0x1000>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_MSDC30_3>,
- <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
- clock-names = "source", "hclk";
- status = "disabled";
- };
-
- ssusb: usb@11271000 {
- compatible = "mediatek,mt8173-mtu3";
- reg = <0 0x11271000 0 0x3000>,
- <0 0x11280700 0 0x0100>;
- reg-names = "mac", "ippc";
- interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
- phys = <&phy_port0 PHY_TYPE_USB3>,
- <&phy_port1 PHY_TYPE_USB2>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
- clocks = <&topckgen CLK_TOP_USB30_SEL>,
- <&pericfg CLK_PERI_USB0>,
- <&pericfg CLK_PERI_USB1>;
- clock-names = "sys_ck",
- "wakeup_deb_p0",
- "wakeup_deb_p1";
- mediatek,syscon-wakeup = <&pericfg>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- status = "disabled";
-
- usb_host: xhci@11270000 {
- compatible = "mediatek,mt8173-xhci";
- reg = <0 0x11270000 0 0x1000>;
- reg-names = "mac";
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
- clocks = <&topckgen CLK_TOP_USB30_SEL>;
- clock-names = "sys_ck";
- status = "disabled";
- };
- };
-
- u3phy: usb-phy@11290000 {
- compatible = "mediatek,mt8173-u3phy";
- reg = <0 0x11290000 0 0x800>;
- clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
- clock-names = "u3phya_ref";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- status = "okay";
-
- phy_port0: port@11290800 {
- reg = <0 0x11290800 0 0x800>;
- #phy-cells = <1>;
- status = "okay";
- };
-
- phy_port1: port@11291000 {
- reg = <0 0x11291000 0 0x800>;
- #phy-cells = <1>;
- status = "okay";
- };
- };
-
- mmsys: clock-controller@14000000 {
- compatible = "mediatek,mt8173-mmsys", "syscon";
- reg = <0 0x14000000 0 0x1000>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- #clock-cells = <1>;
- };
-
- mdp {
- compatible = "mediatek,mt8173-mdp";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- mediatek,vpu = <&vpu>;
-
- mdp_rdma0: rdma@14001000 {
- compatible = "mediatek,mt8173-mdp-rdma";
- reg = <0 0x14001000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RDMA0>,
- <&mmsys CLK_MM_MUTEX_32K>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_RDMA0>;
- mediatek,larb = <&larb0>;
- };
-
- mdp_rdma1: rdma@14002000 {
- compatible = "mediatek,mt8173-mdp-rdma";
- reg = <0 0x14002000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RDMA1>,
- <&mmsys CLK_MM_MUTEX_32K>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_RDMA1>;
- mediatek,larb = <&larb4>;
- };
-
- mdp_rsz0: rsz@14003000 {
- compatible = "mediatek,mt8173-mdp-rsz";
- reg = <0 0x14003000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RSZ0>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- };
-
- mdp_rsz1: rsz@14004000 {
- compatible = "mediatek,mt8173-mdp-rsz";
- reg = <0 0x14004000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RSZ1>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- };
-
- mdp_rsz2: rsz@14005000 {
- compatible = "mediatek,mt8173-mdp-rsz";
- reg = <0 0x14005000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RSZ2>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- };
-
- mdp_wdma0: wdma@14006000 {
- compatible = "mediatek,mt8173-mdp-wdma";
- reg = <0 0x14006000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_WDMA>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_WDMA>;
- mediatek,larb = <&larb0>;
- };
-
- mdp_wrot0: wrot@14007000 {
- compatible = "mediatek,mt8173-mdp-wrot";
- reg = <0 0x14007000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_WROT0>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_WROT0>;
- mediatek,larb = <&larb0>;
- };
-
- mdp_wrot1: wrot@14008000 {
- compatible = "mediatek,mt8173-mdp-wrot";
- reg = <0 0x14008000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_WROT1>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_WROT1>;
- mediatek,larb = <&larb4>;
- };
- };
-
- ovl0: ovl@1400c000 {
- compatible = "mediatek,mt8173-disp-ovl";
- reg = <0 0x1400c000 0 0x1000>;
- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_OVL0>;
- iommus = <&iommu M4U_PORT_DISP_OVL0>;
- mediatek,larb = <&larb0>;
- };
-
- ovl1: ovl@1400d000 {
- compatible = "mediatek,mt8173-disp-ovl";
- reg = <0 0x1400d000 0 0x1000>;
- interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_OVL1>;
- iommus = <&iommu M4U_PORT_DISP_OVL1>;
- mediatek,larb = <&larb4>;
- };
-
- rdma0: rdma@1400e000 {
- compatible = "mediatek,mt8173-disp-rdma";
- reg = <0 0x1400e000 0 0x1000>;
- interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_RDMA0>;
- iommus = <&iommu M4U_PORT_DISP_RDMA0>;
- mediatek,larb = <&larb0>;
- };
-
- rdma1: rdma@1400f000 {
- compatible = "mediatek,mt8173-disp-rdma";
- reg = <0 0x1400f000 0 0x1000>;
- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_RDMA1>;
- iommus = <&iommu M4U_PORT_DISP_RDMA1>;
- mediatek,larb = <&larb4>;
- };
-
- rdma2: rdma@14010000 {
- compatible = "mediatek,mt8173-disp-rdma";
- reg = <0 0x14010000 0 0x1000>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_RDMA2>;
- iommus = <&iommu M4U_PORT_DISP_RDMA2>;
- mediatek,larb = <&larb4>;
- };
-
- wdma0: wdma@14011000 {
- compatible = "mediatek,mt8173-disp-wdma";
- reg = <0 0x14011000 0 0x1000>;
- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_WDMA0>;
- iommus = <&iommu M4U_PORT_DISP_WDMA0>;
- mediatek,larb = <&larb0>;
- };
-
- wdma1: wdma@14012000 {
- compatible = "mediatek,mt8173-disp-wdma";
- reg = <0 0x14012000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_WDMA1>;
- iommus = <&iommu M4U_PORT_DISP_WDMA1>;
- mediatek,larb = <&larb4>;
- };
-
- color0: color@14013000 {
- compatible = "mediatek,mt8173-disp-color";
- reg = <0 0x14013000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_COLOR0>;
- };
-
- color1: color@14014000 {
- compatible = "mediatek,mt8173-disp-color";
- reg = <0 0x14014000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_COLOR1>;
- };
-
- aal@14015000 {
- compatible = "mediatek,mt8173-disp-aal";
- reg = <0 0x14015000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_AAL>;
- };
-
- gamma@14016000 {
- compatible = "mediatek,mt8173-disp-gamma";
- reg = <0 0x14016000 0 0x1000>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_GAMMA>;
- };
-
- merge@14017000 {
- compatible = "mediatek,mt8173-disp-merge";
- reg = <0 0x14017000 0 0x1000>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_MERGE>;
- };
-
- split0: split@14018000 {
- compatible = "mediatek,mt8173-disp-split";
- reg = <0 0x14018000 0 0x1000>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
- };
-
- split1: split@14019000 {
- compatible = "mediatek,mt8173-disp-split";
- reg = <0 0x14019000 0 0x1000>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
- };
-
- ufoe@1401a000 {
- compatible = "mediatek,mt8173-disp-ufoe";
- reg = <0 0x1401a000 0 0x1000>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_UFOE>;
- };
-
- dsi0: dsi@1401b000 {
- compatible = "mediatek,mt8173-dsi";
- reg = <0 0x1401b000 0 0x1000>;
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
- <&mmsys CLK_MM_DSI0_DIGITAL>,
- <&mipi_tx0>;
- clock-names = "engine", "digital", "hs";
- phys = <&mipi_tx0>;
- phy-names = "dphy";
- status = "disabled";
- };
-
- dsi1: dsi@1401c000 {
- compatible = "mediatek,mt8173-dsi";
- reg = <0 0x1401c000 0 0x1000>;
- interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
- <&mmsys CLK_MM_DSI1_DIGITAL>,
- <&mipi_tx1>;
- clock-names = "engine", "digital", "hs";
- phy = <&mipi_tx1>;
- phy-names = "dphy";
- status = "disabled";
- };
-
- dpi0: dpi@1401d000 {
- compatible = "mediatek,mt8173-dpi";
- reg = <0 0x1401d000 0 0x1000>;
- interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DPI_PIXEL>,
- <&mmsys CLK_MM_DPI_ENGINE>,
- <&apmixedsys CLK_APMIXED_TVDPLL>;
- clock-names = "pixel", "engine", "pll";
- status = "disabled";
-
- port {
- dpi0_out: endpoint {
- remote-endpoint = <&hdmi0_in>;
- };
- };
- };
-
- pwm0: pwm@1401e000 {
- compatible = "mediatek,mt8173-disp-pwm",
- "mediatek,mt6595-disp-pwm";
- reg = <0 0x1401e000 0 0x1000>;
- #pwm-cells = <2>;
- clocks = <&mmsys CLK_MM_DISP_PWM026M>,
- <&mmsys CLK_MM_DISP_PWM0MM>;
- clock-names = "main", "mm";
- status = "disabled";
- };
-
- pwm1: pwm@1401f000 {
- compatible = "mediatek,mt8173-disp-pwm",
- "mediatek,mt6595-disp-pwm";
- reg = <0 0x1401f000 0 0x1000>;
- #pwm-cells = <2>;
- clocks = <&mmsys CLK_MM_DISP_PWM126M>,
- <&mmsys CLK_MM_DISP_PWM1MM>;
- clock-names = "main", "mm";
- status = "disabled";
- };
-
- mutex: mutex@14020000 {
- compatible = "mediatek,mt8173-disp-mutex";
- reg = <0 0x14020000 0 0x1000>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_MUTEX_32K>;
- };
-
- larb0: larb@14021000 {
- compatible = "mediatek,mt8173-smi-larb";
- reg = <0 0x14021000 0 0x1000>;
- mediatek,smi = <&smi_common>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_SMI_LARB0>,
- <&mmsys CLK_MM_SMI_LARB0>;
- clock-names = "apb", "smi";
- };
-
- smi_common: smi@14022000 {
- compatible = "mediatek,mt8173-smi-common";
- reg = <0 0x14022000 0 0x1000>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_SMI_COMMON>,
- <&mmsys CLK_MM_SMI_COMMON>;
- clock-names = "apb", "smi";
- };
-
- od@14023000 {
- compatible = "mediatek,mt8173-disp-od";
- reg = <0 0x14023000 0 0x1000>;
- clocks = <&mmsys CLK_MM_DISP_OD>;
- };
-
- hdmi0: hdmi@14025000 {
- compatible = "mediatek,mt8173-hdmi";
- reg = <0 0x14025000 0 0x400>;
- interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
- <&mmsys CLK_MM_HDMI_PLLCK>,
- <&mmsys CLK_MM_HDMI_AUDIO>,
- <&mmsys CLK_MM_HDMI_SPDIF>;
- clock-names = "pixel", "pll", "bclk", "spdif";
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_pin>;
- phys = <&hdmi_phy>;
- phy-names = "hdmi";
- mediatek,syscon-hdmi = <&mmsys 0x900>;
- assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
- assigned-clock-parents = <&hdmi_phy>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- hdmi0_in: endpoint {
- remote-endpoint = <&dpi0_out>;
- };
- };
- };
- };
-
- larb4: larb@14027000 {
- compatible = "mediatek,mt8173-smi-larb";
- reg = <0 0x14027000 0 0x1000>;
- mediatek,smi = <&smi_common>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_SMI_LARB4>,
- <&mmsys CLK_MM_SMI_LARB4>;
- clock-names = "apb", "smi";
- };
-
- imgsys: clock-controller@15000000 {
- compatible = "mediatek,mt8173-imgsys", "syscon";
- reg = <0 0x15000000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- larb2: larb@15001000 {
- compatible = "mediatek,mt8173-smi-larb";
- reg = <0 0x15001000 0 0x1000>;
- mediatek,smi = <&smi_common>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>;
- clocks = <&imgsys CLK_IMG_LARB2_SMI>,
- <&imgsys CLK_IMG_LARB2_SMI>;
- clock-names = "apb", "smi";
- };
-
- vdecsys: clock-controller@16000000 {
- compatible = "mediatek,mt8173-vdecsys", "syscon";
- reg = <0 0x16000000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- vcodec_dec: vcodec@16000000 {
- compatible = "mediatek,mt8173-vcodec-dec";
- reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */
- <0 0x16020000 0 0x1000>, /* VDEC_MISC */
- <0 0x16021000 0 0x800>, /* VDEC_LD */
- <0 0x16021800 0 0x800>, /* VDEC_TOP */
- <0 0x16022000 0 0x1000>, /* VDEC_CM */
- <0 0x16023000 0 0x1000>, /* VDEC_AD */
- <0 0x16024000 0 0x1000>, /* VDEC_AV */
- <0 0x16025000 0 0x1000>, /* VDEC_PP */
- <0 0x16026800 0 0x800>, /* VDEC_HWD */
- <0 0x16027000 0 0x800>, /* VDEC_HWQ */
- <0 0x16027800 0 0x800>, /* VDEC_HWB */
- <0 0x16028400 0 0x400>; /* VDEC_HWG */
- interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
- mediatek,larb = <&larb1>;
- iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
- <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
- <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
- <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
- <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
- <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
- <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
- <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
- mediatek,vpu = <&vpu>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
- clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
- <&topckgen CLK_TOP_UNIVPLL_D2>,
- <&topckgen CLK_TOP_CCI400_SEL>,
- <&topckgen CLK_TOP_VDEC_SEL>,
- <&topckgen CLK_TOP_VCODECPLL>,
- <&apmixedsys CLK_APMIXED_VENCPLL>,
- <&topckgen CLK_TOP_VENC_LT_SEL>,
- <&topckgen CLK_TOP_VCODECPLL_370P5>;
- clock-names = "vcodecpll",
- "univpll_d2",
- "clk_cci400_sel",
- "vdec_sel",
- "vdecpll",
- "vencpll",
- "venc_lt_sel",
- "vdec_bus_clk_src";
- };
-
- larb1: larb@16010000 {
- compatible = "mediatek,mt8173-smi-larb";
- reg = <0 0x16010000 0 0x1000>;
- mediatek,smi = <&smi_common>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
- clocks = <&vdecsys CLK_VDEC_CKEN>,
- <&vdecsys CLK_VDEC_LARB_CKEN>;
- clock-names = "apb", "smi";
- };
-
- vencsys: clock-controller@18000000 {
- compatible = "mediatek,mt8173-vencsys", "syscon";
- reg = <0 0x18000000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- larb3: larb@18001000 {
- compatible = "mediatek,mt8173-smi-larb";
- reg = <0 0x18001000 0 0x1000>;
- mediatek,smi = <&smi_common>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
- clocks = <&vencsys CLK_VENC_CKE1>,
- <&vencsys CLK_VENC_CKE0>;
- clock-names = "apb", "smi";
- };
-
- vcodec_enc: vcodec@18002000 {
- compatible = "mediatek,mt8173-vcodec-enc";
- reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */
- <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
- interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
- mediatek,larb = <&larb3>,
- <&larb5>;
- iommus = <&iommu M4U_PORT_VENC_RCPU>,
- <&iommu M4U_PORT_VENC_REC>,
- <&iommu M4U_PORT_VENC_BSDMA>,
- <&iommu M4U_PORT_VENC_SV_COMV>,
- <&iommu M4U_PORT_VENC_RD_COMV>,
- <&iommu M4U_PORT_VENC_CUR_LUMA>,
- <&iommu M4U_PORT_VENC_CUR_CHROMA>,
- <&iommu M4U_PORT_VENC_REF_LUMA>,
- <&iommu M4U_PORT_VENC_REF_CHROMA>,
- <&iommu M4U_PORT_VENC_NBM_RDMA>,
- <&iommu M4U_PORT_VENC_NBM_WDMA>,
- <&iommu M4U_PORT_VENC_RCPU_SET2>,
- <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
- <&iommu M4U_PORT_VENC_BSDMA_SET2>,
- <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
- <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
- <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
- <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
- <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
- <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
- mediatek,vpu = <&vpu>;
- clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
- <&topckgen CLK_TOP_VENC_SEL>,
- <&topckgen CLK_TOP_UNIVPLL1_D2>,
- <&topckgen CLK_TOP_VENC_LT_SEL>;
- clock-names = "venc_sel_src",
- "venc_sel",
- "venc_lt_sel_src",
- "venc_lt_sel";
- };
-
- vencltsys: clock-controller@19000000 {
- compatible = "mediatek,mt8173-vencltsys", "syscon";
- reg = <0 0x19000000 0 0x1000>;
- #clock-cells = <1>;
+&cpu_thermal {
+ cooling-maps {
+ map@0 {
+ trip = <&target>;
+ cooling-device = <&cpu0 0 0>;
+ contribution = <1024>;
};
-
- larb5: larb@19001000 {
- compatible = "mediatek,mt8173-smi-larb";
- reg = <0 0x19001000 0 0x1000>;
- mediatek,smi = <&smi_common>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
- clocks = <&vencltsys CLK_VENCLT_CKE1>,
- <&vencltsys CLK_VENCLT_CKE0>;
- clock-names = "apb", "smi";
+ map@1 {
+ trip = <&target>;
+ cooling-device = <&cpu2 0 0>;
+ contribution = <2048>;
};
};
};
-
diff --git a/arch/arm64/boot/dts/mediatek/mt8176.dtsi b/arch/arm64/boot/dts/mediatek/mt8176.dtsi
new file mode 100644
index 0000000..2925905
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8176.dtsi
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Yidi Lin <yidi.lin-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "mt817x.dtsi"
+
+/ {
+ compatible = "mediatek,mt8176";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x002>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x003>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ };
+
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ };
+
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ entry-latency-us = <639>;
+ exit-latency-us = <680>;
+ min-residency-us = <1088>;
+ arm,psci-suspend-param = <0x0010000>;
+ };
+ };
+ };
+};
+
+&cpu_thermal {
+ cooling-maps {
+ map@0 {
+ trip = <&target>;
+ cooling-device = <&cpu0 0 0>;
+ contribution = <1024>;
+ };
+ map@1 {
+ trip = <&target>;
+ cooling-device = <&cpu4 0 0>;
+ contribution = <2048>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt817x.dtsi b/arch/arm64/boot/dts/mediatek/mt817x.dtsi
new file mode 100644
index 0000000..ad18439
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt817x.dtsi
@@ -0,0 +1,1199 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ * Author: Eddie Huang <eddie.huang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/clock/mt8173-clk.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/memory/mt8173-larb-port.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/power/mt8173-power.h>
+#include <dt-bindings/reset/mt8173-resets.h>
+#include "mt8173-pinfunc.h"
+
+/ {
+ compatible = "mediatek,mt817x";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ovl0 = &ovl0;
+ ovl1 = &ovl1;
+ rdma0 = &rdma0;
+ rdma1 = &rdma1;
+ rdma2 = &rdma2;
+ wdma0 = &wdma0;
+ wdma1 = &wdma1;
+ color0 = &color0;
+ color1 = &color1;
+ split0 = &split0;
+ split1 = &split1;
+ dpi0 = &dpi0;
+ dsi0 = &dsi0;
+ dsi1 = &dsi1;
+ mdp_rdma0 = &mdp_rdma0;
+ mdp_rdma1 = &mdp_rdma1;
+ mdp_rsz0 = &mdp_rsz0;
+ mdp_rsz1 = &mdp_rsz1;
+ mdp_rsz2 = &mdp_rsz2;
+ mdp_wdma0 = &mdp_wdma0;
+ mdp_wrot0 = &mdp_wrot0;
+ mdp_wrot1 = &mdp_wrot1;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
+ method = "smc";
+ cpu_suspend = <0x84000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0x84000003>;
+ };
+
+ clk26m: oscillator@0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ clk32k: oscillator@1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ clock-output-names = "clk32k";
+ };
+
+ cpum_ck: oscillator@2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "cpum_ck";
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu_thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+
+ thermal-sensors = <&thermal>;
+ sustainable-power = <1500>; /* milliwatts */
+
+ trips {
+ threshold: trip-point@0 {
+ temperature = <68000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ target: trip-point@1 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu_crit@0 {
+ temperature = <115000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ vpu_dma_reserved: vpu_dma_mem_region {
+ compatible = "shared-dma-pool";
+ reg = <0 0xb7000000 0 0x500000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ topckgen: clock-controller@10000000 {
+ compatible = "mediatek,mt8173-topckgen";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: power-controller@10001000 {
+ compatible = "mediatek,mt8173-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pericfg: power-controller@10003000 {
+ compatible = "mediatek,mt8173-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ syscfg_pctl_a: syscfg_pctl_a@10005000 {
+ compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
+ reg = <0 0x10005000 0 0x1000>;
+ };
+
+ pio: pinctrl@0x10005000 {
+ compatible = "mediatek,mt8173-pinctrl";
+ reg = <0 0x1000b000 0 0x1000>;
+ mediatek,pctl-regmap = <&syscfg_pctl_a>;
+ pins-are-numbered;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+
+ hdmi_pin: xxx {
+
+ /*hdmi htplg pin*/
+ pins1 {
+ pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ i2c0_pins_a: i2c0 {
+ pins1 {
+ pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
+ <MT8173_PIN_46_SCL0__FUNC_SCL0>;
+ bias-disable;
+ };
+ };
+
+ i2c1_pins_a: i2c1 {
+ pins1 {
+ pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
+ <MT8173_PIN_126_SCL1__FUNC_SCL1>;
+ bias-disable;
+ };
+ };
+
+ i2c2_pins_a: i2c2 {
+ pins1 {
+ pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
+ <MT8173_PIN_44_SCL2__FUNC_SCL2>;
+ bias-disable;
+ };
+ };
+
+ i2c3_pins_a: i2c3 {
+ pins1 {
+ pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
+ <MT8173_PIN_107_SCL3__FUNC_SCL3>;
+ bias-disable;
+ };
+ };
+
+ i2c4_pins_a: i2c4 {
+ pins1 {
+ pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
+ <MT8173_PIN_134_SCL4__FUNC_SCL4>;
+ bias-disable;
+ };
+ };
+
+ i2c6_pins_a: i2c6 {
+ pins1 {
+ pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
+ <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
+ bias-disable;
+ };
+ };
+ };
+
+ scpsys: scpsys@10006000 {
+ compatible = "mediatek,mt8173-scpsys";
+ #power-domain-cells = <1>;
+ reg = <0 0x10006000 0 0x1000>;
+ clocks = <&clk26m>,
+ <&topckgen CLK_TOP_MM_SEL>,
+ <&topckgen CLK_TOP_VENC_SEL>,
+ <&topckgen CLK_TOP_VENC_LT_SEL>;
+ clock-names = "mfg", "mm", "venc", "venc_lt";
+ infracfg = <&infracfg>;
+ };
+
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8173-wdt",
+ "mediatek,mt6589-wdt";
+ reg = <0 0x10007000 0 0x100>;
+ };
+
+ timer: timer@10008000 {
+ compatible = "mediatek,mt8173-timer",
+ "mediatek,mt6577-timer";
+ reg = <0 0x10008000 0 0x1000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_CLK_13M>,
+ <&topckgen CLK_TOP_RTC_SEL>;
+ };
+
+ pwrap: pwrap@1000d000 {
+ compatible = "mediatek,mt8173-pwrap";
+ reg = <0 0x1000d000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
+ reset-names = "pwrap";
+ clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
+ clock-names = "spi", "wrap";
+ };
+
+ cec: cec@10013000 {
+ compatible = "mediatek,mt8173-cec";
+ reg = <0 0x10013000 0 0xbc>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_CEC>;
+ status = "disabled";
+ };
+
+ vpu: vpu@10020000 {
+ compatible = "mediatek,mt8173-vpu";
+ reg = <0 0x10020000 0 0x30000>,
+ <0 0x10050000 0 0x100>;
+ reg-names = "tcm", "cfg_reg";
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_SCP_SEL>;
+ clock-names = "main";
+ memory-region = <&vpu_dma_reserved>;
+ };
+
+ sysirq: intpol-controller@10200620 {
+ compatible = "mediatek,mt8173-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10200620 0 0x20>;
+ };
+
+ iommu: iommu@10205000 {
+ compatible = "mediatek,mt8173-m4u";
+ reg = <0 0x10205000 0 0x1000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_M4U>;
+ clock-names = "bclk";
+ mediatek,larbs = <&larb0 &larb1 &larb2
+ &larb3 &larb4 &larb5>;
+ #iommu-cells = <1>;
+ };
+
+ efuse: efuse@10206000 {
+ compatible = "mediatek,mt8173-efuse";
+ reg = <0 0x10206000 0 0x1000>;
+ };
+
+ apmixedsys: clock-controller@10209000 {
+ compatible = "mediatek,mt8173-apmixedsys";
+ reg = <0 0x10209000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ hdmi_phy: hdmi-phy@10209100 {
+ compatible = "mediatek,mt8173-hdmi-phy";
+ reg = <0 0x10209100 0 0x24>;
+ clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
+ clock-names = "pll_ref";
+ clock-output-names = "hdmitx_dig_cts";
+ mediatek,ibias = <0xa>;
+ mediatek,ibias_up = <0x1c>;
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ mipi_tx0: mipi-dphy@10215000 {
+ compatible = "mediatek,mt8173-mipi-tx";
+ reg = <0 0x10215000 0 0x1000>;
+ clocks = <&clk26m>;
+ clock-output-names = "mipi_tx0_pll";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ mipi_tx1: mipi-dphy@10216000 {
+ compatible = "mediatek,mt8173-mipi-tx";
+ reg = <0 0x10216000 0 0x1000>;
+ clocks = <&clk26m>;
+ clock-output-names = "mipi_tx1_pll";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@10220000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x10221000 0 0x1000>,
+ <0 0x10222000 0 0x2000>,
+ <0 0x10224000 0 0x2000>,
+ <0 0x10226000 0 0x2000>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ auxadc: auxadc@11001000 {
+ compatible = "mediatek,mt8173-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ clocks = <&pericfg CLK_PERI_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt8173-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x400>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt8173-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x400>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart2: serial@11004000 {
+ compatible = "mediatek,mt8173-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x400>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart3: serial@11005000 {
+ compatible = "mediatek,mt8173-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11005000 0 0x400>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ i2c0: i2c@11007000 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x11007000 0 0x70>,
+ <0 0x11000100 0 0x80>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C0>,
+ <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@11008000 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x11008000 0 0x70>,
+ <0 0x11000180 0 0x80>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C1>,
+ <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@11009000 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x11009000 0 0x70>,
+ <0 0x11000200 0 0x80>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C2>,
+ <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi: spi@1100a000 {
+ compatible = "mediatek,mt8173-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x1100a000 0 0x1000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&pericfg CLK_PERI_SPI0>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ thermal: thermal@1100b000 {
+ #thermal-sensor-cells = <0>;
+ compatible = "mediatek,mt8173-thermal";
+ reg = <0 0x1100b000 0 0x1000>;
+ interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
+ clock-names = "therm", "auxadc";
+ resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
+ mediatek,auxadc = <&auxadc>;
+ mediatek,apmixedsys = <&apmixedsys>;
+ };
+
+ nor_flash: spi@1100d000 {
+ compatible = "mediatek,mt8173-nor";
+ reg = <0 0x1100d000 0 0xe0>;
+ clocks = <&pericfg CLK_PERI_SPI>,
+ <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
+ clock-names = "spi", "sf";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@11010000 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x11010000 0 0x70>,
+ <0 0x11000280 0 0x80>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C3>,
+ <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins_a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@11011000 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x11011000 0 0x70>,
+ <0 0x11000300 0 0x80>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C4>,
+ <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins_a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ hdmiddc0: i2c@11012000 {
+ compatible = "mediatek,mt8173-hdmi-ddc";
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
+ reg = <0 0x11012000 0 0x1C>;
+ clocks = <&pericfg CLK_PERI_I2C5>;
+ clock-names = "ddc-i2c";
+ };
+
+ i2c6: i2c@11013000 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x11013000 0 0x70>,
+ <0 0x11000080 0 0x80>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C6>,
+ <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6_pins_a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ afe: audio-controller@11220000 {
+ compatible = "mediatek,mt8173-afe-pcm";
+ reg = <0 0x11220000 0 0x1000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
+ clocks = <&infracfg CLK_INFRA_AUDIO>,
+ <&topckgen CLK_TOP_AUDIO_SEL>,
+ <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+ <&topckgen CLK_TOP_APLL1_DIV0>,
+ <&topckgen CLK_TOP_APLL2_DIV0>,
+ <&topckgen CLK_TOP_I2S0_M_SEL>,
+ <&topckgen CLK_TOP_I2S1_M_SEL>,
+ <&topckgen CLK_TOP_I2S2_M_SEL>,
+ <&topckgen CLK_TOP_I2S3_M_SEL>,
+ <&topckgen CLK_TOP_I2S3_B_SEL>;
+ clock-names = "infra_sys_audio_clk",
+ "top_pdn_audio",
+ "top_pdn_aud_intbus",
+ "bck0",
+ "bck1",
+ "i2s0_m",
+ "i2s1_m",
+ "i2s2_m",
+ "i2s3_m",
+ "i2s3_b";
+ assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
+ <&topckgen CLK_TOP_AUD_2_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
+ <&topckgen CLK_TOP_APLL2>;
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8173-mmc",
+ "mediatek,mt8135-mmc";
+ reg = <0 0x11230000 0 0x1000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_0>,
+ <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
+ clock-names = "source", "hclk";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11240000 {
+ compatible = "mediatek,mt8173-mmc",
+ "mediatek,mt8135-mmc";
+ reg = <0 0x11240000 0 0x1000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_1>,
+ <&topckgen CLK_TOP_AXI_SEL>;
+ clock-names = "source", "hclk";
+ status = "disabled";
+ };
+
+ mmc2: mmc@11250000 {
+ compatible = "mediatek,mt8173-mmc",
+ "mediatek,mt8135-mmc";
+ reg = <0 0x11250000 0 0x1000>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_2>,
+ <&topckgen CLK_TOP_AXI_SEL>;
+ clock-names = "source", "hclk";
+ status = "disabled";
+ };
+
+ mmc3: mmc@11260000 {
+ compatible = "mediatek,mt8173-mmc",
+ "mediatek,mt8135-mmc";
+ reg = <0 0x11260000 0 0x1000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_3>,
+ <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
+ clock-names = "source", "hclk";
+ status = "disabled";
+ };
+
+ ssusb: usb@11271000 {
+ compatible = "mediatek,mt8173-mtu3";
+ reg = <0 0x11271000 0 0x3000>,
+ <0 0x11280700 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
+ phys = <&phy_port0 PHY_TYPE_USB3>,
+ <&phy_port1 PHY_TYPE_USB2>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
+ clocks = <&topckgen CLK_TOP_USB30_SEL>,
+ <&pericfg CLK_PERI_USB0>,
+ <&pericfg CLK_PERI_USB1>;
+ clock-names = "sys_ck",
+ "wakeup_deb_p0",
+ "wakeup_deb_p1";
+ mediatek,syscon-wakeup = <&pericfg>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usb_host: xhci@11270000 {
+ compatible = "mediatek,mt8173-xhci";
+ reg = <0 0x11270000 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
+ clocks = <&topckgen CLK_TOP_USB30_SEL>;
+ clock-names = "sys_ck";
+ status = "disabled";
+ };
+ };
+
+ u3phy: usb-phy@11290000 {
+ compatible = "mediatek,mt8173-u3phy";
+ reg = <0 0x11290000 0 0x800>;
+ clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
+ clock-names = "u3phya_ref";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "okay";
+
+ phy_port0: port@11290800 {
+ reg = <0 0x11290800 0 0x800>;
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ phy_port1: port@11291000 {
+ reg = <0 0x11291000 0 0x800>;
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
+ mmsys: clock-controller@14000000 {
+ compatible = "mediatek,mt8173-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ #clock-cells = <1>;
+ };
+
+ mdp {
+ compatible = "mediatek,mt8173-mdp";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ mediatek,vpu = <&vpu>;
+
+ mdp_rdma0: rdma@14001000 {
+ compatible = "mediatek,mt8173-mdp-rdma";
+ reg = <0 0x14001000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RDMA0>,
+ <&mmsys CLK_MM_MUTEX_32K>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_RDMA0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ mdp_rdma1: rdma@14002000 {
+ compatible = "mediatek,mt8173-mdp-rdma";
+ reg = <0 0x14002000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RDMA1>,
+ <&mmsys CLK_MM_MUTEX_32K>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_RDMA1>;
+ mediatek,larb = <&larb4>;
+ };
+
+ mdp_rsz0: rsz@14003000 {
+ compatible = "mediatek,mt8173-mdp-rsz";
+ reg = <0 0x14003000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ0>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ };
+
+ mdp_rsz1: rsz@14004000 {
+ compatible = "mediatek,mt8173-mdp-rsz";
+ reg = <0 0x14004000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ1>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ };
+
+ mdp_rsz2: rsz@14005000 {
+ compatible = "mediatek,mt8173-mdp-rsz";
+ reg = <0 0x14005000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ2>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ };
+
+ mdp_wdma0: wdma@14006000 {
+ compatible = "mediatek,mt8173-mdp-wdma";
+ reg = <0 0x14006000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_WDMA>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_WDMA>;
+ mediatek,larb = <&larb0>;
+ };
+
+ mdp_wrot0: wrot@14007000 {
+ compatible = "mediatek,mt8173-mdp-wrot";
+ reg = <0 0x14007000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_WROT0>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_WROT0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ mdp_wrot1: wrot@14008000 {
+ compatible = "mediatek,mt8173-mdp-wrot";
+ reg = <0 0x14008000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_WROT1>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_WROT1>;
+ mediatek,larb = <&larb4>;
+ };
+ };
+
+ ovl0: ovl@1400c000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ iommus = <&iommu M4U_PORT_DISP_OVL0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ ovl1: ovl@1400d000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_OVL1>;
+ iommus = <&iommu M4U_PORT_DISP_OVL1>;
+ mediatek,larb = <&larb4>;
+ };
+
+ rdma0: rdma@1400e000 {
+ compatible = "mediatek,mt8173-disp-rdma";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ rdma1: rdma@1400f000 {
+ compatible = "mediatek,mt8173-disp-rdma";
+ reg = <0 0x1400f000 0 0x1000>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA1>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA1>;
+ mediatek,larb = <&larb4>;
+ };
+
+ rdma2: rdma@14010000 {
+ compatible = "mediatek,mt8173-disp-rdma";
+ reg = <0 0x14010000 0 0x1000>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA2>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA2>;
+ mediatek,larb = <&larb4>;
+ };
+
+ wdma0: wdma@14011000 {
+ compatible = "mediatek,mt8173-disp-wdma";
+ reg = <0 0x14011000 0 0x1000>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_WDMA0>;
+ iommus = <&iommu M4U_PORT_DISP_WDMA0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ wdma1: wdma@14012000 {
+ compatible = "mediatek,mt8173-disp-wdma";
+ reg = <0 0x14012000 0 0x1000>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_WDMA1>;
+ iommus = <&iommu M4U_PORT_DISP_WDMA1>;
+ mediatek,larb = <&larb4>;
+ };
+
+ color0: color@14013000 {
+ compatible = "mediatek,mt8173-disp-color";
+ reg = <0 0x14013000 0 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ };
+
+ color1: color@14014000 {
+ compatible = "mediatek,mt8173-disp-color";
+ reg = <0 0x14014000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR1>;
+ };
+
+ aal@14015000 {
+ compatible = "mediatek,mt8173-disp-aal";
+ reg = <0 0x14015000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_AAL>;
+ };
+
+ gamma@14016000 {
+ compatible = "mediatek,mt8173-disp-gamma";
+ reg = <0 0x14016000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_GAMMA>;
+ };
+
+ merge@14017000 {
+ compatible = "mediatek,mt8173-disp-merge";
+ reg = <0 0x14017000 0 0x1000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_MERGE>;
+ };
+
+ split0: split@14018000 {
+ compatible = "mediatek,mt8173-disp-split";
+ reg = <0 0x14018000 0 0x1000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
+ };
+
+ split1: split@14019000 {
+ compatible = "mediatek,mt8173-disp-split";
+ reg = <0 0x14019000 0 0x1000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
+ };
+
+ ufoe@1401a000 {
+ compatible = "mediatek,mt8173-disp-ufoe";
+ reg = <0 0x1401a000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_UFOE>;
+ };
+
+ dsi0: dsi@1401b000 {
+ compatible = "mediatek,mt8173-dsi";
+ reg = <0 0x1401b000 0 0x1000>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
+ <&mmsys CLK_MM_DSI0_DIGITAL>,
+ <&mipi_tx0>;
+ clock-names = "engine", "digital", "hs";
+ phys = <&mipi_tx0>;
+ phy-names = "dphy";
+ status = "disabled";
+ };
+
+ dsi1: dsi@1401c000 {
+ compatible = "mediatek,mt8173-dsi";
+ reg = <0 0x1401c000 0 0x1000>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
+ <&mmsys CLK_MM_DSI1_DIGITAL>,
+ <&mipi_tx1>;
+ clock-names = "engine", "digital", "hs";
+ phy = <&mipi_tx1>;
+ phy-names = "dphy";
+ status = "disabled";
+ };
+
+ dpi0: dpi@1401d000 {
+ compatible = "mediatek,mt8173-dpi";
+ reg = <0 0x1401d000 0 0x1000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DPI_PIXEL>,
+ <&mmsys CLK_MM_DPI_ENGINE>,
+ <&apmixedsys CLK_APMIXED_TVDPLL>;
+ clock-names = "pixel", "engine", "pll";
+ status = "disabled";
+
+ port {
+ dpi0_out: endpoint {
+ remote-endpoint = <&hdmi0_in>;
+ };
+ };
+ };
+
+ pwm0: pwm@1401e000 {
+ compatible = "mediatek,mt8173-disp-pwm",
+ "mediatek,mt6595-disp-pwm";
+ reg = <0 0x1401e000 0 0x1000>;
+ #pwm-cells = <2>;
+ clocks = <&mmsys CLK_MM_DISP_PWM026M>,
+ <&mmsys CLK_MM_DISP_PWM0MM>;
+ clock-names = "main", "mm";
+ status = "disabled";
+ };
+
+ pwm1: pwm@1401f000 {
+ compatible = "mediatek,mt8173-disp-pwm",
+ "mediatek,mt6595-disp-pwm";
+ reg = <0 0x1401f000 0 0x1000>;
+ #pwm-cells = <2>;
+ clocks = <&mmsys CLK_MM_DISP_PWM126M>,
+ <&mmsys CLK_MM_DISP_PWM1MM>;
+ clock-names = "main", "mm";
+ status = "disabled";
+ };
+
+ mutex: mutex@14020000 {
+ compatible = "mediatek,mt8173-disp-mutex";
+ reg = <0 0x14020000 0 0x1000>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_MUTEX_32K>;
+ };
+
+ larb0: larb@14021000 {
+ compatible = "mediatek,mt8173-smi-larb";
+ reg = <0 0x14021000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_SMI_LARB0>,
+ <&mmsys CLK_MM_SMI_LARB0>;
+ clock-names = "apb", "smi";
+ };
+
+ smi_common: smi@14022000 {
+ compatible = "mediatek,mt8173-smi-common";
+ reg = <0 0x14022000 0 0x1000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_COMMON>;
+ clock-names = "apb", "smi";
+ };
+
+ od@14023000 {
+ compatible = "mediatek,mt8173-disp-od";
+ reg = <0 0x14023000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_OD>;
+ };
+
+ hdmi0: hdmi@14025000 {
+ compatible = "mediatek,mt8173-hdmi";
+ reg = <0 0x14025000 0 0x400>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
+ <&mmsys CLK_MM_HDMI_PLLCK>,
+ <&mmsys CLK_MM_HDMI_AUDIO>,
+ <&mmsys CLK_MM_HDMI_SPDIF>;
+ clock-names = "pixel", "pll", "bclk", "spdif";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pin>;
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi";
+ mediatek,syscon-hdmi = <&mmsys 0x900>;
+ assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
+ assigned-clock-parents = <&hdmi_phy>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+ };
+ };
+
+ larb4: larb@14027000 {
+ compatible = "mediatek,mt8173-smi-larb";
+ reg = <0 0x14027000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_SMI_LARB4>,
+ <&mmsys CLK_MM_SMI_LARB4>;
+ clock-names = "apb", "smi";
+ };
+
+ imgsys: clock-controller@15000000 {
+ compatible = "mediatek,mt8173-imgsys", "syscon";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ larb2: larb@15001000 {
+ compatible = "mediatek,mt8173-smi-larb";
+ reg = <0 0x15001000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>;
+ clocks = <&imgsys CLK_IMG_LARB2_SMI>,
+ <&imgsys CLK_IMG_LARB2_SMI>;
+ clock-names = "apb", "smi";
+ };
+
+ vdecsys: clock-controller@16000000 {
+ compatible = "mediatek,mt8173-vdecsys", "syscon";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vcodec_dec: vcodec@16000000 {
+ compatible = "mediatek,mt8173-vcodec-dec";
+ reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */
+ <0 0x16020000 0 0x1000>, /* VDEC_MISC */
+ <0 0x16021000 0 0x800>, /* VDEC_LD */
+ <0 0x16021800 0 0x800>, /* VDEC_TOP */
+ <0 0x16022000 0 0x1000>, /* VDEC_CM */
+ <0 0x16023000 0 0x1000>, /* VDEC_AD */
+ <0 0x16024000 0 0x1000>, /* VDEC_AV */
+ <0 0x16025000 0 0x1000>, /* VDEC_PP */
+ <0 0x16026800 0 0x800>, /* VDEC_HWD */
+ <0 0x16027000 0 0x800>, /* VDEC_HWQ */
+ <0 0x16027800 0 0x800>, /* VDEC_HWB */
+ <0 0x16028400 0 0x400>; /* VDEC_HWG */
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
+ mediatek,larb = <&larb1>;
+ iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
+ mediatek,vpu = <&vpu>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
+ clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
+ <&topckgen CLK_TOP_UNIVPLL_D2>,
+ <&topckgen CLK_TOP_CCI400_SEL>,
+ <&topckgen CLK_TOP_VDEC_SEL>,
+ <&topckgen CLK_TOP_VCODECPLL>,
+ <&apmixedsys CLK_APMIXED_VENCPLL>,
+ <&topckgen CLK_TOP_VENC_LT_SEL>,
+ <&topckgen CLK_TOP_VCODECPLL_370P5>;
+ clock-names = "vcodecpll",
+ "univpll_d2",
+ "clk_cci400_sel",
+ "vdec_sel",
+ "vdecpll",
+ "vencpll",
+ "venc_lt_sel",
+ "vdec_bus_clk_src";
+ };
+
+ larb1: larb@16010000 {
+ compatible = "mediatek,mt8173-smi-larb";
+ reg = <0 0x16010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
+ clocks = <&vdecsys CLK_VDEC_CKEN>,
+ <&vdecsys CLK_VDEC_LARB_CKEN>;
+ clock-names = "apb", "smi";
+ };
+
+ vencsys: clock-controller@18000000 {
+ compatible = "mediatek,mt8173-vencsys", "syscon";
+ reg = <0 0x18000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ larb3: larb@18001000 {
+ compatible = "mediatek,mt8173-smi-larb";
+ reg = <0 0x18001000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
+ clocks = <&vencsys CLK_VENC_CKE1>,
+ <&vencsys CLK_VENC_CKE0>;
+ clock-names = "apb", "smi";
+ };
+
+ vcodec_enc: vcodec@18002000 {
+ compatible = "mediatek,mt8173-vcodec-enc";
+ reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */
+ <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
+ mediatek,larb = <&larb3>,
+ <&larb5>;
+ iommus = <&iommu M4U_PORT_VENC_RCPU>,
+ <&iommu M4U_PORT_VENC_REC>,
+ <&iommu M4U_PORT_VENC_BSDMA>,
+ <&iommu M4U_PORT_VENC_SV_COMV>,
+ <&iommu M4U_PORT_VENC_RD_COMV>,
+ <&iommu M4U_PORT_VENC_CUR_LUMA>,
+ <&iommu M4U_PORT_VENC_CUR_CHROMA>,
+ <&iommu M4U_PORT_VENC_REF_LUMA>,
+ <&iommu M4U_PORT_VENC_REF_CHROMA>,
+ <&iommu M4U_PORT_VENC_NBM_RDMA>,
+ <&iommu M4U_PORT_VENC_NBM_WDMA>,
+ <&iommu M4U_PORT_VENC_RCPU_SET2>,
+ <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
+ <&iommu M4U_PORT_VENC_BSDMA_SET2>,
+ <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
+ <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
+ <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
+ <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
+ <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
+ <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
+ mediatek,vpu = <&vpu>;
+ clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
+ <&topckgen CLK_TOP_VENC_SEL>,
+ <&topckgen CLK_TOP_UNIVPLL1_D2>,
+ <&topckgen CLK_TOP_VENC_LT_SEL>;
+ clock-names = "venc_sel_src",
+ "venc_sel",
+ "venc_lt_sel_src",
+ "venc_lt_sel";
+ };
+
+ vencltsys: clock-controller@19000000 {
+ compatible = "mediatek,mt8173-vencltsys", "syscon";
+ reg = <0 0x19000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ larb5: larb@19001000 {
+ compatible = "mediatek,mt8173-smi-larb";
+ reg = <0 0x19001000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
+ clocks = <&vencltsys CLK_VENCLT_CKE1>,
+ <&vencltsys CLK_VENCLT_CKE0>;
+ clock-names = "apb", "smi";
+ };
+ };
+};
+
--
1.9.1
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^ permalink raw reply related
* Re: [PATCH v2 6/6] dt-bindings: mt8173-mtu3: add reference clock
From: Chunfeng Yun @ 2017-02-07 6:03 UTC (permalink / raw)
To: Mathias Nyman
Cc: Felipe Balbi, Greg Kroah-Hartman, Matthias Brugger, Rob Herring,
Mark Rutland, Ian Campbell, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-usb-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1486373341-4399-6-git-send-email-chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Please ignore this series of patches, due to the first version have been
merged into usb-next branch except DTS's one[PACH 4/6].
This will cause mtu3 probe failure, so I will send new patches based on
usb-next branch.
sorry
On Mon, 2017-02-06 at 17:29 +0800, Chunfeng Yun wrote:
> Due to the reference clock comes from 26M oscillator directly
> on mt8173, and it is a fixed-clock in DTS which always turned
> on, we ignore it before. But on some platforms, it comes
> from PLL, and need be controlled, so here add it, no matter
> it is a fixed-clock or not.
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
> .../devicetree/bindings/usb/mt8173-mtu3.txt | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/usb/mt8173-mtu3.txt b/Documentation/devicetree/bindings/usb/mt8173-mtu3.txt
> index e049d19..8c976cd 100644
> --- a/Documentation/devicetree/bindings/usb/mt8173-mtu3.txt
> +++ b/Documentation/devicetree/bindings/usb/mt8173-mtu3.txt
> @@ -10,7 +10,7 @@ Required properties:
> - vusb33-supply : regulator of USB avdd3.3v
> - clocks : a list of phandle + clock-specifier pairs, one for each
> entry in clock-names
> - - clock-names : must contain "sys_ck" for clock of controller;
> + - clock-names : must contain "sys_ck" and "ref_ck" for clock of controller;
> "wakeup_deb_p0" and "wakeup_deb_p1" are optional, they are
> depends on "mediatek,enable-wakeup"
> - phys : a list of phandle + phy specifier pairs
> @@ -56,10 +56,10 @@ ssusb: usb@11271000 {
> phys = <&phy_port0 PHY_TYPE_USB3>,
> <&phy_port1 PHY_TYPE_USB2>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
> - clocks = <&topckgen CLK_TOP_USB30_SEL>,
> + clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>,
> <&pericfg CLK_PERI_USB0>,
> <&pericfg CLK_PERI_USB1>;
> - clock-names = "sys_ck",
> + clock-names = "sys_ck", "ref_ck",
> "wakeup_deb_p0",
> "wakeup_deb_p1";
> vusb33-supply = <&mt6397_vusb_reg>;
> @@ -79,8 +79,8 @@ ssusb: usb@11271000 {
> reg-names = "mac";
> interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
> - clocks = <&topckgen CLK_TOP_USB30_SEL>;
> - clock-names = "sys_ck";
> + clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
> + clock-names = "sys_ck", "ref_ck";
> vusb33-supply = <&mt6397_vusb_reg>;
> status = "disabled";
> };
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^ permalink raw reply
* [PATCH -next 1/3] arm64: dts: mt8173: add reference clock for usb
From: Chunfeng Yun @ 2017-02-07 6:13 UTC (permalink / raw)
To: Mathias Nyman, Felipe Balbi
Cc: Greg Kroah-Hartman, Matthias Brugger, Rob Herring, Mark Rutland,
Ian Campbell, Chunfeng Yun, linux-kernel, linux-arm-kernel,
linux-usb, linux-mediatek, devicetree
Due to the reference clock comes from 26M oscillator directly
on mt8173, and it is a fixed-clock in DTS which always turned
on, we ignore it before. But on some platforms, it comes
from PLL, and need be controlled, so here add it, no matter
it is a fixed-clock or not.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 07fd2eb..e2862b6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -729,9 +729,11 @@
<&u2port1 PHY_TYPE_USB2>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
clocks = <&topckgen CLK_TOP_USB30_SEL>,
+ <&clk26m>,
<&pericfg CLK_PERI_USB0>,
<&pericfg CLK_PERI_USB1>;
clock-names = "sys_ck",
+ "ref_ck",
"wakeup_deb_p0",
"wakeup_deb_p1";
mediatek,syscon-wakeup = <&pericfg>;
@@ -746,8 +748,8 @@
reg-names = "mac";
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
- clocks = <&topckgen CLK_TOP_USB30_SEL>;
- clock-names = "sys_ck";
+ clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
+ clock-names = "sys_ck", "ref_ck";
status = "disabled";
};
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH -next 2/3] usb: mtu3: make the reference clock optional
From: Chunfeng Yun @ 2017-02-07 6:13 UTC (permalink / raw)
To: Mathias Nyman, Felipe Balbi
Cc: Greg Kroah-Hartman, Matthias Brugger, Rob Herring, Mark Rutland,
Ian Campbell, Chunfeng Yun, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-usb-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1486448013-8784-1-git-send-email-chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Make the reference clock optional for DTS backward compatibility
and ignore the error if it does not exist.
Signed-off-by: Chunfeng Yun <chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/usb/mtu3/mtu3_plat.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/mtu3/mtu3_plat.c b/drivers/usb/mtu3/mtu3_plat.c
index 19a345d..c3125da 100644
--- a/drivers/usb/mtu3/mtu3_plat.c
+++ b/drivers/usb/mtu3/mtu3_plat.c
@@ -225,10 +225,17 @@ static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
return PTR_ERR(ssusb->sys_clk);
}
+ /*
+ * reference clock is usually a "fixed-clock", make it optional
+ * for backward compatibility and ignore the error if it does
+ * not exist.
+ */
ssusb->ref_clk = devm_clk_get(dev, "ref_ck");
if (IS_ERR(ssusb->ref_clk)) {
- dev_err(dev, "failed to get ref clock\n");
- return PTR_ERR(ssusb->ref_clk);
+ if (PTR_ERR(ssusb->ref_clk) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
+ ssusb->ref_clk = NULL;
}
ssusb->num_phys = of_count_phandle_with_args(node,
--
1.7.9.5
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^ permalink raw reply related
* [PATCH -next 3/3] usb: xhci-mtk: make the reference clock optional
From: Chunfeng Yun @ 2017-02-07 6:13 UTC (permalink / raw)
To: Mathias Nyman, Felipe Balbi
Cc: Greg Kroah-Hartman, Matthias Brugger, Rob Herring, Mark Rutland,
Ian Campbell, Chunfeng Yun, linux-kernel, linux-arm-kernel,
linux-usb, linux-mediatek, devicetree
In-Reply-To: <1486448013-8784-1-git-send-email-chunfeng.yun@mediatek.com>
Make the reference clock optional for DTS backward compatibility
and ignore the error if it does not exist.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/usb/host/xhci-mtk.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
index 4d75ac5..75bae8e 100644
--- a/drivers/usb/host/xhci-mtk.c
+++ b/drivers/usb/host/xhci-mtk.c
@@ -559,10 +559,17 @@ static int xhci_mtk_probe(struct platform_device *pdev)
return PTR_ERR(mtk->sys_clk);
}
+ /*
+ * reference clock is usually a "fixed-clock", make it optional
+ * for backward compatibility and ignore the error if it does
+ * not exist.
+ */
mtk->ref_clk = devm_clk_get(dev, "ref_ck");
if (IS_ERR(mtk->ref_clk)) {
- dev_err(dev, "fail to get ref_ck\n");
- return PTR_ERR(mtk->ref_clk);
+ if (PTR_ERR(mtk->ref_clk) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
+ mtk->ref_clk = NULL;
}
mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
--
1.7.9.5
^ permalink raw reply related
* Re: [PATCH v2, 6/6] dt-bindings: phy-mt65xx-usb: add support for new version phy
From: Chunfeng Yun @ 2017-02-07 6:30 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Rutland, devicetree, Felipe Balbi, Ian Campbell, linux-usb,
linux-kernel, Kishon Vijay Abraham I, linux-mediatek,
Matthias Brugger, linux-arm-kernel
In-Reply-To: <20170127200702.biyvgzgoq3yxx7yx@rob-hp-laptop>
On Fri, 2017-01-27 at 14:07 -0600, Rob Herring wrote:
> On Fri, Jan 20, 2017 at 04:18:41PM +0800, Chunfeng Yun wrote:
> > add a new compatible string for "mt2712", and move reference clock
> > into each port node;
> >
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> > .../devicetree/bindings/phy/phy-mt65xx-usb.txt | 91 +++++++++++++++++---
> > 1 file changed, 77 insertions(+), 14 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt b/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt
> > index 33a2b1e..1d06604 100644
> > --- a/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt
> > +++ b/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt
> > @@ -6,21 +6,27 @@ This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC.
> > Required properties (controller (parent) node):
> > - compatible : should be one of
> > "mediatek,mt2701-u3phy"
> > + "mediatek,mt2712-u3phy"
> > "mediatek,mt8173-u3phy"
> > - - reg : offset and length of register for phy, exclude port's
> > - register.
> > - - clocks : a list of phandle + clock-specifier pairs, one for each
> > - entry in clock-names
> > - - clock-names : must contain
> > - "u3phya_ref": for reference clock of usb3.0 analog phy.
> >
> > Required nodes : a sub-node is required for each port the controller
> > provides. Address range information including the usual
> > 'reg' property is used inside these nodes to describe
> > the controller's topology.
> >
> > +Optional properties (controller (parent) node):
> > + - reg : offset and length of register shared by multiple ports,
>
> How is this optional?
I put register shared by ports in parent node, but no shared register
for new phy, so change it as optional.
>
> > + exclude port's private register. It is needed on mt2701
> > + and mt8173, but not on mt2712.
> > +
> > Required properties (port (child) node):
> > - reg : address and length of the register set for the port.
> > +- clocks : a list of phandle + clock-specifier pairs, one for each
> > + entry in clock-names
> > +- clock-names : must contain
> > + "ref_clk": 48M reference clock for HighSpeed analog phy; and
>
> _clk is redundant. Just "ref"
Ok
>
> > + 26M reference clock for SuperSpeed analog phy, sometimes is
> > + 24M, 25M or 27M, depended on platform.
> > - #phy-cells : should be 1 (See second example)
> > cell after port phandle is phy type from:
> > - PHY_TYPE_USB2
> > @@ -31,21 +37,31 @@ Example:
> > u3phy: usb-phy@11290000 {
> > compatible = "mediatek,mt8173-u3phy";
> > reg = <0 0x11290000 0 0x800>;
> > - clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
> > - clock-names = "u3phya_ref";
> > #address-cells = <2>;
> > #size-cells = <2>;
> > ranges;
> > status = "okay";
> >
> > - phy_port0: port@11290800 {
> > - reg = <0 0x11290800 0 0x800>;
> > + u2port0: port@11290800 {
> > + reg = <0 0x11290800 0 0x100>;
> > + clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
> > + clock-names = "ref_clk";
> > #phy-cells = <1>;
> > status = "okay";
> > };
> >
> > - phy_port1: port@11291000 {
> > - reg = <0 0x11291000 0 0x800>;
> > + u3port0: port@11290900 {
> > + reg = <0 0x11290800 0 0x700>;
> > + clocks = <&clk26m>;
> > + clock-names = "ref_clk";
> > + #phy-cells = <1>;
> > + status = "okay";
> > + };
> > +
> > + u2port1: port@11291000 {
> > + reg = <0 0x11291000 0 0x100>;
> > + clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
> > + clock-names = "ref_clk";
> > #phy-cells = <1>;
> > status = "okay";
> > };
> > @@ -64,7 +80,54 @@ Example:
> >
> > usb30: usb@11270000 {
> > ...
> > - phys = <&phy_port0 PHY_TYPE_USB3>;
> > - phy-names = "usb3-0";
> > + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
> > + phy-names = "usb2-0", "usb3-0";
> > ...
> > };
> > +
> > +
> > +Layout differences of banks between mt8173/mt2701 and mt2712
> > +-------------------------------------------------------------
> > +mt8173 and mt2701:
> > +port offset bank
> > +shared 0x0000 SPLLC
> > + 0x0100 FMREG
> > +u2 port0 0x0800 U2PHY_COM
> > +u3 port0 0x0900 U3PHYD
> > + 0x0a00 U3PHYD_BANK2
> > + 0x0b00 U3PHYA
> > + 0x0c00 U3PHYA_DA
> > +u2 port1 0x1000 U2PHY_COM
> > +u3 port1 0x1100 U3PHYD
> > + 0x1200 U3PHYD_BANK2
> > + 0x1300 U3PHYA
> > + 0x1400 U3PHYA_DA
> > +u2 port2 0x1800 U2PHY_COM
> > + ...
> > +
> > +mt2712:
> > +port offset bank
> > +u2 port0 0x0000 MISC
> > + 0x0100 FMREG
> > + 0x0300 U2PHY_COM
> > +u3 port0 0x0700 SPLLC
> > + 0x0800 CHIP
> > + 0x0900 U3PHYD
> > + 0x0a00 U3PHYD_BANK2
> > + 0x0b00 U3PHYA
> > + 0x0c00 U3PHYA_DA
> > +u2 port1 0x1000 MISC
> > + 0x1100 FMREG
> > + 0x1300 U2PHY_COM
> > +u3 port1 0x1700 SPLLC
> > + 0x1800 CHIP
> > + 0x1900 U3PHYD
> > + 0x1a00 U3PHYD_BANK2
> > + 0x1b00 U3PHYA
> > + 0x1c00 U3PHYA_DA
> > +u2 port2 0x2000 MISC
> > + ...
> > +
> > + SPLLC shared by u3 ports and FMREG shared by u2 ports on
> > +mt8173/mt2701 are put back into each port; a new bank MISC for
> > +u2 ports and CHIP for u3 ports are added on mt2712.
> > --
> > 1.7.9.5
> >
^ permalink raw reply
* [PATCH] [media] mtk-vcodec: fix build errors without DEBUG
From: Minghsiu Tsai @ 2017-02-07 7:40 UTC (permalink / raw)
To: Hans Verkuil, daniel.thompson-QSEj5FYQhm4dnm+yROfE0A, Rob Herring,
Mauro Carvalho Chehab, Matthias Brugger, Daniel Kurtz,
Pawel Osciak
Cc: srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Eddie Huang, Yingjoe Chen,
Tiffany Lin, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-media-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Minghsiu Tsai
Fix build errors after removing DEBUG definition.
Signed-off-by: Minghsiu Tsai <minghsiu.tsai-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c | 9 ++++-----
drivers/media/platform/mtk-vcodec/vdec_vpu_if.c | 5 ++---
drivers/media/platform/mtk-vcodec/venc_vpu_if.c | 4 +---
3 files changed, 7 insertions(+), 11 deletions(-)
diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c
index 0746592..6219c7d 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c
@@ -1126,15 +1126,14 @@ static void vb2ops_vdec_buf_queue(struct vb2_buffer *vb)
* if there is no SPS header or picture info
* in bs
*/
- int log_level = ret ? 0 : 1;
src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
v4l2_m2m_buf_done(to_vb2_v4l2_buffer(src_buf),
VB2_BUF_STATE_DONE);
- mtk_v4l2_debug(log_level,
- "[%d] vdec_if_decode() src_buf=%d, size=%zu, fail=%d, res_chg=%d",
- ctx->id, src_buf->index,
- src_mem.size, ret, res_chg);
+ mtk_v4l2_debug(ret ? 0 : 1,
+ "[%d] vdec_if_decode() src_buf=%d, size=%zu, fail=%d, res_chg=%d",
+ ctx->id, src_buf->index,
+ src_mem.size, ret, res_chg);
return;
}
diff --git a/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c b/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c
index 5a24c51..1abd14e 100644
--- a/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c
+++ b/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c
@@ -70,9 +70,8 @@ void vpu_dec_ipi_handler(void *data, unsigned int len, void *priv)
static int vcodec_vpu_send_msg(struct vdec_vpu_inst *vpu, void *msg, int len)
{
int err;
- uint32_t msg_id = *(uint32_t *)msg;
- mtk_vcodec_debug(vpu, "id=%X", msg_id);
+ mtk_vcodec_debug(vpu, "id=%X", *(uint32_t *)msg);
vpu->failure = 0;
vpu->signaled = 0;
@@ -80,7 +79,7 @@ static int vcodec_vpu_send_msg(struct vdec_vpu_inst *vpu, void *msg, int len)
err = vpu_ipi_send(vpu->dev, vpu->id, msg, len);
if (err) {
mtk_vcodec_err(vpu, "send fail vpu_id=%d msg_id=%X status=%d",
- vpu->id, msg_id, err);
+ vpu->id, *(uint32_t *)msg, err);
return err;
}
diff --git a/drivers/media/platform/mtk-vcodec/venc_vpu_if.c b/drivers/media/platform/mtk-vcodec/venc_vpu_if.c
index a01c759..0d882ac 100644
--- a/drivers/media/platform/mtk-vcodec/venc_vpu_if.c
+++ b/drivers/media/platform/mtk-vcodec/venc_vpu_if.c
@@ -79,10 +79,8 @@ static int vpu_enc_send_msg(struct venc_vpu_inst *vpu, void *msg,
status = vpu_ipi_send(vpu->dev, vpu->id, msg, len);
if (status) {
- uint32_t msg_id = *(uint32_t *)msg;
-
mtk_vcodec_err(vpu, "vpu_ipi_send msg_id %x len %d fail %d",
- msg_id, len, status);
+ *(uint32_t *)msg, len, status);
return -EINVAL;
}
if (vpu->failure)
--
1.9.1
--
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^ permalink raw reply related
* Re: [PATCH] [media] mtk-vcodec: fix build errors without DEBUG
From: Daniel Kurtz @ 2017-02-07 12:17 UTC (permalink / raw)
To: Minghsiu Tsai
Cc: Hans Verkuil, Daniel Thompson, Rob Herring, Mauro Carvalho Chehab,
Matthias Brugger, Pawel Osciak, srv_heupstream, Eddie Huang,
Yingjoe Chen, Tiffany Lin, open list:OPEN FIRMWARE AND...,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-media-u79uwXL29TY76Z2rM5mHXA,
moderated list:ARM/Mediatek SoC support
In-Reply-To: <1486453244-26094-1-git-send-email-minghsiu.tsai-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
On Tue, Feb 7, 2017 at 3:40 PM, Minghsiu Tsai
<minghsiu.tsai-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
> Fix build errors after removing DEBUG definition.
It would be useful to specify which build errors were fixed by this
patch, and a brief description of why - namely because when DEBUG is
not defined, mtk_v4l2_debug() is an empty macros, and therefore the
arguments are unused.
With an updated commit message, this patch is:
Reviewed-by: Daniel Kurtz <djkurtz-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
>
> Signed-off-by: Minghsiu Tsai <minghsiu.tsai-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
> drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c | 9 ++++-----
> drivers/media/platform/mtk-vcodec/vdec_vpu_if.c | 5 ++---
> drivers/media/platform/mtk-vcodec/venc_vpu_if.c | 4 +---
> 3 files changed, 7 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c
> index 0746592..6219c7d 100644
> --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c
> +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c
> @@ -1126,15 +1126,14 @@ static void vb2ops_vdec_buf_queue(struct vb2_buffer *vb)
> * if there is no SPS header or picture info
> * in bs
> */
> - int log_level = ret ? 0 : 1;
>
> src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
> v4l2_m2m_buf_done(to_vb2_v4l2_buffer(src_buf),
> VB2_BUF_STATE_DONE);
> - mtk_v4l2_debug(log_level,
> - "[%d] vdec_if_decode() src_buf=%d, size=%zu, fail=%d, res_chg=%d",
> - ctx->id, src_buf->index,
> - src_mem.size, ret, res_chg);
> + mtk_v4l2_debug(ret ? 0 : 1,
> + "[%d] vdec_if_decode() src_buf=%d, size=%zu, fail=%d, res_chg=%d",
> + ctx->id, src_buf->index,
> + src_mem.size, ret, res_chg);
> return;
> }
>
> diff --git a/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c b/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c
> index 5a24c51..1abd14e 100644
> --- a/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c
> +++ b/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c
> @@ -70,9 +70,8 @@ void vpu_dec_ipi_handler(void *data, unsigned int len, void *priv)
> static int vcodec_vpu_send_msg(struct vdec_vpu_inst *vpu, void *msg, int len)
> {
> int err;
> - uint32_t msg_id = *(uint32_t *)msg;
>
> - mtk_vcodec_debug(vpu, "id=%X", msg_id);
> + mtk_vcodec_debug(vpu, "id=%X", *(uint32_t *)msg);
>
> vpu->failure = 0;
> vpu->signaled = 0;
> @@ -80,7 +79,7 @@ static int vcodec_vpu_send_msg(struct vdec_vpu_inst *vpu, void *msg, int len)
> err = vpu_ipi_send(vpu->dev, vpu->id, msg, len);
> if (err) {
> mtk_vcodec_err(vpu, "send fail vpu_id=%d msg_id=%X status=%d",
> - vpu->id, msg_id, err);
> + vpu->id, *(uint32_t *)msg, err);
> return err;
> }
>
> diff --git a/drivers/media/platform/mtk-vcodec/venc_vpu_if.c b/drivers/media/platform/mtk-vcodec/venc_vpu_if.c
> index a01c759..0d882ac 100644
> --- a/drivers/media/platform/mtk-vcodec/venc_vpu_if.c
> +++ b/drivers/media/platform/mtk-vcodec/venc_vpu_if.c
> @@ -79,10 +79,8 @@ static int vpu_enc_send_msg(struct venc_vpu_inst *vpu, void *msg,
>
> status = vpu_ipi_send(vpu->dev, vpu->id, msg, len);
> if (status) {
> - uint32_t msg_id = *(uint32_t *)msg;
> -
> mtk_vcodec_err(vpu, "vpu_ipi_send msg_id %x len %d fail %d",
> - msg_id, len, status);
> + *(uint32_t *)msg, len, status);
> return -EINVAL;
> }
> if (vpu->failure)
> --
> 1.9.1
>
--
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^ permalink raw reply
* [PATCH -next] [media] mtk-vcodec: remove redundant return value check of platform_get_resource()
From: Wei Yongjun @ 2017-02-07 15:16 UTC (permalink / raw)
To: Tiffany Lin, Andrew-CT Chen, Mauro Carvalho Chehab,
Matthias Brugger
Cc: Wei Yongjun, linux-media, linux-arm-kernel, linux-mediatek
From: Wei Yongjun <weiyongjun1@huawei.com>
Remove unneeded error handling on the result of a call
to platform_get_resource() when the value is passed to
devm_ioremap_resource().
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
---
drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c
index aa81f3c..83f859e 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c
@@ -269,11 +269,6 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
for (i = VENC_SYS, j = 0; i < NUM_MAX_VCODEC_REG_BASE; i++, j++) {
res = platform_get_resource(pdev, IORESOURCE_MEM, j);
- if (res == NULL) {
- dev_err(&pdev->dev, "get memory resource failed.");
- ret = -ENXIO;
- goto err_res;
- }
dev->reg_base[i] = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR((__force void *)dev->reg_base[i])) {
ret = PTR_ERR((__force void *)dev->reg_base[i]);
^ permalink raw reply related
* Re: [PATCH] [media] mtk-vcodec: fix build errors without DEBUG
From: Minghsiu Tsai @ 2017-02-08 1:38 UTC (permalink / raw)
To: Daniel Kurtz
Cc: Hans Verkuil, Daniel Thompson, Rob Herring, Mauro Carvalho Chehab,
Matthias Brugger, Pawel Osciak, srv_heupstream, Eddie Huang,
Yingjoe Chen, Tiffany Lin, open list:OPEN FIRMWARE AND...,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-media-u79uwXL29TY76Z2rM5mHXA,
moderated list:ARM/Mediatek SoC support
In-Reply-To: <CAGS+omAU7UohsUkXwwHyhNh_dSX=R9tLKYvSV5767m81sTf_RA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Tue, 2017-02-07 at 20:17 +0800, Daniel Kurtz wrote:
> On Tue, Feb 7, 2017 at 3:40 PM, Minghsiu Tsai
> <minghsiu.tsai-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
> > Fix build errors after removing DEBUG definition.
>
> It would be useful to specify which build errors were fixed by this
> patch, and a brief description of why - namely because when DEBUG is
> not defined, mtk_v4l2_debug() is an empty macros, and therefore the
> arguments are unused.
>
> With an updated commit message, this patch is:
>
> Reviewed-by: Daniel Kurtz <djkurtz-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
>
Hi Daniel,
Thanks for your review and comment. I will update it soon.
> >
> > Signed-off-by: Minghsiu Tsai <minghsiu.tsai-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > ---
> > drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c | 9 ++++-----
> > drivers/media/platform/mtk-vcodec/vdec_vpu_if.c | 5 ++---
> > drivers/media/platform/mtk-vcodec/venc_vpu_if.c | 4 +---
> > 3 files changed, 7 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c
> > index 0746592..6219c7d 100644
> > --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c
> > +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c
> > @@ -1126,15 +1126,14 @@ static void vb2ops_vdec_buf_queue(struct vb2_buffer *vb)
> > * if there is no SPS header or picture info
> > * in bs
> > */
> > - int log_level = ret ? 0 : 1;
> >
> > src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
> > v4l2_m2m_buf_done(to_vb2_v4l2_buffer(src_buf),
> > VB2_BUF_STATE_DONE);
> > - mtk_v4l2_debug(log_level,
> > - "[%d] vdec_if_decode() src_buf=%d, size=%zu, fail=%d, res_chg=%d",
> > - ctx->id, src_buf->index,
> > - src_mem.size, ret, res_chg);
> > + mtk_v4l2_debug(ret ? 0 : 1,
> > + "[%d] vdec_if_decode() src_buf=%d, size=%zu, fail=%d, res_chg=%d",
> > + ctx->id, src_buf->index,
> > + src_mem.size, ret, res_chg);
> > return;
> > }
> >
> > diff --git a/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c b/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c
> > index 5a24c51..1abd14e 100644
> > --- a/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c
> > +++ b/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c
> > @@ -70,9 +70,8 @@ void vpu_dec_ipi_handler(void *data, unsigned int len, void *priv)
> > static int vcodec_vpu_send_msg(struct vdec_vpu_inst *vpu, void *msg, int len)
> > {
> > int err;
> > - uint32_t msg_id = *(uint32_t *)msg;
> >
> > - mtk_vcodec_debug(vpu, "id=%X", msg_id);
> > + mtk_vcodec_debug(vpu, "id=%X", *(uint32_t *)msg);
> >
> > vpu->failure = 0;
> > vpu->signaled = 0;
> > @@ -80,7 +79,7 @@ static int vcodec_vpu_send_msg(struct vdec_vpu_inst *vpu, void *msg, int len)
> > err = vpu_ipi_send(vpu->dev, vpu->id, msg, len);
> > if (err) {
> > mtk_vcodec_err(vpu, "send fail vpu_id=%d msg_id=%X status=%d",
> > - vpu->id, msg_id, err);
> > + vpu->id, *(uint32_t *)msg, err);
> > return err;
> > }
> >
> > diff --git a/drivers/media/platform/mtk-vcodec/venc_vpu_if.c b/drivers/media/platform/mtk-vcodec/venc_vpu_if.c
> > index a01c759..0d882ac 100644
> > --- a/drivers/media/platform/mtk-vcodec/venc_vpu_if.c
> > +++ b/drivers/media/platform/mtk-vcodec/venc_vpu_if.c
> > @@ -79,10 +79,8 @@ static int vpu_enc_send_msg(struct venc_vpu_inst *vpu, void *msg,
> >
> > status = vpu_ipi_send(vpu->dev, vpu->id, msg, len);
> > if (status) {
> > - uint32_t msg_id = *(uint32_t *)msg;
> > -
> > mtk_vcodec_err(vpu, "vpu_ipi_send msg_id %x len %d fail %d",
> > - msg_id, len, status);
> > + *(uint32_t *)msg, len, status);
> > return -EINVAL;
> > }
> > if (vpu->failure)
> > --
> > 1.9.1
> >
--
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^ permalink raw reply
* [PATCH v2] [media] mtk-vcodec: fix build errors without DEBUG
From: Minghsiu Tsai @ 2017-02-08 2:09 UTC (permalink / raw)
To: Hans Verkuil, daniel.thompson-QSEj5FYQhm4dnm+yROfE0A, Rob Herring,
Mauro Carvalho Chehab, Matthias Brugger, Daniel Kurtz,
Pawel Osciak
Cc: srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Eddie Huang, Yingjoe Chen,
Tiffany Lin, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-media-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Minghsiu Tsai
After removing DEBUG from mtk_vcodec_util.h, some build errors are
generated as the following:
.../drivers/media/platform/mtk-vcodec/vdec_vpu_if.c: In function 'vcodec_vpu_send_msg':
.../drivers/media/platform/mtk-vcodec/vdec_vpu_if.c:73:11: warning: unused variable 'msg_id' [-Wunused-variable]
uint32_t msg_id = *(uint32_t *)msg;
^
.../drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c: In function 'vb2ops_vdec_buf_queue':
.../drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c:1129:7: warning: unused variable 'log_level' [-Wunused-variable]
int log_level = ret ? 0 : 1;
^
.../drivers/media/platform/mtk-vcodec/venc_vpu_if.c: In function 'vpu_enc_send_msg':
.../drivers/media/platform/mtk-vcodec/venc_vpu_if.c:82:12: warning: unused variable 'msg_id' [-Wunused-variable]
uint32_t msg_id = *(uint32_t *)msg;
^
It is because mtk_vcodec_debug() and mtk_vcodec_err() are defined as empty
macros. Without DEBUG definition, the variable for debugging is not used
anymore. Fixing build errors is just by moving the assignment of the
variable to the argument of mtk_vcodec_debug() and mtk_vcodec_err().
Within the patch, build pass with/without DEBUG definition, and functions
still work fine.
Signed-off-by: Minghsiu Tsai <minghsiu.tsai-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Reviewed-by: Daniel Kurtz <djkurtz-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---
Changes in v2:
. Update commit message
---
drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c | 9 ++++-----
drivers/media/platform/mtk-vcodec/vdec_vpu_if.c | 5 ++---
drivers/media/platform/mtk-vcodec/venc_vpu_if.c | 4 +---
3 files changed, 7 insertions(+), 11 deletions(-)
diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c
index 0746592..6219c7d 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c
@@ -1126,15 +1126,14 @@ static void vb2ops_vdec_buf_queue(struct vb2_buffer *vb)
* if there is no SPS header or picture info
* in bs
*/
- int log_level = ret ? 0 : 1;
src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
v4l2_m2m_buf_done(to_vb2_v4l2_buffer(src_buf),
VB2_BUF_STATE_DONE);
- mtk_v4l2_debug(log_level,
- "[%d] vdec_if_decode() src_buf=%d, size=%zu, fail=%d, res_chg=%d",
- ctx->id, src_buf->index,
- src_mem.size, ret, res_chg);
+ mtk_v4l2_debug(ret ? 0 : 1,
+ "[%d] vdec_if_decode() src_buf=%d, size=%zu, fail=%d, res_chg=%d",
+ ctx->id, src_buf->index,
+ src_mem.size, ret, res_chg);
return;
}
diff --git a/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c b/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c
index 5a24c51..1abd14e 100644
--- a/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c
+++ b/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c
@@ -70,9 +70,8 @@ void vpu_dec_ipi_handler(void *data, unsigned int len, void *priv)
static int vcodec_vpu_send_msg(struct vdec_vpu_inst *vpu, void *msg, int len)
{
int err;
- uint32_t msg_id = *(uint32_t *)msg;
- mtk_vcodec_debug(vpu, "id=%X", msg_id);
+ mtk_vcodec_debug(vpu, "id=%X", *(uint32_t *)msg);
vpu->failure = 0;
vpu->signaled = 0;
@@ -80,7 +79,7 @@ static int vcodec_vpu_send_msg(struct vdec_vpu_inst *vpu, void *msg, int len)
err = vpu_ipi_send(vpu->dev, vpu->id, msg, len);
if (err) {
mtk_vcodec_err(vpu, "send fail vpu_id=%d msg_id=%X status=%d",
- vpu->id, msg_id, err);
+ vpu->id, *(uint32_t *)msg, err);
return err;
}
diff --git a/drivers/media/platform/mtk-vcodec/venc_vpu_if.c b/drivers/media/platform/mtk-vcodec/venc_vpu_if.c
index a01c759..0d882ac 100644
--- a/drivers/media/platform/mtk-vcodec/venc_vpu_if.c
+++ b/drivers/media/platform/mtk-vcodec/venc_vpu_if.c
@@ -79,10 +79,8 @@ static int vpu_enc_send_msg(struct venc_vpu_inst *vpu, void *msg,
status = vpu_ipi_send(vpu->dev, vpu->id, msg, len);
if (status) {
- uint32_t msg_id = *(uint32_t *)msg;
-
mtk_vcodec_err(vpu, "vpu_ipi_send msg_id %x len %d fail %d",
- msg_id, len, status);
+ *(uint32_t *)msg, len, status);
return -EINVAL;
}
if (vpu->failure)
--
1.9.1
--
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^ permalink raw reply related
* [PATCH v2 0/4] leds: add leds-mt6323 support on MT7623 SoC
From: sean.wang @ 2017-02-08 2:19 UTC (permalink / raw)
To: rpurdie, jacek.anaszewski, lee.jones, matthias.bgg, pavel,
robh+dt, mark.rutland
Cc: devicetree, keyhaede, Sean Wang, linux-kernel, linux-mediatek,
linux-leds, linux-arm-kernel
From: Sean Wang <sean.wang@mediatek.com>
MT7623 SoC uses MT6323 PMIC as the default power supply
which has LED function insides. The patchset introduces
the LED support for MT6323 with on, off and hardware
dimmed and blinked and it should work on other similar
SoCs if also using MT6323.
Changes since v1:
All changes only within 0003-leds-Add-LED-support-for-MT6323-PMIC.patch,
including below items
- fixed typo in the comments
- sorted include directives alphabetically
- applied all register definitions with MT6323 prefix
- removed the redundant structure declaration
- fixed coding style defined in kernel doc format consistently
- added error handling into all the occurrences where regmap APIs
are used
- removed loudly debug message
- made magic constant into meaningful macro
- added missing mutex_destroy when module removed called
- updated module license with GPL
- fixed sparse warnings
Sean Wang (4):
Documentation: devicetree: Add document bindings for leds-mt6323
Documentation: devicetree: Add LED subnode binding for MT6323 PMIC
leds: Add LED support for MT6323 PMIC
mfd: mt6397: Add MT6323 LED support into MT6397 driver
.../devicetree/bindings/leds/leds-mt6323.txt | 60 +++
Documentation/devicetree/bindings/mfd/mt6397.txt | 4 +
drivers/leds/Kconfig | 8 +
drivers/leds/Makefile | 1 +
drivers/leds/leds-mt6323.c | 464 +++++++++++++++++++++
drivers/mfd/mt6397-core.c | 4 +
6 files changed, 541 insertions(+)
create mode 100644 Documentation/devicetree/bindings/leds/leds-mt6323.txt
create mode 100644 drivers/leds/leds-mt6323.c
--
1.9.1
^ permalink raw reply
* [PATCH v2 1/4] Documentation: devicetree: Add document bindings for leds-mt6323
From: sean.wang @ 2017-02-08 2:19 UTC (permalink / raw)
To: rpurdie, jacek.anaszewski, lee.jones, matthias.bgg, pavel,
robh+dt, mark.rutland
Cc: devicetree, keyhaede, Sean Wang, linux-kernel, linux-mediatek,
linux-leds, linux-arm-kernel
In-Reply-To: <1486520357-13096-1-git-send-email-sean.wang@mediatek.com>
From: Sean Wang <sean.wang@mediatek.com>
This patch adds documentation for devicetree bindings
for LED support on MT6323 PMIC
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/leds/leds-mt6323.txt | 60 ++++++++++++++++++++++
1 file changed, 60 insertions(+)
create mode 100644 Documentation/devicetree/bindings/leds/leds-mt6323.txt
diff --git a/Documentation/devicetree/bindings/leds/leds-mt6323.txt b/Documentation/devicetree/bindings/leds/leds-mt6323.txt
new file mode 100644
index 0000000..82bbf0c
--- /dev/null
+++ b/Documentation/devicetree/bindings/leds/leds-mt6323.txt
@@ -0,0 +1,60 @@
+Device Tree Bindings for LED support on MT6323 PMIC
+
+MT6323 LED controller is subfunction provided by
+MT6323 PMIC, so the LED controller are defined as
+the subnode of the function node provided by MT6323
+PMIC controller that is being defined as one kind of
+Muti-Function Device (MFD) using shared bus called
+PMIC wrapper for each subfunction to access remote
+MT6323 PMIC hardware.
+
+For MT6323 MFD bindings see:
+Documentation/devicetree/bindings/mfd/mt6397.txt
+For MediaTek PMIC wrapper bindings see:
+Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
+
+There's sub-node for the LED controller that describes
+the initial behavior for each LED physcially and currently
+only four LED sub-nodes could be supported.
+
+Required properties:
+- compatible : must be "mediatek,mt6323-led"
+
+Optional properties:
+- label : (optional)
+ see Documentation/devicetree/bindings/leds/common.txt
+- linux,default-trigger : (optional)
+ see Documentation/devicetree/bindings/leds/common.txt
+- default-state: (optional) The initial state of the LED
+ see Documentation/devicetree/bindings/leds/common.txt
+
+Example:
+
+&pwrap {
+ pmic: mt6323 {
+ compatible = "mediatek,mt6323";
+ interrupt-parent = <&pio>;
+ interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ mt6323led: mt6323led{
+ compatible = "mediatek,mt6323-led";
+
+ led0: isink0 {
+ lebel = "LED0"
+ linux,default-trigger = "timer";
+ default-state = "on";
+ };
+ led1: isink1 {
+ label = "LED1";
+ default-state = "on";
+ };
+ led2: isink2 {
+ label = "LED2";
+ linux,default-trigger = "timer";
+ default-state = "off";
+ };
+ };
+ };
+};
--
1.9.1
^ permalink raw reply related
* [PATCH v2 2/4] Documentation: devicetree: Add LED subnode binding for MT6323 PMIC
From: sean.wang-NuS5LvNUpcJWk0Htik3J/w @ 2017-02-08 2:19 UTC (permalink / raw)
To: rpurdie-Fm38FmjxZ/leoWH0uzbU5w,
jacek.anaszewski-Re5JQEeQqe8AvxtiuMwx3w,
lee.jones-QSEj5FYQhm4dnm+yROfE0A,
matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w, pavel-+ZI9xUNit7I,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
keyhaede-Re5JQEeQqe8AvxtiuMwx3w, Sean Wang,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-leds-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1486520357-13096-1-git-send-email-sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
From: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
This patch adds documentation for devicetree bindings
for LED support as the subnode of MT6323 PMIC
Signed-off-by: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
Documentation/devicetree/bindings/mfd/mt6397.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt
index 949c85f..c568d52 100644
--- a/Documentation/devicetree/bindings/mfd/mt6397.txt
+++ b/Documentation/devicetree/bindings/mfd/mt6397.txt
@@ -34,6 +34,10 @@ Optional subnodes:
- clk
Required properties:
- compatible: "mediatek,mt6397-clk"
+- led
+ Required properties:
+ - compatible: "mediatek,mt6323-led"
+ see Documentation/devicetree/bindings/leds/leds-mt6323.txt
Example:
pwrap: pwrap@1000f000 {
--
1.9.1
^ permalink raw reply related
* [PATCH v2 3/4] leds: Add LED support for MT6323 PMIC
From: sean.wang @ 2017-02-08 2:19 UTC (permalink / raw)
To: rpurdie, jacek.anaszewski, lee.jones, matthias.bgg, pavel,
robh+dt, mark.rutland
Cc: devicetree, keyhaede, Sean Wang, linux-kernel, linux-mediatek,
linux-leds, linux-arm-kernel
In-Reply-To: <1486520357-13096-1-git-send-email-sean.wang@mediatek.com>
From: Sean Wang <sean.wang@mediatek.com>
MT6323 PMIC is a multi-function device that includes
LED function. It allows attaching upto 4 LEDs which can
either be on, off or dimmed and/or blinked with the the
controller.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
drivers/leds/Kconfig | 8 +
drivers/leds/Makefile | 1 +
drivers/leds/leds-mt6323.c | 464 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 473 insertions(+)
create mode 100644 drivers/leds/leds-mt6323.c
diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index c621cbb..30095fc 100644
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -117,6 +117,14 @@ config LEDS_MIKROTIK_RB532
This option enables support for the so called "User LED" of
Mikrotik's Routerboard 532.
+config LEDS_MT6323
+ tristate "LED Support for Mediatek MT6323 PMIC"
+ depends on LEDS_CLASS
+ depends on MFD_MT6397
+ help
+ This option enables support for on-chip LED drivers found on
+ Mediatek MT6323 PMIC.
+
config LEDS_S3C24XX
tristate "LED Support for Samsung S3C24XX GPIO LEDs"
depends on LEDS_CLASS
diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
index 6b82737..4feb332 100644
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -72,6 +72,7 @@ obj-$(CONFIG_LEDS_IS31FL32XX) += leds-is31fl32xx.o
obj-$(CONFIG_LEDS_PM8058) += leds-pm8058.o
obj-$(CONFIG_LEDS_MLXCPLD) += leds-mlxcpld.o
obj-$(CONFIG_LEDS_NIC78BX) += leds-nic78bx.o
+obj-$(CONFIG_LEDS_MT6323) += leds-mt6323.o
# LED SPI Drivers
obj-$(CONFIG_LEDS_DAC124S085) += leds-dac124s085.o
diff --git a/drivers/leds/leds-mt6323.c b/drivers/leds/leds-mt6323.c
new file mode 100644
index 0000000..f6eeb6c
--- /dev/null
+++ b/drivers/leds/leds-mt6323.c
@@ -0,0 +1,464 @@
+/*
+ * LED driver for Mediatek MT6323 PMIC
+ *
+ * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/leds.h>
+#include <linux/mfd/mt6323/registers.h>
+#include <linux/mfd/mt6397/core.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+/*
+ * Register field for MT6323_TOP_CKPDN0 to enable
+ * 32K clock common for LED device
+ */
+#define MT6323_RG_DRV_32K_CK_PDN BIT(11)
+#define MT6323_RG_DRV_32K_CK_PDN_MASK BIT(11)
+
+/*
+ * Register field for MT6323_TOP_CKPDN2 to enable
+ * individual clock for LED device
+ */
+#define MT6323_RG_ISINK_CK_PDN(i) BIT(i)
+#define MT6323_RG_ISINK_CK_PDN_MASK(i) BIT(i)
+
+/*
+ * Register field for MT6323_TOP_CKCON1 to select
+ * clock source
+ */
+#define MT6323_RG_ISINK_CK_SEL_MASK(i) (BIT(10) << (i))
+
+/*
+ * Register for MT6323_ISINK_CON0 to setup the
+ * duty cycle of the blink
+ */
+#define MT6323_ISINK_CON0(i) (MT6323_ISINK0_CON0 + 0x8 * (i))
+#define MT6323_ISINK_DIM_DUTY_MASK (0x1f << 8)
+#define MT6323_ISINK_DIM_DUTY(i) (((i) << 8) & \
+ MT6323_ISINK_DIM_DUTY_MASK)
+
+/*
+ * Register to setup the period of the blink
+ */
+#define MT6323_ISINK_CON1(i) (MT6323_ISINK0_CON1 + 0x8 * (i))
+#define MT6323_ISINK_DIM_FSEL_MASK (0xffff)
+#define MT6323_ISINK_DIM_FSEL(i) ((i) & MT6323_ISINK_DIM_FSEL_MASK)
+
+/*
+ * Register to control the brightness
+ */
+#define MT6323_ISINK_CON2(i) (MT6323_ISINK0_CON2 + 0x8 * (i))
+#define MT6323_ISINK_CH_STEP_SHIFT 12
+#define MT6323_ISINK_CH_STEP_MASK (0x7 << 12)
+#define MT6323_ISINK_CH_STEP(i) (((i) << 12) & \
+ MT6323_ISINK_CH_STEP_MASK)
+#define MT6323_ISINK_SFSTR0_TC_MASK (0x3 << 1)
+#define MT6323_ISINK_SFSTR0_TC(i) (((i) << 1) & \
+ MT6323_ISINK_SFSTR0_TC_MASK)
+#define MT6323_ISINK_SFSTR0_EN_MASK BIT(0)
+#define MT6323_ISINK_SFSTR0_EN BIT(0)
+
+/*
+ * Register to LED channel enablement
+ */
+#define MT6323_ISINK_CH_EN_MASK(i) BIT(i)
+#define MT6323_ISINK_CH_EN(i) BIT(i)
+
+#define MTK_MAX_PERIOD 10000
+#define MTK_MAX_DEVICES 4
+#define MTK_MAX_BRIGHTNESS 6
+#define MTK_UNIT_DUTY 3125
+
+struct mtk_leds;
+
+/**
+ * struct mtk_led - state container for the LED device
+ * @id: the identifier in MT6323 LED device
+ * @parent: the pointer to MT6323 LED controller
+ * @cdev: LED class device for this LED device
+ * @current_brightness: current state of the LED device
+ */
+struct mtk_led {
+ int id;
+ struct mtk_leds *parent;
+ struct led_classdev cdev;
+ u8 current_brightness;
+};
+
+/**
+ * struct mtk_leds - state container for holding LED controller
+ * of the driver
+ * @dev: The device pointer
+ * @hw: The underlying hardware providing shared
+ * bus for the register operations
+ * @led_num: How much the LED device the controller could control
+ * @lock: The lock among process context
+ * @led: The array that contains the state of individual
+ * LED device
+ */
+struct mtk_leds {
+ struct device *dev;
+ struct mt6397_chip *hw;
+ u8 led_num;
+ /* protect among process context */
+ struct mutex lock;
+ struct mtk_led led[MTK_MAX_DEVICES];
+};
+
+static int mtk_led_hw_off(struct led_classdev *cdev)
+{
+ struct mtk_led *led = container_of(cdev, struct mtk_led, cdev);
+ struct mtk_leds *leds = led->parent;
+ struct regmap *regmap = leds->hw->regmap;
+ unsigned int status;
+ int ret;
+
+ status = MT6323_ISINK_CH_EN(led->id);
+ ret = regmap_update_bits(regmap, MT6323_ISINK_EN_CTRL,
+ MT6323_ISINK_CH_EN_MASK(led->id), ~status);
+ if (ret < 0)
+ return ret;
+
+ usleep_range(100, 300);
+ ret = regmap_update_bits(regmap, MT6323_TOP_CKPDN2,
+ MT6323_RG_ISINK_CK_PDN_MASK(led->id),
+ MT6323_RG_ISINK_CK_PDN(led->id));
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int get_mtk_led_hw_brightness(struct led_classdev *cdev)
+{
+ struct mtk_led *led = container_of(cdev, struct mtk_led, cdev);
+ struct mtk_leds *leds = led->parent;
+ struct regmap *regmap = leds->hw->regmap;
+ unsigned int status;
+ int ret;
+
+ ret = regmap_read(regmap, MT6323_TOP_CKPDN2, &status);
+ if (ret < 0)
+ return ret;
+
+ if (status & MT6323_RG_ISINK_CK_PDN_MASK(led->id))
+ return 0;
+
+ ret = regmap_read(regmap, MT6323_ISINK_EN_CTRL, &status);
+ if (ret < 0)
+ return ret;
+
+ if (!(status & MT6323_ISINK_CH_EN(led->id)))
+ return 0;
+
+ ret = regmap_read(regmap, MT6323_ISINK_CON2(led->id), &status);
+ if (ret < 0)
+ return ret;
+
+ return ((status & MT6323_ISINK_CH_STEP_MASK)
+ >> MT6323_ISINK_CH_STEP_SHIFT) + 1;
+}
+
+static int mtk_led_hw_on(struct led_classdev *cdev)
+{
+ struct mtk_led *led = container_of(cdev, struct mtk_led, cdev);
+ struct mtk_leds *leds = led->parent;
+ struct regmap *regmap = leds->hw->regmap;
+ unsigned int status;
+ int ret;
+
+ /*
+ * Setup required clock source, enable the corresponding
+ * clock and channel and let work with continuous blink as
+ * the default
+ */
+ ret = regmap_update_bits(regmap, MT6323_TOP_CKCON1,
+ MT6323_RG_ISINK_CK_SEL_MASK(led->id), 0);
+ if (ret < 0)
+ return ret;
+
+ status = MT6323_RG_ISINK_CK_PDN(led->id);
+ ret = regmap_update_bits(regmap, MT6323_TOP_CKPDN2,
+ MT6323_RG_ISINK_CK_PDN_MASK(led->id),
+ ~status);
+ if (ret < 0)
+ return ret;
+
+ usleep_range(100, 300);
+
+ ret = regmap_update_bits(regmap, MT6323_ISINK_EN_CTRL,
+ MT6323_ISINK_CH_EN_MASK(led->id),
+ MT6323_ISINK_CH_EN(led->id));
+ if (ret < 0)
+ return ret;
+
+ ret = regmap_update_bits(regmap, MT6323_ISINK_CON2(led->id),
+ MT6323_ISINK_CH_STEP_MASK,
+ MT6323_ISINK_CH_STEP(1));
+ if (ret < 0)
+ return ret;
+
+ ret = regmap_update_bits(regmap, MT6323_ISINK_CON0(led->id),
+ MT6323_ISINK_DIM_DUTY_MASK,
+ MT6323_ISINK_DIM_DUTY(31));
+ if (ret < 0)
+ return ret;
+
+ ret = regmap_update_bits(regmap, MT6323_ISINK_CON1(led->id),
+ MT6323_ISINK_DIM_FSEL_MASK,
+ MT6323_ISINK_DIM_FSEL(1000));
+ if (ret < 0)
+ return ret;
+
+ led->current_brightness = 1;
+
+ return 0;
+}
+
+static int mtk_led_set_blink(struct led_classdev *cdev,
+ unsigned long *delay_on,
+ unsigned long *delay_off)
+{
+ struct mtk_led *led = container_of(cdev, struct mtk_led, cdev);
+ struct mtk_leds *leds = led->parent;
+ struct regmap *regmap = leds->hw->regmap;
+ u16 period;
+ u8 duty_cycle, duty_hw;
+ int ret;
+
+ /*
+ * Units are in ms , if over the hardware able
+ * to support, fallback into software blink
+ */
+ if (*delay_on + *delay_off > MTK_MAX_PERIOD)
+ return -EINVAL;
+
+ /*
+ * LED subsystem requires a default user
+ * friendly blink pattern for the LED so using
+ * 1Hz duty cycle 50% here if without specific
+ * value delay_on and delay off being assigned
+ */
+ if (*delay_on == 0 && *delay_off == 0) {
+ *delay_on = 500;
+ *delay_off = 500;
+ }
+
+ period = *delay_on + *delay_off;
+
+ /*
+ * duty_cycle is the percentage of period during
+ * which the led is ON
+ */
+ duty_cycle = 100 * (*delay_on) / period;
+
+ mutex_lock(&leds->lock);
+
+ if (!led->current_brightness) {
+ ret = mtk_led_hw_on(cdev);
+ if (ret < 0)
+ goto out;
+ }
+
+ duty_hw = DIV_ROUND_CLOSEST(duty_cycle * 1000, MTK_UNIT_DUTY);
+ ret = regmap_update_bits(regmap, MT6323_ISINK_CON0(led->id),
+ MT6323_ISINK_DIM_DUTY_MASK,
+ MT6323_ISINK_DIM_DUTY(duty_hw));
+ if (ret < 0)
+ goto out;
+
+ ret = regmap_update_bits(regmap, MT6323_ISINK_CON1(led->id),
+ MT6323_ISINK_DIM_FSEL_MASK,
+ MT6323_ISINK_DIM_FSEL(period - 1));
+out:
+ mutex_unlock(&leds->lock);
+
+ return ret;
+}
+
+static int mtk_led_set_brightness(struct led_classdev *cdev,
+ enum led_brightness brightness)
+{
+ struct mtk_led *led = container_of(cdev, struct mtk_led, cdev);
+ struct mtk_leds *leds = led->parent;
+ struct regmap *regmap = leds->hw->regmap;
+ int ret;
+
+ mutex_lock(&leds->lock);
+
+ if (!led->current_brightness && brightness) {
+ ret = mtk_led_hw_on(cdev);
+ if (ret < 0)
+ goto out;
+ }
+
+ if (brightness) {
+ /*
+ * Setup current output for the corresponding
+ * brightness level
+ */
+ ret = regmap_update_bits(regmap, MT6323_ISINK_CON2(led->id),
+ MT6323_ISINK_CH_STEP_MASK,
+ MT6323_ISINK_CH_STEP(brightness - 1));
+ if (ret < 0)
+ goto out;
+
+ ret = regmap_update_bits(regmap, MT6323_ISINK_CON2(led->id),
+ MT6323_ISINK_SFSTR0_TC_MASK |
+ MT6323_ISINK_SFSTR0_EN_MASK,
+ MT6323_ISINK_SFSTR0_TC(2) |
+ MT6323_ISINK_SFSTR0_EN);
+ if (ret < 0)
+ goto out;
+ } else {
+ ret = mtk_led_hw_off(cdev);
+ if (ret < 0)
+ goto out;
+ }
+
+ led->current_brightness = brightness;
+out:
+ mutex_unlock(&leds->lock);
+
+ return ret;
+}
+
+static int mt6323_led_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *child;
+ struct mt6397_chip *hw = dev_get_drvdata(pdev->dev.parent);
+ struct mtk_leds *leds;
+ int ret, i = 0, count;
+ const char *state;
+ unsigned int status;
+
+ count = of_get_child_count(np);
+ if (!count)
+ return -ENODEV;
+
+ /*
+ * The number the LEDs on MT6323 could be support is
+ * up to MTK_MAX_DEVICES
+ */
+ count = (count <= MTK_MAX_DEVICES) ? count : MTK_MAX_DEVICES;
+
+ leds = devm_kzalloc(dev, sizeof(struct mtk_leds) +
+ sizeof(struct mtk_led) * count,
+ GFP_KERNEL);
+ if (!leds)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, leds);
+ leds->dev = dev;
+
+ /*
+ * leds->hw points to the underlying bus for the register
+ * controlled
+ */
+ leds->hw = hw;
+ mutex_init(&leds->lock);
+ leds->led_num = count;
+
+ status = MT6323_RG_DRV_32K_CK_PDN;
+ ret = regmap_update_bits(leds->hw->regmap, MT6323_TOP_CKPDN0,
+ MT6323_RG_DRV_32K_CK_PDN_MASK, ~status);
+ if (ret < 0) {
+ dev_err(leds->dev,
+ "Failed to update MT6323_TOP_CKPDN0 Register\n");
+ return ret;
+ }
+
+ for_each_available_child_of_node(np, child) {
+ leds->led[i].cdev.name =
+ of_get_property(child, "label", NULL) ? :
+ child->name;
+ leds->led[i].cdev.default_trigger = of_get_property(child,
+ "linux,default-trigger",
+ NULL);
+ leds->led[i].cdev.max_brightness = MTK_MAX_BRIGHTNESS;
+ leds->led[i].cdev.brightness_set_blocking =
+ mtk_led_set_brightness;
+ leds->led[i].cdev.blink_set = mtk_led_set_blink;
+ leds->led[i].id = i;
+ leds->led[i].parent = leds;
+ state = of_get_property(child, "default-state", NULL);
+ if (state) {
+ if (!strcmp(state, "keep")) {
+ leds->led[i].current_brightness =
+ get_mtk_led_hw_brightness(&leds->led[i].cdev);
+ } else if (!strcmp(state, "on")) {
+ mtk_led_set_brightness(&leds->led[i].cdev, 1);
+ } else {
+ mtk_led_set_brightness(&leds->led[i].cdev,
+ 0);
+ }
+ }
+ ret = devm_led_classdev_register(dev, &leds->led[i].cdev);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to register LED: %d\n",
+ ret);
+ return ret;
+ }
+ leds->led[i].cdev.dev->of_node = child;
+ i++;
+ }
+
+ return 0;
+}
+
+static int mt6323_led_remove(struct platform_device *pdev)
+{
+ struct mtk_leds *leds = platform_get_drvdata(pdev);
+ int i;
+
+ /*
+ * Turned the LED to OFF state on driver removal
+ */
+ for (i = 0 ; i < leds->led_num ; i++)
+ mtk_led_hw_off(&leds->led[i].cdev);
+
+ regmap_update_bits(leds->hw->regmap, MT6323_TOP_CKPDN0,
+ MT6323_RG_DRV_32K_CK_PDN_MASK,
+ MT6323_RG_DRV_32K_CK_PDN);
+
+ mutex_destroy(&leds->lock);
+
+ return 0;
+}
+
+static const struct of_device_id mt6323_led_dt_match[] = {
+ { .compatible = "mediatek,mt6323-led" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mt6323_led_dt_match);
+
+static struct platform_driver mt6323_led_driver = {
+ .probe = mt6323_led_probe,
+ .remove = mt6323_led_remove,
+ .driver = {
+ .name = "mt6323-led",
+ .of_match_table = mt6323_led_dt_match,
+ },
+};
+
+module_platform_driver(mt6323_led_driver);
+
+MODULE_DESCRIPTION("LED driver for Mediatek MT6323 PMIC");
+MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
+MODULE_LICENSE("GPL");
--
1.9.1
^ permalink raw reply related
* [PATCH v2 4/4] mfd: mt6397: Add MT6323 LED support into MT6397 driver
From: sean.wang @ 2017-02-08 2:19 UTC (permalink / raw)
To: rpurdie, jacek.anaszewski, lee.jones, matthias.bgg, pavel,
robh+dt, mark.rutland
Cc: devicetree, linux-leds, linux-mediatek, linux-arm-kernel,
linux-kernel, keyhaede, Sean Wang
In-Reply-To: <1486520357-13096-1-git-send-email-sean.wang@mediatek.com>
From: Sean Wang <sean.wang@mediatek.com>
Add compatible string as "mt6323-led" that will make
the OF core spawn child devices for the LED subnode
of that MT6323 MFD device.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
drivers/mfd/mt6397-core.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
index e14d8b0..8e601c8 100644
--- a/drivers/mfd/mt6397-core.c
+++ b/drivers/mfd/mt6397-core.c
@@ -48,6 +48,10 @@
.name = "mt6323-regulator",
.of_compatible = "mediatek,mt6323-regulator"
},
+ {
+ .name = "mt6323-led",
+ .of_compatible = "mediatek,mt6323-led"
+ },
};
static const struct mfd_cell mt6397_devs[] = {
--
1.9.1
^ permalink raw reply related
* Re: [PATCH v2 1/4] Documentation: devicetree: Add document bindings for leds-mt6323
From: Andrew Lunn @ 2017-02-08 2:47 UTC (permalink / raw)
To: sean.wang
Cc: rpurdie, jacek.anaszewski, lee.jones, matthias.bgg, pavel,
robh+dt, mark.rutland, devicetree, keyhaede, linux-kernel,
linux-mediatek, linux-leds, linux-arm-kernel
In-Reply-To: <1486520357-13096-2-git-send-email-sean.wang@mediatek.com>
> + led0: isink0 {
> + lebel = "LED0"
label, not lebel.
Andrew
^ permalink raw reply
* [PATCH] thermal: mt8173: minor mtk_thermal.c cleanups
From: Dawei Chien @ 2017-02-08 5:31 UTC (permalink / raw)
To: Zhang Rui, Eduardo Valentin
Cc: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Russell King, Matthias Brugger, linux-pm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Sascha Hauer, Fan Chen,
Eddie Huang, Yingjoe Chen, Erin Lo, Dawei Chien
Thermal driver should read TEMP_MSR3 if thermal bank with 4 sensors.
However, Currently thermal driver don't need read TEMP_MSR3 since
thermal controller only use 3 sensors for each thermal bank.
Signed-off-by: Dawei Chien <dawei.chien-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/thermal/mtk_thermal.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c
index 34169c3..c124151 100644
--- a/drivers/thermal/mtk_thermal.c
+++ b/drivers/thermal/mtk_thermal.c
@@ -191,7 +191,7 @@ struct mtk_thermal {
};
const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
- TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR2
+ TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
};
const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* Re: [PATCH v2 4/4] mfd: mt6397: Add MT6323 LED support into MT6397 driver
From: Lee Jones @ 2017-02-08 12:21 UTC (permalink / raw)
To: sean.wang
Cc: rpurdie, jacek.anaszewski, matthias.bgg, pavel, robh+dt,
mark.rutland, devicetree, linux-leds, linux-mediatek,
linux-arm-kernel, linux-kernel, keyhaede
In-Reply-To: <1486520357-13096-5-git-send-email-sean.wang@mediatek.com>
On Wed, 08 Feb 2017, sean.wang@mediatek.com wrote:
> From: Sean Wang <sean.wang@mediatek.com>
>
> Add compatible string as "mt6323-led" that will make
> the OF core spawn child devices for the LED subnode
> of that MT6323 MFD device.
>
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> ---
> drivers/mfd/mt6397-core.c | 4 ++++
> 1 file changed, 4 insertions(+)
Applied, thanks.
> diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
> index e14d8b0..8e601c8 100644
> --- a/drivers/mfd/mt6397-core.c
> +++ b/drivers/mfd/mt6397-core.c
> @@ -48,6 +48,10 @@
> .name = "mt6323-regulator",
> .of_compatible = "mediatek,mt6323-regulator"
> },
> + {
> + .name = "mt6323-led",
> + .of_compatible = "mediatek,mt6323-led"
> + },
> };
>
> static const struct mfd_cell mt6397_devs[] = {
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* Re: [PATCH v2 2/4] Documentation: devicetree: Add LED subnode binding for MT6323 PMIC
From: Lee Jones @ 2017-02-08 12:22 UTC (permalink / raw)
To: sean.wang
Cc: rpurdie, jacek.anaszewski, matthias.bgg, pavel, robh+dt,
mark.rutland, devicetree, linux-leds, linux-mediatek,
linux-arm-kernel, linux-kernel, keyhaede
In-Reply-To: <1486520357-13096-3-git-send-email-sean.wang@mediatek.com>
On Wed, 08 Feb 2017, sean.wang@mediatek.com wrote:
> From: Sean Wang <sean.wang@mediatek.com>
>
> This patch adds documentation for devicetree bindings
> for LED support as the subnode of MT6323 PMIC
>
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> Documentation/devicetree/bindings/mfd/mt6397.txt | 4 ++++
> 1 file changed, 4 insertions(+)
Applied, thanks.
> diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt
> index 949c85f..c568d52 100644
> --- a/Documentation/devicetree/bindings/mfd/mt6397.txt
> +++ b/Documentation/devicetree/bindings/mfd/mt6397.txt
> @@ -34,6 +34,10 @@ Optional subnodes:
> - clk
> Required properties:
> - compatible: "mediatek,mt6397-clk"
> +- led
> + Required properties:
> + - compatible: "mediatek,mt6323-led"
> + see Documentation/devicetree/bindings/leds/leds-mt6323.txt
>
> Example:
> pwrap: pwrap@1000f000 {
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* Re: [PATCH v2 3/4] leds: Add LED support for MT6323 PMIC
From: Jacek Anaszewski @ 2017-02-08 21:00 UTC (permalink / raw)
To: sean.wang, rpurdie, lee.jones, matthias.bgg, pavel, robh+dt,
mark.rutland
Cc: devicetree, keyhaede, linux-kernel, linux-mediatek, linux-leds,
linux-arm-kernel
In-Reply-To: <1486520357-13096-4-git-send-email-sean.wang@mediatek.com>
Hi Sean,
Thanks for the update. Some nitpicking below.
On 02/08/2017 03:19 AM, sean.wang@mediatek.com wrote:
> From: Sean Wang <sean.wang@mediatek.com>
>
> MT6323 PMIC is a multi-function device that includes
> LED function. It allows attaching upto 4 LEDs which can
s/upto/up to/
> either be on, off or dimmed and/or blinked with the the
> controller.
>
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> ---
> drivers/leds/Kconfig | 8 +
> drivers/leds/Makefile | 1 +
> drivers/leds/leds-mt6323.c | 464 +++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 473 insertions(+)
> create mode 100644 drivers/leds/leds-mt6323.c
>
> diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
> index c621cbb..30095fc 100644
> --- a/drivers/leds/Kconfig
> +++ b/drivers/leds/Kconfig
> @@ -117,6 +117,14 @@ config LEDS_MIKROTIK_RB532
> This option enables support for the so called "User LED" of
> Mikrotik's Routerboard 532.
>
> +config LEDS_MT6323
> + tristate "LED Support for Mediatek MT6323 PMIC"
> + depends on LEDS_CLASS
> + depends on MFD_MT6397
> + help
> + This option enables support for on-chip LED drivers found on
> + Mediatek MT6323 PMIC.
> +
> config LEDS_S3C24XX
> tristate "LED Support for Samsung S3C24XX GPIO LEDs"
> depends on LEDS_CLASS
> diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
> index 6b82737..4feb332 100644
> --- a/drivers/leds/Makefile
> +++ b/drivers/leds/Makefile
> @@ -72,6 +72,7 @@ obj-$(CONFIG_LEDS_IS31FL32XX) += leds-is31fl32xx.o
> obj-$(CONFIG_LEDS_PM8058) += leds-pm8058.o
> obj-$(CONFIG_LEDS_MLXCPLD) += leds-mlxcpld.o
> obj-$(CONFIG_LEDS_NIC78BX) += leds-nic78bx.o
> +obj-$(CONFIG_LEDS_MT6323) += leds-mt6323.o
>
> # LED SPI Drivers
> obj-$(CONFIG_LEDS_DAC124S085) += leds-dac124s085.o
> diff --git a/drivers/leds/leds-mt6323.c b/drivers/leds/leds-mt6323.c
> new file mode 100644
> index 0000000..f6eeb6c
> --- /dev/null
> +++ b/drivers/leds/leds-mt6323.c
> @@ -0,0 +1,464 @@
> +/*
> + * LED driver for Mediatek MT6323 PMIC
> + *
> + * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +#include <linux/kernel.h>
> +#include <linux/leds.h>
> +#include <linux/mfd/mt6323/registers.h>
> +#include <linux/mfd/mt6397/core.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +/*
> + * Register field for MT6323_TOP_CKPDN0 to enable
> + * 32K clock common for LED device
Please put a dot at the and of sentence in case of each comment
starting from capital letter.
> + */
> +#define MT6323_RG_DRV_32K_CK_PDN BIT(11)
> +#define MT6323_RG_DRV_32K_CK_PDN_MASK BIT(11)
> +
> +/*
> + * Register field for MT6323_TOP_CKPDN2 to enable
> + * individual clock for LED device
> + */
> +#define MT6323_RG_ISINK_CK_PDN(i) BIT(i)
> +#define MT6323_RG_ISINK_CK_PDN_MASK(i) BIT(i)
> +
> +/*
> + * Register field for MT6323_TOP_CKCON1 to select
> + * clock source
> + */
> +#define MT6323_RG_ISINK_CK_SEL_MASK(i) (BIT(10) << (i))
> +
> +/*
> + * Register for MT6323_ISINK_CON0 to setup the
> + * duty cycle of the blink
> + */
> +#define MT6323_ISINK_CON0(i) (MT6323_ISINK0_CON0 + 0x8 * (i))
> +#define MT6323_ISINK_DIM_DUTY_MASK (0x1f << 8)
> +#define MT6323_ISINK_DIM_DUTY(i) (((i) << 8) & \
> + MT6323_ISINK_DIM_DUTY_MASK)
> +
> +/*
> + * Register to setup the period of the blink
> + */
This fits in a single line, so can be wrapped with /* */ like :
/* Register to setup the period of the blink */
The same applies to the other similar occurrences.
> +#define MT6323_ISINK_CON1(i) (MT6323_ISINK0_CON1 + 0x8 * (i))
> +#define MT6323_ISINK_DIM_FSEL_MASK (0xffff)
> +#define MT6323_ISINK_DIM_FSEL(i) ((i) & MT6323_ISINK_DIM_FSEL_MASK)
> +
> +/*
> + * Register to control the brightness
> + */
> +#define MT6323_ISINK_CON2(i) (MT6323_ISINK0_CON2 + 0x8 * (i))
> +#define MT6323_ISINK_CH_STEP_SHIFT 12
> +#define MT6323_ISINK_CH_STEP_MASK (0x7 << 12)
> +#define MT6323_ISINK_CH_STEP(i) (((i) << 12) & \
> + MT6323_ISINK_CH_STEP_MASK)
> +#define MT6323_ISINK_SFSTR0_TC_MASK (0x3 << 1)
> +#define MT6323_ISINK_SFSTR0_TC(i) (((i) << 1) & \
> + MT6323_ISINK_SFSTR0_TC_MASK)
> +#define MT6323_ISINK_SFSTR0_EN_MASK BIT(0)
> +#define MT6323_ISINK_SFSTR0_EN BIT(0)
> +
> +/*
> + * Register to LED channel enablement
> + */
> +#define MT6323_ISINK_CH_EN_MASK(i) BIT(i)
> +#define MT6323_ISINK_CH_EN(i) BIT(i)
> +
> +#define MTK_MAX_PERIOD 10000
> +#define MTK_MAX_DEVICES 4
s/MAX_DEVICES/MAX_LEDS/
> +#define MTK_MAX_BRIGHTNESS 6
> +#define MTK_UNIT_DUTY 3125
Why MTK and not MT6323?
> +
> +struct mtk_leds;
Similarly - let's turn it to struct mt6323_leds.
> +
> +/**
> + * struct mtk_led - state container for the LED device
> + * @id: the identifier in MT6323 LED device
> + * @parent: the pointer to MT6323 LED controller
> + * @cdev: LED class device for this LED device
> + * @current_brightness: current state of the LED device
> + */
> +struct mtk_led {
struct mt6323_led
> + int id;
> + struct mtk_leds *parent;
> + struct led_classdev cdev;
> + u8 current_brightness;
> +};
> +
> +/**
> + * struct mtk_leds - state container for holding LED controller
> + * of the driver
> + * @dev: The device pointer
Begin the property description with lowercase, like you're doing it
in case of struct mtk_led above.
> + * @hw: The underlying hardware providing shared
> + * bus for the register operations
> + * @led_num: How much the LED device the controller could control
> + * @lock: The lock among process context
> + * @led: The array that contains the state of individual
> + * LED device
> + */
> +struct mtk_leds {
> + struct device *dev;
> + struct mt6397_chip *hw;
> + u8 led_num;
> + /* protect among process context */
> + struct mutex lock;
> + struct mtk_led led[MTK_MAX_DEVICES];
> +};
> +
> +static int mtk_led_hw_off(struct led_classdev *cdev)
Please switch namespacing prefix of all functions from mtk to mt6323.
> +{
> + struct mtk_led *led = container_of(cdev, struct mtk_led, cdev);
> + struct mtk_leds *leds = led->parent;
> + struct regmap *regmap = leds->hw->regmap;
> + unsigned int status;
> + int ret;
> +
> + status = MT6323_ISINK_CH_EN(led->id);
> + ret = regmap_update_bits(regmap, MT6323_ISINK_EN_CTRL,
> + MT6323_ISINK_CH_EN_MASK(led->id), ~status);
> + if (ret < 0)
> + return ret;
> +
> + usleep_range(100, 300);
> + ret = regmap_update_bits(regmap, MT6323_TOP_CKPDN2,
> + MT6323_RG_ISINK_CK_PDN_MASK(led->id),
> + MT6323_RG_ISINK_CK_PDN(led->id));
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +
> +static int get_mtk_led_hw_brightness(struct led_classdev *cdev)
mt6323_get_led_hw_brightness
> +{
> + struct mtk_led *led = container_of(cdev, struct mtk_led, cdev);
> + struct mtk_leds *leds = led->parent;
> + struct regmap *regmap = leds->hw->regmap;
> + unsigned int status;
> + int ret;
> +
> + ret = regmap_read(regmap, MT6323_TOP_CKPDN2, &status);
> + if (ret < 0)
> + return ret;
> +
> + if (status & MT6323_RG_ISINK_CK_PDN_MASK(led->id))
> + return 0;
> +
> + ret = regmap_read(regmap, MT6323_ISINK_EN_CTRL, &status);
> + if (ret < 0)
> + return ret;
> +
> + if (!(status & MT6323_ISINK_CH_EN(led->id)))
> + return 0;
> +
> + ret = regmap_read(regmap, MT6323_ISINK_CON2(led->id), &status);
> + if (ret < 0)
> + return ret;
> +
> + return ((status & MT6323_ISINK_CH_STEP_MASK)
> + >> MT6323_ISINK_CH_STEP_SHIFT) + 1;
> +}
> +
> +static int mtk_led_hw_on(struct led_classdev *cdev)
> +{
> + struct mtk_led *led = container_of(cdev, struct mtk_led, cdev);
> + struct mtk_leds *leds = led->parent;
> + struct regmap *regmap = leds->hw->regmap;
> + unsigned int status;
> + int ret;
> +
> + /*
> + * Setup required clock source, enable the corresponding
> + * clock and channel and let work with continuous blink as
> + * the default
> + */
> + ret = regmap_update_bits(regmap, MT6323_TOP_CKCON1,
> + MT6323_RG_ISINK_CK_SEL_MASK(led->id), 0);
> + if (ret < 0)
> + return ret;
> +
> + status = MT6323_RG_ISINK_CK_PDN(led->id);
> + ret = regmap_update_bits(regmap, MT6323_TOP_CKPDN2,
> + MT6323_RG_ISINK_CK_PDN_MASK(led->id),
> + ~status);
> + if (ret < 0)
> + return ret;
> +
> + usleep_range(100, 300);
> +
> + ret = regmap_update_bits(regmap, MT6323_ISINK_EN_CTRL,
> + MT6323_ISINK_CH_EN_MASK(led->id),
> + MT6323_ISINK_CH_EN(led->id));
> + if (ret < 0)
> + return ret;
> +
> + ret = regmap_update_bits(regmap, MT6323_ISINK_CON2(led->id),
> + MT6323_ISINK_CH_STEP_MASK,
> + MT6323_ISINK_CH_STEP(1));
> + if (ret < 0)
> + return ret;
> +
> + ret = regmap_update_bits(regmap, MT6323_ISINK_CON0(led->id),
> + MT6323_ISINK_DIM_DUTY_MASK,
> + MT6323_ISINK_DIM_DUTY(31));
> + if (ret < 0)
> + return ret;
> +
> + ret = regmap_update_bits(regmap, MT6323_ISINK_CON1(led->id),
> + MT6323_ISINK_DIM_FSEL_MASK,
> + MT6323_ISINK_DIM_FSEL(1000));
> + if (ret < 0)
> + return ret;
> +
> + led->current_brightness = 1;
> +
> + return 0;
> +}
> +
> +static int mtk_led_set_blink(struct led_classdev *cdev,
> + unsigned long *delay_on,
> + unsigned long *delay_off)
> +{
> + struct mtk_led *led = container_of(cdev, struct mtk_led, cdev);
> + struct mtk_leds *leds = led->parent;
> + struct regmap *regmap = leds->hw->regmap;
> + u16 period;
> + u8 duty_cycle, duty_hw;
> + int ret;
> +
> + /*
> + * Units are in ms , if over the hardware able
s/ms ,/ms,/
> + * to support, fallback into software blink
> + */
> + if (*delay_on + *delay_off > MTK_MAX_PERIOD)
> + return -EINVAL;
> +
> + /*
> + * LED subsystem requires a default user
> + * friendly blink pattern for the LED so using
> + * 1Hz duty cycle 50% here if without specific
> + * value delay_on and delay off being assigned
> + */
> + if (*delay_on == 0 && *delay_off == 0) {
> + *delay_on = 500;
> + *delay_off = 500;
> + }
> +
> + period = *delay_on + *delay_off;
> +
> + /*
> + * duty_cycle is the percentage of period during
> + * which the led is ON
> + */
> + duty_cycle = 100 * (*delay_on) / period;
> +
> + mutex_lock(&leds->lock);
> +
> + if (!led->current_brightness) {
> + ret = mtk_led_hw_on(cdev);
> + if (ret < 0)
> + goto out;
> + }
> +
> + duty_hw = DIV_ROUND_CLOSEST(duty_cycle * 1000, MTK_UNIT_DUTY);
> + ret = regmap_update_bits(regmap, MT6323_ISINK_CON0(led->id),
> + MT6323_ISINK_DIM_DUTY_MASK,
> + MT6323_ISINK_DIM_DUTY(duty_hw));
> + if (ret < 0)
> + goto out;
> +
> + ret = regmap_update_bits(regmap, MT6323_ISINK_CON1(led->id),
> + MT6323_ISINK_DIM_FSEL_MASK,
> + MT6323_ISINK_DIM_FSEL(period - 1));
> +out:
> + mutex_unlock(&leds->lock);
> +
> + return ret;
> +}
> +
> +static int mtk_led_set_brightness(struct led_classdev *cdev,
> + enum led_brightness brightness)
> +{
> + struct mtk_led *led = container_of(cdev, struct mtk_led, cdev);
> + struct mtk_leds *leds = led->parent;
> + struct regmap *regmap = leds->hw->regmap;
> + int ret;
> +
> + mutex_lock(&leds->lock);
> +
> + if (!led->current_brightness && brightness) {
> + ret = mtk_led_hw_on(cdev);
> + if (ret < 0)
> + goto out;
> + }
> +
> + if (brightness) {
> + /*
> + * Setup current output for the corresponding
> + * brightness level
> + */
> + ret = regmap_update_bits(regmap, MT6323_ISINK_CON2(led->id),
> + MT6323_ISINK_CH_STEP_MASK,
> + MT6323_ISINK_CH_STEP(brightness - 1));
> + if (ret < 0)
> + goto out;
> +
> + ret = regmap_update_bits(regmap, MT6323_ISINK_CON2(led->id),
> + MT6323_ISINK_SFSTR0_TC_MASK |
> + MT6323_ISINK_SFSTR0_EN_MASK,
> + MT6323_ISINK_SFSTR0_TC(2) |
> + MT6323_ISINK_SFSTR0_EN);
> + if (ret < 0)
> + goto out;
> + } else {
> + ret = mtk_led_hw_off(cdev);
> + if (ret < 0)
> + goto out;
> + }
> +
> + led->current_brightness = brightness;
> +out:
> + mutex_unlock(&leds->lock);
> +
> + return ret;
> +}
> +
> +static int mt6323_led_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = pdev->dev.of_node;
> + struct device_node *child;
> + struct mt6397_chip *hw = dev_get_drvdata(pdev->dev.parent);
> + struct mtk_leds *leds;
> + int ret, i = 0, count;
> + const char *state;
> + unsigned int status;
> +
> + count = of_get_child_count(np);
> + if (!count)
> + return -ENODEV;
> +
> + /*
> + * The number the LEDs on MT6323 could be support is
> + * up to MTK_MAX_DEVICES
> + */
We're going to change the macro name to MT6323_MAX_LEDS - it will be
self-explanatory then, and the comment will be redundant here.
> + count = (count <= MTK_MAX_DEVICES) ? count : MTK_MAX_DEVICES;
> +
> + leds = devm_kzalloc(dev, sizeof(struct mtk_leds) +
> + sizeof(struct mtk_led) * count,
> + GFP_KERNEL);
> + if (!leds)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, leds);
> + leds->dev = dev;
> +
> + /*
> + * leds->hw points to the underlying bus for the register
> + * controlled
> + */
> + leds->hw = hw;
> + mutex_init(&leds->lock);
> + leds->led_num = count;
> +
> + status = MT6323_RG_DRV_32K_CK_PDN;
> + ret = regmap_update_bits(leds->hw->regmap, MT6323_TOP_CKPDN0,
> + MT6323_RG_DRV_32K_CK_PDN_MASK, ~status);
> + if (ret < 0) {
> + dev_err(leds->dev,
> + "Failed to update MT6323_TOP_CKPDN0 Register\n");
> + return ret;
> + }
> +
> + for_each_available_child_of_node(np, child) {
> + leds->led[i].cdev.name =
> + of_get_property(child, "label", NULL) ? :
> + child->name;
> + leds->led[i].cdev.default_trigger = of_get_property(child,
> + "linux,default-trigger",
> + NULL);
> + leds->led[i].cdev.max_brightness = MTK_MAX_BRIGHTNESS;
> + leds->led[i].cdev.brightness_set_blocking =
> + mtk_led_set_brightness;
> + leds->led[i].cdev.blink_set = mtk_led_set_blink;
> + leds->led[i].id = i;
> + leds->led[i].parent = leds;
> + state = of_get_property(child, "default-state", NULL);
> + if (state) {
> + if (!strcmp(state, "keep")) {
> + leds->led[i].current_brightness =
> + get_mtk_led_hw_brightness(&leds->led[i].cdev);
> + } else if (!strcmp(state, "on")) {
> + mtk_led_set_brightness(&leds->led[i].cdev, 1);
> + } else {
> + mtk_led_set_brightness(&leds->led[i].cdev,
> + 0);
> + }
> + }
> + ret = devm_led_classdev_register(dev, &leds->led[i].cdev);
> + if (ret) {
> + dev_err(&pdev->dev, "Failed to register LED: %d\n",
> + ret);
> + return ret;
> + }
> + leds->led[i].cdev.dev->of_node = child;
> + i++;
> + }
> +
> + return 0;
> +}
> +
> +static int mt6323_led_remove(struct platform_device *pdev)
> +{
> + struct mtk_leds *leds = platform_get_drvdata(pdev);
> + int i;
> +
> + /*
> + * Turned the LED to OFF state on driver removal
How about:
/* Turn the LEDs off on driver removal. */
> + */
> + for (i = 0 ; i < leds->led_num ; i++)
> + mtk_led_hw_off(&leds->led[i].cdev);
> +
> + regmap_update_bits(leds->hw->regmap, MT6323_TOP_CKPDN0,
> + MT6323_RG_DRV_32K_CK_PDN_MASK,
> + MT6323_RG_DRV_32K_CK_PDN);
> +
> + mutex_destroy(&leds->lock);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id mt6323_led_dt_match[] = {
> + { .compatible = "mediatek,mt6323-led" },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, mt6323_led_dt_match);
> +
> +static struct platform_driver mt6323_led_driver = {
> + .probe = mt6323_led_probe,
> + .remove = mt6323_led_remove,
> + .driver = {
> + .name = "mt6323-led",
> + .of_match_table = mt6323_led_dt_match,
> + },
> +};
> +
> +module_platform_driver(mt6323_led_driver);
> +
> +MODULE_DESCRIPTION("LED driver for Mediatek MT6323 PMIC");
> +MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
> +MODULE_LICENSE("GPL");
>
--
Best regards,
Jacek Anaszewski
^ permalink raw reply
* Re: [PATCH v2 01/10] Document: DT: mediatek: multiple base address support for sysirq
From: Rob Herring @ 2017-02-08 23:20 UTC (permalink / raw)
To: Mars Cheng
Cc: Matthias Brugger, CC Hwang, Loda Chou, Miles Chen, Jades Shih,
Yingjoe Chen, My Chuang, linux-kernel, linux-mediatek, devicetree,
wsd_upstream, Marc Zyngier, Thomas Gleixner, Will Deacon,
Stephen Boyd, linux-clk, Chieh-Jay Liu
In-Reply-To: <1486383336-16892-2-git-send-email-mars.cheng@mediatek.com>
On Mon, Feb 06, 2017 at 08:15:27PM +0800, Mars Cheng wrote:
> This describes how to specify multiple base addresses for sysirq
> in mediatek platforms.
>
> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
> ---
> .../interrupt-controller/mediatek,sysirq.txt | 13 +++++++++----
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
> index 9d1d72c..1718454 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
> +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
> @@ -18,16 +18,21 @@ Required properties:
> "mediatek,mt2701-sysirq"
> - interrupt-controller : Identifies the node as an interrupt controller
> - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
> +- #intpol-bases: Indicate how many base addresses to be used, default is 1.
There is no point in this. It can either be implied by the compatible
string or you just try to get the resource for the 2nd region. (Or in DT
terms, get the size of reg.)
> - interrupt-parent: phandle of irq parent for sysirq. The parent must
> use the same interrupt-cells format as GIC.
> - reg: Physical base address of the intpol registers and length of memory
> - mapped region.
> + mapped region. Could be multiple bases here. Ex: mt6797 needs 2 reg, others
> + need 1. If not set, the default is 1.
>
> Example:
> - sysirq: interrupt-controller@10200100 {
> - compatible = "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq";
> + sysirq: intpol-controller@10200620 {
> + compatible = "mediatek,mt6797-sysirq",
> + "mediatek,mt6577-sysirq";
> interrupt-controller;
> #interrupt-cells = <3>;
> + #intpol-bases = <2>;
> interrupt-parent = <&gic>;
> - reg = <0 0x10200100 0 0x1c>;
> + reg = <0 0x10220620 0 0x20>,
> + <0 0x10220690 0 0x10>;
> };
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v2 03/10] Document: DT: Add bindings for mediatek MT6797 SoC Platform
From: Rob Herring @ 2017-02-09 0:34 UTC (permalink / raw)
To: Mars Cheng
Cc: Matthias Brugger, CC Hwang, Loda Chou, Miles Chen, Jades Shih,
Yingjoe Chen, My Chuang, linux-kernel, linux-mediatek, devicetree,
wsd_upstream, Marc Zyngier, Thomas Gleixner, Will Deacon,
Stephen Boyd, linux-clk, Chieh-Jay Liu
In-Reply-To: <1486383336-16892-4-git-send-email-mars.cheng@mediatek.com>
On Mon, Feb 06, 2017 at 08:15:29PM +0800, Mars Cheng wrote:
> This adds dt-binding documentation for Mediatek MT6797. Only
> include very basic items, gic, uart timer and cpu.
For the subject:
"dt-bindings: arm: Add Mediatek MT6797 SoC Platform"
Otherwise,
Acked-by: Rob Herring <robh@kernel.org>
>
> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
> ---
> Documentation/devicetree/bindings/arm/mediatek.txt | 4 ++++
> .../interrupt-controller/mediatek,sysirq.txt | 1 +
> .../devicetree/bindings/serial/mtk-uart.txt | 1 +
> 3 files changed, 6 insertions(+)
^ permalink raw reply
* Re: [PATCH v2 05/10] dt-bindings: arm: mediatek: document clk bindings for MT6797
From: Rob Herring @ 2017-02-09 0:35 UTC (permalink / raw)
To: Mars Cheng
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, CC Hwang,
wsd_upstream-NuS5LvNUpcJWk0Htik3J/w, Marc Zyngier, Will Deacon,
Loda Chou, linux-kernel-u79uwXL29TY76Z2rM5mHXA, Jades Shih,
linux-clk-u79uwXL29TY76Z2rM5mHXA, Miles Chen, Kevin-CW Chen,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, My Chuang,
Matthias Brugger, Yingjoe Chen, Thomas Gleixner, Stephen Boyd,
Chieh-Jay Liu
In-Reply-To: <1486383336-16892-6-git-send-email-mars.cheng-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
On Mon, Feb 06, 2017 at 08:15:31PM +0800, Mars Cheng wrote:
> From: Kevin-CW Chen <kevin-cw.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
>
> This patch adds the binding documentation for apmixedsys, imgsys,
> infracfg, mmsys, topckgen, vdecsys and vencsys for MT6797.
>
> Signed-off-by: Kevin-CW Chen <kevin-cw.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> Signed-off-by: Mars Cheng <mars.cheng-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
> .../bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 +
> .../bindings/arm/mediatek/mediatek,imgsys.txt | 1 +
> .../bindings/arm/mediatek/mediatek,infracfg.txt | 1 +
> .../bindings/arm/mediatek/mediatek,mmsys.txt | 1 +
> .../bindings/arm/mediatek/mediatek,topckgen.txt | 1 +
> .../bindings/arm/mediatek/mediatek,vdecsys.txt | 1 +
> .../bindings/arm/mediatek/mediatek,vencsys.txt | 3 ++-
> 7 files changed, 8 insertions(+), 1 deletion(-)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
^ permalink raw reply
* Re: [PATCH v2 08/10] soc: mediatek: add MT6797 power dt-bindings
From: Rob Herring @ 2017-02-09 0:37 UTC (permalink / raw)
To: Mars Cheng
Cc: Matthias Brugger, CC Hwang, Loda Chou, Miles Chen, Jades Shih,
Yingjoe Chen, My Chuang, linux-kernel, linux-mediatek, devicetree,
wsd_upstream, Marc Zyngier, Thomas Gleixner, Will Deacon,
Stephen Boyd, linux-clk, Chieh-Jay Liu, Kevin-CW Chen
In-Reply-To: <1486383336-16892-9-git-send-email-mars.cheng@mediatek.com>
On Mon, Feb 06, 2017 at 08:15:34PM +0800, Mars Cheng wrote:
> This adds power dt-bindings for MT6797
Some consistency in the subject for bindings please.
>
> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
> Signed-off-by: Kevin-CW Chen <kevin-cw.chen@mediatek.com>
> ---
> .../devicetree/bindings/soc/mediatek/scpsys.txt | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
> index 16fe94d..b1d165b 100644
> --- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
> +++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
> @@ -9,11 +9,14 @@ domain control.
>
> The driver implements the Generic PM domain bindings described in
> power/power_domain.txt. It provides the power domains defined in
> -include/dt-bindings/power/mt8173-power.h and mt2701-power.h.
> +- include/dt-bindings/power/mt8173-power.h
> +- include/dt-bindings/power/mt6797-power.h
> +- include/dt-bindings/power/mt2701-power.h
>
> Required properties:
> - compatible: Should be one of:
> - "mediatek,mt2701-scpsys"
> + - "mediatek,mt6797-scpsys"
> - "mediatek,mt8173-scpsys"
> - #power-domain-cells: Must be 1
> - reg: Address range of the SCPSYS unit
> @@ -22,6 +25,7 @@ Required properties:
> These are clocks which hardware needs to be
> enabled before enabling certain power domains.
> Required clocks for MT2701: "mm", "mfg", "ethif"
> + Required clocks for MT6797: "mm", "mfg", "vdec"
> Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
>
> Optional properties:
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
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