* Re: [PATCH v2 08/10] soc: mediatek: add MT6797 power dt-bindings
From: Rob Herring @ 2017-02-09 0:37 UTC (permalink / raw)
To: Mars Cheng
Cc: Matthias Brugger, CC Hwang, Loda Chou, Miles Chen, Jades Shih,
Yingjoe Chen, My Chuang, linux-kernel, linux-mediatek, devicetree,
wsd_upstream, Marc Zyngier, Thomas Gleixner, Will Deacon,
Stephen Boyd, linux-clk, Chieh-Jay Liu, Kevin-CW Chen
In-Reply-To: <1486383336-16892-9-git-send-email-mars.cheng@mediatek.com>
On Mon, Feb 06, 2017 at 08:15:34PM +0800, Mars Cheng wrote:
> This adds power dt-bindings for MT6797
Some consistency in the subject for bindings please.
>
> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
> Signed-off-by: Kevin-CW Chen <kevin-cw.chen@mediatek.com>
> ---
> .../devicetree/bindings/soc/mediatek/scpsys.txt | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
> index 16fe94d..b1d165b 100644
> --- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
> +++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
> @@ -9,11 +9,14 @@ domain control.
>
> The driver implements the Generic PM domain bindings described in
> power/power_domain.txt. It provides the power domains defined in
> -include/dt-bindings/power/mt8173-power.h and mt2701-power.h.
> +- include/dt-bindings/power/mt8173-power.h
> +- include/dt-bindings/power/mt6797-power.h
> +- include/dt-bindings/power/mt2701-power.h
>
> Required properties:
> - compatible: Should be one of:
> - "mediatek,mt2701-scpsys"
> + - "mediatek,mt6797-scpsys"
> - "mediatek,mt8173-scpsys"
> - #power-domain-cells: Must be 1
> - reg: Address range of the SCPSYS unit
> @@ -22,6 +25,7 @@ Required properties:
> These are clocks which hardware needs to be
> enabled before enabling certain power domains.
> Required clocks for MT2701: "mm", "mfg", "ethif"
> + Required clocks for MT6797: "mm", "mfg", "vdec"
> Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
>
> Optional properties:
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v2 08/10] soc: mediatek: add MT6797 power dt-bindings
From: Mars Cheng @ 2017-02-09 1:32 UTC (permalink / raw)
To: Rob Herring
Cc: Matthias Brugger, CC Hwang, Loda Chou, Miles Chen, Jades Shih,
Yingjoe Chen, My Chuang, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
wsd_upstream-NuS5LvNUpcJWk0Htik3J/w, Marc Zyngier,
Thomas Gleixner, Will Deacon, Stephen Boyd,
linux-clk-u79uwXL29TY76Z2rM5mHXA, Chieh-Jay Liu, Kevin-CW Chen
In-Reply-To: <20170209003741.nxcdxah5ydcj6v33@rob-hp-laptop>
On Wed, 2017-02-08 at 18:37 -0600, Rob Herring wrote:
> On Mon, Feb 06, 2017 at 08:15:34PM +0800, Mars Cheng wrote:
> > This adds power dt-bindings for MT6797
>
> Some consistency in the subject for bindings please.
Got it, will use the format like "dt-bindings: xxx: xxx" to send patch
set v3
Thanks.
>
> >
> > Signed-off-by: Mars Cheng <mars.cheng-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > Signed-off-by: Kevin-CW Chen <kevin-cw.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > ---
> > .../devicetree/bindings/soc/mediatek/scpsys.txt | 6 +++++-
> > 1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
> > index 16fe94d..b1d165b 100644
> > --- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
> > +++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
> > @@ -9,11 +9,14 @@ domain control.
> >
> > The driver implements the Generic PM domain bindings described in
> > power/power_domain.txt. It provides the power domains defined in
> > -include/dt-bindings/power/mt8173-power.h and mt2701-power.h.
> > +- include/dt-bindings/power/mt8173-power.h
> > +- include/dt-bindings/power/mt6797-power.h
> > +- include/dt-bindings/power/mt2701-power.h
> >
> > Required properties:
> > - compatible: Should be one of:
> > - "mediatek,mt2701-scpsys"
> > + - "mediatek,mt6797-scpsys"
> > - "mediatek,mt8173-scpsys"
> > - #power-domain-cells: Must be 1
> > - reg: Address range of the SCPSYS unit
> > @@ -22,6 +25,7 @@ Required properties:
> > These are clocks which hardware needs to be
> > enabled before enabling certain power domains.
> > Required clocks for MT2701: "mm", "mfg", "ethif"
> > + Required clocks for MT6797: "mm", "mfg", "vdec"
> > Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
> >
> > Optional properties:
> > --
> > 1.7.9.5
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe devicetree" in
> > the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v2 01/10] Document: DT: mediatek: multiple base address support for sysirq
From: Mars Cheng @ 2017-02-09 1:47 UTC (permalink / raw)
To: Rob Herring
Cc: Matthias Brugger, CC Hwang, Loda Chou, Miles Chen, Jades Shih,
Yingjoe Chen, My Chuang, linux-kernel, linux-mediatek, devicetree,
wsd_upstream, Marc Zyngier, Thomas Gleixner, Will Deacon,
Stephen Boyd, linux-clk, Chieh-Jay Liu
In-Reply-To: <20170208232039.p7ljh4krndtn2edy@rob-hp-laptop>
Hi Rob,
On Wed, 2017-02-08 at 17:20 -0600, Rob Herring wrote:
> On Mon, Feb 06, 2017 at 08:15:27PM +0800, Mars Cheng wrote:
> > This describes how to specify multiple base addresses for sysirq
> > in mediatek platforms.
> >
> > Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
> > ---
> > .../interrupt-controller/mediatek,sysirq.txt | 13 +++++++++----
> > 1 file changed, 9 insertions(+), 4 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
> > index 9d1d72c..1718454 100644
> > --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
> > @@ -18,16 +18,21 @@ Required properties:
> > "mediatek,mt2701-sysirq"
> > - interrupt-controller : Identifies the node as an interrupt controller
> > - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
> > +- #intpol-bases: Indicate how many base addresses to be used, default is 1.
>
> There is no point in this. It can either be implied by the compatible
> string or you just try to get the resource for the 2nd region. (Or in DT
> terms, get the size of reg.)
>
Originally I try to mimic #redistributor-regions in
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt.
But I think you are right since irq-gic-v3 has several kinds of bases in
reg so that they need an indicator to decode. For irq-mtk-sysirq, we can
just try 2nd region and increment a counter to get the number of bases.
Will fix this in v3.
Thanks.
> > - interrupt-parent: phandle of irq parent for sysirq. The parent must
> > use the same interrupt-cells format as GIC.
> > - reg: Physical base address of the intpol registers and length of memory
> > - mapped region.
> > + mapped region. Could be multiple bases here. Ex: mt6797 needs 2 reg, others
> > + need 1. If not set, the default is 1.
> >
> > Example:
> > - sysirq: interrupt-controller@10200100 {
> > - compatible = "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq";
> > + sysirq: intpol-controller@10200620 {
> > + compatible = "mediatek,mt6797-sysirq",
> > + "mediatek,mt6577-sysirq";
> > interrupt-controller;
> > #interrupt-cells = <3>;
> > + #intpol-bases = <2>;
> > interrupt-parent = <&gic>;
> > - reg = <0 0x10200100 0 0x1c>;
> > + reg = <0 0x10220620 0 0x20>,
> > + <0 0x10220690 0 0x10>;
> > };
> > --
> > 1.7.9.5
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe devicetree" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH] arm64: use linux/sizes.h for constants
From: Miles Chen @ 2017-02-09 1:52 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Miles Chen, linux-mediatek, linux-kernel, linux-arm-kernel,
wsd_upstream
Use linux/size.h to improve code readability.
Signed-off-by: Miles Chen <miles.chen@mediatek.com>
---
arch/arm64/kernel/process.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index a3a2816..aaac783 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -407,7 +407,7 @@ unsigned long arch_align_stack(unsigned long sp)
unsigned long arch_randomize_brk(struct mm_struct *mm)
{
if (is_compat_task())
- return randomize_page(mm->brk, 0x02000000);
+ return randomize_page(mm->brk, SZ_32M);
else
- return randomize_page(mm->brk, 0x40000000);
+ return randomize_page(mm->brk, SZ_1G);
}
--
1.9.1
^ permalink raw reply related
* Re: [PATCH v6 3/3] arm: dts: mt2701: Add node for Mediatek JPEG Decoder
From: Rick Chang @ 2017-02-09 2:10 UTC (permalink / raw)
To: Hans Verkuil, Matthias Brugger
Cc: devicetree, Laurent Pinchart, Minghsiu Tsai, srv_heupstream,
James Liao, Mauro Carvalho Chehab, linux-kernel, Rob Herring,
linux-mediatek, Eddie Huang, linux-arm-kernel, linux-media
In-Reply-To: <267403e5-18ac-0c74-10ca-cc36b909dfb4@gmail.com>
Hi Hans,
All the dependences of this patch have been merged into v4.10-next.Could
you take v9 of this patch set? Matthias will help us to take the dts
part.
Best Regards,
Rick
On Fri, 2017-01-13 at 16:02 +0100, Matthias Brugger wrote:
> Hi James,
>
> On 10/01/17 02:28, Eddie Huang wrote:
> > Hi Matthias,
> >
> > On Mon, 2017-01-09 at 19:45 +0100, Matthias Brugger wrote:
> >>
> >> On 09/01/17 12:29, Hans Verkuil wrote:
> >>> Hi Rick,
> >>>
> >>> On 01/06/2017 03:34 AM, Rick Chang wrote:
> >>>> Hi Hans,
> >>>>
> >>>> The dependence on [1] has been merged in 4.10, but [2] has not.Do you have
> >>>> any idea about this patch series? Should we wait for [2] or we could merge
> >>>> the source code and dt-binding first?
> >>>
> >>> Looking at [2] I noticed that the last comment was July 4th. What is the reason
> >>> it hasn't been merged yet?
> >>>
> >>> If I know [2] will be merged for 4.11, then I am fine with merging this media
> >>> patch series. The dependency of this patch on [2] is something Mauro can handle.
> >>>
> >>> If [2] is not merged for 4.11, then I think it is better to wait until it is
> >>> merged.
> >>>
> >>
> >> I can't take [2] because there is no scpsys in the dts present. It seems
> >> that it got never posted.
> >>
> >> Rick can you please follow-up with James and provide a patch which adds
> >> a scpsys node to the mt2701.dtsi?
> >>
> >
> > James sent three MT2701 dts patches [1] two weeks ago, these three
> > patches include scpsys node. Please take a reference. And We will send
> > new MT2701 ionmmu/smi dtsi node patch base on [1] later, thus you can
> > accept and merge to 4.11.
> >
>
> Thanks for the clarification. I pulled all this patches into
> v4.10-next/dts32
>
> Hans will you take v9 of this patch set?
> Then I'll take the dts patch.
>
> Regards,
> Matthias
>
> > [1]
> > https://patchwork.kernel.org/patch/9489991/
> > https://patchwork.kernel.org/patch/9489985/
> > https://patchwork.kernel.org/patch/9489989/
> >
> > Thanks,
> > Eddie
> >
> >
^ permalink raw reply
* [PATCH] arm64: use is_vmalloc_addr
From: Miles Chen @ 2017-02-09 2:20 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Miles Chen, linux-mediatek, linux-kernel, linux-arm-kernel,
wsd_upstream
To is_vmalloc_addr() to check if an address is a vmalloc address
instead of checking VMALLOC_START and VMALLOC_END manually.
Signed-off-by: Miles Chen <miles.chen@mediatek.com>
---
arch/arm64/mm/ioremap.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/mm/ioremap.c b/arch/arm64/mm/ioremap.c
index 01e88c8..71d6b04 100644
--- a/arch/arm64/mm/ioremap.c
+++ b/arch/arm64/mm/ioremap.c
@@ -88,7 +88,7 @@ void __iounmap(volatile void __iomem *io_addr)
* We could get an address outside vmalloc range in case
* of ioremap_cache() reusing a RAM mapping.
*/
- if (VMALLOC_START <= addr && addr < VMALLOC_END)
+ if (is_vmalloc_addr(addr))
vunmap((void *)addr);
}
EXPORT_SYMBOL(__iounmap);
--
1.9.1
^ permalink raw reply related
* irqchip/gic: avoid magic irq number
From: Mars Cheng @ 2017-02-09 3:15 UTC (permalink / raw)
To: Marc Zyngier
Cc: CC Hwang, wsd_upstream, Mars Cheng, Loda Chou, linux-kernel,
Jades Shih, Miles Chen, linux-mediatek, My Chuang,
Matthias Brugger, Yingjoe Chen, linux-arm-kernel
use defines instead of magic numbers
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
---
drivers/irqchip/irq-gic-v3-its.c | 7 +++---
drivers/irqchip/irq-gic-v3.c | 41 +++++++++++++++++---------------
drivers/irqchip/irq-gic.c | 38 ++++++++++++++++-------------
include/linux/irqchip/arm-gic-common.h | 12 ++++++++++
include/linux/irqchip/arm-gic-v3.h | 2 ++
5 files changed, 61 insertions(+), 39 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 69b040f..ceca96d 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -588,7 +588,8 @@ static void lpi_set_config(struct irq_data *d, bool enable)
struct its_device *its_dev = irq_data_get_irq_chip_data(d);
irq_hw_number_t hwirq = d->hwirq;
u32 id = its_get_event_id(d);
- u8 *cfg = page_address(gic_rdists->prop_page) + hwirq - 8192;
+ u8 *cfg = page_address(gic_rdists->prop_page) + hwirq -
+ GIC_FIRST_LPI_IRQ;
if (enable)
*cfg |= LPI_PROP_ENABLED;
@@ -691,12 +692,12 @@ static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
static int its_lpi_to_chunk(int lpi)
{
- return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT;
+ return (lpi - GIC_FIRST_LPI_IRQ) >> IRQS_PER_CHUNK_SHIFT;
}
static int its_chunk_to_lpi(int chunk)
{
- return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192;
+ return (chunk << IRQS_PER_CHUNK_SHIFT) + GIC_FIRST_LPI_IRQ;
}
static int __init its_lpi_init(u32 id_bits)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index c132f29..577ab0b 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -56,7 +56,7 @@ struct gic_chip_data {
u64 redist_stride;
u32 nr_redist_regions;
unsigned int irq_nr;
- struct partition_desc *ppi_descs[16];
+ struct partition_desc *ppi_descs[GIC_NR_PPI];
};
static struct gic_chip_data gic_data __read_mostly;
@@ -78,7 +78,7 @@ static inline unsigned int gic_irq(struct irq_data *d)
static inline int gic_irq_in_rdist(struct irq_data *d)
{
- return gic_irq(d) < 32;
+ return gic_irq(d) < GIC_FIRST_SPI_IRQ;
}
static inline void __iomem *gic_dist_base(struct irq_data *d)
@@ -86,7 +86,7 @@ static inline void __iomem *gic_dist_base(struct irq_data *d)
if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */
return gic_data_rdist_sgi_base();
- if (d->hwirq <= 1023) /* SPI -> dist_base */
+ if (d->hwirq <= GIC_SPURIOUS_IRQ) /* SPI -> dist_base */
return gic_data.dist_base;
return NULL;
@@ -289,7 +289,8 @@ static void gic_eoimode1_eoi_irq(struct irq_data *d)
* No need to deactivate an LPI, or an interrupt that
* is is getting forwarded to a vcpu.
*/
- if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
+ if (gic_irq(d) >= GIC_FIRST_LPI_IRQ ||
+ irqd_is_forwarded_to_vcpu(d))
return;
gic_write_dir(gic_irq(d));
}
@@ -301,12 +302,13 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
void __iomem *base;
/* Interrupt configuration for SGIs can't be changed */
- if (irq < 16)
+ if (irq <= GIC_LAST_SGI_IRQ)
return -EINVAL;
/* SPIs have restrictions on the supported types */
- if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
- type != IRQ_TYPE_EDGE_RISING)
+ if (irq >= GIC_FIRST_SPI_IRQ &&
+ type != IRQ_TYPE_LEVEL_HIGH &&
+ type != IRQ_TYPE_EDGE_RISING)
return -EINVAL;
if (gic_irq_in_rdist(d)) {
@@ -348,7 +350,8 @@ static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs
do {
irqnr = gic_read_iar();
- if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) {
+ if (likely(irqnr > GIC_LAST_SGI_IRQ && irqnr < GIC_MAX_IRQ) ||
+ irqnr >= GIC_FIRST_LPI_IRQ) {
int err;
if (static_key_true(&supports_deactivate))
@@ -358,7 +361,7 @@ static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs
if (err) {
WARN_ONCE(true, "Unexpected interrupt received!\n");
if (static_key_true(&supports_deactivate)) {
- if (irqnr < 8192)
+ if (irqnr < GIC_FIRST_LPI_IRQ)
gic_write_dir(irqnr);
} else {
gic_write_eoir(irqnr);
@@ -366,7 +369,7 @@ static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs
}
continue;
}
- if (irqnr < 16) {
+ if (irqnr <= GIC_LAST_SGI_IRQ) {
gic_write_eoir(irqnr);
if (static_key_true(&supports_deactivate))
gic_write_dir(irqnr);
@@ -744,30 +747,30 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
chip = &gic_eoimode1_chip;
/* SGIs are private to the core kernel */
- if (hw < 16)
+ if (hw < GIC_NR_SGI)
return -EPERM;
/* Nothing here */
- if (hw >= gic_data.irq_nr && hw < 8192)
+ if (hw >= gic_data.irq_nr && hw < GIC_FIRST_LPI_IRQ)
return -EPERM;
/* Off limits */
if (hw >= GIC_ID_NR)
return -EPERM;
/* PPIs */
- if (hw < 32) {
+ if (hw < GIC_FIRST_SPI_IRQ) {
irq_set_percpu_devid(irq);
irq_domain_set_info(d, irq, hw, chip, d->host_data,
handle_percpu_devid_irq, NULL, NULL);
irq_set_status_flags(irq, IRQ_NOAUTOEN);
}
/* SPIs */
- if (hw >= 32 && hw < gic_data.irq_nr) {
+ if (hw >= GIC_FIRST_SPI_IRQ && hw < gic_data.irq_nr) {
irq_domain_set_info(d, irq, hw, chip, d->host_data,
handle_fasteoi_irq, NULL, NULL);
irq_set_probe(irq);
}
/* LPIs */
- if (hw >= 8192 && hw < GIC_ID_NR) {
+ if (hw >= GIC_FIRST_LPI_IRQ && hw < GIC_ID_NR) {
if (!gic_dist_supports_lpis())
return -EPERM;
irq_domain_set_info(d, irq, hw, chip, d->host_data,
@@ -788,10 +791,10 @@ static int gic_irq_domain_translate(struct irq_domain *d,
switch (fwspec->param[0]) {
case 0: /* SPI */
- *hwirq = fwspec->param[1] + 32;
+ *hwirq = fwspec->param[1] + GIC_FIRST_SPI_IRQ;
break;
case 1: /* PPI */
- *hwirq = fwspec->param[1] + 16;
+ *hwirq = fwspec->param[1] + GIC_FIRST_PPI_IRQ;
break;
case GIC_IRQ_TYPE_LPI: /* LPI */
*hwirq = fwspec->param[1];
@@ -933,8 +936,8 @@ static int __init gic_init_bases(void __iomem *dist_base,
typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer);
gic_irqs = GICD_TYPER_IRQS(typer);
- if (gic_irqs > 1020)
- gic_irqs = 1020;
+ if (gic_irqs > GIC_MAX_IRQ)
+ gic_irqs = GIC_MAX_IRQ;
gic_data.irq_nr = gic_irqs;
gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 1b1df4f..70f6392 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -76,10 +76,10 @@ struct gic_chip_data {
void __iomem *raw_cpu_base;
u32 percpu_offset;
#if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
- u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
- u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
- u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
- u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
+ u32 saved_spi_enable[DIV_ROUND_UP(GIC_LAST_SPI_IRQ, 32)];
+ u32 saved_spi_active[DIV_ROUND_UP(GIC_LAST_SPI_IRQ, 32)];
+ u32 saved_spi_conf[DIV_ROUND_UP(GIC_LAST_SPI_IRQ, 16)];
+ u32 saved_spi_target[DIV_ROUND_UP(GIC_LAST_SPI_IRQ, 4)];
u32 __percpu *saved_ppi_enable;
u32 __percpu *saved_ppi_active;
u32 __percpu *saved_ppi_conf;
@@ -296,12 +296,13 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
unsigned int gicirq = gic_irq(d);
/* Interrupt configuration for SGIs can't be changed */
- if (gicirq < 16)
+ if (gicirq < GIC_FIRST_PPI_IRQ)
return -EINVAL;
/* SPIs have restrictions on the supported types */
- if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
- type != IRQ_TYPE_EDGE_RISING)
+ if (gicirq >= GIC_FIRST_SPI_IRQ &&
+ type != IRQ_TYPE_LEVEL_HIGH &&
+ type != IRQ_TYPE_EDGE_RISING)
return -EINVAL;
return gic_configure_irq(gicirq, type, base, NULL);
@@ -358,13 +359,14 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
irqnr = irqstat & GICC_IAR_INT_ID_MASK;
- if (likely(irqnr > 15 && irqnr < 1020)) {
+ if (likely((irqnr > GIC_LAST_SGI_IRQ) &&
+ (irqnr < GIC_FIRST_SPECIAL_IRQ))) {
if (static_key_true(&supports_deactivate))
writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
handle_domain_irq(gic->domain, irqnr, regs);
continue;
}
- if (irqnr < 16) {
+ if (irqnr < GIC_FIRST_PPI_IRQ) {
writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
if (static_key_true(&supports_deactivate))
writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE);
@@ -401,7 +403,8 @@ static void gic_handle_cascade_irq(struct irq_desc *desc)
goto out;
cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
- if (unlikely(gic_irq < 32 || gic_irq > 1020))
+ if (unlikely(gic_irq < GIC_FIRST_SPI_IRQ ||
+ gic_irq > GIC_LAST_SPI_IRQ))
handle_bad_irq(desc);
else
generic_handle_irq(cascade_irq);
@@ -1109,8 +1112,8 @@ static int gic_init_bases(struct gic_chip_data *gic, int irq_start,
*/
gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
gic_irqs = (gic_irqs + 1) * 32;
- if (gic_irqs > 1020)
- gic_irqs = 1020;
+ if (gic_irqs > GIC_MAX_IRQ)
+ gic_irqs = GIC_MAX_IRQ;
gic->gic_irqs = gic_irqs;
if (handle) { /* DT/ACPI */
@@ -1123,17 +1126,18 @@ static int gic_init_bases(struct gic_chip_data *gic, int irq_start,
* For secondary GICs, skip over PPIs, too.
*/
if (gic == &gic_data[0] && (irq_start & 31) > 0) {
- hwirq_base = 16;
+ hwirq_base = GIC_FIRST_PPI_IRQ;
if (irq_start != -1)
- irq_start = (irq_start & ~31) + 16;
+ irq_start = (irq_start & ~31) +
+ GIC_FIRST_PPI_IRQ;
} else {
- hwirq_base = 32;
+ hwirq_base = GIC_FIRST_SPI_IRQ;
}
gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
- irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
- numa_node_id());
+ irq_base = irq_alloc_descs(irq_start, GIC_FIRST_PPI_IRQ,
+ gic_irqs, numa_node_id());
if (irq_base < 0) {
WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
irq_start);
diff --git a/include/linux/irqchip/arm-gic-common.h b/include/linux/irqchip/arm-gic-common.h
index c647b05..1d37cce 100644
--- a/include/linux/irqchip/arm-gic-common.h
+++ b/include/linux/irqchip/arm-gic-common.h
@@ -13,6 +13,18 @@
#include <linux/types.h>
#include <linux/ioport.h>
+#define GIC_FIRST_SGI_IRQ 0
+#define GIC_LAST_SGI_IRQ 15
+#define GIC_NR_SGI (GIC_LAST_SGI_IRQ - GIC_FIRST_SGI_IRQ + 1)
+#define GIC_FIRST_PPI_IRQ 16
+#define GIC_LAST_PPI_IRQ 31
+#define GIC_NR_PPI (GIC_LAST_PPI_IRQ - GIC_FIRST_PPI_IRQ + 1)
+#define GIC_FIRST_SPI_IRQ 32
+#define GIC_LAST_SPI_IRQ 1019
+#define GIC_MAX_IRQ 1020
+#define GIC_FIRST_SPECIAL_IRQ 1020
+#define GIC_SPURIOUS_IRQ 1023
+
enum gic_type {
GIC_V2,
GIC_V3,
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index e808f8a..894aebf 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -408,6 +408,8 @@
#define ICC_SGI1R_AFFINITY_3_SHIFT 48
#define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_3_SHIFT)
+#define GIC_FIRST_LPI_IRQ 8192
+
#include <asm/arch_gicv3.h>
#ifndef __ASSEMBLY__
--
1.7.9.5
^ permalink raw reply related
* [PATCH] mm: cleanups for printing phys_addr_t and dma_addr_t
From: Miles Chen @ 2017-02-09 5:34 UTC (permalink / raw)
To: Andrew Morton
Cc: linux-kernel, linux-mm, wsd_upstream, linux-mediatek, Miles Chen
cleanup rest of dma_addr_t and phys_addr_t type casting in mm
use %pad for dma_addr_t
use %pa for phys_addr_t
Signed-off-by: Miles Chen <miles.chen@mediatek.com>
---
mm/dmapool.c | 16 ++++++++--------
mm/vmalloc.c | 2 +-
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/mm/dmapool.c b/mm/dmapool.c
index abcbfe8..cef82b8 100644
--- a/mm/dmapool.c
+++ b/mm/dmapool.c
@@ -434,11 +434,11 @@ void dma_pool_free(struct dma_pool *pool, void *vaddr, dma_addr_t dma)
spin_unlock_irqrestore(&pool->lock, flags);
if (pool->dev)
dev_err(pool->dev,
- "dma_pool_free %s, %p (bad vaddr)/%Lx\n",
- pool->name, vaddr, (unsigned long long)dma);
+ "dma_pool_free %s, %p (bad vaddr)/%pad\n",
+ pool->name, vaddr, &dma);
else
- pr_err("dma_pool_free %s, %p (bad vaddr)/%Lx\n",
- pool->name, vaddr, (unsigned long long)dma);
+ pr_err("dma_pool_free %s, %p (bad vaddr)/%pad\n",
+ pool->name, vaddr, &dma);
return;
}
{
@@ -450,11 +450,11 @@ void dma_pool_free(struct dma_pool *pool, void *vaddr, dma_addr_t dma)
}
spin_unlock_irqrestore(&pool->lock, flags);
if (pool->dev)
- dev_err(pool->dev, "dma_pool_free %s, dma %Lx already free\n",
- pool->name, (unsigned long long)dma);
+ dev_err(pool->dev, "dma_pool_free %s, dma %pad already free\n",
+ pool->name, &dma);
else
- pr_err("dma_pool_free %s, dma %Lx already free\n",
- pool->name, (unsigned long long)dma);
+ pr_err("dma_pool_free %s, dma %pad already free\n",
+ pool->name, &dma);
return;
}
}
diff --git a/mm/vmalloc.c b/mm/vmalloc.c
index 3ca82d4..05c594d 100644
--- a/mm/vmalloc.c
+++ b/mm/vmalloc.c
@@ -2654,7 +2654,7 @@ static int s_show(struct seq_file *m, void *p)
seq_printf(m, " pages=%d", v->nr_pages);
if (v->phys_addr)
- seq_printf(m, " phys=%llx", (unsigned long long)v->phys_addr);
+ seq_printf(m, " phys=%pa", &v->phys_addr);
if (v->flags & VM_IOREMAP)
seq_puts(m, " ioremap");
--
1.9.1
--
To unsubscribe, send a message with 'unsubscribe linux-mm' in
the body to majordomo@kvack.org. For more info on Linux MM,
see: http://www.linux-mm.org/ .
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^ permalink raw reply related
* Re: [PATCH v2 3/4] leds: Add LED support for MT6323 PMIC
From: Sean Wang @ 2017-02-09 6:09 UTC (permalink / raw)
To: Jacek Anaszewski
Cc: mark.rutland, devicetree, keyhaede, linux-kernel, robh+dt,
rpurdie, linux-arm-kernel, pavel, matthias.bgg, linux-mediatek,
lee.jones, linux-leds
In-Reply-To: <a410da2e-ce5f-6263-2d7d-79f4b358a848@gmail.com>
Hi Jacek,
All looks make sense. I'll keep following up.
Sean
On Wed, 2017-02-08 at 22:00 +0100, Jacek Anaszewski wrote:
> Hi Sean,
>
> Thanks for the update. Some nitpicking below.
>
> On 02/08/2017 03:19 AM, sean.wang@mediatek.com wrote:
> > From: Sean Wang <sean.wang@mediatek.com>
> >
> > MT6323 PMIC is a multi-function device that includes
> > LED function. It allows attaching upto 4 LEDs which can
>
> s/upto/up to/
>
> > either be on, off or dimmed and/or blinked with the the
> > controller.
> >
> > Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> > ---
> > drivers/leds/Kconfig | 8 +
> > drivers/leds/Makefile | 1 +
> > drivers/leds/leds-mt6323.c | 464 +++++++++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 473 insertions(+)
> > create mode 100644 drivers/leds/leds-mt6323.c
> >
> > diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
> > index c621cbb..30095fc 100644
> > --- a/drivers/leds/Kconfig
> > +++ b/drivers/leds/Kconfig
> > @@ -117,6 +117,14 @@ config LEDS_MIKROTIK_RB532
> > This option enables support for the so called "User LED" of
> > Mikrotik's Routerboard 532.
> >
> > +config LEDS_MT6323
> > + tristate "LED Support for Mediatek MT6323 PMIC"
> > + depends on LEDS_CLASS
> > + depends on MFD_MT6397
> > + help
> > + This option enables support for on-chip LED drivers found on
> > + Mediatek MT6323 PMIC.
> > +
> > config LEDS_S3C24XX
> > tristate "LED Support for Samsung S3C24XX GPIO LEDs"
> > depends on LEDS_CLASS
> > diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
> > index 6b82737..4feb332 100644
> > --- a/drivers/leds/Makefile
> > +++ b/drivers/leds/Makefile
> > @@ -72,6 +72,7 @@ obj-$(CONFIG_LEDS_IS31FL32XX) += leds-is31fl32xx.o
> > obj-$(CONFIG_LEDS_PM8058) += leds-pm8058.o
> > obj-$(CONFIG_LEDS_MLXCPLD) += leds-mlxcpld.o
> > obj-$(CONFIG_LEDS_NIC78BX) += leds-nic78bx.o
> > +obj-$(CONFIG_LEDS_MT6323) += leds-mt6323.o
> >
> > # LED SPI Drivers
> > obj-$(CONFIG_LEDS_DAC124S085) += leds-dac124s085.o
> > diff --git a/drivers/leds/leds-mt6323.c b/drivers/leds/leds-mt6323.c
> > new file mode 100644
> > index 0000000..f6eeb6c
> > --- /dev/null
> > +++ b/drivers/leds/leds-mt6323.c
> > @@ -0,0 +1,464 @@
> > +/*
> > + * LED driver for Mediatek MT6323 PMIC
> > + *
> > + * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +#include <linux/kernel.h>
> > +#include <linux/leds.h>
> > +#include <linux/mfd/mt6323/registers.h>
> > +#include <linux/mfd/mt6397/core.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/regmap.h>
> > +
> > +/*
> > + * Register field for MT6323_TOP_CKPDN0 to enable
> > + * 32K clock common for LED device
>
> Please put a dot at the and of sentence in case of each comment
> starting from capital letter.
>
> > + */
> > +#define MT6323_RG_DRV_32K_CK_PDN BIT(11)
> > +#define MT6323_RG_DRV_32K_CK_PDN_MASK BIT(11)
> > +
> > +/*
> > + * Register field for MT6323_TOP_CKPDN2 to enable
> > + * individual clock for LED device
> > + */
> > +#define MT6323_RG_ISINK_CK_PDN(i) BIT(i)
> > +#define MT6323_RG_ISINK_CK_PDN_MASK(i) BIT(i)
> > +
> > +/*
> > + * Register field for MT6323_TOP_CKCON1 to select
> > + * clock source
> > + */
> > +#define MT6323_RG_ISINK_CK_SEL_MASK(i) (BIT(10) << (i))
> > +
> > +/*
> > + * Register for MT6323_ISINK_CON0 to setup the
> > + * duty cycle of the blink
> > + */
> > +#define MT6323_ISINK_CON0(i) (MT6323_ISINK0_CON0 + 0x8 * (i))
> > +#define MT6323_ISINK_DIM_DUTY_MASK (0x1f << 8)
> > +#define MT6323_ISINK_DIM_DUTY(i) (((i) << 8) & \
> > + MT6323_ISINK_DIM_DUTY_MASK)
> > +
> > +/*
> > + * Register to setup the period of the blink
> > + */
>
> This fits in a single line, so can be wrapped with /* */ like :
>
> /* Register to setup the period of the blink */
>
> The same applies to the other similar occurrences.
>
> > +#define MT6323_ISINK_CON1(i) (MT6323_ISINK0_CON1 + 0x8 * (i))
> > +#define MT6323_ISINK_DIM_FSEL_MASK (0xffff)
> > +#define MT6323_ISINK_DIM_FSEL(i) ((i) & MT6323_ISINK_DIM_FSEL_MASK)
> > +
> > +/*
> > + * Register to control the brightness
> > + */
> > +#define MT6323_ISINK_CON2(i) (MT6323_ISINK0_CON2 + 0x8 * (i))
> > +#define MT6323_ISINK_CH_STEP_SHIFT 12
> > +#define MT6323_ISINK_CH_STEP_MASK (0x7 << 12)
> > +#define MT6323_ISINK_CH_STEP(i) (((i) << 12) & \
> > + MT6323_ISINK_CH_STEP_MASK)
> > +#define MT6323_ISINK_SFSTR0_TC_MASK (0x3 << 1)
> > +#define MT6323_ISINK_SFSTR0_TC(i) (((i) << 1) & \
> > + MT6323_ISINK_SFSTR0_TC_MASK)
> > +#define MT6323_ISINK_SFSTR0_EN_MASK BIT(0)
> > +#define MT6323_ISINK_SFSTR0_EN BIT(0)
> > +
> > +/*
> > + * Register to LED channel enablement
> > + */
> > +#define MT6323_ISINK_CH_EN_MASK(i) BIT(i)
> > +#define MT6323_ISINK_CH_EN(i) BIT(i)
> > +
> > +#define MTK_MAX_PERIOD 10000
> > +#define MTK_MAX_DEVICES 4
>
> s/MAX_DEVICES/MAX_LEDS/
>
> > +#define MTK_MAX_BRIGHTNESS 6
> > +#define MTK_UNIT_DUTY 3125
>
> Why MTK and not MT6323?
>
> > +
> > +struct mtk_leds;
>
> Similarly - let's turn it to struct mt6323_leds.
>
> > +
> > +/**
> > + * struct mtk_led - state container for the LED device
> > + * @id: the identifier in MT6323 LED device
> > + * @parent: the pointer to MT6323 LED controller
> > + * @cdev: LED class device for this LED device
> > + * @current_brightness: current state of the LED device
> > + */
> > +struct mtk_led {
>
> struct mt6323_led
>
> > + int id;
> > + struct mtk_leds *parent;
> > + struct led_classdev cdev;
> > + u8 current_brightness;
> > +};
> > +
> > +/**
> > + * struct mtk_leds - state container for holding LED controller
> > + * of the driver
> > + * @dev: The device pointer
>
> Begin the property description with lowercase, like you're doing it
> in case of struct mtk_led above.
>
> > + * @hw: The underlying hardware providing shared
> > + * bus for the register operations
> > + * @led_num: How much the LED device the controller could control
> > + * @lock: The lock among process context
> > + * @led: The array that contains the state of individual
> > + * LED device
> > + */
> > +struct mtk_leds {
> > + struct device *dev;
> > + struct mt6397_chip *hw;
> > + u8 led_num;
> > + /* protect among process context */
> > + struct mutex lock;
> > + struct mtk_led led[MTK_MAX_DEVICES];
> > +};
> > +
> > +static int mtk_led_hw_off(struct led_classdev *cdev)
>
> Please switch namespacing prefix of all functions from mtk to mt6323.
>
> > +{
> > + struct mtk_led *led = container_of(cdev, struct mtk_led, cdev);
> > + struct mtk_leds *leds = led->parent;
> > + struct regmap *regmap = leds->hw->regmap;
> > + unsigned int status;
> > + int ret;
> > +
> > + status = MT6323_ISINK_CH_EN(led->id);
> > + ret = regmap_update_bits(regmap, MT6323_ISINK_EN_CTRL,
> > + MT6323_ISINK_CH_EN_MASK(led->id), ~status);
> > + if (ret < 0)
> > + return ret;
> > +
> > + usleep_range(100, 300);
> > + ret = regmap_update_bits(regmap, MT6323_TOP_CKPDN2,
> > + MT6323_RG_ISINK_CK_PDN_MASK(led->id),
> > + MT6323_RG_ISINK_CK_PDN(led->id));
> > + if (ret < 0)
> > + return ret;
> > +
> > + return 0;
> > +}
> > +
> > +static int get_mtk_led_hw_brightness(struct led_classdev *cdev)
>
> mt6323_get_led_hw_brightness
>
> > +{
> > + struct mtk_led *led = container_of(cdev, struct mtk_led, cdev);
> > + struct mtk_leds *leds = led->parent;
> > + struct regmap *regmap = leds->hw->regmap;
> > + unsigned int status;
> > + int ret;
> > +
> > + ret = regmap_read(regmap, MT6323_TOP_CKPDN2, &status);
> > + if (ret < 0)
> > + return ret;
> > +
> > + if (status & MT6323_RG_ISINK_CK_PDN_MASK(led->id))
> > + return 0;
> > +
> > + ret = regmap_read(regmap, MT6323_ISINK_EN_CTRL, &status);
> > + if (ret < 0)
> > + return ret;
> > +
> > + if (!(status & MT6323_ISINK_CH_EN(led->id)))
> > + return 0;
> > +
> > + ret = regmap_read(regmap, MT6323_ISINK_CON2(led->id), &status);
> > + if (ret < 0)
> > + return ret;
> > +
> > + return ((status & MT6323_ISINK_CH_STEP_MASK)
> > + >> MT6323_ISINK_CH_STEP_SHIFT) + 1;
> > +}
> > +
> > +static int mtk_led_hw_on(struct led_classdev *cdev)
> > +{
> > + struct mtk_led *led = container_of(cdev, struct mtk_led, cdev);
> > + struct mtk_leds *leds = led->parent;
> > + struct regmap *regmap = leds->hw->regmap;
> > + unsigned int status;
> > + int ret;
> > +
> > + /*
> > + * Setup required clock source, enable the corresponding
> > + * clock and channel and let work with continuous blink as
> > + * the default
> > + */
> > + ret = regmap_update_bits(regmap, MT6323_TOP_CKCON1,
> > + MT6323_RG_ISINK_CK_SEL_MASK(led->id), 0);
> > + if (ret < 0)
> > + return ret;
> > +
> > + status = MT6323_RG_ISINK_CK_PDN(led->id);
> > + ret = regmap_update_bits(regmap, MT6323_TOP_CKPDN2,
> > + MT6323_RG_ISINK_CK_PDN_MASK(led->id),
> > + ~status);
> > + if (ret < 0)
> > + return ret;
> > +
> > + usleep_range(100, 300);
> > +
> > + ret = regmap_update_bits(regmap, MT6323_ISINK_EN_CTRL,
> > + MT6323_ISINK_CH_EN_MASK(led->id),
> > + MT6323_ISINK_CH_EN(led->id));
> > + if (ret < 0)
> > + return ret;
> > +
> > + ret = regmap_update_bits(regmap, MT6323_ISINK_CON2(led->id),
> > + MT6323_ISINK_CH_STEP_MASK,
> > + MT6323_ISINK_CH_STEP(1));
> > + if (ret < 0)
> > + return ret;
> > +
> > + ret = regmap_update_bits(regmap, MT6323_ISINK_CON0(led->id),
> > + MT6323_ISINK_DIM_DUTY_MASK,
> > + MT6323_ISINK_DIM_DUTY(31));
> > + if (ret < 0)
> > + return ret;
> > +
> > + ret = regmap_update_bits(regmap, MT6323_ISINK_CON1(led->id),
> > + MT6323_ISINK_DIM_FSEL_MASK,
> > + MT6323_ISINK_DIM_FSEL(1000));
> > + if (ret < 0)
> > + return ret;
> > +
> > + led->current_brightness = 1;
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_led_set_blink(struct led_classdev *cdev,
> > + unsigned long *delay_on,
> > + unsigned long *delay_off)
> > +{
> > + struct mtk_led *led = container_of(cdev, struct mtk_led, cdev);
> > + struct mtk_leds *leds = led->parent;
> > + struct regmap *regmap = leds->hw->regmap;
> > + u16 period;
> > + u8 duty_cycle, duty_hw;
> > + int ret;
> > +
> > + /*
> > + * Units are in ms , if over the hardware able
>
> s/ms ,/ms,/
>
> > + * to support, fallback into software blink
> > + */
> > + if (*delay_on + *delay_off > MTK_MAX_PERIOD)
> > + return -EINVAL;
> > +
> > + /*
> > + * LED subsystem requires a default user
> > + * friendly blink pattern for the LED so using
> > + * 1Hz duty cycle 50% here if without specific
> > + * value delay_on and delay off being assigned
> > + */
> > + if (*delay_on == 0 && *delay_off == 0) {
> > + *delay_on = 500;
> > + *delay_off = 500;
> > + }
> > +
> > + period = *delay_on + *delay_off;
> > +
> > + /*
> > + * duty_cycle is the percentage of period during
> > + * which the led is ON
> > + */
> > + duty_cycle = 100 * (*delay_on) / period;
> > +
> > + mutex_lock(&leds->lock);
> > +
> > + if (!led->current_brightness) {
> > + ret = mtk_led_hw_on(cdev);
> > + if (ret < 0)
> > + goto out;
> > + }
> > +
> > + duty_hw = DIV_ROUND_CLOSEST(duty_cycle * 1000, MTK_UNIT_DUTY);
> > + ret = regmap_update_bits(regmap, MT6323_ISINK_CON0(led->id),
> > + MT6323_ISINK_DIM_DUTY_MASK,
> > + MT6323_ISINK_DIM_DUTY(duty_hw));
> > + if (ret < 0)
> > + goto out;
> > +
> > + ret = regmap_update_bits(regmap, MT6323_ISINK_CON1(led->id),
> > + MT6323_ISINK_DIM_FSEL_MASK,
> > + MT6323_ISINK_DIM_FSEL(period - 1));
> > +out:
> > + mutex_unlock(&leds->lock);
> > +
> > + return ret;
> > +}
> > +
> > +static int mtk_led_set_brightness(struct led_classdev *cdev,
> > + enum led_brightness brightness)
> > +{
> > + struct mtk_led *led = container_of(cdev, struct mtk_led, cdev);
> > + struct mtk_leds *leds = led->parent;
> > + struct regmap *regmap = leds->hw->regmap;
> > + int ret;
> > +
> > + mutex_lock(&leds->lock);
> > +
> > + if (!led->current_brightness && brightness) {
> > + ret = mtk_led_hw_on(cdev);
> > + if (ret < 0)
> > + goto out;
> > + }
> > +
> > + if (brightness) {
> > + /*
> > + * Setup current output for the corresponding
> > + * brightness level
> > + */
> > + ret = regmap_update_bits(regmap, MT6323_ISINK_CON2(led->id),
> > + MT6323_ISINK_CH_STEP_MASK,
> > + MT6323_ISINK_CH_STEP(brightness - 1));
> > + if (ret < 0)
> > + goto out;
> > +
> > + ret = regmap_update_bits(regmap, MT6323_ISINK_CON2(led->id),
> > + MT6323_ISINK_SFSTR0_TC_MASK |
> > + MT6323_ISINK_SFSTR0_EN_MASK,
> > + MT6323_ISINK_SFSTR0_TC(2) |
> > + MT6323_ISINK_SFSTR0_EN);
> > + if (ret < 0)
> > + goto out;
> > + } else {
> > + ret = mtk_led_hw_off(cdev);
> > + if (ret < 0)
> > + goto out;
> > + }
> > +
> > + led->current_brightness = brightness;
> > +out:
> > + mutex_unlock(&leds->lock);
> > +
> > + return ret;
> > +}
> > +
> > +static int mt6323_led_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct device_node *np = pdev->dev.of_node;
> > + struct device_node *child;
> > + struct mt6397_chip *hw = dev_get_drvdata(pdev->dev.parent);
> > + struct mtk_leds *leds;
> > + int ret, i = 0, count;
> > + const char *state;
> > + unsigned int status;
> > +
> > + count = of_get_child_count(np);
> > + if (!count)
> > + return -ENODEV;
> > +
> > + /*
> > + * The number the LEDs on MT6323 could be support is
> > + * up to MTK_MAX_DEVICES
> > + */
>
> We're going to change the macro name to MT6323_MAX_LEDS - it will be
> self-explanatory then, and the comment will be redundant here.
>
> > + count = (count <= MTK_MAX_DEVICES) ? count : MTK_MAX_DEVICES;
> > +
> > + leds = devm_kzalloc(dev, sizeof(struct mtk_leds) +
> > + sizeof(struct mtk_led) * count,
> > + GFP_KERNEL);
> > + if (!leds)
> > + return -ENOMEM;
> > +
> > + platform_set_drvdata(pdev, leds);
> > + leds->dev = dev;
> > +
> > + /*
> > + * leds->hw points to the underlying bus for the register
> > + * controlled
> > + */
> > + leds->hw = hw;
> > + mutex_init(&leds->lock);
> > + leds->led_num = count;
> > +
> > + status = MT6323_RG_DRV_32K_CK_PDN;
> > + ret = regmap_update_bits(leds->hw->regmap, MT6323_TOP_CKPDN0,
> > + MT6323_RG_DRV_32K_CK_PDN_MASK, ~status);
> > + if (ret < 0) {
> > + dev_err(leds->dev,
> > + "Failed to update MT6323_TOP_CKPDN0 Register\n");
> > + return ret;
> > + }
> > +
> > + for_each_available_child_of_node(np, child) {
> > + leds->led[i].cdev.name =
> > + of_get_property(child, "label", NULL) ? :
> > + child->name;
> > + leds->led[i].cdev.default_trigger = of_get_property(child,
> > + "linux,default-trigger",
> > + NULL);
> > + leds->led[i].cdev.max_brightness = MTK_MAX_BRIGHTNESS;
> > + leds->led[i].cdev.brightness_set_blocking =
> > + mtk_led_set_brightness;
> > + leds->led[i].cdev.blink_set = mtk_led_set_blink;
> > + leds->led[i].id = i;
> > + leds->led[i].parent = leds;
> > + state = of_get_property(child, "default-state", NULL);
> > + if (state) {
> > + if (!strcmp(state, "keep")) {
> > + leds->led[i].current_brightness =
> > + get_mtk_led_hw_brightness(&leds->led[i].cdev);
> > + } else if (!strcmp(state, "on")) {
> > + mtk_led_set_brightness(&leds->led[i].cdev, 1);
> > + } else {
> > + mtk_led_set_brightness(&leds->led[i].cdev,
> > + 0);
> > + }
> > + }
> > + ret = devm_led_classdev_register(dev, &leds->led[i].cdev);
> > + if (ret) {
> > + dev_err(&pdev->dev, "Failed to register LED: %d\n",
> > + ret);
> > + return ret;
> > + }
> > + leds->led[i].cdev.dev->of_node = child;
> > + i++;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int mt6323_led_remove(struct platform_device *pdev)
> > +{
> > + struct mtk_leds *leds = platform_get_drvdata(pdev);
> > + int i;
> > +
> > + /*
> > + * Turned the LED to OFF state on driver removal
>
> How about:
>
> /* Turn the LEDs off on driver removal. */
>
>
> > + */
> > + for (i = 0 ; i < leds->led_num ; i++)
> > + mtk_led_hw_off(&leds->led[i].cdev);
> > +
> > + regmap_update_bits(leds->hw->regmap, MT6323_TOP_CKPDN0,
> > + MT6323_RG_DRV_32K_CK_PDN_MASK,
> > + MT6323_RG_DRV_32K_CK_PDN);
> > +
> > + mutex_destroy(&leds->lock);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id mt6323_led_dt_match[] = {
> > + { .compatible = "mediatek,mt6323-led" },
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, mt6323_led_dt_match);
> > +
> > +static struct platform_driver mt6323_led_driver = {
> > + .probe = mt6323_led_probe,
> > + .remove = mt6323_led_remove,
> > + .driver = {
> > + .name = "mt6323-led",
> > + .of_match_table = mt6323_led_dt_match,
> > + },
> > +};
> > +
> > +module_platform_driver(mt6323_led_driver);
> > +
> > +MODULE_DESCRIPTION("LED driver for Mediatek MT6323 PMIC");
> > +MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
> > +MODULE_LICENSE("GPL");
> >
>
^ permalink raw reply
* Re: [PATCH] arm64: use is_vmalloc_addr
From: kbuild test robot @ 2017-02-09 8:37 UTC (permalink / raw)
Cc: kbuild-all, Catalin Marinas, Will Deacon, linux-arm-kernel,
linux-kernel, linux-mediatek, wsd_upstream, Miles Chen
In-Reply-To: <1486606807-32097-1-git-send-email-miles.chen@mediatek.com>
[-- Attachment #1: Type: text/plain, Size: 2363 bytes --]
Hi Miles,
[auto build test WARNING on arm64/for-next/core]
[also build test WARNING on v4.10-rc7 next-20170208]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Miles-Chen/arm64-use-is_vmalloc_addr/20170209-103100
base: https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git for-next/core
config: arm64-defconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64
All warnings (new ones prefixed by >>):
arch/arm64/mm/ioremap.c: In function '__iounmap':
>> arch/arm64/mm/ioremap.c:91:22: warning: passing argument 1 of 'is_vmalloc_addr' makes pointer from integer without a cast [-Wint-conversion]
if (is_vmalloc_addr(addr))
^~~~
In file included from arch/arm64/mm/ioremap.c:24:0:
include/linux/mm.h:472:20: note: expected 'const void *' but argument is of type 'long unsigned int'
static inline bool is_vmalloc_addr(const void *x)
^~~~~~~~~~~~~~~
vim +/is_vmalloc_addr +91 arch/arm64/mm/ioremap.c
75
76 void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot)
77 {
78 return __ioremap_caller(phys_addr, size, prot,
79 __builtin_return_address(0));
80 }
81 EXPORT_SYMBOL(__ioremap);
82
83 void __iounmap(volatile void __iomem *io_addr)
84 {
85 unsigned long addr = (unsigned long)io_addr & PAGE_MASK;
86
87 /*
88 * We could get an address outside vmalloc range in case
89 * of ioremap_cache() reusing a RAM mapping.
90 */
> 91 if (is_vmalloc_addr(addr))
92 vunmap((void *)addr);
93 }
94 EXPORT_SYMBOL(__iounmap);
95
96 void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size)
97 {
98 /* For normal memory we already have a cacheable mapping. */
99 if (pfn_valid(__phys_to_pfn(phys_addr)))
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 33971 bytes --]
^ permalink raw reply
* Re: [PATCH v2 02/10] irqchip: mtk-sysirq: extend intpol base to arbitrary number
From: Marc Zyngier @ 2017-02-09 9:03 UTC (permalink / raw)
To: Mars Cheng, Matthias Brugger
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, CC Hwang,
wsd_upstream-NuS5LvNUpcJWk0Htik3J/w, Will Deacon, Loda Chou,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Jades Shih,
linux-clk-u79uwXL29TY76Z2rM5mHXA, Miles Chen,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, My Chuang,
Yingjoe Chen, Thomas Gleixner, Stephen Boyd, Chieh-Jay Liu
In-Reply-To: <1486383336-16892-3-git-send-email-mars.cheng-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
On 06/02/17 12:15, Mars Cheng wrote:
> Originally driver only supports one base. However, MT6797 has
> more than one bases to configure interrupt polarity. To support
> possible design change, here comes a solution to use arbitrary
> number of bases.
>
> Signed-off-by: Mars Cheng <mars.cheng-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
> drivers/irqchip/irq-mtk-sysirq.c | 71 +++++++++++++++++++++++++++-----------
> 1 file changed, 50 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/irqchip/irq-mtk-sysirq.c b/drivers/irqchip/irq-mtk-sysirq.c
> index 63ac73b..2645706 100644
> --- a/drivers/irqchip/irq-mtk-sysirq.c
> +++ b/drivers/irqchip/irq-mtk-sysirq.c
> @@ -24,7 +24,9 @@
>
> struct mtk_sysirq_chip_data {
> spinlock_t lock;
> - void __iomem *intpol_base;
> + u32 nr_intpol_bases;
> + void __iomem **intpol_bases;
> + u32 *intpol_words;
> };
>
> static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
> @@ -33,13 +35,15 @@ static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
> struct mtk_sysirq_chip_data *chip_data = data->chip_data;
> u32 offset, reg_index, value;
> unsigned long flags;
> - int ret;
> + int ret, i;
>
> offset = hwirq & 0x1f;
> reg_index = hwirq >> 5;
> + for (i = 0; reg_index >= chip_data->intpol_words[i]; i++)
> + reg_index -= chip_data->intpol_words[i];
Two questions:
- What guarantees that two successive regions deal with consecutive
interrupts? For example, if I have region A that deals with interrupts
0-31, what guarantees that region B covers 32-63?
- Given that there is a static relation between a region and a hwirq,
can't you compute this relation at init time, and let set_type be a fast
path?
>
> spin_lock_irqsave(&chip_data->lock, flags);
> - value = readl_relaxed(chip_data->intpol_base + reg_index * 4);
> + value = readl_relaxed(chip_data->intpol_bases[i] + reg_index * 4);
> if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_EDGE_FALLING) {
> if (type == IRQ_TYPE_LEVEL_LOW)
> type = IRQ_TYPE_LEVEL_HIGH;
> @@ -49,7 +53,8 @@ static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
> } else {
> value &= ~(1 << offset);
> }
> - writel(value, chip_data->intpol_base + reg_index * 4);
> +
> + writel(value, chip_data->intpol_bases[i] + reg_index * 4);
Why do you have a writel here, while you're using relaxed accessors
otherwise? Is there anything else that needs to be made visible to the
irqchip?
>
> data = data->parent_data;
> ret = data->chip->irq_set_type(data, type);
> @@ -124,8 +129,7 @@ static int __init mtk_sysirq_of_init(struct device_node *node,
> {
> struct irq_domain *domain, *domain_parent;
> struct mtk_sysirq_chip_data *chip_data;
> - int ret, size, intpol_num;
> - struct resource res;
> + int ret, size, intpol_num = 0, nr_intpol_bases, i;
>
> domain_parent = irq_find_host(parent);
> if (!domain_parent) {
> @@ -133,36 +137,61 @@ static int __init mtk_sysirq_of_init(struct device_node *node,
> return -EINVAL;
> }
>
> - ret = of_address_to_resource(node, 0, &res);
> - if (ret)
> - return ret;
> -
> chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL);
> if (!chip_data)
> return -ENOMEM;
>
> - size = resource_size(&res);
> - intpol_num = size * 8;
> - chip_data->intpol_base = ioremap(res.start, size);
> - if (!chip_data->intpol_base) {
> - pr_err("mtk_sysirq: unable to map sysirq register\n");
> - ret = -ENXIO;
> - goto out_free;
> + if (of_property_read_u32(node, "#intpol-bases", &nr_intpol_bases))
> + nr_intpol_bases = 1;
> +
> + chip_data->intpol_words =
> + kcalloc(nr_intpol_bases, sizeof(u32), GFP_KERNEL);
Please keep the assignment on a single line.
> + if (!chip_data->intpol_words) {
> + ret = -ENOMEM;
> + goto out_free_chip;
> + }
> +
> + chip_data->intpol_bases =
> + kcalloc(nr_intpol_bases, sizeof(void __iomem *), GFP_KERNEL);
Same here.
> + if (!chip_data->intpol_bases) {
> + ret = -ENOMEM;
> + goto out_free_intpol_words;
> + }
> +
> + for (i = 0; i < nr_intpol_bases; i++) {
> + struct resource res;
> +
> + ret = of_address_to_resource(node, i, &res);
> + size = resource_size(&res);
> + intpol_num += size * 8;
> + chip_data->intpol_words[i] = size / 4;
> + chip_data->intpol_bases[i] = of_iomap(node, i);
> + if (ret || !chip_data->intpol_bases[i]) {
> + pr_err("%s: couldn't map region %d\n",
> + node->full_name, i);
> + ret = -ENODEV;
> + goto out_free_intpol;
> + }
> }
>
> domain = irq_domain_add_hierarchy(domain_parent, 0, intpol_num, node,
> &sysirq_domain_ops, chip_data);
> if (!domain) {
> ret = -ENOMEM;
> - goto out_unmap;
> + goto out_free_intpol;
> }
> spin_lock_init(&chip_data->lock);
>
> return 0;
>
> -out_unmap:
> - iounmap(chip_data->intpol_base);
> -out_free:
> +out_free_intpol:
> + for (i = 0; i < nr_intpol_bases; i++)
> + if (chip_data->intpol_bases[i])
> + iounmap(chip_data->intpol_bases[i]);
> + kfree(chip_data->intpol_bases);
> +out_free_intpol_words:
> + kfree(chip_data->intpol_words);
> +out_free_chip:
> kfree(chip_data);
> return ret;
> }
>
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* Re: [PATCH v2 02/10] irqchip: mtk-sysirq: extend intpol base to arbitrary number
From: Mars Cheng @ 2017-02-09 9:31 UTC (permalink / raw)
To: Marc Zyngier
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, CC Hwang,
wsd_upstream-NuS5LvNUpcJWk0Htik3J/w, Will Deacon, Loda Chou,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Jades Shih,
linux-clk-u79uwXL29TY76Z2rM5mHXA, Miles Chen,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, My Chuang,
Matthias Brugger, Yingjoe Chen, Thomas Gleixner, Stephen Boyd,
Chieh-Jay Liu
In-Reply-To: <2079ad73-6d7d-d20f-2945-68ea9fbd9b50-5wv7dgnIgG8@public.gmane.org>
On Thu, 2017-02-09 at 09:03 +0000, Marc Zyngier wrote:
> On 06/02/17 12:15, Mars Cheng wrote:
> > Originally driver only supports one base. However, MT6797 has
> > more than one bases to configure interrupt polarity. To support
> > possible design change, here comes a solution to use arbitrary
> > number of bases.
> >
> > Signed-off-by: Mars Cheng <mars.cheng-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > ---
> > drivers/irqchip/irq-mtk-sysirq.c | 71 +++++++++++++++++++++++++++-----------
> > 1 file changed, 50 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/irqchip/irq-mtk-sysirq.c b/drivers/irqchip/irq-mtk-sysirq.c
> > index 63ac73b..2645706 100644
> > --- a/drivers/irqchip/irq-mtk-sysirq.c
> > +++ b/drivers/irqchip/irq-mtk-sysirq.c
> > @@ -24,7 +24,9 @@
> >
> > struct mtk_sysirq_chip_data {
> > spinlock_t lock;
> > - void __iomem *intpol_base;
> > + u32 nr_intpol_bases;
> > + void __iomem **intpol_bases;
> > + u32 *intpol_words;
> > };
> >
> > static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
> > @@ -33,13 +35,15 @@ static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
> > struct mtk_sysirq_chip_data *chip_data = data->chip_data;
> > u32 offset, reg_index, value;
> > unsigned long flags;
> > - int ret;
> > + int ret, i;
> >
> > offset = hwirq & 0x1f;
> > reg_index = hwirq >> 5;
> > + for (i = 0; reg_index >= chip_data->intpol_words[i]; i++)
> > + reg_index -= chip_data->intpol_words[i];
>
> Two questions:
> - What guarantees that two successive regions deal with consecutive
> interrupts? For example, if I have region A that deals with interrupts
> 0-31, what guarantees that region B covers 32-63?
It is guaranteed by mediatek's chip design team. For those chips with
multiple bases, they all have the consecutive interrupts in the next
region.
> - Given that there is a static relation between a region and a hwirq,
> can't you compute this relation at init time, and let set_type be a fast
> path?
>
sure, I can do this to optimize set_type. will do it in v3
> >
> > spin_lock_irqsave(&chip_data->lock, flags);
> > - value = readl_relaxed(chip_data->intpol_base + reg_index * 4);
> > + value = readl_relaxed(chip_data->intpol_bases[i] + reg_index * 4);
> > if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_EDGE_FALLING) {
> > if (type == IRQ_TYPE_LEVEL_LOW)
> > type = IRQ_TYPE_LEVEL_HIGH;
> > @@ -49,7 +53,8 @@ static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
> > } else {
> > value &= ~(1 << offset);
> > }
> > - writel(value, chip_data->intpol_base + reg_index * 4);
> > +
> > + writel(value, chip_data->intpol_bases[i] + reg_index * 4);
>
> Why do you have a writel here, while you're using relaxed accessors
> otherwise? Is there anything else that needs to be made visible to the
> irqchip?
>
before we call spin_unlock_irqrestore() in the end of set_type, polarity
should take effect so we use writel() here. This patch did not change
the usage.
> >
> > data = data->parent_data;
> > ret = data->chip->irq_set_type(data, type);
> > @@ -124,8 +129,7 @@ static int __init mtk_sysirq_of_init(struct device_node *node,
> > {
> > struct irq_domain *domain, *domain_parent;
> > struct mtk_sysirq_chip_data *chip_data;
> > - int ret, size, intpol_num;
> > - struct resource res;
> > + int ret, size, intpol_num = 0, nr_intpol_bases, i;
> >
> > domain_parent = irq_find_host(parent);
> > if (!domain_parent) {
> > @@ -133,36 +137,61 @@ static int __init mtk_sysirq_of_init(struct device_node *node,
> > return -EINVAL;
> > }
> >
> > - ret = of_address_to_resource(node, 0, &res);
> > - if (ret)
> > - return ret;
> > -
> > chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL);
> > if (!chip_data)
> > return -ENOMEM;
> >
> > - size = resource_size(&res);
> > - intpol_num = size * 8;
> > - chip_data->intpol_base = ioremap(res.start, size);
> > - if (!chip_data->intpol_base) {
> > - pr_err("mtk_sysirq: unable to map sysirq register\n");
> > - ret = -ENXIO;
> > - goto out_free;
> > + if (of_property_read_u32(node, "#intpol-bases", &nr_intpol_bases))
> > + nr_intpol_bases = 1;
> > +
> > + chip_data->intpol_words =
> > + kcalloc(nr_intpol_bases, sizeof(u32), GFP_KERNEL);
>
> Please keep the assignment on a single line.
>
Got it, but another warning (prefer 75 char in single line) would pop
up. Would you still like me to keep it on a single line?
> > + if (!chip_data->intpol_words) {
> > + ret = -ENOMEM;
> > + goto out_free_chip;
> > + }
> > +
> > + chip_data->intpol_bases =
> > + kcalloc(nr_intpol_bases, sizeof(void __iomem *), GFP_KERNEL);
>
> Same here.
>
> > + if (!chip_data->intpol_bases) {
> > + ret = -ENOMEM;
> > + goto out_free_intpol_words;
> > + }
> > +
> > + for (i = 0; i < nr_intpol_bases; i++) {
> > + struct resource res;
> > +
> > + ret = of_address_to_resource(node, i, &res);
> > + size = resource_size(&res);
> > + intpol_num += size * 8;
> > + chip_data->intpol_words[i] = size / 4;
> > + chip_data->intpol_bases[i] = of_iomap(node, i);
> > + if (ret || !chip_data->intpol_bases[i]) {
> > + pr_err("%s: couldn't map region %d\n",
> > + node->full_name, i);
> > + ret = -ENODEV;
> > + goto out_free_intpol;
> > + }
> > }
> >
> > domain = irq_domain_add_hierarchy(domain_parent, 0, intpol_num, node,
> > &sysirq_domain_ops, chip_data);
> > if (!domain) {
> > ret = -ENOMEM;
> > - goto out_unmap;
> > + goto out_free_intpol;
> > }
> > spin_lock_init(&chip_data->lock);
> >
> > return 0;
> >
> > -out_unmap:
> > - iounmap(chip_data->intpol_base);
> > -out_free:
> > +out_free_intpol:
> > + for (i = 0; i < nr_intpol_bases; i++)
> > + if (chip_data->intpol_bases[i])
> > + iounmap(chip_data->intpol_bases[i]);
> > + kfree(chip_data->intpol_bases);
> > +out_free_intpol_words:
> > + kfree(chip_data->intpol_words);
> > +out_free_chip:
> > kfree(chip_data);
> > return ret;
> > }
> >
>
> Thanks,
>
> M.
Thanks,
Mars Cheng
^ permalink raw reply
* Re: [PATCH v2 02/10] irqchip: mtk-sysirq: extend intpol base to arbitrary number
From: Marc Zyngier @ 2017-02-09 9:43 UTC (permalink / raw)
To: Mars Cheng
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, CC Hwang,
wsd_upstream-NuS5LvNUpcJWk0Htik3J/w, Will Deacon, Loda Chou,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Jades Shih,
linux-clk-u79uwXL29TY76Z2rM5mHXA, Miles Chen,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, My Chuang,
Matthias Brugger, Yingjoe Chen, Thomas Gleixner, Stephen Boyd,
Chieh-Jay Liu
In-Reply-To: <1486632694.8348.14.camel@mtkswgap22>
On 09/02/17 09:31, Mars Cheng wrote:
> On Thu, 2017-02-09 at 09:03 +0000, Marc Zyngier wrote:
>> On 06/02/17 12:15, Mars Cheng wrote:
>>> Originally driver only supports one base. However, MT6797 has
>>> more than one bases to configure interrupt polarity. To support
>>> possible design change, here comes a solution to use arbitrary
>>> number of bases.
>>>
>>> Signed-off-by: Mars Cheng <mars.cheng-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
>>> ---
>>> drivers/irqchip/irq-mtk-sysirq.c | 71 +++++++++++++++++++++++++++-----------
>>> 1 file changed, 50 insertions(+), 21 deletions(-)
>>>
>>> diff --git a/drivers/irqchip/irq-mtk-sysirq.c b/drivers/irqchip/irq-mtk-sysirq.c
>>> index 63ac73b..2645706 100644
>>> --- a/drivers/irqchip/irq-mtk-sysirq.c
>>> +++ b/drivers/irqchip/irq-mtk-sysirq.c
>>> @@ -24,7 +24,9 @@
>>>
>>> struct mtk_sysirq_chip_data {
>>> spinlock_t lock;
>>> - void __iomem *intpol_base;
>>> + u32 nr_intpol_bases;
>>> + void __iomem **intpol_bases;
>>> + u32 *intpol_words;
>>> };
>>>
>>> static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
>>> @@ -33,13 +35,15 @@ static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
>>> struct mtk_sysirq_chip_data *chip_data = data->chip_data;
>>> u32 offset, reg_index, value;
>>> unsigned long flags;
>>> - int ret;
>>> + int ret, i;
>>>
>>> offset = hwirq & 0x1f;
>>> reg_index = hwirq >> 5;
>>> + for (i = 0; reg_index >= chip_data->intpol_words[i]; i++)
>>> + reg_index -= chip_data->intpol_words[i];
>>
>> Two questions:
>> - What guarantees that two successive regions deal with consecutive
>> interrupts? For example, if I have region A that deals with interrupts
>> 0-31, what guarantees that region B covers 32-63?
>
> It is guaranteed by mediatek's chip design team. For those chips with
> multiple bases, they all have the consecutive interrupts in the next
> region.
Hum. OK. We'll see how long this holds true, I suppose.
>
>> - Given that there is a static relation between a region and a hwirq,
>> can't you compute this relation at init time, and let set_type be a fast
>> path?
>>
>
> sure, I can do this to optimize set_type. will do it in v3
>
>>>
>>> spin_lock_irqsave(&chip_data->lock, flags);
>>> - value = readl_relaxed(chip_data->intpol_base + reg_index * 4);
>>> + value = readl_relaxed(chip_data->intpol_bases[i] + reg_index * 4);
>>> if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_EDGE_FALLING) {
>>> if (type == IRQ_TYPE_LEVEL_LOW)
>>> type = IRQ_TYPE_LEVEL_HIGH;
>>> @@ -49,7 +53,8 @@ static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
>>> } else {
>>> value &= ~(1 << offset);
>>> }
>>> - writel(value, chip_data->intpol_base + reg_index * 4);
>>> +
>>> + writel(value, chip_data->intpol_bases[i] + reg_index * 4);
>>
>> Why do you have a writel here, while you're using relaxed accessors
>> otherwise? Is there anything else that needs to be made visible to the
>> irqchip?
>>
>
> before we call spin_unlock_irqrestore() in the end of set_type, polarity
> should take effect so we use writel() here. This patch did not change
> the usage.
That's not what I mean. writel has a DSB *before* performing the write
to the device. Do you have any write (to memory) that needs to be made
visible to the irqchip before the write to the register occurs?
Looking at the code, I'd say no. This is a standard device
read-modify-write sequence, no in-memory data that needs to make it
before the write occurs.
So please turn this into a writel_relaxed.
>
>>>
>>> data = data->parent_data;
>>> ret = data->chip->irq_set_type(data, type);
>>> @@ -124,8 +129,7 @@ static int __init mtk_sysirq_of_init(struct device_node *node,
>>> {
>>> struct irq_domain *domain, *domain_parent;
>>> struct mtk_sysirq_chip_data *chip_data;
>>> - int ret, size, intpol_num;
>>> - struct resource res;
>>> + int ret, size, intpol_num = 0, nr_intpol_bases, i;
>>>
>>> domain_parent = irq_find_host(parent);
>>> if (!domain_parent) {
>>> @@ -133,36 +137,61 @@ static int __init mtk_sysirq_of_init(struct device_node *node,
>>> return -EINVAL;
>>> }
>>>
>>> - ret = of_address_to_resource(node, 0, &res);
>>> - if (ret)
>>> - return ret;
>>> -
>>> chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL);
>>> if (!chip_data)
>>> return -ENOMEM;
>>>
>>> - size = resource_size(&res);
>>> - intpol_num = size * 8;
>>> - chip_data->intpol_base = ioremap(res.start, size);
>>> - if (!chip_data->intpol_base) {
>>> - pr_err("mtk_sysirq: unable to map sysirq register\n");
>>> - ret = -ENXIO;
>>> - goto out_free;
>>> + if (of_property_read_u32(node, "#intpol-bases", &nr_intpol_bases))
>>> + nr_intpol_bases = 1;
>>> +
>>> + chip_data->intpol_words =
>>> + kcalloc(nr_intpol_bases, sizeof(u32), GFP_KERNEL);
>>
>> Please keep the assignment on a single line.
>>
>
> Got it, but another warning (prefer 75 char in single line) would pop
> up. Would you still like me to keep it on a single line?
rm scripts/checkpatch.pl
Look, no warning! More seriously, if you're really worried about this,
you can reformat it:
chip_data->intpol_words = kcalloc(nr_intpol_bases,
sizeof(u32), GFP_KERNEL);
like this.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* Re: [PATCH v2 02/10] irqchip: mtk-sysirq: extend intpol base to arbitrary number
From: Mars Cheng @ 2017-02-09 9:49 UTC (permalink / raw)
To: Marc Zyngier
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, CC Hwang,
wsd_upstream-NuS5LvNUpcJWk0Htik3J/w, Will Deacon, Loda Chou,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Jades Shih,
linux-clk-u79uwXL29TY76Z2rM5mHXA, Miles Chen,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, My Chuang,
Matthias Brugger, Yingjoe Chen, Thomas Gleixner, Stephen Boyd,
Chieh-Jay Liu
In-Reply-To: <504b27fa-412b-8f21-d9c3-5e2c7dc67dd5-5wv7dgnIgG8@public.gmane.org>
On Thu, 2017-02-09 at 09:43 +0000, Marc Zyngier wrote:
> On 09/02/17 09:31, Mars Cheng wrote:
> > On Thu, 2017-02-09 at 09:03 +0000, Marc Zyngier wrote:
> >> On 06/02/17 12:15, Mars Cheng wrote:
> >>> Originally driver only supports one base. However, MT6797 has
> >>> more than one bases to configure interrupt polarity. To support
> >>> possible design change, here comes a solution to use arbitrary
> >>> number of bases.
> >>>
> >>> Signed-off-by: Mars Cheng <mars.cheng-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> >>> ---
> >>> drivers/irqchip/irq-mtk-sysirq.c | 71 +++++++++++++++++++++++++++-----------
> >>> 1 file changed, 50 insertions(+), 21 deletions(-)
> >>>
> >>> diff --git a/drivers/irqchip/irq-mtk-sysirq.c b/drivers/irqchip/irq-mtk-sysirq.c
> >>> index 63ac73b..2645706 100644
> >>> --- a/drivers/irqchip/irq-mtk-sysirq.c
> >>> +++ b/drivers/irqchip/irq-mtk-sysirq.c
> >>> @@ -24,7 +24,9 @@
> >>>
> >>> struct mtk_sysirq_chip_data {
> >>> spinlock_t lock;
> >>> - void __iomem *intpol_base;
> >>> + u32 nr_intpol_bases;
> >>> + void __iomem **intpol_bases;
> >>> + u32 *intpol_words;
> >>> };
> >>>
> >>> static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
> >>> @@ -33,13 +35,15 @@ static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
> >>> struct mtk_sysirq_chip_data *chip_data = data->chip_data;
> >>> u32 offset, reg_index, value;
> >>> unsigned long flags;
> >>> - int ret;
> >>> + int ret, i;
> >>>
> >>> offset = hwirq & 0x1f;
> >>> reg_index = hwirq >> 5;
> >>> + for (i = 0; reg_index >= chip_data->intpol_words[i]; i++)
> >>> + reg_index -= chip_data->intpol_words[i];
> >>
> >> Two questions:
> >> - What guarantees that two successive regions deal with consecutive
> >> interrupts? For example, if I have region A that deals with interrupts
> >> 0-31, what guarantees that region B covers 32-63?
> >
> > It is guaranteed by mediatek's chip design team. For those chips with
> > multiple bases, they all have the consecutive interrupts in the next
> > region.
>
> Hum. OK. We'll see how long this holds true, I suppose.
>
> >
> >> - Given that there is a static relation between a region and a hwirq,
> >> can't you compute this relation at init time, and let set_type be a fast
> >> path?
> >>
> >
> > sure, I can do this to optimize set_type. will do it in v3
> >
> >>>
> >>> spin_lock_irqsave(&chip_data->lock, flags);
> >>> - value = readl_relaxed(chip_data->intpol_base + reg_index * 4);
> >>> + value = readl_relaxed(chip_data->intpol_bases[i] + reg_index * 4);
> >>> if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_EDGE_FALLING) {
> >>> if (type == IRQ_TYPE_LEVEL_LOW)
> >>> type = IRQ_TYPE_LEVEL_HIGH;
> >>> @@ -49,7 +53,8 @@ static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
> >>> } else {
> >>> value &= ~(1 << offset);
> >>> }
> >>> - writel(value, chip_data->intpol_base + reg_index * 4);
> >>> +
> >>> + writel(value, chip_data->intpol_bases[i] + reg_index * 4);
> >>
> >> Why do you have a writel here, while you're using relaxed accessors
> >> otherwise? Is there anything else that needs to be made visible to the
> >> irqchip?
> >>
> >
> > before we call spin_unlock_irqrestore() in the end of set_type, polarity
> > should take effect so we use writel() here. This patch did not change
> > the usage.
>
> That's not what I mean. writel has a DSB *before* performing the write
> to the device. Do you have any write (to memory) that needs to be made
> visible to the irqchip before the write to the register occurs?
>
> Looking at the code, I'd say no. This is a standard device
> read-modify-write sequence, no in-memory data that needs to make it
> before the write occurs.
>
> So please turn this into a writel_relaxed.
Got it, you are right. will fix this in v3.
>
> >
> >>>
> >>> data = data->parent_data;
> >>> ret = data->chip->irq_set_type(data, type);
> >>> @@ -124,8 +129,7 @@ static int __init mtk_sysirq_of_init(struct device_node *node,
> >>> {
> >>> struct irq_domain *domain, *domain_parent;
> >>> struct mtk_sysirq_chip_data *chip_data;
> >>> - int ret, size, intpol_num;
> >>> - struct resource res;
> >>> + int ret, size, intpol_num = 0, nr_intpol_bases, i;
> >>>
> >>> domain_parent = irq_find_host(parent);
> >>> if (!domain_parent) {
> >>> @@ -133,36 +137,61 @@ static int __init mtk_sysirq_of_init(struct device_node *node,
> >>> return -EINVAL;
> >>> }
> >>>
> >>> - ret = of_address_to_resource(node, 0, &res);
> >>> - if (ret)
> >>> - return ret;
> >>> -
> >>> chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL);
> >>> if (!chip_data)
> >>> return -ENOMEM;
> >>>
> >>> - size = resource_size(&res);
> >>> - intpol_num = size * 8;
> >>> - chip_data->intpol_base = ioremap(res.start, size);
> >>> - if (!chip_data->intpol_base) {
> >>> - pr_err("mtk_sysirq: unable to map sysirq register\n");
> >>> - ret = -ENXIO;
> >>> - goto out_free;
> >>> + if (of_property_read_u32(node, "#intpol-bases", &nr_intpol_bases))
> >>> + nr_intpol_bases = 1;
> >>> +
> >>> + chip_data->intpol_words =
> >>> + kcalloc(nr_intpol_bases, sizeof(u32), GFP_KERNEL);
> >>
> >> Please keep the assignment on a single line.
> >>
> >
> > Got it, but another warning (prefer 75 char in single line) would pop
> > up. Would you still like me to keep it on a single line?
>
> rm scripts/checkpatch.pl
>
> Look, no warning! More seriously, if you're really worried about this,
> you can reformat it:
>
> chip_data->intpol_words = kcalloc(nr_intpol_bases,
> sizeof(u32), GFP_KERNEL);
>
> like this.
>
Got it, will fix it in v3. Thanks. :-)
> Thanks,
>
> M.
^ permalink raw reply
* Re: [PATCH] arm64: use is_vmalloc_addr
From: Miles Chen @ 2017-02-09 11:28 UTC (permalink / raw)
To: kbuild test robot
Cc: wsd_upstream, Catalin Marinas, Will Deacon, linux-kernel,
linux-mediatek, kbuild-all, linux-arm-kernel
In-Reply-To: <201702091600.7Yg9Yj0D%fengguang.wu@intel.com>
On Thu, 2017-02-09 at 16:37 +0800, kbuild test robot wrote:
> Hi Miles,
>
> [auto build test WARNING on arm64/for-next/core]
> [also build test WARNING on v4.10-rc7 next-20170208]
> [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
>
> url: https://github.com/0day-ci/linux/commits/Miles-Chen/arm64-use-is_vmalloc_addr/20170209-103100
> base: https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git for-next/core
> config: arm64-defconfig (attached as .config)
> compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
> reproduce:
> wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # save the attached .config to linux build tree
> make.cross ARCH=arm64
>
> All warnings (new ones prefixed by >>):
>
> arch/arm64/mm/ioremap.c: In function '__iounmap':
> >> arch/arm64/mm/ioremap.c:91:22: warning: passing argument 1 of 'is_vmalloc_addr' makes pointer from integer without a cast [-Wint-conversion]
> if (is_vmalloc_addr(addr))
> ^~~~
> In file included from arch/arm64/mm/ioremap.c:24:0:
> include/linux/mm.h:472:20: note: expected 'const void *' but argument is of type 'long unsigned int'
> static inline bool is_vmalloc_addr(const void *x)
> ^~~~~~~~~~~~~~~
>
Sorry for that. I'll send patch v2 without the build warning.
> vim +/is_vmalloc_addr +91 arch/arm64/mm/ioremap.c
>
> 75
> 76 void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot)
> 77 {
> 78 return __ioremap_caller(phys_addr, size, prot,
> 79 __builtin_return_address(0));
> 80 }
> 81 EXPORT_SYMBOL(__ioremap);
> 82
> 83 void __iounmap(volatile void __iomem *io_addr)
> 84 {
> 85 unsigned long addr = (unsigned long)io_addr & PAGE_MASK;
> 86
> 87 /*
> 88 * We could get an address outside vmalloc range in case
> 89 * of ioremap_cache() reusing a RAM mapping.
> 90 */
> > 91 if (is_vmalloc_addr(addr))
> 92 vunmap((void *)addr);
> 93 }
> 94 EXPORT_SYMBOL(__iounmap);
> 95
> 96 void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size)
> 97 {
> 98 /* For normal memory we already have a cacheable mapping. */
> 99 if (pfn_valid(__phys_to_pfn(phys_addr)))
>
> ---
> 0-DAY kernel test infrastructure Open Source Technology Center
> https://lists.01.org/pipermail/kbuild-all Intel Corporation
^ permalink raw reply
* [PATCH 09/11] iommu/mediatek: Make use of iommu_device_register interface
From: Joerg Roedel @ 2017-02-09 11:32 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Lorenzo Pieralisi, Alex Williamson,
David Woodhouse
Cc: Joerg Roedel, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Matthias Brugger,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1486639981-32368-1-git-send-email-joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>
From: Joerg Roedel <jroedel-l3A5Bk7waGM@public.gmane.org>
Register individual Mediatek IOMMUs to the iommu core and
add sysfs entries.
Cc: Matthias Brugger <matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Signed-off-by: Joerg Roedel <jroedel-l3A5Bk7waGM@public.gmane.org>
---
drivers/iommu/mtk_iommu.c | 26 ++++++++++++++++++++++++++
drivers/iommu/mtk_iommu.h | 2 ++
2 files changed, 28 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 1479c76..d484fa6 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -360,11 +360,15 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
static int mtk_iommu_add_device(struct device *dev)
{
+ struct mtk_iommu_data *data;
struct iommu_group *group;
if (!dev->iommu_fwspec || dev->iommu_fwspec->ops != &mtk_iommu_ops)
return -ENODEV; /* Not a iommu client device */
+ data = dev->iommu_fwspec->iommu_priv;
+ iommu_device_link(&data->iommu, dev);
+
group = iommu_group_get_for_dev(dev);
if (IS_ERR(group))
return PTR_ERR(group);
@@ -375,9 +379,14 @@ static int mtk_iommu_add_device(struct device *dev)
static void mtk_iommu_remove_device(struct device *dev)
{
+ struct mtk_iommu_data *data;
+
if (!dev->iommu_fwspec || dev->iommu_fwspec->ops != &mtk_iommu_ops)
return;
+ data = dev->iommu_fwspec->iommu_priv;
+ iommu_device_unlink(&data->iommu, dev);
+
iommu_group_remove_device(dev);
iommu_fwspec_free(dev);
}
@@ -497,6 +506,7 @@ static int mtk_iommu_probe(struct platform_device *pdev)
struct mtk_iommu_data *data;
struct device *dev = &pdev->dev;
struct resource *res;
+ resource_size_t ioaddr;
struct component_match *match = NULL;
void *protect;
int i, larb_nr, ret;
@@ -519,6 +529,7 @@ static int mtk_iommu_probe(struct platform_device *pdev)
data->base = devm_ioremap_resource(dev, res);
if (IS_ERR(data->base))
return PTR_ERR(data->base);
+ ioaddr = res->start;
data->irq = platform_get_irq(pdev, 0);
if (data->irq < 0)
@@ -567,6 +578,18 @@ static int mtk_iommu_probe(struct platform_device *pdev)
if (ret)
return ret;
+ ret = iommu_device_sysfs_add(&data->iommu, dev, NULL,
+ "mtk-iommu.%pa", &ioaddr);
+ if (ret)
+ return ret;
+
+ iommu_device_set_ops(&data->iommu, &mtk_iommu_ops);
+ iommu_device_set_fwnode(&data->iommu, &pdev->dev.of_node->fwnode);
+
+ ret = iommu_device_register(&data->iommu);
+ if (ret)
+ return ret;
+
if (!iommu_present(&platform_bus_type))
bus_set_iommu(&platform_bus_type, &mtk_iommu_ops);
@@ -577,6 +600,9 @@ static int mtk_iommu_remove(struct platform_device *pdev)
{
struct mtk_iommu_data *data = platform_get_drvdata(pdev);
+ iommu_device_sysfs_remove(&data->iommu);
+ iommu_device_unregister(&data->iommu);
+
if (iommu_present(&platform_bus_type))
bus_set_iommu(&platform_bus_type, NULL);
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 50177f7..2a28ead 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -47,6 +47,8 @@ struct mtk_iommu_data {
struct iommu_group *m4u_group;
struct mtk_smi_iommu smi_imu; /* SMI larb iommu info */
bool enable_4GB;
+
+ struct iommu_device iommu;
};
static inline int compare_of(struct device *dev, void *data)
--
1.9.1
^ permalink raw reply related
* [PATCH v2] arm64: use is_vmalloc_addr
From: Miles Chen @ 2017-02-09 11:45 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Miles Chen, linux-mediatek, linux-kernel, linux-arm-kernel,
wsd_upstream
To is_vmalloc_addr() to check if an address is a vmalloc address
instead of checking VMALLOC_START and VMALLOC_END manually.
Signed-off-by: Miles Chen <miles.chen@mediatek.com>
---
arch/arm64/mm/ioremap.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/mm/ioremap.c b/arch/arm64/mm/ioremap.c
index 01e88c8..c4c8cd4 100644
--- a/arch/arm64/mm/ioremap.c
+++ b/arch/arm64/mm/ioremap.c
@@ -88,7 +88,7 @@ void __iounmap(volatile void __iomem *io_addr)
* We could get an address outside vmalloc range in case
* of ioremap_cache() reusing a RAM mapping.
*/
- if (VMALLOC_START <= addr && addr < VMALLOC_END)
+ if (is_vmalloc_addr((void *)addr))
vunmap((void *)addr);
}
EXPORT_SYMBOL(__iounmap);
--
1.9.1
^ permalink raw reply related
* Re: [PATCH v20 2/4] mailbox: mediatek: Add Mediatek CMDQ driver
From: Horng-Shyang Liao @ 2017-02-09 12:03 UTC (permalink / raw)
To: Jassi Brar
Cc: Daniel Kurtz, Monica Wang, Jiaguang Zhang, Nicolas Boichat,
cawa cheng, hs.liao, Bibby Hsieh, YT Shen, Damon Chu,
Devicetree List, Sascha Hauer, Daoyuan Huang, Sascha Hauer,
Houlong Wei, Glory Hung, CK HU, Rob Herring, linux-mediatek,
Matthias Brugger, linux-arm-kernel@lists.infradead.org,
srv_heupstream, Josh-YC Liu, Linux
In-Reply-To: <1486359476.11424.33.camel@mtksdaap41>
On Mon, 2017-02-06 at 13:37 +0800, Horng-Shyang Liao wrote:
> Hi Jassi,
>
> On Wed, 2017-02-01 at 10:52 +0530, Jassi Brar wrote:
> > On Thu, Jan 26, 2017 at 2:07 PM, Horng-Shyang Liao <hs.liao@mediatek.com> wrote:
> > > Hi Jassi,
> > >
> > > On Thu, 2017-01-26 at 10:08 +0530, Jassi Brar wrote:
> > >> On Wed, Jan 4, 2017 at 8:36 AM, HS Liao <hs.liao@mediatek.com> wrote:
> > >>
> > >> > diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
> > >> > new file mode 100644
> > >> > index 0000000..747bcd3
> > >> > --- /dev/null
> > >> > +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> > >>
> > >> ...
> > >>
> > >> > +static void cmdq_task_exec(struct cmdq_pkt *pkt, struct cmdq_thread *thread)
> > >> > +{
> > >> > + struct cmdq *cmdq;
> > >> > + struct cmdq_task *task;
> > >> > + unsigned long curr_pa, end_pa;
> > >> > +
> > >> > + cmdq = dev_get_drvdata(thread->chan->mbox->dev);
> > >> > +
> > >> > + /* Client should not flush new tasks if suspended. */
> > >> > + WARN_ON(cmdq->suspended);
> > >> > +
> > >> > + task = kzalloc(sizeof(*task), GFP_ATOMIC);
> > >> > + task->cmdq = cmdq;
> > >> > + INIT_LIST_HEAD(&task->list_entry);
> > >> > + task->pa_base = dma_map_single(cmdq->mbox.dev, pkt->va_base,
> > >> > + pkt->cmd_buf_size, DMA_TO_DEVICE);
> > >> >
> > >> You seem to parse the requests and responses, that should ideally be
> > >> done in client driver.
> > >> Also, we are here in atomic context, can you move it in client driver
> > >> (before the spin_lock)?
> > >> Maybe by adding a new 'pa_base' member as well in 'cmdq_pkt'.
> > >
> > > will do
>
> I agree with moving dma_map_single out from spin_lock.
>
> However, mailbox clients cannot map virtual memory to mailbox
> controller's device for DMA. In our previous discussion, we decided to
> remove mailbox_controller.h from clients to restrict their capabilities.
>
> Please take a look at following link from 2016/9/22 to 2016/9/30 about
> mailbox_controller.h.
> https://patchwork.kernel.org/patch/9312953/
>
> Is there any better place to do dma_map_single?
Hi Jassi,
According to previous discussion, we have two requirements:
(1) CMDQ clients should not access mailbox_controller.h;
(2) dma_map_single should not put inside spin_lock.
I think a trade-off solution is to put in mtk-cmdq-helper.c.
Although it is a mailbox client, it is not a CMDQ client.
We can include mailbox_controller.h in mtk-cmdq-helper.c
(instead of mtk-cmdq.h), and then map dma at cmdq_pkt_flush_async
before mbox_send_message.
pkt->pa_base = dma_map_single(client->chan->mbox->dev, pkt->va_base,
pkt->cmd_buf_size, DMA_TO_DEVICE);
What do you think?
Thanks,
HS
> > >> ....
> > >> > +
> > >> > + cmdq->mbox.num_chans = CMDQ_THR_MAX_COUNT;
> > >> > + cmdq->mbox.ops = &cmdq_mbox_chan_ops;
> > >> > + cmdq->mbox.of_xlate = cmdq_xlate;
> > >> > +
> > >> > + /* make use of TXDONE_BY_ACK */
> > >> > + cmdq->mbox.txdone_irq = false;
> > >> > + cmdq->mbox.txdone_poll = false;
> > >> > +
> > >> > + for (i = 0; i < ARRAY_SIZE(cmdq->thread); i++) {
> > >> >
> > >> You mean i < CMDQ_THR_MAX_COUNT
> > >
> > > will do
> > >
> > >> > + cmdq->thread[i].base = cmdq->base + CMDQ_THR_BASE +
> > >> > + CMDQ_THR_SIZE * i;
> > >> > + INIT_LIST_HEAD(&cmdq->thread[i].task_busy_list);
> > >> >
> > >> You seem the queue mailbox requests in this controller driver? why not
> > >> use the mailbox api for that?
> > >>
> > >> > + init_timer(&cmdq->thread[i].timeout);
> > >> > + cmdq->thread[i].timeout.function = cmdq_thread_handle_timeout;
> > >> > + cmdq->thread[i].timeout.data = (unsigned long)&cmdq->thread[i];
> > >> >
> > >> Here again... you seem to ignore the polling mechanism provided by the
> > >> mailbox api, and implement your own.
> > >
> > > The queue is used to record the tasks which are flushed into CMDQ
> > > hardware (GCE). We are handling time critical tasks, so we have to
> > > queue them in GCE rather than a software queue (e.g. mailbox buffer).
> > > Let me use display as an example. Many display tasks are flushed into
> > > CMDQ to wait next vsync event. When vsync event is triggered by display
> > > hardware, GCE needs to process all flushed tasks "within vblank" to
> > > prevent garbage on screen. This is all done by GCE (without CPU)
> > > to fulfill time critical requirement. After GCE finish its work,
> > > it will generate interrupts, and then CMDQ driver will let clients know
> > > which tasks are done.
> > >
> > Does the GCE provide any 'lock' to prevent modifying (by adding tasks
> > to) the GCE h/w buffer when it is processing it at vsync? Otherwise
>
> CPU will suspend GCE when adding a task (cmdq_thread_suspend),
> and resume GCE after adding task is done (cmdq_thread_resume).
> If GCE is processing task(s) at vsync and CPU wants to add a new task
> at the same time, CPU will detect this situation
> (by cmdq_thread_is_in_wfe), resume GCE immediately, and then add
> following task(s) to wait for next vsync event.
> All the above logic is implemented at cmdq_task_exec.
>
> > there maybe race/error. If there is such a 'lock' flag/irq, that could
> > help here. However, you are supposed to know your h/w better, so I
> > will accept this implementation assuming it can't be done any better.
> >
> > Please address other comments and resubmit.
> >
> > Thanks
>
> After we figure out a better solution for dma_map_single issue, I will
> resubmit a new version.
>
> Thanks,
> HS
^ permalink raw reply
* Re: [PATCH v2 3/4] leds: Add LED support for MT6323 PMIC
From: Pavel Machek @ 2017-02-09 14:23 UTC (permalink / raw)
To: Jacek Anaszewski
Cc: mark.rutland, devicetree, keyhaede, sean.wang, linux-kernel,
robh+dt, rpurdie, linux-arm-kernel, matthias.bgg, linux-mediatek,
lee.jones, linux-leds
In-Reply-To: <a410da2e-ce5f-6263-2d7d-79f4b358a848@gmail.com>
Hi!
> > +/*
> > + * Register for MT6323_ISINK_CON0 to setup the
> > + * duty cycle of the blink
> > + */
> > +#define MT6323_ISINK_CON0(i) (MT6323_ISINK0_CON0 + 0x8 * (i))
> > +#define MT6323_ISINK_DIM_DUTY_MASK (0x1f << 8)
> > +#define MT6323_ISINK_DIM_DUTY(i) (((i) << 8) & \
> > + MT6323_ISINK_DIM_DUTY_MASK)
> > +
> > +/*
> > + * Register to setup the period of the blink
> > + */
>
> This fits in a single line, so can be wrapped with /* */ like :
People do this to make blocks stand out, and to make it similar to other blocks
above. I believe this is ok.
Pavel
^ permalink raw reply
* Re: [RESEND PATCH 1/2] Documentation: devicetree: Add i2c binding for mediatek MT2701 Soc Platform
From: Wolfram Sang @ 2017-02-09 16:35 UTC (permalink / raw)
To: Jun Gao
Cc: devicetree, srv_heupstream, linux-kernel, linux-mediatek,
linux-i2c, Matthias Brugger, linux-arm-kernel
In-Reply-To: <1484732461-13594-2-git-send-email-jun.gao@mediatek.com>
[-- Attachment #1.1: Type: text/plain, Size: 1863 bytes --]
On Wed, Jan 18, 2017 at 05:41:00PM +0800, Jun Gao wrote:
> From: Jun Gao <jun.gao@mediatek.com>
>
> This add i2c DT binding to i2c-mt6577.txt for MT2701.
>
> Signed-off-by: Jun Gao <jun.gao@mediatek.com>
> ---
> .../devicetree/bindings/i2c/i2c-mt6577.txt | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt b/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
> index 0ce6fa3..ef22ecf 100644
> --- a/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
> +++ b/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
> @@ -4,11 +4,12 @@ The Mediatek's I2C controller is used to interface with I2C devices.
>
> Required properties:
> - compatible: value should be either of the following.
> - (a) "mediatek,mt6577-i2c", for i2c compatible with mt6577 i2c.
> - (b) "mediatek,mt6589-i2c", for i2c compatible with mt6589 i2c.
> - (c) "mediatek,mt8127-i2c", for i2c compatible with mt8127 i2c.
> - (d) "mediatek,mt8135-i2c", for i2c compatible with mt8135 i2c.
> - (e) "mediatek,mt8173-i2c", for i2c compatible with mt8173 i2c.
> + "mediatek,mt2701-i2c", for i2c compatible with mt2701 i2c.
> + "mediatek,mt6577-i2c", for i2c compatible with mt6577 i2c.
> + "mediatek,mt6589-i2c", for i2c compatible with mt6589 i2c.
> + "mediatek,mt8127-i2c", for i2c compatible with mt8127 i2c.
> + "mediatek,mt8135-i2c", for i2c compatible with mt8135 i2c.
> + "mediatek,mt8173-i2c", for i2c compatible with mt8173 i2c.
> - reg: physical base address of the controller and dma base, length of memory
> mapped region.
> - interrupts: interrupt number to the cpu.
Are there no driver changes needed? It currently lists only 3 of the
above. If so, that would be nice to be mentioned in the commit message.
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v2 3/4] leds: Add LED support for MT6323 PMIC
From: Jacek Anaszewski @ 2017-02-09 20:35 UTC (permalink / raw)
To: Pavel Machek
Cc: sean.wang, rpurdie, lee.jones, matthias.bgg, robh+dt,
mark.rutland, devicetree, linux-leds, linux-mediatek,
linux-arm-kernel, linux-kernel, keyhaede
In-Reply-To: <20170209142344.GA23373@xo-6d-61-c0.localdomain>
On 02/09/2017 03:23 PM, Pavel Machek wrote:
> Hi!
>
>>> +/*
>>> + * Register for MT6323_ISINK_CON0 to setup the
>>> + * duty cycle of the blink
>>> + */
>>> +#define MT6323_ISINK_CON0(i) (MT6323_ISINK0_CON0 + 0x8 * (i))
>>> +#define MT6323_ISINK_DIM_DUTY_MASK (0x1f << 8)
>>> +#define MT6323_ISINK_DIM_DUTY(i) (((i) << 8) & \
>>> + MT6323_ISINK_DIM_DUTY_MASK)
>>> +
>>> +/*
>>> + * Register to setup the period of the blink
>>> + */
>>
>> This fits in a single line, so can be wrapped with /* */ like :
>
> People do this to make blocks stand out, and to make it similar to other blocks
> above. I believe this is ok.
It generates unnecessary lines of code, but I'm not going to
argue, let's leave it to the developer's taste.
--
Best regards,
Jacek Anaszewski
^ permalink raw reply
* Re: [PATCH] thermal: mt8173: minor mtk_thermal.c cleanups
From: Matthias Brugger @ 2017-02-09 21:25 UTC (permalink / raw)
To: Dawei Chien, Zhang Rui, Eduardo Valentin
Cc: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Russell King, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, srv_heupstream, Sascha Hauer,
Fan Chen, Eddie Huang, Yingjoe Chen, Erin Lo
In-Reply-To: <1486531862-31945-1-git-send-email-dawei.chien@mediatek.com>
On 02/08/2017 06:31 AM, Dawei Chien wrote:
> Thermal driver should read TEMP_MSR3 if thermal bank with 4 sensors.
> However, Currently thermal driver don't need read TEMP_MSR3 since
> thermal controller only use 3 sensors for each thermal bank.
>
> Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
> ---
Actually the commit message should state:
Fixes: b7cf0053738c ("thermal: Add Mediatek thermal driver for mt2701.")
...and get backported to v4.9 and v4.10.
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Regards,
Matthias
> drivers/thermal/mtk_thermal.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c
> index 34169c3..c124151 100644
> --- a/drivers/thermal/mtk_thermal.c
> +++ b/drivers/thermal/mtk_thermal.c
> @@ -191,7 +191,7 @@ struct mtk_thermal {
> };
>
> const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
> - TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR2
> + TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
> };
>
> const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
>
^ permalink raw reply
* Re: [PATCH] arm64: dts: mediatek: add mt8176 device tree
From: Matthias Brugger @ 2017-02-09 21:30 UTC (permalink / raw)
To: Yidi Lin, Rob Herring
Cc: Mark Rutland, devicetree, srv_heupstream, linux-kernel,
Daniel Kurtz, linux-mediatek, linux-arm-kernel
In-Reply-To: <1486445710-40140-1-git-send-email-yidi.lin@mediatek.com>
On 02/07/2017 06:35 AM, Yidi Lin wrote:
> The core configuration is the only difference between mt8173 and mt8176.
> Like what arm/juno and marvell/armada-ap806 did, this change splits
> mt8173.dtsi into mt817x.dtsi and mt8173.dtsi. mt817x.dtsi defines the
> common blocks for mt8173 and mt8176. mt8173.dtsi and mt8176.dtsi
> describe mt8173 and mt8176 respectively.
>
> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
> ---
Please split this in two patches. The first one introduces mt871x.dtsi and the
second adds the new mt8176.dtsi
Thanks,
Matthias
> Documentation/devicetree/bindings/arm/mediatek.txt | 1 +
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 1205 +-------------------
> arch/arm64/boot/dts/mediatek/mt8176.dtsi | 125 ++
> arch/arm64/boot/dts/mediatek/mt817x.dtsi | 1199 +++++++++++++++++++
> 4 files changed, 1338 insertions(+), 1192 deletions(-)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8176.dtsi
> create mode 100644 arch/arm64/boot/dts/mediatek/mt817x.dtsi
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
> index c860b24..f305149 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek.txt
> +++ b/Documentation/devicetree/bindings/arm/mediatek.txt
> @@ -16,6 +16,7 @@ compatible: Must contain one of
> "mediatek,mt8127"
> "mediatek,mt8135"
> "mediatek,mt8173"
> + "mediatek,mt8176"
>
>
> Supported boards:
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 12e7027..c0a9cfa 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (c) 2014 MediaTek Inc.
> + * Copyright (c) 2016 MediaTek Inc.
> * Author: Eddie Huang <eddie.huang@mediatek.com>
> *
> * This program is free software; you can redistribute it and/or modify
> @@ -11,45 +11,10 @@
> * GNU General Public License for more details.
> */
>
> -#include <dt-bindings/clock/mt8173-clk.h>
> -#include <dt-bindings/interrupt-controller/irq.h>
> -#include <dt-bindings/interrupt-controller/arm-gic.h>
> -#include <dt-bindings/memory/mt8173-larb-port.h>
> -#include <dt-bindings/phy/phy.h>
> -#include <dt-bindings/power/mt8173-power.h>
> -#include <dt-bindings/reset/mt8173-resets.h>
> -#include "mt8173-pinfunc.h"
> +#include "mt817x.dtsi"
>
> / {
> compatible = "mediatek,mt8173";
> - interrupt-parent = <&sysirq>;
> - #address-cells = <2>;
> - #size-cells = <2>;
> -
> - aliases {
> - ovl0 = &ovl0;
> - ovl1 = &ovl1;
> - rdma0 = &rdma0;
> - rdma1 = &rdma1;
> - rdma2 = &rdma2;
> - wdma0 = &wdma0;
> - wdma1 = &wdma1;
> - color0 = &color0;
> - color1 = &color1;
> - split0 = &split0;
> - split1 = &split1;
> - dpi0 = &dpi0;
> - dsi0 = &dsi0;
> - dsi1 = &dsi1;
> - mdp_rdma0 = &mdp_rdma0;
> - mdp_rdma1 = &mdp_rdma1;
> - mdp_rsz0 = &mdp_rsz0;
> - mdp_rsz1 = &mdp_rsz1;
> - mdp_rsz2 = &mdp_rsz2;
> - mdp_wdma0 = &mdp_wdma0;
> - mdp_wrot0 = &mdp_wrot0;
> - mdp_wrot1 = &mdp_wrot1;
> - };
>
> cpus {
> #address-cells = <1>;
> @@ -120,1163 +85,19 @@
> };
> };
> };
> +};
>
> - psci {
> - compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
> - method = "smc";
> - cpu_suspend = <0x84000001>;
> - cpu_off = <0x84000002>;
> - cpu_on = <0x84000003>;
> - };
> -
> - clk26m: oscillator@0 {
> - compatible = "fixed-clock";
> - #clock-cells = <0>;
> - clock-frequency = <26000000>;
> - clock-output-names = "clk26m";
> - };
> -
> - clk32k: oscillator@1 {
> - compatible = "fixed-clock";
> - #clock-cells = <0>;
> - clock-frequency = <32000>;
> - clock-output-names = "clk32k";
> - };
> -
> - cpum_ck: oscillator@2 {
> - compatible = "fixed-clock";
> - #clock-cells = <0>;
> - clock-frequency = <0>;
> - clock-output-names = "cpum_ck";
> - };
> -
> - thermal-zones {
> - cpu_thermal: cpu_thermal {
> - polling-delay-passive = <1000>; /* milliseconds */
> - polling-delay = <1000>; /* milliseconds */
> -
> - thermal-sensors = <&thermal>;
> - sustainable-power = <1500>; /* milliwatts */
> -
> - trips {
> - threshold: trip-point@0 {
> - temperature = <68000>;
> - hysteresis = <2000>;
> - type = "passive";
> - };
> -
> - target: trip-point@1 {
> - temperature = <85000>;
> - hysteresis = <2000>;
> - type = "passive";
> - };
> -
> - cpu_crit: cpu_crit@0 {
> - temperature = <115000>;
> - hysteresis = <2000>;
> - type = "critical";
> - };
> - };
> -
> - cooling-maps {
> - map@0 {
> - trip = <&target>;
> - cooling-device = <&cpu0 0 0>;
> - contribution = <1024>;
> - };
> - map@1 {
> - trip = <&target>;
> - cooling-device = <&cpu2 0 0>;
> - contribution = <2048>;
> - };
> - };
> - };
> - };
> -
> - reserved-memory {
> - #address-cells = <2>;
> - #size-cells = <2>;
> - ranges;
> - vpu_dma_reserved: vpu_dma_mem_region {
> - compatible = "shared-dma-pool";
> - reg = <0 0xb7000000 0 0x500000>;
> - alignment = <0x1000>;
> - no-map;
> - };
> - };
> -
> - timer {
> - compatible = "arm,armv8-timer";
> - interrupt-parent = <&gic>;
> - interrupts = <GIC_PPI 13
> - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> - <GIC_PPI 14
> - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> - <GIC_PPI 11
> - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> - <GIC_PPI 10
> - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> - };
> -
> - soc {
> - #address-cells = <2>;
> - #size-cells = <2>;
> - compatible = "simple-bus";
> - ranges;
> -
> - topckgen: clock-controller@10000000 {
> - compatible = "mediatek,mt8173-topckgen";
> - reg = <0 0x10000000 0 0x1000>;
> - #clock-cells = <1>;
> - };
> -
> - infracfg: power-controller@10001000 {
> - compatible = "mediatek,mt8173-infracfg", "syscon";
> - reg = <0 0x10001000 0 0x1000>;
> - #clock-cells = <1>;
> - #reset-cells = <1>;
> - };
> -
> - pericfg: power-controller@10003000 {
> - compatible = "mediatek,mt8173-pericfg", "syscon";
> - reg = <0 0x10003000 0 0x1000>;
> - #clock-cells = <1>;
> - #reset-cells = <1>;
> - };
> -
> - syscfg_pctl_a: syscfg_pctl_a@10005000 {
> - compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
> - reg = <0 0x10005000 0 0x1000>;
> - };
> -
> - pio: pinctrl@0x10005000 {
> - compatible = "mediatek,mt8173-pinctrl";
> - reg = <0 0x1000b000 0 0x1000>;
> - mediatek,pctl-regmap = <&syscfg_pctl_a>;
> - pins-are-numbered;
> - gpio-controller;
> - #gpio-cells = <2>;
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> -
> - hdmi_pin: xxx {
> -
> - /*hdmi htplg pin*/
> - pins1 {
> - pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
> - input-enable;
> - bias-pull-down;
> - };
> - };
> -
> - i2c0_pins_a: i2c0 {
> - pins1 {
> - pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
> - <MT8173_PIN_46_SCL0__FUNC_SCL0>;
> - bias-disable;
> - };
> - };
> -
> - i2c1_pins_a: i2c1 {
> - pins1 {
> - pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
> - <MT8173_PIN_126_SCL1__FUNC_SCL1>;
> - bias-disable;
> - };
> - };
> -
> - i2c2_pins_a: i2c2 {
> - pins1 {
> - pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
> - <MT8173_PIN_44_SCL2__FUNC_SCL2>;
> - bias-disable;
> - };
> - };
> -
> - i2c3_pins_a: i2c3 {
> - pins1 {
> - pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
> - <MT8173_PIN_107_SCL3__FUNC_SCL3>;
> - bias-disable;
> - };
> - };
> -
> - i2c4_pins_a: i2c4 {
> - pins1 {
> - pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
> - <MT8173_PIN_134_SCL4__FUNC_SCL4>;
> - bias-disable;
> - };
> - };
> -
> - i2c6_pins_a: i2c6 {
> - pins1 {
> - pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
> - <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
> - bias-disable;
> - };
> - };
> - };
> -
> - scpsys: scpsys@10006000 {
> - compatible = "mediatek,mt8173-scpsys";
> - #power-domain-cells = <1>;
> - reg = <0 0x10006000 0 0x1000>;
> - clocks = <&clk26m>,
> - <&topckgen CLK_TOP_MM_SEL>,
> - <&topckgen CLK_TOP_VENC_SEL>,
> - <&topckgen CLK_TOP_VENC_LT_SEL>;
> - clock-names = "mfg", "mm", "venc", "venc_lt";
> - infracfg = <&infracfg>;
> - };
> -
> - watchdog: watchdog@10007000 {
> - compatible = "mediatek,mt8173-wdt",
> - "mediatek,mt6589-wdt";
> - reg = <0 0x10007000 0 0x100>;
> - };
> -
> - timer: timer@10008000 {
> - compatible = "mediatek,mt8173-timer",
> - "mediatek,mt6577-timer";
> - reg = <0 0x10008000 0 0x1000>;
> - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&infracfg CLK_INFRA_CLK_13M>,
> - <&topckgen CLK_TOP_RTC_SEL>;
> - };
> -
> - pwrap: pwrap@1000d000 {
> - compatible = "mediatek,mt8173-pwrap";
> - reg = <0 0x1000d000 0 0x1000>;
> - reg-names = "pwrap";
> - interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> - resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
> - reset-names = "pwrap";
> - clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
> - clock-names = "spi", "wrap";
> - };
> -
> - cec: cec@10013000 {
> - compatible = "mediatek,mt8173-cec";
> - reg = <0 0x10013000 0 0xbc>;
> - interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&infracfg CLK_INFRA_CEC>;
> - status = "disabled";
> - };
> -
> - vpu: vpu@10020000 {
> - compatible = "mediatek,mt8173-vpu";
> - reg = <0 0x10020000 0 0x30000>,
> - <0 0x10050000 0 0x100>;
> - reg-names = "tcm", "cfg_reg";
> - interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&topckgen CLK_TOP_SCP_SEL>;
> - clock-names = "main";
> - memory-region = <&vpu_dma_reserved>;
> - };
> -
> - sysirq: intpol-controller@10200620 {
> - compatible = "mediatek,mt8173-sysirq",
> - "mediatek,mt6577-sysirq";
> - interrupt-controller;
> - #interrupt-cells = <3>;
> - interrupt-parent = <&gic>;
> - reg = <0 0x10200620 0 0x20>;
> - };
> -
> - iommu: iommu@10205000 {
> - compatible = "mediatek,mt8173-m4u";
> - reg = <0 0x10205000 0 0x1000>;
> - interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&infracfg CLK_INFRA_M4U>;
> - clock-names = "bclk";
> - mediatek,larbs = <&larb0 &larb1 &larb2
> - &larb3 &larb4 &larb5>;
> - #iommu-cells = <1>;
> - };
> -
> - efuse: efuse@10206000 {
> - compatible = "mediatek,mt8173-efuse";
> - reg = <0 0x10206000 0 0x1000>;
> - };
> -
> - apmixedsys: clock-controller@10209000 {
> - compatible = "mediatek,mt8173-apmixedsys";
> - reg = <0 0x10209000 0 0x1000>;
> - #clock-cells = <1>;
> - };
> -
> - hdmi_phy: hdmi-phy@10209100 {
> - compatible = "mediatek,mt8173-hdmi-phy";
> - reg = <0 0x10209100 0 0x24>;
> - clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
> - clock-names = "pll_ref";
> - clock-output-names = "hdmitx_dig_cts";
> - mediatek,ibias = <0xa>;
> - mediatek,ibias_up = <0x1c>;
> - #clock-cells = <0>;
> - #phy-cells = <0>;
> - status = "disabled";
> - };
> -
> - mipi_tx0: mipi-dphy@10215000 {
> - compatible = "mediatek,mt8173-mipi-tx";
> - reg = <0 0x10215000 0 0x1000>;
> - clocks = <&clk26m>;
> - clock-output-names = "mipi_tx0_pll";
> - #clock-cells = <0>;
> - #phy-cells = <0>;
> - status = "disabled";
> - };
> -
> - mipi_tx1: mipi-dphy@10216000 {
> - compatible = "mediatek,mt8173-mipi-tx";
> - reg = <0 0x10216000 0 0x1000>;
> - clocks = <&clk26m>;
> - clock-output-names = "mipi_tx1_pll";
> - #clock-cells = <0>;
> - #phy-cells = <0>;
> - status = "disabled";
> - };
> -
> - gic: interrupt-controller@10220000 {
> - compatible = "arm,gic-400";
> - #interrupt-cells = <3>;
> - interrupt-parent = <&gic>;
> - interrupt-controller;
> - reg = <0 0x10221000 0 0x1000>,
> - <0 0x10222000 0 0x2000>,
> - <0 0x10224000 0 0x2000>,
> - <0 0x10226000 0 0x2000>;
> - interrupts = <GIC_PPI 9
> - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> - };
> -
> - auxadc: auxadc@11001000 {
> - compatible = "mediatek,mt8173-auxadc";
> - reg = <0 0x11001000 0 0x1000>;
> - clocks = <&pericfg CLK_PERI_AUXADC>;
> - clock-names = "main";
> - #io-channel-cells = <1>;
> - };
> -
> - uart0: serial@11002000 {
> - compatible = "mediatek,mt8173-uart",
> - "mediatek,mt6577-uart";
> - reg = <0 0x11002000 0 0x400>;
> - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
> - clock-names = "baud", "bus";
> - status = "disabled";
> - };
> -
> - uart1: serial@11003000 {
> - compatible = "mediatek,mt8173-uart",
> - "mediatek,mt6577-uart";
> - reg = <0 0x11003000 0 0x400>;
> - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
> - clock-names = "baud", "bus";
> - status = "disabled";
> - };
> -
> - uart2: serial@11004000 {
> - compatible = "mediatek,mt8173-uart",
> - "mediatek,mt6577-uart";
> - reg = <0 0x11004000 0 0x400>;
> - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
> - clock-names = "baud", "bus";
> - status = "disabled";
> - };
> -
> - uart3: serial@11005000 {
> - compatible = "mediatek,mt8173-uart",
> - "mediatek,mt6577-uart";
> - reg = <0 0x11005000 0 0x400>;
> - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
> - clock-names = "baud", "bus";
> - status = "disabled";
> - };
> -
> - i2c0: i2c@11007000 {
> - compatible = "mediatek,mt8173-i2c";
> - reg = <0 0x11007000 0 0x70>,
> - <0 0x11000100 0 0x80>;
> - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
> - clock-div = <16>;
> - clocks = <&pericfg CLK_PERI_I2C0>,
> - <&pericfg CLK_PERI_AP_DMA>;
> - clock-names = "main", "dma";
> - pinctrl-names = "default";
> - pinctrl-0 = <&i2c0_pins_a>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - status = "disabled";
> - };
> -
> - i2c1: i2c@11008000 {
> - compatible = "mediatek,mt8173-i2c";
> - reg = <0 0x11008000 0 0x70>,
> - <0 0x11000180 0 0x80>;
> - interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
> - clock-div = <16>;
> - clocks = <&pericfg CLK_PERI_I2C1>,
> - <&pericfg CLK_PERI_AP_DMA>;
> - clock-names = "main", "dma";
> - pinctrl-names = "default";
> - pinctrl-0 = <&i2c1_pins_a>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - status = "disabled";
> - };
> -
> - i2c2: i2c@11009000 {
> - compatible = "mediatek,mt8173-i2c";
> - reg = <0 0x11009000 0 0x70>,
> - <0 0x11000200 0 0x80>;
> - interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
> - clock-div = <16>;
> - clocks = <&pericfg CLK_PERI_I2C2>,
> - <&pericfg CLK_PERI_AP_DMA>;
> - clock-names = "main", "dma";
> - pinctrl-names = "default";
> - pinctrl-0 = <&i2c2_pins_a>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - status = "disabled";
> - };
> -
> - spi: spi@1100a000 {
> - compatible = "mediatek,mt8173-spi";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - reg = <0 0x1100a000 0 0x1000>;
> - interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
> - <&topckgen CLK_TOP_SPI_SEL>,
> - <&pericfg CLK_PERI_SPI0>;
> - clock-names = "parent-clk", "sel-clk", "spi-clk";
> - status = "disabled";
> - };
> -
> - thermal: thermal@1100b000 {
> - #thermal-sensor-cells = <0>;
> - compatible = "mediatek,mt8173-thermal";
> - reg = <0 0x1100b000 0 0x1000>;
> - interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
> - clock-names = "therm", "auxadc";
> - resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
> - mediatek,auxadc = <&auxadc>;
> - mediatek,apmixedsys = <&apmixedsys>;
> - };
> -
> - nor_flash: spi@1100d000 {
> - compatible = "mediatek,mt8173-nor";
> - reg = <0 0x1100d000 0 0xe0>;
> - clocks = <&pericfg CLK_PERI_SPI>,
> - <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
> - clock-names = "spi", "sf";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - status = "disabled";
> - };
> -
> - i2c3: i2c@11010000 {
> - compatible = "mediatek,mt8173-i2c";
> - reg = <0 0x11010000 0 0x70>,
> - <0 0x11000280 0 0x80>;
> - interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
> - clock-div = <16>;
> - clocks = <&pericfg CLK_PERI_I2C3>,
> - <&pericfg CLK_PERI_AP_DMA>;
> - clock-names = "main", "dma";
> - pinctrl-names = "default";
> - pinctrl-0 = <&i2c3_pins_a>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - status = "disabled";
> - };
> -
> - i2c4: i2c@11011000 {
> - compatible = "mediatek,mt8173-i2c";
> - reg = <0 0x11011000 0 0x70>,
> - <0 0x11000300 0 0x80>;
> - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
> - clock-div = <16>;
> - clocks = <&pericfg CLK_PERI_I2C4>,
> - <&pericfg CLK_PERI_AP_DMA>;
> - clock-names = "main", "dma";
> - pinctrl-names = "default";
> - pinctrl-0 = <&i2c4_pins_a>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - status = "disabled";
> - };
> -
> - hdmiddc0: i2c@11012000 {
> - compatible = "mediatek,mt8173-hdmi-ddc";
> - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
> - reg = <0 0x11012000 0 0x1C>;
> - clocks = <&pericfg CLK_PERI_I2C5>;
> - clock-names = "ddc-i2c";
> - };
> -
> - i2c6: i2c@11013000 {
> - compatible = "mediatek,mt8173-i2c";
> - reg = <0 0x11013000 0 0x70>,
> - <0 0x11000080 0 0x80>;
> - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
> - clock-div = <16>;
> - clocks = <&pericfg CLK_PERI_I2C6>,
> - <&pericfg CLK_PERI_AP_DMA>;
> - clock-names = "main", "dma";
> - pinctrl-names = "default";
> - pinctrl-0 = <&i2c6_pins_a>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - status = "disabled";
> - };
> -
> - afe: audio-controller@11220000 {
> - compatible = "mediatek,mt8173-afe-pcm";
> - reg = <0 0x11220000 0 0x1000>;
> - interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
> - clocks = <&infracfg CLK_INFRA_AUDIO>,
> - <&topckgen CLK_TOP_AUDIO_SEL>,
> - <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
> - <&topckgen CLK_TOP_APLL1_DIV0>,
> - <&topckgen CLK_TOP_APLL2_DIV0>,
> - <&topckgen CLK_TOP_I2S0_M_SEL>,
> - <&topckgen CLK_TOP_I2S1_M_SEL>,
> - <&topckgen CLK_TOP_I2S2_M_SEL>,
> - <&topckgen CLK_TOP_I2S3_M_SEL>,
> - <&topckgen CLK_TOP_I2S3_B_SEL>;
> - clock-names = "infra_sys_audio_clk",
> - "top_pdn_audio",
> - "top_pdn_aud_intbus",
> - "bck0",
> - "bck1",
> - "i2s0_m",
> - "i2s1_m",
> - "i2s2_m",
> - "i2s3_m",
> - "i2s3_b";
> - assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
> - <&topckgen CLK_TOP_AUD_2_SEL>;
> - assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
> - <&topckgen CLK_TOP_APLL2>;
> - };
> -
> - mmc0: mmc@11230000 {
> - compatible = "mediatek,mt8173-mmc",
> - "mediatek,mt8135-mmc";
> - reg = <0 0x11230000 0 0x1000>;
> - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&pericfg CLK_PERI_MSDC30_0>,
> - <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
> - clock-names = "source", "hclk";
> - status = "disabled";
> - };
> -
> - mmc1: mmc@11240000 {
> - compatible = "mediatek,mt8173-mmc",
> - "mediatek,mt8135-mmc";
> - reg = <0 0x11240000 0 0x1000>;
> - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&pericfg CLK_PERI_MSDC30_1>,
> - <&topckgen CLK_TOP_AXI_SEL>;
> - clock-names = "source", "hclk";
> - status = "disabled";
> - };
> -
> - mmc2: mmc@11250000 {
> - compatible = "mediatek,mt8173-mmc",
> - "mediatek,mt8135-mmc";
> - reg = <0 0x11250000 0 0x1000>;
> - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&pericfg CLK_PERI_MSDC30_2>,
> - <&topckgen CLK_TOP_AXI_SEL>;
> - clock-names = "source", "hclk";
> - status = "disabled";
> - };
> -
> - mmc3: mmc@11260000 {
> - compatible = "mediatek,mt8173-mmc",
> - "mediatek,mt8135-mmc";
> - reg = <0 0x11260000 0 0x1000>;
> - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&pericfg CLK_PERI_MSDC30_3>,
> - <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
> - clock-names = "source", "hclk";
> - status = "disabled";
> - };
> -
> - ssusb: usb@11271000 {
> - compatible = "mediatek,mt8173-mtu3";
> - reg = <0 0x11271000 0 0x3000>,
> - <0 0x11280700 0 0x0100>;
> - reg-names = "mac", "ippc";
> - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
> - phys = <&phy_port0 PHY_TYPE_USB3>,
> - <&phy_port1 PHY_TYPE_USB2>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
> - clocks = <&topckgen CLK_TOP_USB30_SEL>,
> - <&pericfg CLK_PERI_USB0>,
> - <&pericfg CLK_PERI_USB1>;
> - clock-names = "sys_ck",
> - "wakeup_deb_p0",
> - "wakeup_deb_p1";
> - mediatek,syscon-wakeup = <&pericfg>;
> - #address-cells = <2>;
> - #size-cells = <2>;
> - ranges;
> - status = "disabled";
> -
> - usb_host: xhci@11270000 {
> - compatible = "mediatek,mt8173-xhci";
> - reg = <0 0x11270000 0 0x1000>;
> - reg-names = "mac";
> - interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
> - clocks = <&topckgen CLK_TOP_USB30_SEL>;
> - clock-names = "sys_ck";
> - status = "disabled";
> - };
> - };
> -
> - u3phy: usb-phy@11290000 {
> - compatible = "mediatek,mt8173-u3phy";
> - reg = <0 0x11290000 0 0x800>;
> - clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
> - clock-names = "u3phya_ref";
> - #address-cells = <2>;
> - #size-cells = <2>;
> - ranges;
> - status = "okay";
> -
> - phy_port0: port@11290800 {
> - reg = <0 0x11290800 0 0x800>;
> - #phy-cells = <1>;
> - status = "okay";
> - };
> -
> - phy_port1: port@11291000 {
> - reg = <0 0x11291000 0 0x800>;
> - #phy-cells = <1>;
> - status = "okay";
> - };
> - };
> -
> - mmsys: clock-controller@14000000 {
> - compatible = "mediatek,mt8173-mmsys", "syscon";
> - reg = <0 0x14000000 0 0x1000>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - #clock-cells = <1>;
> - };
> -
> - mdp {
> - compatible = "mediatek,mt8173-mdp";
> - #address-cells = <2>;
> - #size-cells = <2>;
> - ranges;
> - mediatek,vpu = <&vpu>;
> -
> - mdp_rdma0: rdma@14001000 {
> - compatible = "mediatek,mt8173-mdp-rdma";
> - reg = <0 0x14001000 0 0x1000>;
> - clocks = <&mmsys CLK_MM_MDP_RDMA0>,
> - <&mmsys CLK_MM_MUTEX_32K>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - iommus = <&iommu M4U_PORT_MDP_RDMA0>;
> - mediatek,larb = <&larb0>;
> - };
> -
> - mdp_rdma1: rdma@14002000 {
> - compatible = "mediatek,mt8173-mdp-rdma";
> - reg = <0 0x14002000 0 0x1000>;
> - clocks = <&mmsys CLK_MM_MDP_RDMA1>,
> - <&mmsys CLK_MM_MUTEX_32K>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - iommus = <&iommu M4U_PORT_MDP_RDMA1>;
> - mediatek,larb = <&larb4>;
> - };
> -
> - mdp_rsz0: rsz@14003000 {
> - compatible = "mediatek,mt8173-mdp-rsz";
> - reg = <0 0x14003000 0 0x1000>;
> - clocks = <&mmsys CLK_MM_MDP_RSZ0>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - };
> -
> - mdp_rsz1: rsz@14004000 {
> - compatible = "mediatek,mt8173-mdp-rsz";
> - reg = <0 0x14004000 0 0x1000>;
> - clocks = <&mmsys CLK_MM_MDP_RSZ1>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - };
> -
> - mdp_rsz2: rsz@14005000 {
> - compatible = "mediatek,mt8173-mdp-rsz";
> - reg = <0 0x14005000 0 0x1000>;
> - clocks = <&mmsys CLK_MM_MDP_RSZ2>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - };
> -
> - mdp_wdma0: wdma@14006000 {
> - compatible = "mediatek,mt8173-mdp-wdma";
> - reg = <0 0x14006000 0 0x1000>;
> - clocks = <&mmsys CLK_MM_MDP_WDMA>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - iommus = <&iommu M4U_PORT_MDP_WDMA>;
> - mediatek,larb = <&larb0>;
> - };
> -
> - mdp_wrot0: wrot@14007000 {
> - compatible = "mediatek,mt8173-mdp-wrot";
> - reg = <0 0x14007000 0 0x1000>;
> - clocks = <&mmsys CLK_MM_MDP_WROT0>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - iommus = <&iommu M4U_PORT_MDP_WROT0>;
> - mediatek,larb = <&larb0>;
> - };
> -
> - mdp_wrot1: wrot@14008000 {
> - compatible = "mediatek,mt8173-mdp-wrot";
> - reg = <0 0x14008000 0 0x1000>;
> - clocks = <&mmsys CLK_MM_MDP_WROT1>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - iommus = <&iommu M4U_PORT_MDP_WROT1>;
> - mediatek,larb = <&larb4>;
> - };
> - };
> -
> - ovl0: ovl@1400c000 {
> - compatible = "mediatek,mt8173-disp-ovl";
> - reg = <0 0x1400c000 0 0x1000>;
> - interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - clocks = <&mmsys CLK_MM_DISP_OVL0>;
> - iommus = <&iommu M4U_PORT_DISP_OVL0>;
> - mediatek,larb = <&larb0>;
> - };
> -
> - ovl1: ovl@1400d000 {
> - compatible = "mediatek,mt8173-disp-ovl";
> - reg = <0 0x1400d000 0 0x1000>;
> - interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - clocks = <&mmsys CLK_MM_DISP_OVL1>;
> - iommus = <&iommu M4U_PORT_DISP_OVL1>;
> - mediatek,larb = <&larb4>;
> - };
> -
> - rdma0: rdma@1400e000 {
> - compatible = "mediatek,mt8173-disp-rdma";
> - reg = <0 0x1400e000 0 0x1000>;
> - interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> - iommus = <&iommu M4U_PORT_DISP_RDMA0>;
> - mediatek,larb = <&larb0>;
> - };
> -
> - rdma1: rdma@1400f000 {
> - compatible = "mediatek,mt8173-disp-rdma";
> - reg = <0 0x1400f000 0 0x1000>;
> - interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> - iommus = <&iommu M4U_PORT_DISP_RDMA1>;
> - mediatek,larb = <&larb4>;
> - };
> -
> - rdma2: rdma@14010000 {
> - compatible = "mediatek,mt8173-disp-rdma";
> - reg = <0 0x14010000 0 0x1000>;
> - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - clocks = <&mmsys CLK_MM_DISP_RDMA2>;
> - iommus = <&iommu M4U_PORT_DISP_RDMA2>;
> - mediatek,larb = <&larb4>;
> - };
> -
> - wdma0: wdma@14011000 {
> - compatible = "mediatek,mt8173-disp-wdma";
> - reg = <0 0x14011000 0 0x1000>;
> - interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - clocks = <&mmsys CLK_MM_DISP_WDMA0>;
> - iommus = <&iommu M4U_PORT_DISP_WDMA0>;
> - mediatek,larb = <&larb0>;
> - };
> -
> - wdma1: wdma@14012000 {
> - compatible = "mediatek,mt8173-disp-wdma";
> - reg = <0 0x14012000 0 0x1000>;
> - interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - clocks = <&mmsys CLK_MM_DISP_WDMA1>;
> - iommus = <&iommu M4U_PORT_DISP_WDMA1>;
> - mediatek,larb = <&larb4>;
> - };
> -
> - color0: color@14013000 {
> - compatible = "mediatek,mt8173-disp-color";
> - reg = <0 0x14013000 0 0x1000>;
> - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> - };
> -
> - color1: color@14014000 {
> - compatible = "mediatek,mt8173-disp-color";
> - reg = <0 0x14014000 0 0x1000>;
> - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - clocks = <&mmsys CLK_MM_DISP_COLOR1>;
> - };
> -
> - aal@14015000 {
> - compatible = "mediatek,mt8173-disp-aal";
> - reg = <0 0x14015000 0 0x1000>;
> - interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - clocks = <&mmsys CLK_MM_DISP_AAL>;
> - };
> -
> - gamma@14016000 {
> - compatible = "mediatek,mt8173-disp-gamma";
> - reg = <0 0x14016000 0 0x1000>;
> - interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - clocks = <&mmsys CLK_MM_DISP_GAMMA>;
> - };
> -
> - merge@14017000 {
> - compatible = "mediatek,mt8173-disp-merge";
> - reg = <0 0x14017000 0 0x1000>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - clocks = <&mmsys CLK_MM_DISP_MERGE>;
> - };
> -
> - split0: split@14018000 {
> - compatible = "mediatek,mt8173-disp-split";
> - reg = <0 0x14018000 0 0x1000>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
> - };
> -
> - split1: split@14019000 {
> - compatible = "mediatek,mt8173-disp-split";
> - reg = <0 0x14019000 0 0x1000>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
> - };
> -
> - ufoe@1401a000 {
> - compatible = "mediatek,mt8173-disp-ufoe";
> - reg = <0 0x1401a000 0 0x1000>;
> - interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - clocks = <&mmsys CLK_MM_DISP_UFOE>;
> - };
> -
> - dsi0: dsi@1401b000 {
> - compatible = "mediatek,mt8173-dsi";
> - reg = <0 0x1401b000 0 0x1000>;
> - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
> - <&mmsys CLK_MM_DSI0_DIGITAL>,
> - <&mipi_tx0>;
> - clock-names = "engine", "digital", "hs";
> - phys = <&mipi_tx0>;
> - phy-names = "dphy";
> - status = "disabled";
> - };
> -
> - dsi1: dsi@1401c000 {
> - compatible = "mediatek,mt8173-dsi";
> - reg = <0 0x1401c000 0 0x1000>;
> - interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
> - <&mmsys CLK_MM_DSI1_DIGITAL>,
> - <&mipi_tx1>;
> - clock-names = "engine", "digital", "hs";
> - phy = <&mipi_tx1>;
> - phy-names = "dphy";
> - status = "disabled";
> - };
> -
> - dpi0: dpi@1401d000 {
> - compatible = "mediatek,mt8173-dpi";
> - reg = <0 0x1401d000 0 0x1000>;
> - interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - clocks = <&mmsys CLK_MM_DPI_PIXEL>,
> - <&mmsys CLK_MM_DPI_ENGINE>,
> - <&apmixedsys CLK_APMIXED_TVDPLL>;
> - clock-names = "pixel", "engine", "pll";
> - status = "disabled";
> -
> - port {
> - dpi0_out: endpoint {
> - remote-endpoint = <&hdmi0_in>;
> - };
> - };
> - };
> -
> - pwm0: pwm@1401e000 {
> - compatible = "mediatek,mt8173-disp-pwm",
> - "mediatek,mt6595-disp-pwm";
> - reg = <0 0x1401e000 0 0x1000>;
> - #pwm-cells = <2>;
> - clocks = <&mmsys CLK_MM_DISP_PWM026M>,
> - <&mmsys CLK_MM_DISP_PWM0MM>;
> - clock-names = "main", "mm";
> - status = "disabled";
> - };
> -
> - pwm1: pwm@1401f000 {
> - compatible = "mediatek,mt8173-disp-pwm",
> - "mediatek,mt6595-disp-pwm";
> - reg = <0 0x1401f000 0 0x1000>;
> - #pwm-cells = <2>;
> - clocks = <&mmsys CLK_MM_DISP_PWM126M>,
> - <&mmsys CLK_MM_DISP_PWM1MM>;
> - clock-names = "main", "mm";
> - status = "disabled";
> - };
> -
> - mutex: mutex@14020000 {
> - compatible = "mediatek,mt8173-disp-mutex";
> - reg = <0 0x14020000 0 0x1000>;
> - interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - clocks = <&mmsys CLK_MM_MUTEX_32K>;
> - };
> -
> - larb0: larb@14021000 {
> - compatible = "mediatek,mt8173-smi-larb";
> - reg = <0 0x14021000 0 0x1000>;
> - mediatek,smi = <&smi_common>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - clocks = <&mmsys CLK_MM_SMI_LARB0>,
> - <&mmsys CLK_MM_SMI_LARB0>;
> - clock-names = "apb", "smi";
> - };
> -
> - smi_common: smi@14022000 {
> - compatible = "mediatek,mt8173-smi-common";
> - reg = <0 0x14022000 0 0x1000>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - clocks = <&mmsys CLK_MM_SMI_COMMON>,
> - <&mmsys CLK_MM_SMI_COMMON>;
> - clock-names = "apb", "smi";
> - };
> -
> - od@14023000 {
> - compatible = "mediatek,mt8173-disp-od";
> - reg = <0 0x14023000 0 0x1000>;
> - clocks = <&mmsys CLK_MM_DISP_OD>;
> - };
> -
> - hdmi0: hdmi@14025000 {
> - compatible = "mediatek,mt8173-hdmi";
> - reg = <0 0x14025000 0 0x400>;
> - interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
> - <&mmsys CLK_MM_HDMI_PLLCK>,
> - <&mmsys CLK_MM_HDMI_AUDIO>,
> - <&mmsys CLK_MM_HDMI_SPDIF>;
> - clock-names = "pixel", "pll", "bclk", "spdif";
> - pinctrl-names = "default";
> - pinctrl-0 = <&hdmi_pin>;
> - phys = <&hdmi_phy>;
> - phy-names = "hdmi";
> - mediatek,syscon-hdmi = <&mmsys 0x900>;
> - assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
> - assigned-clock-parents = <&hdmi_phy>;
> - status = "disabled";
> -
> - ports {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - port@0 {
> - reg = <0>;
> -
> - hdmi0_in: endpoint {
> - remote-endpoint = <&dpi0_out>;
> - };
> - };
> - };
> - };
> -
> - larb4: larb@14027000 {
> - compatible = "mediatek,mt8173-smi-larb";
> - reg = <0 0x14027000 0 0x1000>;
> - mediatek,smi = <&smi_common>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - clocks = <&mmsys CLK_MM_SMI_LARB4>,
> - <&mmsys CLK_MM_SMI_LARB4>;
> - clock-names = "apb", "smi";
> - };
> -
> - imgsys: clock-controller@15000000 {
> - compatible = "mediatek,mt8173-imgsys", "syscon";
> - reg = <0 0x15000000 0 0x1000>;
> - #clock-cells = <1>;
> - };
> -
> - larb2: larb@15001000 {
> - compatible = "mediatek,mt8173-smi-larb";
> - reg = <0 0x15001000 0 0x1000>;
> - mediatek,smi = <&smi_common>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>;
> - clocks = <&imgsys CLK_IMG_LARB2_SMI>,
> - <&imgsys CLK_IMG_LARB2_SMI>;
> - clock-names = "apb", "smi";
> - };
> -
> - vdecsys: clock-controller@16000000 {
> - compatible = "mediatek,mt8173-vdecsys", "syscon";
> - reg = <0 0x16000000 0 0x1000>;
> - #clock-cells = <1>;
> - };
> -
> - vcodec_dec: vcodec@16000000 {
> - compatible = "mediatek,mt8173-vcodec-dec";
> - reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */
> - <0 0x16020000 0 0x1000>, /* VDEC_MISC */
> - <0 0x16021000 0 0x800>, /* VDEC_LD */
> - <0 0x16021800 0 0x800>, /* VDEC_TOP */
> - <0 0x16022000 0 0x1000>, /* VDEC_CM */
> - <0 0x16023000 0 0x1000>, /* VDEC_AD */
> - <0 0x16024000 0 0x1000>, /* VDEC_AV */
> - <0 0x16025000 0 0x1000>, /* VDEC_PP */
> - <0 0x16026800 0 0x800>, /* VDEC_HWD */
> - <0 0x16027000 0 0x800>, /* VDEC_HWQ */
> - <0 0x16027800 0 0x800>, /* VDEC_HWB */
> - <0 0x16028400 0 0x400>; /* VDEC_HWG */
> - interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
> - mediatek,larb = <&larb1>;
> - iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
> - <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
> - <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
> - <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
> - <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
> - <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
> - <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
> - <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
> - mediatek,vpu = <&vpu>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
> - clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
> - <&topckgen CLK_TOP_UNIVPLL_D2>,
> - <&topckgen CLK_TOP_CCI400_SEL>,
> - <&topckgen CLK_TOP_VDEC_SEL>,
> - <&topckgen CLK_TOP_VCODECPLL>,
> - <&apmixedsys CLK_APMIXED_VENCPLL>,
> - <&topckgen CLK_TOP_VENC_LT_SEL>,
> - <&topckgen CLK_TOP_VCODECPLL_370P5>;
> - clock-names = "vcodecpll",
> - "univpll_d2",
> - "clk_cci400_sel",
> - "vdec_sel",
> - "vdecpll",
> - "vencpll",
> - "venc_lt_sel",
> - "vdec_bus_clk_src";
> - };
> -
> - larb1: larb@16010000 {
> - compatible = "mediatek,mt8173-smi-larb";
> - reg = <0 0x16010000 0 0x1000>;
> - mediatek,smi = <&smi_common>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
> - clocks = <&vdecsys CLK_VDEC_CKEN>,
> - <&vdecsys CLK_VDEC_LARB_CKEN>;
> - clock-names = "apb", "smi";
> - };
> -
> - vencsys: clock-controller@18000000 {
> - compatible = "mediatek,mt8173-vencsys", "syscon";
> - reg = <0 0x18000000 0 0x1000>;
> - #clock-cells = <1>;
> - };
> -
> - larb3: larb@18001000 {
> - compatible = "mediatek,mt8173-smi-larb";
> - reg = <0 0x18001000 0 0x1000>;
> - mediatek,smi = <&smi_common>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
> - clocks = <&vencsys CLK_VENC_CKE1>,
> - <&vencsys CLK_VENC_CKE0>;
> - clock-names = "apb", "smi";
> - };
> -
> - vcodec_enc: vcodec@18002000 {
> - compatible = "mediatek,mt8173-vcodec-enc";
> - reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */
> - <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
> - interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
> - <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
> - mediatek,larb = <&larb3>,
> - <&larb5>;
> - iommus = <&iommu M4U_PORT_VENC_RCPU>,
> - <&iommu M4U_PORT_VENC_REC>,
> - <&iommu M4U_PORT_VENC_BSDMA>,
> - <&iommu M4U_PORT_VENC_SV_COMV>,
> - <&iommu M4U_PORT_VENC_RD_COMV>,
> - <&iommu M4U_PORT_VENC_CUR_LUMA>,
> - <&iommu M4U_PORT_VENC_CUR_CHROMA>,
> - <&iommu M4U_PORT_VENC_REF_LUMA>,
> - <&iommu M4U_PORT_VENC_REF_CHROMA>,
> - <&iommu M4U_PORT_VENC_NBM_RDMA>,
> - <&iommu M4U_PORT_VENC_NBM_WDMA>,
> - <&iommu M4U_PORT_VENC_RCPU_SET2>,
> - <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
> - <&iommu M4U_PORT_VENC_BSDMA_SET2>,
> - <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
> - <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
> - <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
> - <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
> - <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
> - <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
> - mediatek,vpu = <&vpu>;
> - clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
> - <&topckgen CLK_TOP_VENC_SEL>,
> - <&topckgen CLK_TOP_UNIVPLL1_D2>,
> - <&topckgen CLK_TOP_VENC_LT_SEL>;
> - clock-names = "venc_sel_src",
> - "venc_sel",
> - "venc_lt_sel_src",
> - "venc_lt_sel";
> - };
> -
> - vencltsys: clock-controller@19000000 {
> - compatible = "mediatek,mt8173-vencltsys", "syscon";
> - reg = <0 0x19000000 0 0x1000>;
> - #clock-cells = <1>;
> +&cpu_thermal {
> + cooling-maps {
> + map@0 {
> + trip = <&target>;
> + cooling-device = <&cpu0 0 0>;
> + contribution = <1024>;
> };
> -
> - larb5: larb@19001000 {
> - compatible = "mediatek,mt8173-smi-larb";
> - reg = <0 0x19001000 0 0x1000>;
> - mediatek,smi = <&smi_common>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
> - clocks = <&vencltsys CLK_VENCLT_CKE1>,
> - <&vencltsys CLK_VENCLT_CKE0>;
> - clock-names = "apb", "smi";
> + map@1 {
> + trip = <&target>;
> + cooling-device = <&cpu2 0 0>;
> + contribution = <2048>;
> };
> };
> };
> -
> diff --git a/arch/arm64/boot/dts/mediatek/mt8176.dtsi b/arch/arm64/boot/dts/mediatek/mt8176.dtsi
> new file mode 100644
> index 0000000..2925905
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8176.dtsi
> @@ -0,0 +1,125 @@
> +/*
> + * Copyright (c) 2017 MediaTek Inc.
> + * Author: Yidi Lin <yidi.lin@mediatek.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include "mt817x.dtsi"
> +
> +/ {
> + compatible = "mediatek,mt8176";
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + core2 {
> + cpu = <&cpu2>;
> + };
> + core3 {
> + cpu = <&cpu3>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&cpu4>;
> + };
> + core1 {
> + cpu = <&cpu5>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x000>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x001>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0>;
> + };
> +
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x002>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0>;
> + };
> +
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x003>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0>;
> + };
> +
> + cpu4: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0>;
> + };
> +
> + cpu5: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0>;
> + };
> +
> + idle-states {
> + entry-method = "psci";
> +
> + CPU_SLEEP_0: cpu-sleep-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <639>;
> + exit-latency-us = <680>;
> + min-residency-us = <1088>;
> + arm,psci-suspend-param = <0x0010000>;
> + };
> + };
> + };
> +};
> +
> +&cpu_thermal {
> + cooling-maps {
> + map@0 {
> + trip = <&target>;
> + cooling-device = <&cpu0 0 0>;
> + contribution = <1024>;
> + };
> + map@1 {
> + trip = <&target>;
> + cooling-device = <&cpu4 0 0>;
> + contribution = <2048>;
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/mediatek/mt817x.dtsi b/arch/arm64/boot/dts/mediatek/mt817x.dtsi
> new file mode 100644
> index 0000000..ad18439
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt817x.dtsi
> @@ -0,0 +1,1199 @@
> +/*
> + * Copyright (c) 2016 MediaTek Inc.
> + * Author: Eddie Huang <eddie.huang@mediatek.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <dt-bindings/clock/mt8173-clk.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/memory/mt8173-larb-port.h>
> +#include <dt-bindings/phy/phy.h>
> +#include <dt-bindings/power/mt8173-power.h>
> +#include <dt-bindings/reset/mt8173-resets.h>
> +#include "mt8173-pinfunc.h"
> +
> +/ {
> + compatible = "mediatek,mt817x";
> + interrupt-parent = <&sysirq>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + ovl0 = &ovl0;
> + ovl1 = &ovl1;
> + rdma0 = &rdma0;
> + rdma1 = &rdma1;
> + rdma2 = &rdma2;
> + wdma0 = &wdma0;
> + wdma1 = &wdma1;
> + color0 = &color0;
> + color1 = &color1;
> + split0 = &split0;
> + split1 = &split1;
> + dpi0 = &dpi0;
> + dsi0 = &dsi0;
> + dsi1 = &dsi1;
> + mdp_rdma0 = &mdp_rdma0;
> + mdp_rdma1 = &mdp_rdma1;
> + mdp_rsz0 = &mdp_rsz0;
> + mdp_rsz1 = &mdp_rsz1;
> + mdp_rsz2 = &mdp_rsz2;
> + mdp_wdma0 = &mdp_wdma0;
> + mdp_wrot0 = &mdp_wrot0;
> + mdp_wrot1 = &mdp_wrot1;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
> + method = "smc";
> + cpu_suspend = <0x84000001>;
> + cpu_off = <0x84000002>;
> + cpu_on = <0x84000003>;
> + };
> +
> + clk26m: oscillator@0 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + clock-output-names = "clk26m";
> + };
> +
> + clk32k: oscillator@1 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32000>;
> + clock-output-names = "clk32k";
> + };
> +
> + cpum_ck: oscillator@2 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <0>;
> + clock-output-names = "cpum_ck";
> + };
> +
> + thermal-zones {
> + cpu_thermal: cpu_thermal {
> + polling-delay-passive = <1000>; /* milliseconds */
> + polling-delay = <1000>; /* milliseconds */
> +
> + thermal-sensors = <&thermal>;
> + sustainable-power = <1500>; /* milliwatts */
> +
> + trips {
> + threshold: trip-point@0 {
> + temperature = <68000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + target: trip-point@1 {
> + temperature = <85000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit: cpu_crit@0 {
> + temperature = <115000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> + };
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + vpu_dma_reserved: vpu_dma_mem_region {
> + compatible = "shared-dma-pool";
> + reg = <0 0xb7000000 0 0x500000>;
> + alignment = <0x1000>;
> + no-map;
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_PPI 13
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + topckgen: clock-controller@10000000 {
> + compatible = "mediatek,mt8173-topckgen";
> + reg = <0 0x10000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + infracfg: power-controller@10001000 {
> + compatible = "mediatek,mt8173-infracfg", "syscon";
> + reg = <0 0x10001000 0 0x1000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + pericfg: power-controller@10003000 {
> + compatible = "mediatek,mt8173-pericfg", "syscon";
> + reg = <0 0x10003000 0 0x1000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + syscfg_pctl_a: syscfg_pctl_a@10005000 {
> + compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
> + reg = <0 0x10005000 0 0x1000>;
> + };
> +
> + pio: pinctrl@0x10005000 {
> + compatible = "mediatek,mt8173-pinctrl";
> + reg = <0 0x1000b000 0 0x1000>;
> + mediatek,pctl-regmap = <&syscfg_pctl_a>;
> + pins-are-numbered;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> +
> + hdmi_pin: xxx {
> +
> + /*hdmi htplg pin*/
> + pins1 {
> + pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
> + input-enable;
> + bias-pull-down;
> + };
> + };
> +
> + i2c0_pins_a: i2c0 {
> + pins1 {
> + pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
> + <MT8173_PIN_46_SCL0__FUNC_SCL0>;
> + bias-disable;
> + };
> + };
> +
> + i2c1_pins_a: i2c1 {
> + pins1 {
> + pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
> + <MT8173_PIN_126_SCL1__FUNC_SCL1>;
> + bias-disable;
> + };
> + };
> +
> + i2c2_pins_a: i2c2 {
> + pins1 {
> + pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
> + <MT8173_PIN_44_SCL2__FUNC_SCL2>;
> + bias-disable;
> + };
> + };
> +
> + i2c3_pins_a: i2c3 {
> + pins1 {
> + pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
> + <MT8173_PIN_107_SCL3__FUNC_SCL3>;
> + bias-disable;
> + };
> + };
> +
> + i2c4_pins_a: i2c4 {
> + pins1 {
> + pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
> + <MT8173_PIN_134_SCL4__FUNC_SCL4>;
> + bias-disable;
> + };
> + };
> +
> + i2c6_pins_a: i2c6 {
> + pins1 {
> + pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
> + <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
> + bias-disable;
> + };
> + };
> + };
> +
> + scpsys: scpsys@10006000 {
> + compatible = "mediatek,mt8173-scpsys";
> + #power-domain-cells = <1>;
> + reg = <0 0x10006000 0 0x1000>;
> + clocks = <&clk26m>,
> + <&topckgen CLK_TOP_MM_SEL>,
> + <&topckgen CLK_TOP_VENC_SEL>,
> + <&topckgen CLK_TOP_VENC_LT_SEL>;
> + clock-names = "mfg", "mm", "venc", "venc_lt";
> + infracfg = <&infracfg>;
> + };
> +
> + watchdog: watchdog@10007000 {
> + compatible = "mediatek,mt8173-wdt",
> + "mediatek,mt6589-wdt";
> + reg = <0 0x10007000 0 0x100>;
> + };
> +
> + timer: timer@10008000 {
> + compatible = "mediatek,mt8173-timer",
> + "mediatek,mt6577-timer";
> + reg = <0 0x10008000 0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&infracfg CLK_INFRA_CLK_13M>,
> + <&topckgen CLK_TOP_RTC_SEL>;
> + };
> +
> + pwrap: pwrap@1000d000 {
> + compatible = "mediatek,mt8173-pwrap";
> + reg = <0 0x1000d000 0 0x1000>;
> + reg-names = "pwrap";
> + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> + resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
> + reset-names = "pwrap";
> + clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
> + clock-names = "spi", "wrap";
> + };
> +
> + cec: cec@10013000 {
> + compatible = "mediatek,mt8173-cec";
> + reg = <0 0x10013000 0 0xbc>;
> + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&infracfg CLK_INFRA_CEC>;
> + status = "disabled";
> + };
> +
> + vpu: vpu@10020000 {
> + compatible = "mediatek,mt8173-vpu";
> + reg = <0 0x10020000 0 0x30000>,
> + <0 0x10050000 0 0x100>;
> + reg-names = "tcm", "cfg_reg";
> + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&topckgen CLK_TOP_SCP_SEL>;
> + clock-names = "main";
> + memory-region = <&vpu_dma_reserved>;
> + };
> +
> + sysirq: intpol-controller@10200620 {
> + compatible = "mediatek,mt8173-sysirq",
> + "mediatek,mt6577-sysirq";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupt-parent = <&gic>;
> + reg = <0 0x10200620 0 0x20>;
> + };
> +
> + iommu: iommu@10205000 {
> + compatible = "mediatek,mt8173-m4u";
> + reg = <0 0x10205000 0 0x1000>;
> + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&infracfg CLK_INFRA_M4U>;
> + clock-names = "bclk";
> + mediatek,larbs = <&larb0 &larb1 &larb2
> + &larb3 &larb4 &larb5>;
> + #iommu-cells = <1>;
> + };
> +
> + efuse: efuse@10206000 {
> + compatible = "mediatek,mt8173-efuse";
> + reg = <0 0x10206000 0 0x1000>;
> + };
> +
> + apmixedsys: clock-controller@10209000 {
> + compatible = "mediatek,mt8173-apmixedsys";
> + reg = <0 0x10209000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + hdmi_phy: hdmi-phy@10209100 {
> + compatible = "mediatek,mt8173-hdmi-phy";
> + reg = <0 0x10209100 0 0x24>;
> + clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
> + clock-names = "pll_ref";
> + clock-output-names = "hdmitx_dig_cts";
> + mediatek,ibias = <0xa>;
> + mediatek,ibias_up = <0x1c>;
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> + mipi_tx0: mipi-dphy@10215000 {
> + compatible = "mediatek,mt8173-mipi-tx";
> + reg = <0 0x10215000 0 0x1000>;
> + clocks = <&clk26m>;
> + clock-output-names = "mipi_tx0_pll";
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> + mipi_tx1: mipi-dphy@10216000 {
> + compatible = "mediatek,mt8173-mipi-tx";
> + reg = <0 0x10216000 0 0x1000>;
> + clocks = <&clk26m>;
> + clock-output-names = "mipi_tx1_pll";
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> + gic: interrupt-controller@10220000 {
> + compatible = "arm,gic-400";
> + #interrupt-cells = <3>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + reg = <0 0x10221000 0 0x1000>,
> + <0 0x10222000 0 0x2000>,
> + <0 0x10224000 0 0x2000>,
> + <0 0x10226000 0 0x2000>;
> + interrupts = <GIC_PPI 9
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + auxadc: auxadc@11001000 {
> + compatible = "mediatek,mt8173-auxadc";
> + reg = <0 0x11001000 0 0x1000>;
> + clocks = <&pericfg CLK_PERI_AUXADC>;
> + clock-names = "main";
> + #io-channel-cells = <1>;
> + };
> +
> + uart0: serial@11002000 {
> + compatible = "mediatek,mt8173-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11002000 0 0x400>;
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + uart1: serial@11003000 {
> + compatible = "mediatek,mt8173-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11003000 0 0x400>;
> + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + uart2: serial@11004000 {
> + compatible = "mediatek,mt8173-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11004000 0 0x400>;
> + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + uart3: serial@11005000 {
> + compatible = "mediatek,mt8173-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11005000 0 0x400>;
> + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + i2c0: i2c@11007000 {
> + compatible = "mediatek,mt8173-i2c";
> + reg = <0 0x11007000 0 0x70>,
> + <0 0x11000100 0 0x80>;
> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
> + clock-div = <16>;
> + clocks = <&pericfg CLK_PERI_I2C0>,
> + <&pericfg CLK_PERI_AP_DMA>;
> + clock-names = "main", "dma";
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0_pins_a>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c@11008000 {
> + compatible = "mediatek,mt8173-i2c";
> + reg = <0 0x11008000 0 0x70>,
> + <0 0x11000180 0 0x80>;
> + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
> + clock-div = <16>;
> + clocks = <&pericfg CLK_PERI_I2C1>,
> + <&pericfg CLK_PERI_AP_DMA>;
> + clock-names = "main", "dma";
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c1_pins_a>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c2: i2c@11009000 {
> + compatible = "mediatek,mt8173-i2c";
> + reg = <0 0x11009000 0 0x70>,
> + <0 0x11000200 0 0x80>;
> + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
> + clock-div = <16>;
> + clocks = <&pericfg CLK_PERI_I2C2>,
> + <&pericfg CLK_PERI_AP_DMA>;
> + clock-names = "main", "dma";
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c2_pins_a>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + spi: spi@1100a000 {
> + compatible = "mediatek,mt8173-spi";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0 0x1100a000 0 0x1000>;
> + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
> + <&topckgen CLK_TOP_SPI_SEL>,
> + <&pericfg CLK_PERI_SPI0>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + status = "disabled";
> + };
> +
> + thermal: thermal@1100b000 {
> + #thermal-sensor-cells = <0>;
> + compatible = "mediatek,mt8173-thermal";
> + reg = <0 0x1100b000 0 0x1000>;
> + interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
> + clock-names = "therm", "auxadc";
> + resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
> + mediatek,auxadc = <&auxadc>;
> + mediatek,apmixedsys = <&apmixedsys>;
> + };
> +
> + nor_flash: spi@1100d000 {
> + compatible = "mediatek,mt8173-nor";
> + reg = <0 0x1100d000 0 0xe0>;
> + clocks = <&pericfg CLK_PERI_SPI>,
> + <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
> + clock-names = "spi", "sf";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c3: i2c@11010000 {
> + compatible = "mediatek,mt8173-i2c";
> + reg = <0 0x11010000 0 0x70>,
> + <0 0x11000280 0 0x80>;
> + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
> + clock-div = <16>;
> + clocks = <&pericfg CLK_PERI_I2C3>,
> + <&pericfg CLK_PERI_AP_DMA>;
> + clock-names = "main", "dma";
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c3_pins_a>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c4: i2c@11011000 {
> + compatible = "mediatek,mt8173-i2c";
> + reg = <0 0x11011000 0 0x70>,
> + <0 0x11000300 0 0x80>;
> + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
> + clock-div = <16>;
> + clocks = <&pericfg CLK_PERI_I2C4>,
> + <&pericfg CLK_PERI_AP_DMA>;
> + clock-names = "main", "dma";
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c4_pins_a>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + hdmiddc0: i2c@11012000 {
> + compatible = "mediatek,mt8173-hdmi-ddc";
> + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
> + reg = <0 0x11012000 0 0x1C>;
> + clocks = <&pericfg CLK_PERI_I2C5>;
> + clock-names = "ddc-i2c";
> + };
> +
> + i2c6: i2c@11013000 {
> + compatible = "mediatek,mt8173-i2c";
> + reg = <0 0x11013000 0 0x70>,
> + <0 0x11000080 0 0x80>;
> + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
> + clock-div = <16>;
> + clocks = <&pericfg CLK_PERI_I2C6>,
> + <&pericfg CLK_PERI_AP_DMA>;
> + clock-names = "main", "dma";
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c6_pins_a>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + afe: audio-controller@11220000 {
> + compatible = "mediatek,mt8173-afe-pcm";
> + reg = <0 0x11220000 0 0x1000>;
> + interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
> + clocks = <&infracfg CLK_INFRA_AUDIO>,
> + <&topckgen CLK_TOP_AUDIO_SEL>,
> + <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
> + <&topckgen CLK_TOP_APLL1_DIV0>,
> + <&topckgen CLK_TOP_APLL2_DIV0>,
> + <&topckgen CLK_TOP_I2S0_M_SEL>,
> + <&topckgen CLK_TOP_I2S1_M_SEL>,
> + <&topckgen CLK_TOP_I2S2_M_SEL>,
> + <&topckgen CLK_TOP_I2S3_M_SEL>,
> + <&topckgen CLK_TOP_I2S3_B_SEL>;
> + clock-names = "infra_sys_audio_clk",
> + "top_pdn_audio",
> + "top_pdn_aud_intbus",
> + "bck0",
> + "bck1",
> + "i2s0_m",
> + "i2s1_m",
> + "i2s2_m",
> + "i2s3_m",
> + "i2s3_b";
> + assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
> + <&topckgen CLK_TOP_AUD_2_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
> + <&topckgen CLK_TOP_APLL2>;
> + };
> +
> + mmc0: mmc@11230000 {
> + compatible = "mediatek,mt8173-mmc",
> + "mediatek,mt8135-mmc";
> + reg = <0 0x11230000 0 0x1000>;
> + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&pericfg CLK_PERI_MSDC30_0>,
> + <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
> + clock-names = "source", "hclk";
> + status = "disabled";
> + };
> +
> + mmc1: mmc@11240000 {
> + compatible = "mediatek,mt8173-mmc",
> + "mediatek,mt8135-mmc";
> + reg = <0 0x11240000 0 0x1000>;
> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&pericfg CLK_PERI_MSDC30_1>,
> + <&topckgen CLK_TOP_AXI_SEL>;
> + clock-names = "source", "hclk";
> + status = "disabled";
> + };
> +
> + mmc2: mmc@11250000 {
> + compatible = "mediatek,mt8173-mmc",
> + "mediatek,mt8135-mmc";
> + reg = <0 0x11250000 0 0x1000>;
> + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&pericfg CLK_PERI_MSDC30_2>,
> + <&topckgen CLK_TOP_AXI_SEL>;
> + clock-names = "source", "hclk";
> + status = "disabled";
> + };
> +
> + mmc3: mmc@11260000 {
> + compatible = "mediatek,mt8173-mmc",
> + "mediatek,mt8135-mmc";
> + reg = <0 0x11260000 0 0x1000>;
> + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&pericfg CLK_PERI_MSDC30_3>,
> + <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
> + clock-names = "source", "hclk";
> + status = "disabled";
> + };
> +
> + ssusb: usb@11271000 {
> + compatible = "mediatek,mt8173-mtu3";
> + reg = <0 0x11271000 0 0x3000>,
> + <0 0x11280700 0 0x0100>;
> + reg-names = "mac", "ippc";
> + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
> + phys = <&phy_port0 PHY_TYPE_USB3>,
> + <&phy_port1 PHY_TYPE_USB2>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
> + clocks = <&topckgen CLK_TOP_USB30_SEL>,
> + <&pericfg CLK_PERI_USB0>,
> + <&pericfg CLK_PERI_USB1>;
> + clock-names = "sys_ck",
> + "wakeup_deb_p0",
> + "wakeup_deb_p1";
> + mediatek,syscon-wakeup = <&pericfg>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + usb_host: xhci@11270000 {
> + compatible = "mediatek,mt8173-xhci";
> + reg = <0 0x11270000 0 0x1000>;
> + reg-names = "mac";
> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
> + clocks = <&topckgen CLK_TOP_USB30_SEL>;
> + clock-names = "sys_ck";
> + status = "disabled";
> + };
> + };
> +
> + u3phy: usb-phy@11290000 {
> + compatible = "mediatek,mt8173-u3phy";
> + reg = <0 0x11290000 0 0x800>;
> + clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
> + clock-names = "u3phya_ref";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "okay";
> +
> + phy_port0: port@11290800 {
> + reg = <0 0x11290800 0 0x800>;
> + #phy-cells = <1>;
> + status = "okay";
> + };
> +
> + phy_port1: port@11291000 {
> + reg = <0 0x11291000 0 0x800>;
> + #phy-cells = <1>;
> + status = "okay";
> + };
> + };
> +
> + mmsys: clock-controller@14000000 {
> + compatible = "mediatek,mt8173-mmsys", "syscon";
> + reg = <0 0x14000000 0 0x1000>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + #clock-cells = <1>;
> + };
> +
> + mdp {
> + compatible = "mediatek,mt8173-mdp";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + mediatek,vpu = <&vpu>;
> +
> + mdp_rdma0: rdma@14001000 {
> + compatible = "mediatek,mt8173-mdp-rdma";
> + reg = <0 0x14001000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RDMA0>,
> + <&mmsys CLK_MM_MUTEX_32K>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + iommus = <&iommu M4U_PORT_MDP_RDMA0>;
> + mediatek,larb = <&larb0>;
> + };
> +
> + mdp_rdma1: rdma@14002000 {
> + compatible = "mediatek,mt8173-mdp-rdma";
> + reg = <0 0x14002000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RDMA1>,
> + <&mmsys CLK_MM_MUTEX_32K>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + iommus = <&iommu M4U_PORT_MDP_RDMA1>;
> + mediatek,larb = <&larb4>;
> + };
> +
> + mdp_rsz0: rsz@14003000 {
> + compatible = "mediatek,mt8173-mdp-rsz";
> + reg = <0 0x14003000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RSZ0>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + };
> +
> + mdp_rsz1: rsz@14004000 {
> + compatible = "mediatek,mt8173-mdp-rsz";
> + reg = <0 0x14004000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RSZ1>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + };
> +
> + mdp_rsz2: rsz@14005000 {
> + compatible = "mediatek,mt8173-mdp-rsz";
> + reg = <0 0x14005000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RSZ2>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + };
> +
> + mdp_wdma0: wdma@14006000 {
> + compatible = "mediatek,mt8173-mdp-wdma";
> + reg = <0 0x14006000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_WDMA>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + iommus = <&iommu M4U_PORT_MDP_WDMA>;
> + mediatek,larb = <&larb0>;
> + };
> +
> + mdp_wrot0: wrot@14007000 {
> + compatible = "mediatek,mt8173-mdp-wrot";
> + reg = <0 0x14007000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_WROT0>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + iommus = <&iommu M4U_PORT_MDP_WROT0>;
> + mediatek,larb = <&larb0>;
> + };
> +
> + mdp_wrot1: wrot@14008000 {
> + compatible = "mediatek,mt8173-mdp-wrot";
> + reg = <0 0x14008000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_WROT1>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + iommus = <&iommu M4U_PORT_MDP_WROT1>;
> + mediatek,larb = <&larb4>;
> + };
> + };
> +
> + ovl0: ovl@1400c000 {
> + compatible = "mediatek,mt8173-disp-ovl";
> + reg = <0 0x1400c000 0 0x1000>;
> + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&mmsys CLK_MM_DISP_OVL0>;
> + iommus = <&iommu M4U_PORT_DISP_OVL0>;
> + mediatek,larb = <&larb0>;
> + };
> +
> + ovl1: ovl@1400d000 {
> + compatible = "mediatek,mt8173-disp-ovl";
> + reg = <0 0x1400d000 0 0x1000>;
> + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&mmsys CLK_MM_DISP_OVL1>;
> + iommus = <&iommu M4U_PORT_DISP_OVL1>;
> + mediatek,larb = <&larb4>;
> + };
> +
> + rdma0: rdma@1400e000 {
> + compatible = "mediatek,mt8173-disp-rdma";
> + reg = <0 0x1400e000 0 0x1000>;
> + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> + iommus = <&iommu M4U_PORT_DISP_RDMA0>;
> + mediatek,larb = <&larb0>;
> + };
> +
> + rdma1: rdma@1400f000 {
> + compatible = "mediatek,mt8173-disp-rdma";
> + reg = <0 0x1400f000 0 0x1000>;
> + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> + iommus = <&iommu M4U_PORT_DISP_RDMA1>;
> + mediatek,larb = <&larb4>;
> + };
> +
> + rdma2: rdma@14010000 {
> + compatible = "mediatek,mt8173-disp-rdma";
> + reg = <0 0x14010000 0 0x1000>;
> + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA2>;
> + iommus = <&iommu M4U_PORT_DISP_RDMA2>;
> + mediatek,larb = <&larb4>;
> + };
> +
> + wdma0: wdma@14011000 {
> + compatible = "mediatek,mt8173-disp-wdma";
> + reg = <0 0x14011000 0 0x1000>;
> + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&mmsys CLK_MM_DISP_WDMA0>;
> + iommus = <&iommu M4U_PORT_DISP_WDMA0>;
> + mediatek,larb = <&larb0>;
> + };
> +
> + wdma1: wdma@14012000 {
> + compatible = "mediatek,mt8173-disp-wdma";
> + reg = <0 0x14012000 0 0x1000>;
> + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&mmsys CLK_MM_DISP_WDMA1>;
> + iommus = <&iommu M4U_PORT_DISP_WDMA1>;
> + mediatek,larb = <&larb4>;
> + };
> +
> + color0: color@14013000 {
> + compatible = "mediatek,mt8173-disp-color";
> + reg = <0 0x14013000 0 0x1000>;
> + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> + };
> +
> + color1: color@14014000 {
> + compatible = "mediatek,mt8173-disp-color";
> + reg = <0 0x14014000 0 0x1000>;
> + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&mmsys CLK_MM_DISP_COLOR1>;
> + };
> +
> + aal@14015000 {
> + compatible = "mediatek,mt8173-disp-aal";
> + reg = <0 0x14015000 0 0x1000>;
> + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&mmsys CLK_MM_DISP_AAL>;
> + };
> +
> + gamma@14016000 {
> + compatible = "mediatek,mt8173-disp-gamma";
> + reg = <0 0x14016000 0 0x1000>;
> + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&mmsys CLK_MM_DISP_GAMMA>;
> + };
> +
> + merge@14017000 {
> + compatible = "mediatek,mt8173-disp-merge";
> + reg = <0 0x14017000 0 0x1000>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&mmsys CLK_MM_DISP_MERGE>;
> + };
> +
> + split0: split@14018000 {
> + compatible = "mediatek,mt8173-disp-split";
> + reg = <0 0x14018000 0 0x1000>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
> + };
> +
> + split1: split@14019000 {
> + compatible = "mediatek,mt8173-disp-split";
> + reg = <0 0x14019000 0 0x1000>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
> + };
> +
> + ufoe@1401a000 {
> + compatible = "mediatek,mt8173-disp-ufoe";
> + reg = <0 0x1401a000 0 0x1000>;
> + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&mmsys CLK_MM_DISP_UFOE>;
> + };
> +
> + dsi0: dsi@1401b000 {
> + compatible = "mediatek,mt8173-dsi";
> + reg = <0 0x1401b000 0 0x1000>;
> + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
> + <&mmsys CLK_MM_DSI0_DIGITAL>,
> + <&mipi_tx0>;
> + clock-names = "engine", "digital", "hs";
> + phys = <&mipi_tx0>;
> + phy-names = "dphy";
> + status = "disabled";
> + };
> +
> + dsi1: dsi@1401c000 {
> + compatible = "mediatek,mt8173-dsi";
> + reg = <0 0x1401c000 0 0x1000>;
> + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
> + <&mmsys CLK_MM_DSI1_DIGITAL>,
> + <&mipi_tx1>;
> + clock-names = "engine", "digital", "hs";
> + phy = <&mipi_tx1>;
> + phy-names = "dphy";
> + status = "disabled";
> + };
> +
> + dpi0: dpi@1401d000 {
> + compatible = "mediatek,mt8173-dpi";
> + reg = <0 0x1401d000 0 0x1000>;
> + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&mmsys CLK_MM_DPI_PIXEL>,
> + <&mmsys CLK_MM_DPI_ENGINE>,
> + <&apmixedsys CLK_APMIXED_TVDPLL>;
> + clock-names = "pixel", "engine", "pll";
> + status = "disabled";
> +
> + port {
> + dpi0_out: endpoint {
> + remote-endpoint = <&hdmi0_in>;
> + };
> + };
> + };
> +
> + pwm0: pwm@1401e000 {
> + compatible = "mediatek,mt8173-disp-pwm",
> + "mediatek,mt6595-disp-pwm";
> + reg = <0 0x1401e000 0 0x1000>;
> + #pwm-cells = <2>;
> + clocks = <&mmsys CLK_MM_DISP_PWM026M>,
> + <&mmsys CLK_MM_DISP_PWM0MM>;
> + clock-names = "main", "mm";
> + status = "disabled";
> + };
> +
> + pwm1: pwm@1401f000 {
> + compatible = "mediatek,mt8173-disp-pwm",
> + "mediatek,mt6595-disp-pwm";
> + reg = <0 0x1401f000 0 0x1000>;
> + #pwm-cells = <2>;
> + clocks = <&mmsys CLK_MM_DISP_PWM126M>,
> + <&mmsys CLK_MM_DISP_PWM1MM>;
> + clock-names = "main", "mm";
> + status = "disabled";
> + };
> +
> + mutex: mutex@14020000 {
> + compatible = "mediatek,mt8173-disp-mutex";
> + reg = <0 0x14020000 0 0x1000>;
> + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&mmsys CLK_MM_MUTEX_32K>;
> + };
> +
> + larb0: larb@14021000 {
> + compatible = "mediatek,mt8173-smi-larb";
> + reg = <0 0x14021000 0 0x1000>;
> + mediatek,smi = <&smi_common>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&mmsys CLK_MM_SMI_LARB0>,
> + <&mmsys CLK_MM_SMI_LARB0>;
> + clock-names = "apb", "smi";
> + };
> +
> + smi_common: smi@14022000 {
> + compatible = "mediatek,mt8173-smi-common";
> + reg = <0 0x14022000 0 0x1000>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&mmsys CLK_MM_SMI_COMMON>,
> + <&mmsys CLK_MM_SMI_COMMON>;
> + clock-names = "apb", "smi";
> + };
> +
> + od@14023000 {
> + compatible = "mediatek,mt8173-disp-od";
> + reg = <0 0x14023000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_DISP_OD>;
> + };
> +
> + hdmi0: hdmi@14025000 {
> + compatible = "mediatek,mt8173-hdmi";
> + reg = <0 0x14025000 0 0x400>;
> + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
> + <&mmsys CLK_MM_HDMI_PLLCK>,
> + <&mmsys CLK_MM_HDMI_AUDIO>,
> + <&mmsys CLK_MM_HDMI_SPDIF>;
> + clock-names = "pixel", "pll", "bclk", "spdif";
> + pinctrl-names = "default";
> + pinctrl-0 = <&hdmi_pin>;
> + phys = <&hdmi_phy>;
> + phy-names = "hdmi";
> + mediatek,syscon-hdmi = <&mmsys 0x900>;
> + assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
> + assigned-clock-parents = <&hdmi_phy>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + hdmi0_in: endpoint {
> + remote-endpoint = <&dpi0_out>;
> + };
> + };
> + };
> + };
> +
> + larb4: larb@14027000 {
> + compatible = "mediatek,mt8173-smi-larb";
> + reg = <0 0x14027000 0 0x1000>;
> + mediatek,smi = <&smi_common>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&mmsys CLK_MM_SMI_LARB4>,
> + <&mmsys CLK_MM_SMI_LARB4>;
> + clock-names = "apb", "smi";
> + };
> +
> + imgsys: clock-controller@15000000 {
> + compatible = "mediatek,mt8173-imgsys", "syscon";
> + reg = <0 0x15000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + larb2: larb@15001000 {
> + compatible = "mediatek,mt8173-smi-larb";
> + reg = <0 0x15001000 0 0x1000>;
> + mediatek,smi = <&smi_common>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>;
> + clocks = <&imgsys CLK_IMG_LARB2_SMI>,
> + <&imgsys CLK_IMG_LARB2_SMI>;
> + clock-names = "apb", "smi";
> + };
> +
> + vdecsys: clock-controller@16000000 {
> + compatible = "mediatek,mt8173-vdecsys", "syscon";
> + reg = <0 0x16000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + vcodec_dec: vcodec@16000000 {
> + compatible = "mediatek,mt8173-vcodec-dec";
> + reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */
> + <0 0x16020000 0 0x1000>, /* VDEC_MISC */
> + <0 0x16021000 0 0x800>, /* VDEC_LD */
> + <0 0x16021800 0 0x800>, /* VDEC_TOP */
> + <0 0x16022000 0 0x1000>, /* VDEC_CM */
> + <0 0x16023000 0 0x1000>, /* VDEC_AD */
> + <0 0x16024000 0 0x1000>, /* VDEC_AV */
> + <0 0x16025000 0 0x1000>, /* VDEC_PP */
> + <0 0x16026800 0 0x800>, /* VDEC_HWD */
> + <0 0x16027000 0 0x800>, /* VDEC_HWQ */
> + <0 0x16027800 0 0x800>, /* VDEC_HWB */
> + <0 0x16028400 0 0x400>; /* VDEC_HWG */
> + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
> + mediatek,larb = <&larb1>;
> + iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
> + <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
> + <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
> + <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
> + <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
> + <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
> + <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
> + <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
> + mediatek,vpu = <&vpu>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
> + clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
> + <&topckgen CLK_TOP_UNIVPLL_D2>,
> + <&topckgen CLK_TOP_CCI400_SEL>,
> + <&topckgen CLK_TOP_VDEC_SEL>,
> + <&topckgen CLK_TOP_VCODECPLL>,
> + <&apmixedsys CLK_APMIXED_VENCPLL>,
> + <&topckgen CLK_TOP_VENC_LT_SEL>,
> + <&topckgen CLK_TOP_VCODECPLL_370P5>;
> + clock-names = "vcodecpll",
> + "univpll_d2",
> + "clk_cci400_sel",
> + "vdec_sel",
> + "vdecpll",
> + "vencpll",
> + "venc_lt_sel",
> + "vdec_bus_clk_src";
> + };
> +
> + larb1: larb@16010000 {
> + compatible = "mediatek,mt8173-smi-larb";
> + reg = <0 0x16010000 0 0x1000>;
> + mediatek,smi = <&smi_common>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
> + clocks = <&vdecsys CLK_VDEC_CKEN>,
> + <&vdecsys CLK_VDEC_LARB_CKEN>;
> + clock-names = "apb", "smi";
> + };
> +
> + vencsys: clock-controller@18000000 {
> + compatible = "mediatek,mt8173-vencsys", "syscon";
> + reg = <0 0x18000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + larb3: larb@18001000 {
> + compatible = "mediatek,mt8173-smi-larb";
> + reg = <0 0x18001000 0 0x1000>;
> + mediatek,smi = <&smi_common>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
> + clocks = <&vencsys CLK_VENC_CKE1>,
> + <&vencsys CLK_VENC_CKE0>;
> + clock-names = "apb", "smi";
> + };
> +
> + vcodec_enc: vcodec@18002000 {
> + compatible = "mediatek,mt8173-vcodec-enc";
> + reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */
> + <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
> + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
> + mediatek,larb = <&larb3>,
> + <&larb5>;
> + iommus = <&iommu M4U_PORT_VENC_RCPU>,
> + <&iommu M4U_PORT_VENC_REC>,
> + <&iommu M4U_PORT_VENC_BSDMA>,
> + <&iommu M4U_PORT_VENC_SV_COMV>,
> + <&iommu M4U_PORT_VENC_RD_COMV>,
> + <&iommu M4U_PORT_VENC_CUR_LUMA>,
> + <&iommu M4U_PORT_VENC_CUR_CHROMA>,
> + <&iommu M4U_PORT_VENC_REF_LUMA>,
> + <&iommu M4U_PORT_VENC_REF_CHROMA>,
> + <&iommu M4U_PORT_VENC_NBM_RDMA>,
> + <&iommu M4U_PORT_VENC_NBM_WDMA>,
> + <&iommu M4U_PORT_VENC_RCPU_SET2>,
> + <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
> + <&iommu M4U_PORT_VENC_BSDMA_SET2>,
> + <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
> + <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
> + <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
> + <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
> + <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
> + <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
> + mediatek,vpu = <&vpu>;
> + clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
> + <&topckgen CLK_TOP_VENC_SEL>,
> + <&topckgen CLK_TOP_UNIVPLL1_D2>,
> + <&topckgen CLK_TOP_VENC_LT_SEL>;
> + clock-names = "venc_sel_src",
> + "venc_sel",
> + "venc_lt_sel_src",
> + "venc_lt_sel";
> + };
> +
> + vencltsys: clock-controller@19000000 {
> + compatible = "mediatek,mt8173-vencltsys", "syscon";
> + reg = <0 0x19000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + larb5: larb@19001000 {
> + compatible = "mediatek,mt8173-smi-larb";
> + reg = <0 0x19001000 0 0x1000>;
> + mediatek,smi = <&smi_common>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
> + clocks = <&vencltsys CLK_VENCLT_CKE1>,
> + <&vencltsys CLK_VENCLT_CKE0>;
> + clock-names = "apb", "smi";
> + };
> + };
> +};
> +
>
^ permalink raw reply
* Re: [PATCH -next] [media] mtk-vcodec: remove redundant return value check of platform_get_resource()
From: Tiffany Lin @ 2017-02-10 3:35 UTC (permalink / raw)
To: Wei Yongjun
Cc: Andrew-CT Chen, Mauro Carvalho Chehab, Matthias Brugger,
Wei Yongjun, linux-media, linux-arm-kernel, linux-mediatek
In-Reply-To: <20170207151620.12711-1-weiyj.lk@gmail.com>
On Tue, 2017-02-07 at 15:16 +0000, Wei Yongjun wrote:
> From: Wei Yongjun <weiyongjun1@huawei.com>
>
> Remove unneeded error handling on the result of a call
> to platform_get_resource() when the value is passed to
> devm_ioremap_resource().
>
> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Acked-by:Tiffany Lin <tiffany.lin@mediatek.com>
> ---
> drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c | 5 -----
> 1 file changed, 5 deletions(-)
>
> diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c
> index aa81f3c..83f859e 100644
> --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c
> +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c
> @@ -269,11 +269,6 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
>
> for (i = VENC_SYS, j = 0; i < NUM_MAX_VCODEC_REG_BASE; i++, j++) {
> res = platform_get_resource(pdev, IORESOURCE_MEM, j);
> - if (res == NULL) {
> - dev_err(&pdev->dev, "get memory resource failed.");
> - ret = -ENXIO;
> - goto err_res;
> - }
> dev->reg_base[i] = devm_ioremap_resource(&pdev->dev, res);
> if (IS_ERR((__force void *)dev->reg_base[i])) {
> ret = PTR_ERR((__force void *)dev->reg_base[i]);
>
>
>
^ permalink raw reply
* Re: [PATCH v2 07/10] soc: mediatek: refine scysys for mediatek platforms
From: Matthias Brugger @ 2017-02-11 23:15 UTC (permalink / raw)
To: Mars Cheng
Cc: CC Hwang, Loda Chou, Miles Chen, Jades Shih, Yingjoe Chen,
My Chuang, linux-kernel, linux-mediatek, devicetree, wsd_upstream,
Marc Zyngier, Thomas Gleixner, Will Deacon, Stephen Boyd,
linux-clk, Chieh-Jay Liu, Kevin-CW Chen
In-Reply-To: <1486383336-16892-8-git-send-email-mars.cheng@mediatek.com>
On 02/06/2017 01:15 PM, Mars Cheng wrote:
> This adds 2 refinements: avoid fixed spm power statue and add vdec item
>
Please be more explicit in the commit message.
> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
> Signed-off-by: Kevin-CW Chen <kevin-cw.chen@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-scpsys.c | 35 +++++++++++++++++++++++++++++------
> 1 file changed, 29 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> index beb7916..a8ba800 100644
> --- a/drivers/soc/mediatek/mtk-scpsys.c
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -71,6 +71,7 @@ enum clk_id {
> CLK_VENC,
> CLK_VENC_LT,
> CLK_ETHIF,
> + CLK_VDEC,
> CLK_MAX,
> };
>
> @@ -81,6 +82,7 @@ enum clk_id {
> "venc",
> "venc_lt",
> "ethif",
> + "vdec",
> NULL,
> };
Put CLK_VDEC addition in the patch where you add support for mt6797.
Thanks,
Matthias
>
> @@ -107,21 +109,28 @@ struct scp_domain {
> struct regulator *supply;
> };
>
> +struct scp_ctrl_reg {
> + int pwr_sta_offs;
> + int pwr_sta2nd_offs;
> +};
> +
> struct scp {
> struct scp_domain *domains;
> struct genpd_onecell_data pd_data;
> struct device *dev;
> void __iomem *base;
> struct regmap *infracfg;
> + struct scp_ctrl_reg ctrl_reg;
> };
>
> static int scpsys_domain_is_on(struct scp_domain *scpd)
> {
> struct scp *scp = scpd->scp;
>
> - u32 status = readl(scp->base + SPM_PWR_STATUS) & scpd->data->sta_mask;
> - u32 status2 = readl(scp->base + SPM_PWR_STATUS_2ND) &
> - scpd->data->sta_mask;
> + u32 status = readl(scp->base + scp->ctrl_reg.pwr_sta_offs) &
> + scpd->data->sta_mask;
> + u32 status2 = readl(scp->base + scp->ctrl_reg.pwr_sta2nd_offs) &
> + scpd->data->sta_mask;
>
> /*
> * A domain is on when both status bits are set. If only one is set
> @@ -346,7 +355,8 @@ static void init_clks(struct platform_device *pdev, struct clk **clk)
> }
>
> static struct scp *init_scp(struct platform_device *pdev,
> - const struct scp_domain_data *scp_domain_data, int num)
> + const struct scp_domain_data *scp_domain_data, int num,
> + struct scp_ctrl_reg *scp_ctrl_reg)
> {
> struct genpd_onecell_data *pd_data;
> struct resource *res;
> @@ -358,6 +368,9 @@ static struct scp *init_scp(struct platform_device *pdev,
> if (!scp)
> return ERR_PTR(-ENOMEM);
>
> + scp->ctrl_reg.pwr_sta_offs = scp_ctrl_reg->pwr_sta_offs;
> + scp->ctrl_reg.pwr_sta2nd_offs = scp_ctrl_reg->pwr_sta2nd_offs;
> +
> scp->dev = &pdev->dev;
>
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> @@ -556,8 +569,13 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> static int __init scpsys_probe_mt2701(struct platform_device *pdev)
> {
> struct scp *scp;
> + struct scp_ctrl_reg scp_reg;
>
> - scp = init_scp(pdev, scp_domain_data_mt2701, NUM_DOMAINS_MT2701);
> + scp_reg.pwr_sta_offs = SPM_PWR_STATUS;
> + scp_reg.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND;
> +
> + scp = init_scp(pdev, scp_domain_data_mt2701, NUM_DOMAINS_MT2701,
> + &scp_reg);
> if (IS_ERR(scp))
> return PTR_ERR(scp);
>
> @@ -667,8 +685,13 @@ static int __init scpsys_probe_mt8173(struct platform_device *pdev)
> struct scp *scp;
> struct genpd_onecell_data *pd_data;
> int ret;
> + struct scp_ctrl_reg scp_reg;
> +
> + scp_reg.pwr_sta_offs = SPM_PWR_STATUS;
> + scp_reg.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND;
>
> - scp = init_scp(pdev, scp_domain_data_mt8173, NUM_DOMAINS_MT8173);
> + scp = init_scp(pdev, scp_domain_data_mt8173, NUM_DOMAINS_MT8173,
> + &scp_reg);
> if (IS_ERR(scp))
> return PTR_ERR(scp);
>
>
^ permalink raw reply
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