* [PATCH net-next v2] dt-bindings: net: rename the bindings document for MediaTek STAR EMAC
From: Bartosz Golaszewski @ 2020-05-28 13:59 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski, Rob Herring, Matthias Brugger
Cc: devicetree, Stephane Le Provost, Bartosz Golaszewski, netdev,
linux-kernel, Fabien Parent, linux-mediatek, Andrew Perepech,
Pedro Tsai, linux-arm-kernel
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
The driver itself was renamed before getting merged into mainline, but
the binding document kept the old name. This makes both names consistent.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
v1 -> v2:
- update the id field as well
.../net/{mediatek,eth-mac.yaml => mediatek,star-emac.yaml} | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
rename Documentation/devicetree/bindings/net/{mediatek,eth-mac.yaml => mediatek,star-emac.yaml} (96%)
diff --git a/Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml b/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml
similarity index 96%
rename from Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml
rename to Documentation/devicetree/bindings/net/mediatek,star-emac.yaml
index f85d91a9d6e5..aea88e621792 100644
--- a/Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml
+++ b/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: http://devicetree.org/schemas/net/mediatek,eth-mac.yaml#
+$id: http://devicetree.org/schemas/net/mediatek,star-emac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek STAR Ethernet MAC Controller
--
2.26.1
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* Re: [PATCH 1/2] regmap: provide helpers for simple bit operations
From: Bartosz Golaszewski @ 2020-05-28 13:57 UTC (permalink / raw)
To: Mark Brown
Cc: Stephane Le Provost, Bartosz Golaszewski, netdev, Sean Wang,
Linux Kernel Mailing List, Mark Lee, Fabien Parent, Pedro Tsai,
moderated list:ARM/Mediatek SoC..., Andrew Perepech, John Crispin,
Matthias Brugger, Jakub Kicinski, David S . Miller, Linux ARM
In-Reply-To: <20200528134802.GE3606@sirena.org.uk>
czw., 28 maj 2020 o 15:48 Mark Brown <broonie@kernel.org> napisał(a):
>
> On Thu, May 28, 2020 at 03:32:40PM +0200, Bartosz Golaszewski wrote:
> > czw., 28 maj 2020 o 15:29 Mark Brown <broonie@kernel.org> napisał(a):
>
> > > Why macros and not static inlines?
>
> > The existing regmap_update_bits_*() helpers are macros too, so I tried
> > to stay consistent. Any reason why they are macros and not static
> > inlines? If there's none, then why not convert them too? Otherwise
> > we'd have a static inline expanding a macro which in turn is calling a
> > function (regmap_update_bits_base()).
>
> Not really, I think it was just that they're argument tables. It'd be
> good to convert them.
Ok. So I'm seeing there are a lot of macros in regmap.h that could
become static inlines but given the amount of regmap users: how about
we do it separately and in the meantime I'll just modify this series
to use static inlines?
Bartosz
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* Re: [PATCH net-next] dt-bindings: net: rename the bindings document for MediaTek STAR MAC
From: Bartosz Golaszewski @ 2020-05-28 13:50 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: linux-devicetree, Stephane Le Provost, netdev, LKML,
Fabien Parent, Rob Herring, linux-mediatek, Andrew Perepech,
Pedro Tsai, Matthias Brugger, Jakub Kicinski, David S . Miller,
arm-soc
In-Reply-To: <20200528132743.9221-1-brgl@bgdev.pl>
czw., 28 maj 2020 o 15:27 Bartosz Golaszewski <brgl@bgdev.pl> napisał(a):
>
> From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>
> The driver itself was renamed before getting merged into mainline, but
> the binding document kept the old name. This makes both names consistent.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> ---
> .../net/{mediatek,eth-mac.yaml => mediatek,star-emac.yaml} | 0
> 1 file changed, 0 insertions(+), 0 deletions(-)
> rename Documentation/devicetree/bindings/net/{mediatek,eth-mac.yaml => mediatek,star-emac.yaml} (100%)
>
> diff --git a/Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml b/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml
> similarity index 100%
> rename from Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml
> rename to Documentation/devicetree/bindings/net/mediatek,star-emac.yaml
> --
> 2.26.1
>
-ETOOEARLY David please don't apply this - the id field needs to be
updated too. I'll send a v2.
Bartosz
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* Re: [PATCH 1/2] regmap: provide helpers for simple bit operations
From: Mark Brown @ 2020-05-28 13:48 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Stephane Le Provost, Bartosz Golaszewski, netdev, Sean Wang,
Linux Kernel Mailing List, Mark Lee, Fabien Parent, Pedro Tsai,
moderated list:ARM/Mediatek SoC..., Andrew Perepech, John Crispin,
Matthias Brugger, Jakub Kicinski, David S . Miller, Linux ARM
In-Reply-To: <CAMRc=MejeXv6vd5iRW_EB3XqBtdCWDcV=4BOCDDFd4D0-y9LUA@mail.gmail.com>
[-- Attachment #1.1: Type: text/plain, Size: 613 bytes --]
On Thu, May 28, 2020 at 03:32:40PM +0200, Bartosz Golaszewski wrote:
> czw., 28 maj 2020 o 15:29 Mark Brown <broonie@kernel.org> napisał(a):
> > Why macros and not static inlines?
> The existing regmap_update_bits_*() helpers are macros too, so I tried
> to stay consistent. Any reason why they are macros and not static
> inlines? If there's none, then why not convert them too? Otherwise
> we'd have a static inline expanding a macro which in turn is calling a
> function (regmap_update_bits_base()).
Not really, I think it was just that they're argument tables. It'd be
good to convert them.
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* Re: [PATCH v4 3/4] dmaengine: mediatek-cqdma: fix compatible
From: Matthias Brugger @ 2020-05-28 13:39 UTC (permalink / raw)
To: EastL, Sean Wang
Cc: mark.rutland, devicetree, wsd_upstream, linux-kernel, vkoul,
robh+dt, linux-mediatek, dmaengine, linux-arm-kernel
In-Reply-To: <1590659832-31476-4-git-send-email-EastL.Lee@mediatek.com>
On 28/05/2020 11:57, EastL wrote:
> This patch fixes mediatek-cqdma compatible to common.
>
> Signed-off-by: EastL <EastL.Lee@mediatek.com>
> ---
> drivers/dma/mediatek/mtk-cqdma.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
> index 905bbcb..bca7118 100644
> --- a/drivers/dma/mediatek/mtk-cqdma.c
> +++ b/drivers/dma/mediatek/mtk-cqdma.c
> @@ -544,7 +544,7 @@ static void mtk_cqdma_hw_deinit(struct mtk_cqdma_device *cqdma)
> }
>
> static const struct of_device_id mtk_cqdma_match[] = {
> - { .compatible = "mediatek,mt6765-cqdma" },
> + { .compatible = "mediatek,cqdma" },
We can't just delete and old compatible. If other cqdma IP blocks are the same
as mt6795, we should instead add entries in the binding description with
fallback compatible. For example for mt6779 the DTS would look like this:
compatible = "mediatek,mt6779-cqdma", "mediatek,mt6765-cqdma";
This way we the kernel will take care to bind the device against the driver with
mt7665-cqdma, but leaves us the posibillity to add any changes to the driver in
the future if we find some bugs/features for mt6779 that are not present in mt6765.
Regards,
Matthias
> { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, mtk_cqdma_match);
>
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* Re: [PATCH 1/2] regmap: provide helpers for simple bit operations
From: Bartosz Golaszewski @ 2020-05-28 13:32 UTC (permalink / raw)
To: Mark Brown
Cc: Stephane Le Provost, Bartosz Golaszewski, netdev, Sean Wang,
Linux Kernel Mailing List, Mark Lee, Fabien Parent, Pedro Tsai,
moderated list:ARM/Mediatek SoC..., Andrew Perepech, John Crispin,
Matthias Brugger, Jakub Kicinski, David S . Miller, Linux ARM
In-Reply-To: <20200528132938.GC3606@sirena.org.uk>
czw., 28 maj 2020 o 15:29 Mark Brown <broonie@kernel.org> napisał(a):
>
> On Thu, May 28, 2020 at 02:34:58PM +0200, Bartosz Golaszewski wrote:
>
> > This adds three new macros for simple bit operations: set_bits,
> > clear_bits and test_bits.
>
> Why macros and not static inlines?
The existing regmap_update_bits_*() helpers are macros too, so I tried
to stay consistent. Any reason why they are macros and not static
inlines? If there's none, then why not convert them too? Otherwise
we'd have a static inline expanding a macro which in turn is calling a
function (regmap_update_bits_base()).
Bartosz
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^ permalink raw reply
* Re: [PATCH 1/2] regmap: provide helpers for simple bit operations
From: Mark Brown @ 2020-05-28 13:29 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Stephane Le Provost, Bartosz Golaszewski, netdev, Sean Wang,
linux-kernel, Mark Lee, Fabien Parent, Pedro Tsai, linux-mediatek,
Andrew Perepech, John Crispin, Matthias Brugger, Jakub Kicinski,
David S . Miller, linux-arm-kernel
In-Reply-To: <20200528123459.21168-2-brgl@bgdev.pl>
[-- Attachment #1.1: Type: text/plain, Size: 200 bytes --]
On Thu, May 28, 2020 at 02:34:58PM +0200, Bartosz Golaszewski wrote:
> This adds three new macros for simple bit operations: set_bits,
> clear_bits and test_bits.
Why macros and not static inlines?
[-- Attachment #1.2: signature.asc --]
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[-- Attachment #2: Type: text/plain, Size: 170 bytes --]
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^ permalink raw reply
* [PATCH net-next] dt-bindings: net: rename the bindings document for MediaTek STAR MAC
From: Bartosz Golaszewski @ 2020-05-28 13:27 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski, Rob Herring, Matthias Brugger
Cc: devicetree, Stephane Le Provost, Bartosz Golaszewski, netdev,
linux-kernel, Fabien Parent, linux-mediatek, Andrew Perepech,
Pedro Tsai, linux-arm-kernel
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
The driver itself was renamed before getting merged into mainline, but
the binding document kept the old name. This makes both names consistent.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
.../net/{mediatek,eth-mac.yaml => mediatek,star-emac.yaml} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/net/{mediatek,eth-mac.yaml => mediatek,star-emac.yaml} (100%)
diff --git a/Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml b/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml
similarity index 100%
rename from Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml
rename to Documentation/devicetree/bindings/net/mediatek,star-emac.yaml
--
2.26.1
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* [PATCH 2/2] net: ethernet: mtk-star-emac: use regmap bitops
From: Bartosz Golaszewski @ 2020-05-28 12:34 UTC (permalink / raw)
To: John Crispin, Sean Wang, Mark Lee, David S . Miller,
Jakub Kicinski, Matthias Brugger, Mark Brown
Cc: Stephane Le Provost, Bartosz Golaszewski, netdev, linux-kernel,
Fabien Parent, linux-mediatek, Andrew Perepech, Pedro Tsai,
linux-arm-kernel
In-Reply-To: <20200528123459.21168-1-brgl@bgdev.pl>
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Shrink the code visually by replacing regmap_update_bits() with
appropriate regmap bit operations where applicable.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
drivers/net/ethernet/mediatek/mtk_star_emac.c | 80 ++++++++-----------
1 file changed, 35 insertions(+), 45 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c
index 8596ca0e60eb..326ac792a4a0 100644
--- a/drivers/net/ethernet/mediatek/mtk_star_emac.c
+++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c
@@ -413,8 +413,8 @@ static void mtk_star_dma_unmap_tx(struct mtk_star_priv *priv,
static void mtk_star_nic_disable_pd(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_MAC_CFG,
- MTK_STAR_BIT_MAC_CFG_NIC_PD, 0);
+ regmap_clear_bits(priv->regs, MTK_STAR_REG_MAC_CFG,
+ MTK_STAR_BIT_MAC_CFG_NIC_PD);
}
/* Unmask the three interrupts we care about, mask all others. */
@@ -434,41 +434,38 @@ static void mtk_star_intr_disable(struct mtk_star_priv *priv)
static void mtk_star_intr_enable_tx(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_INT_MASK,
- MTK_STAR_BIT_INT_STS_TNTC, 0);
+ regmap_clear_bits(priv->regs, MTK_STAR_REG_INT_MASK,
+ MTK_STAR_BIT_INT_STS_TNTC);
}
static void mtk_star_intr_enable_rx(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_INT_MASK,
- MTK_STAR_BIT_INT_STS_FNRC, 0);
+ regmap_clear_bits(priv->regs, MTK_STAR_REG_INT_MASK,
+ MTK_STAR_BIT_INT_STS_FNRC);
}
static void mtk_star_intr_enable_stats(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_INT_MASK,
- MTK_STAR_REG_INT_STS_MIB_CNT_TH, 0);
+ regmap_clear_bits(priv->regs, MTK_STAR_REG_INT_MASK,
+ MTK_STAR_REG_INT_STS_MIB_CNT_TH);
}
static void mtk_star_intr_disable_tx(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_INT_MASK,
- MTK_STAR_BIT_INT_STS_TNTC,
- MTK_STAR_BIT_INT_STS_TNTC);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_INT_MASK,
+ MTK_STAR_BIT_INT_STS_TNTC);
}
static void mtk_star_intr_disable_rx(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_INT_MASK,
- MTK_STAR_BIT_INT_STS_FNRC,
- MTK_STAR_BIT_INT_STS_FNRC);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_INT_MASK,
+ MTK_STAR_BIT_INT_STS_FNRC);
}
static void mtk_star_intr_disable_stats(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_INT_MASK,
- MTK_STAR_REG_INT_STS_MIB_CNT_TH,
- MTK_STAR_REG_INT_STS_MIB_CNT_TH);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_INT_MASK,
+ MTK_STAR_REG_INT_STS_MIB_CNT_TH);
}
static unsigned int mtk_star_intr_read(struct mtk_star_priv *priv)
@@ -524,12 +521,10 @@ static void mtk_star_dma_init(struct mtk_star_priv *priv)
static void mtk_star_dma_start(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_TX_DMA_CTRL,
- MTK_STAR_BIT_TX_DMA_CTRL_START,
- MTK_STAR_BIT_TX_DMA_CTRL_START);
- regmap_update_bits(priv->regs, MTK_STAR_REG_RX_DMA_CTRL,
- MTK_STAR_BIT_RX_DMA_CTRL_START,
- MTK_STAR_BIT_RX_DMA_CTRL_START);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_TX_DMA_CTRL,
+ MTK_STAR_BIT_TX_DMA_CTRL_START);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_RX_DMA_CTRL,
+ MTK_STAR_BIT_RX_DMA_CTRL_START);
}
static void mtk_star_dma_stop(struct mtk_star_priv *priv)
@@ -553,16 +548,14 @@ static void mtk_star_dma_disable(struct mtk_star_priv *priv)
static void mtk_star_dma_resume_rx(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_RX_DMA_CTRL,
- MTK_STAR_BIT_RX_DMA_CTRL_RESUME,
- MTK_STAR_BIT_RX_DMA_CTRL_RESUME);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_RX_DMA_CTRL,
+ MTK_STAR_BIT_RX_DMA_CTRL_RESUME);
}
static void mtk_star_dma_resume_tx(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_TX_DMA_CTRL,
- MTK_STAR_BIT_TX_DMA_CTRL_RESUME,
- MTK_STAR_BIT_TX_DMA_CTRL_RESUME);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_TX_DMA_CTRL,
+ MTK_STAR_BIT_TX_DMA_CTRL_RESUME);
}
static void mtk_star_set_mac_addr(struct net_device *ndev)
@@ -845,8 +838,8 @@ static int mtk_star_hash_wait_ok(struct mtk_star_priv *priv)
return ret;
/* Check the BIST_OK bit. */
- regmap_read(priv->regs, MTK_STAR_REG_HASH_CTRL, &val);
- if (!(val & MTK_STAR_BIT_HASH_CTRL_BIST_OK))
+ if (!regmap_test_bits(priv->regs, MTK_STAR_REG_HASH_CTRL,
+ MTK_STAR_BIT_HASH_CTRL_BIST_OK))
return -EIO;
return 0;
@@ -880,12 +873,10 @@ static int mtk_star_reset_hash_table(struct mtk_star_priv *priv)
if (ret)
return ret;
- regmap_update_bits(priv->regs, MTK_STAR_REG_HASH_CTRL,
- MTK_STAR_BIT_HASH_CTRL_BIST_EN,
- MTK_STAR_BIT_HASH_CTRL_BIST_EN);
- regmap_update_bits(priv->regs, MTK_STAR_REG_TEST1,
- MTK_STAR_BIT_TEST1_RST_HASH_MBIST,
- MTK_STAR_BIT_TEST1_RST_HASH_MBIST);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_HASH_CTRL,
+ MTK_STAR_BIT_HASH_CTRL_BIST_EN);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_TEST1,
+ MTK_STAR_BIT_TEST1_RST_HASH_MBIST);
return mtk_star_hash_wait_ok(priv);
}
@@ -1016,13 +1007,13 @@ static int mtk_star_enable(struct net_device *ndev)
return ret;
/* Setup the hashing algorithm */
- regmap_update_bits(priv->regs, MTK_STAR_REG_ARL_CFG,
- MTK_STAR_BIT_ARL_CFG_HASH_ALG |
- MTK_STAR_BIT_ARL_CFG_MISC_MODE, 0);
+ regmap_clear_bits(priv->regs, MTK_STAR_REG_ARL_CFG,
+ MTK_STAR_BIT_ARL_CFG_HASH_ALG |
+ MTK_STAR_BIT_ARL_CFG_MISC_MODE);
/* Don't strip VLAN tags */
- regmap_update_bits(priv->regs, MTK_STAR_REG_MAC_CFG,
- MTK_STAR_BIT_MAC_CFG_VLAN_STRIP, 0);
+ regmap_clear_bits(priv->regs, MTK_STAR_REG_MAC_CFG,
+ MTK_STAR_BIT_MAC_CFG_VLAN_STRIP);
/* Setup DMA */
mtk_star_dma_init(priv);
@@ -1204,9 +1195,8 @@ static void mtk_star_set_rx_mode(struct net_device *ndev)
int ret;
if (ndev->flags & IFF_PROMISC) {
- regmap_update_bits(priv->regs, MTK_STAR_REG_ARL_CFG,
- MTK_STAR_BIT_ARL_CFG_MISC_MODE,
- MTK_STAR_BIT_ARL_CFG_MISC_MODE);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_ARL_CFG,
+ MTK_STAR_BIT_ARL_CFG_MISC_MODE);
} else if (netdev_mc_count(ndev) > MTK_STAR_HASHTABLE_MC_LIMIT ||
ndev->flags & IFF_ALLMULTI) {
for (i = 0; i < MTK_STAR_HASHTABLE_SIZE_MAX; i++) {
--
2.25.0
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* [PATCH 1/2] regmap: provide helpers for simple bit operations
From: Bartosz Golaszewski @ 2020-05-28 12:34 UTC (permalink / raw)
To: John Crispin, Sean Wang, Mark Lee, David S . Miller,
Jakub Kicinski, Matthias Brugger, Mark Brown
Cc: Stephane Le Provost, Bartosz Golaszewski, netdev, linux-kernel,
Fabien Parent, linux-mediatek, Andrew Perepech, Pedro Tsai,
linux-arm-kernel
In-Reply-To: <20200528123459.21168-1-brgl@bgdev.pl>
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
In many instances regmap_update_bits() is used for simple bit setting
and clearing. In these cases the last argument is redundant and we can
hide it with a macro.
This adds three new macros for simple bit operations: set_bits,
clear_bits and test_bits.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
include/linux/regmap.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/include/linux/regmap.h b/include/linux/regmap.h
index 40b07168fd8e..6ef829169f36 100644
--- a/include/linux/regmap.h
+++ b/include/linux/regmap.h
@@ -71,6 +71,24 @@ struct reg_sequence {
unsigned int delay_us;
};
+#define regmap_set_bits(map, reg, bits) \
+ regmap_update_bits_base(map, reg, bits, bits, NULL, false, false)
+#define regmap_clear_bits(map, reg, bits) \
+ regmap_update_bits_base(map, reg, bits, 0, NULL, false, false)
+/*
+ * Returns -1 if the underlying regmap_read() fails, 0 if at least one of the
+ * tested bits is not set and 1 if all tested bits are set.
+ */
+#define regmap_test_bits(map, reg, bits) \
+({ \
+ unsigned int __val, __ret, __bits; \
+ __bits = (bits); \
+ __ret = regmap_read(map, reg, &__val); \
+ if (__ret == 0) \
+ __ret = (__val & __bits) == __bits ? 1 : 0; \
+ __ret; \
+})
+
#define regmap_update_bits(map, reg, mask, val) \
regmap_update_bits_base(map, reg, mask, val, NULL, false, false)
#define regmap_update_bits_async(map, reg, mask, val)\
--
2.25.0
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^ permalink raw reply related
* [PATCH 0/2] regmap: provide simple bitops and use them in a driver
From: Bartosz Golaszewski @ 2020-05-28 12:34 UTC (permalink / raw)
To: John Crispin, Sean Wang, Mark Lee, David S . Miller,
Jakub Kicinski, Matthias Brugger, Mark Brown
Cc: Stephane Le Provost, Bartosz Golaszewski, netdev, linux-kernel,
Fabien Parent, linux-mediatek, Andrew Perepech, Pedro Tsai,
linux-arm-kernel
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Hi Mark,
I noticed that oftentimes I use regmap_update_bits() for simple bit
setting or clearing. In this case the fourth argument is superfluous as
it's always 0 or equal to the mask argument.
This series proposes to add simple bit operations for setting, clearing
and testing specific bits with regmap.
The second patch uses all three in a driver that got recently picked into
the net-next tree.
The patches obviously target different trees so - if you're ok with
the change itself - I propose you pick the first one into your regmap
tree for v5.8 and then I'll resend the second patch to add the first
user for these macros for v5.9.
Bartosz Golaszewski (2):
regmap: provide helpers for simple bit operations
net: ethernet: mtk-star-emac: use regmap bitops
drivers/net/ethernet/mediatek/mtk_star_emac.c | 80 ++++++++-----------
include/linux/regmap.h | 18 +++++
2 files changed, 53 insertions(+), 45 deletions(-)
--
2.25.0
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^ permalink raw reply
* Re: [PATCH v5 4/6] pinctrl: mediatek: add pinctrl support for MT6779 SoC
From: Hanks Chen @ 2020-05-28 12:34 UTC (permalink / raw)
To: Sean Wang
Cc: Mark Rutland, devicetree, wsd_upstream, Andy Teng, Linus Walleij,
lkml, Rob Herring, moderated list:ARM/Mediatek SoC support,
Matthias Brugger, Mars Cheng
In-Reply-To: <CAGp9Lzrci=qhU6QXPfGg=-dGtKNq1Xn-rhYWvPp-8Wj6v6oJwA@mail.gmail.com>
On Thu, 2020-04-02 at 14:46 -0700, Sean Wang wrote:
> Hi Hanks,
>
> On Wed, Mar 25, 2020 at 2:31 AM Hanks Chen <hanks.chen@mediatek.com> wrote:
> >
> > This adds MT6779 pinctrl driver based on MediaTek pinctrl-paris core.
> >
>
> We can add some useful help text about MT6779 pinctrl, especially
> about specific parts like virtual gpio and its attributes
> Then Acked-by: Sean Wang <sean.wang@kernel.org>
>
Got it, I'll add it in next version.
Thanks for the advices.
> > Signed-off-by: Hanks Chen <hanks.chen@mediatek.com>
> > Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
> > Signed-off-by: Andy Teng <andy.teng@mediatek.com>
> > ---
> > drivers/pinctrl/mediatek/Kconfig | 7 +
> > drivers/pinctrl/mediatek/Makefile | 1 +
> > drivers/pinctrl/mediatek/pinctrl-mt6779.c | 775 +++++++++
> > drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h | 2085 +++++++++++++++++++++++++
> > 4 files changed, 2868 insertions(+)
> > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6779.c
> > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h
> >
> > diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
> > index 701f9af..f628d01 100644
> > --- a/drivers/pinctrl/mediatek/Kconfig
> > +++ b/drivers/pinctrl/mediatek/Kconfig
> > @@ -86,6 +86,13 @@ config PINCTRL_MT6765
> > default ARM64 && ARCH_MEDIATEK
> > select PINCTRL_MTK_PARIS
> >
> > +config PINCTRL_MT6779
> > + bool "Mediatek MT6779 pin control"
> > + depends on OF
> > + depends on ARM64 || COMPILE_TEST
> > + default ARM64 && ARCH_MEDIATEK
> > + select PINCTRL_MTK_PARIS
> > +
> > config PINCTRL_MT6797
> > bool "Mediatek MT6797 pin control"
> > depends on OF
> > diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
> > index a74325a..59c1c60 100644
> > --- a/drivers/pinctrl/mediatek/Makefile
> > +++ b/drivers/pinctrl/mediatek/Makefile
> > @@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o
> > obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
> > obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
> > obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o
> > +obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o
> > obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o
> > obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
> > obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
> > diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6779.c b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
> > new file mode 100644
> > index 0000000..145bf22
> > --- /dev/null
> > +++ b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
> > @@ -0,0 +1,775 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2019 MediaTek Inc.
> > + * Author: Andy Teng <andy.teng@mediatek.com>
> > + *
> > + */
> > +
> > +#include "pinctrl-mtk-mt6779.h"
> > +#include "pinctrl-paris.h"
> > +
> > +/* MT6779 have multiple bases to program pin configuration listed as the below:
> > + * gpio:0x10005000, iocfg_rm:0x11C20000, iocfg_br:0x11D10000,
> > + * iocfg_lm:0x11E20000, iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000,
> > + * iocfg_lt:0x11F20000, iocfg_tl:0x11F30000
> > + * _i_based could be used to indicate what base the pin should be mapped into.
> > + */
> > +
> > +#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
> > + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
> > + 32, 0)
> > +
>
> <snip>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
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^ permalink raw reply
* Re: [RESEND PATCH v11 2/3] drivers: input: keyboard: Add mtk keypad driver
From: Marco Felsch @ 2020-05-28 12:33 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Dmitry Torokhov, linux-mediatek, linux-input, Yingjoe Chen,
Fengping Yu, linux-arm-kernel
In-Reply-To: <20200528122248.GL1634618@smile.fi.intel.com>
On 20-05-28 15:22, Andy Shevchenko wrote:
> On Thu, May 28, 2020 at 01:45:58PM +0200, Marco Felsch wrote:
> > On 20-05-28 13:27, Andy Shevchenko wrote:
> > > On Thu, May 28, 2020 at 05:01:47PM +0800, Fengping Yu wrote:
>
> ...
>
> > > > + select CONFIG_REGMAP_MMIO
> > >
> > > This is wrong.
> >
> > Why is this wrong? The driver uses the rmap-mmio functions.
>
> In Kconfig CONFIG_ prefix is implied.
>
> There is no CONFIG_CONFIG_REGMAP_MMIO.
>
> > Thanks for the explanation =)
>
> Sorry, I think it's obvious...
Damn, you right it is. Bloody automatism mismatch in my brain.
Regards,
Marco
>
> > > > + select INPUT_MATRIXKMAP
>
> --
> With Best Regards,
> Andy Shevchenko
>
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^ permalink raw reply
* Re: [RESEND PATCH v11 2/3] drivers: input: keyboard: Add mtk keypad driver
From: Andy Shevchenko @ 2020-05-28 12:22 UTC (permalink / raw)
To: Marco Felsch
Cc: Dmitry Torokhov, linux-mediatek, linux-input, Yingjoe Chen,
Fengping Yu, linux-arm-kernel
In-Reply-To: <20200528114558.5decxsun2o65k2fr@pengutronix.de>
On Thu, May 28, 2020 at 01:45:58PM +0200, Marco Felsch wrote:
> On 20-05-28 13:27, Andy Shevchenko wrote:
> > On Thu, May 28, 2020 at 05:01:47PM +0800, Fengping Yu wrote:
...
> > > + select CONFIG_REGMAP_MMIO
> >
> > This is wrong.
>
> Why is this wrong? The driver uses the rmap-mmio functions.
In Kconfig CONFIG_ prefix is implied.
There is no CONFIG_CONFIG_REGMAP_MMIO.
> Thanks for the explanation =)
Sorry, I think it's obvious...
> > > + select INPUT_MATRIXKMAP
--
With Best Regards,
Andy Shevchenko
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^ permalink raw reply
* Re: [PATCH v5 2/6] pinctrl: mediatek: update pinmux definitions for mt6779
From: Hanks Chen @ 2020-05-28 11:59 UTC (permalink / raw)
To: Sean Wang
Cc: Mark Rutland, devicetree, wsd_upstream, Andy Teng, Linus Walleij,
lkml, Rob Herring, moderated list:ARM/Mediatek SoC support,
Matthias Brugger, Mars Cheng
In-Reply-To: <CAGp9LzoULALLvO+x2TnO=K=pSD05bJFowB-usAcrpz0ddEN+Ug@mail.gmail.com>
On Thu, 2020-04-02 at 14:54 -0700, Sean Wang wrote:
> Hi, Hanks
>
> Just a few nitpicks and then Acked-by: Sean Wang <sean.wang@kernel.org>
>
> On Wed, Mar 25, 2020 at 2:31 AM Hanks Chen <hanks.chen@mediatek.com> wrote:
> >
> > Add devicetree bindings for Mediatek mt6779 SoC Pin Controller.
> >
> > Signed-off-by: Hanks Chen <hanks.chen@mediatek.com>
> > Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
> > Signed-off-by: Andy Teng <andy.teng@mediatek.com>
> > ---
> > include/dt-bindings/pinctrl/mt6779-pinfunc.h | 1242 ++++++++++++++++++++++++++
> > 1 file changed, 1242 insertions(+)
> > create mode 100644 include/dt-bindings/pinctrl/mt6779-pinfunc.h
> >
> > diff --git a/include/dt-bindings/pinctrl/mt6779-pinfunc.h b/include/dt-bindings/pinctrl/mt6779-pinfunc.h
> > new file mode 100644
> > index 0000000..4698d2f
> > --- /dev/null
> > +++ b/include/dt-bindings/pinctrl/mt6779-pinfunc.h
> > @@ -0,0 +1,1242 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (C) 2019 MediaTek Inc.
> > + * Author: Andy Teng <andy.teng@mediatek.com>
> > + *
> > + */
> > +
> > +#ifndef __MT6779_PINFUNC_H
> > +#define __MT6779_PINFUNC_H
> > +
> > +#include "mt65xx.h"
>
> Use the standard include path instead: #include <dt-bindings/pinctrl/mt65xx.h>
>
Got it, I'll revise it in next version
Thanks for your comment.
> > +
> <snip>
> > +
> > +#define PINMUX_GPIO209__FUNC_GPIO209 (MTK_PIN_NO(209) | 0)
> > +
> > +#endif /* __MT6779-PINFUNC_H */
> __MT6779_PINFUNC_H
> > --
> > 1.7.9.5
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^ permalink raw reply
* Re: [PATCH v5 1/6] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
From: Hanks Chen @ 2020-05-28 11:51 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Rutland, devicetree, wsd_upstream, Andy Teng, Linus Walleij,
Sean Wang, linux-kernel@vger.kernel.org,
moderated list:ARM/Mediatek SoC support, Matthias Brugger
In-Reply-To: <CAL_Jsq+Znnk=L=ztTyVrs4i0tiN0TrWwcaujAm_Lp1wd9pWiZQ@mail.gmail.com>
On Thu, 2020-03-26 at 11:43 -0600, Rob Herring wrote:
> On Wed, Mar 25, 2020 at 3:31 AM Hanks Chen <hanks.chen@mediatek.com> wrote:
> >
> > From: Andy Teng <andy.teng@mediatek.com>
> >
> > Add devicetree bindings for MediaTek MT6779 pinctrl driver.
> >
> > Signed-off-by: Andy Teng <andy.teng@mediatek.com>
> > ---
> > .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 208 ++++++++++++++++++++
> > 1 file changed, 208 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
>
> The header belongs in this patch so that 'make dt_binding_check' works.
>
> >
> > diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
> > new file mode 100644
> > index 0000000..5f9bbf1
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
> > @@ -0,0 +1,208 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek MT6779 Pin Controller Device Tree Bindings
> > +
> > +maintainers:
> > + - Andy Teng <andy.teng@mediatek.com>
> > +
> > +description: |+
> > + The pin controller node should be the child of a syscon node with the
> > + required property:
> > + - compatible: "syscon"
> > +
> > +properties:
> > + compatible:
> > + const: mediatek,mt6779-pinctrl
> > +
> > + reg:
> > + minItems: 9
> > + maxItems: 9
> > + description: |
> > + physical address base for gpio-related control registers.
> > +
> > + reg-names:
> > + description: |
> > + GPIO base register names.
>
> Need to define what the names are and the order.
Got it, I'll add it in next version.
Thanks
>
> > +
> > + gpio-controller: true
> > +
> > + "#gpio-cells":
> > + const: 2
> > + description: |
> > + Number of cells in GPIO specifier. Since the generic GPIO
> > + binding is used, the amount of cells must be specified as 2. See the below
> > + mentioned gpio binding representation for description of particular cells.
> > +
> > + gpio-ranges:
> > + minItems: 1
> > + maxItems: 5
> > + description: |
> > + GPIO valid number range.
> > +
> > + interrupt-controller: true
> > +
> > + interrupts:
> > + minItems: 1
> > + maxItems: 4
>
> Need to define what the interrupts are.
>
Got it, I'll add it in the next version.
Thanks.
> > + description: |
> > + The interrupt outputs to sysirq.
> > +
> > + "#interrupt-cells":
> > + const: 2
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - reg-names
> > + - gpio-controller
> > + - "#gpio-cells"
> > + - gpio-ranges
> > + - interrupt-controller
> > + - interrupts
> > + - "#interrupt-cells"
> > +
> > +patternProperties:
> > + '^pins*$':
>
> '-pins$' would be preferred.
>
Got it, I'll fix it in next version.
Thanks.
> > + type: object
> > + description: |
> > + A pinctrl node should contain at least one subnodes representing the
> > + pinctrl groups available on the machine. Each subnode will list the
> > + pins it needs, and how they should be configured, with regard to muxer
> > + configuration, pullups, drive strength, input enable/disable and input schmitt.
> > +
> > + properties:
> > + pinmux:
>
> There's a common schema for all these properties. You need to
> reference it (with $ref) and only define which properties you are
> using and any additional constraints.
>
Got it, thx!
> > + description:
> > + integer array, represents gpio pin number and mux setting.
> > + Supported pin number and mux varies for different SoCs, and are defined
> > + as macros in boot/dts/<soc>-pinfunc.h directly.
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32-array
> > + bias-disable:
> > + type: boolean
> > +
> > + bias-pull-up:
> > + oneOf:
> > + - type: boolean
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > + bias-pull-down:
> > + oneOf:
> > + - type: boolean
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > + input-enable:
> > + type: boolean
> > +
> > + input-disable:
> > + type: boolean
> > +
> > + output-low:
> > + type: boolean
> > +
> > + output-high:
> > + type: boolean
> > +
> > + input-schmitt-enable:
> > + type: boolean
> > +
> > + input-schmitt-disable:
> > + type: boolean
> > +
> > + mediatek,pull-up-adv:
> > + description: |
> > + Pull up setings for 2 pull resistors, R0 and R1. User can
> > + configure those special pins. Valid arguments are described as below:
> > + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disable.
> > + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
> > + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
> > + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > + - enum: [0, 1, 2, 3]
> > +
> > + mediatek,pull-down-adv:
> > + description: |
> > + Pull down settings for 2 pull resistors, R0 and R1. User can
> > + configure those special pins. Valid arguments are described as below:
> > + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disable.
> > + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
> > + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
> > + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > + - enum: [0, 1, 2, 3]
> > +
> > + drive-strength:
> > + description: |
> > + Selects the drive strength for the specified pins in mA.
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > + - enum: [2, 4, 6, 8, 10, 12, 14, 16]
> > +
> > + required:
> > + - pinmux
>
> Add:
>
> additionalProperties: false
>
> additionalProperties: false
>
Got it, I'll add it, thx!
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/pinctrl/mt6779-pinfunc.h>
> > +
> > + pio: pinctrl@10005000 {
> > + compatible = "mediatek,mt6779-pinctrl";
> > + reg = <0 0x10005000 0 0x1000>,
> > + <0 0x11c20000 0 0x1000>,
> > + <0 0x11d10000 0 0x1000>,
> > + <0 0x11e20000 0 0x1000>,
> > + <0 0x11e70000 0 0x1000>,
> > + <0 0x11ea0000 0 0x1000>,
> > + <0 0x11f20000 0 0x1000>,
> > + <0 0x11f30000 0 0x1000>,
> > + <0 0x1000b000 0 0x1000>;
> > + reg-names = "gpio", "iocfg_rm",
> > + "iocfg_br", "iocfg_lm",
> > + "iocfg_lb", "iocfg_rt",
> > + "iocfg_lt", "iocfg_tl",
> > + "eint";
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + gpio-ranges = <&pio 0 0 210>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > + mmc0_pins_default: mmc0default {
> > + pins_cmd_dat {
>
> The 2 levels of nodes here doesn't match your schema.
>
> Also, don't use '_' in node names.
>
I'll fix it in next version, thx!
> > + pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>,
> > + <PINMUX_GPIO172__FUNC_MSDC0_DAT1>,
> > + <PINMUX_GPIO169__FUNC_MSDC0_DAT2>,
> > + <PINMUX_GPIO177__FUNC_MSDC0_DAT3>,
> > + <PINMUX_GPIO170__FUNC_MSDC0_DAT4>,
> > + <PINMUX_GPIO173__FUNC_MSDC0_DAT5>,
> > + <PINMUX_GPIO171__FUNC_MSDC0_DAT6>,
> > + <PINMUX_GPIO174__FUNC_MSDC0_DAT7>,
> > + <PINMUX_GPIO167__FUNC_MSDC0_CMD>;
> > + input-enable;
> > + mediatek,pull-up-adv = <1>;
> > + };
> > + pins_clk {
> > + pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>;
> > + mediatek,pull-down-adv = <2>;
> > + };
> > + pins_rst {
> > + pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>;
> > + mediatek,pull-up-adv = <0>;
> > + };
> > + };
> > +
> > + mmc0 {
> > + pinctrl-0 = <&mmc0_pins_default>;
> > + pinctrl-names = "default";
> > + };
> > + };
> > +
> > --
> > 1.7.9.5
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^ permalink raw reply
* Re: [RESEND PATCH v11 2/3] drivers: input: keyboard: Add mtk keypad driver
From: Marco Felsch @ 2020-05-28 11:45 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Dmitry Torokhov, linux-mediatek, linux-input, Yingjoe Chen,
Fengping Yu, linux-arm-kernel
In-Reply-To: <20200528102730.GK1634618@smile.fi.intel.com>
Hi Andy,
On 20-05-28 13:27, Andy Shevchenko wrote:
> On Thu, May 28, 2020 at 05:01:47PM +0800, Fengping Yu wrote:
> > From: "fengping.yu" <fengping.yu@mediatek.com>
> >
> > This adds matrix keypad support for Mediatek SoCs.
>
> ...
>
> > +config KEYBOARD_MTK_KPD
> > + tristate "MediaTek Keypad Support"
> > + depends on ARCH_MEDIATEK || COMPILE_TEST
>
> > + select CONFIG_REGMAP_MMIO
>
> This is wrong.
Why is this wrong? The driver uses the rmap-mmio functions.
Thanks for the explanation =)
Marco
>
> > + select INPUT_MATRIXKMAP
>
> ...
>
> > + ret = devm_add_action_or_reset(&pdev->dev, kpd_clk_disable,
> > + keypad->clk);
>
> I would leave on one line (only 81 characters).
>
> > + if (ret)
> > + return ret;
>
> --
> With Best Regards,
> Andy Shevchenko
>
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^ permalink raw reply
* Re: [RESEND PATCH v11 2/3] drivers: input: keyboard: Add mtk keypad driver
From: Andy Shevchenko @ 2020-05-28 10:27 UTC (permalink / raw)
To: Fengping Yu
Cc: Dmitry Torokhov, Marco Felsch, linux-mediatek, linux-input,
Yingjoe Chen, linux-arm-kernel
In-Reply-To: <20200528090144.54033-3-fengping.yu@mediatek.com>
On Thu, May 28, 2020 at 05:01:47PM +0800, Fengping Yu wrote:
> From: "fengping.yu" <fengping.yu@mediatek.com>
>
> This adds matrix keypad support for Mediatek SoCs.
...
> +config KEYBOARD_MTK_KPD
> + tristate "MediaTek Keypad Support"
> + depends on ARCH_MEDIATEK || COMPILE_TEST
> + select CONFIG_REGMAP_MMIO
This is wrong.
> + select INPUT_MATRIXKMAP
...
> + ret = devm_add_action_or_reset(&pdev->dev, kpd_clk_disable,
> + keypad->clk);
I would leave on one line (only 81 characters).
> + if (ret)
> + return ret;
--
With Best Regards,
Andy Shevchenko
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply
* Re: [RESEND PATCH v11] Add matrix keypad driver support for Mediatek SoCs
From: Andy Shevchenko @ 2020-05-28 10:24 UTC (permalink / raw)
To: Fengping Yu
Cc: Dmitry Torokhov, Marco Felsch, linux-mediatek, linux-input,
Yingjoe Chen, linux-arm-kernel
In-Reply-To: <20200528090144.54033-1-fengping.yu@mediatek.com>
On Thu, May 28, 2020 at 05:01:42PM +0800, Fengping Yu wrote:
>
> Change since v10:
> - add wakeup source setting in probe function
You forgot tags by Marco
>
> fengping.yu (3):
> dt-bindings: Add keypad devicetree documentation
> drivers: input: keyboard: Add mtk keypad driver
> configs: defconfig: Add CONFIG_KEYBOARD_MTK_KPD=m
>
> .../devicetree/bindings/input/mtk-kpd.yaml | 95 ++++++++
> arch/arm64/configs/defconfig | 1 +
> drivers/input/keyboard/Kconfig | 11 +
> drivers/input/keyboard/Makefile | 1 +
> drivers/input/keyboard/mtk-kpd.c | 206 ++++++++++++++++++
> 5 files changed, 314 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/input/mtk-kpd.yaml
> create mode 100644 drivers/input/keyboard/mtk-kpd.c
>
> --
> 2.18.0
>
--
With Best Regards,
Andy Shevchenko
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^ permalink raw reply
* [PATCH] Bluetooth: btmtkuart: add missed functions in the error paths of btmtuart_probe()
From: Chuhong Yuan @ 2020-05-28 10:20 UTC (permalink / raw)
Cc: Johan Hedberg, Marcel Holtmann, Sean Wang, Chuhong Yuan,
linux-kernel, linux-bluetooth, linux-mediatek, Matthias Brugger,
linux-arm-kernel
btmtuart_probe() misses several function calls in its error paths,
including hci_free_dev() and clk_disable_unprepare().
Refactor the code and call correct undo functions to fix the error
paths.
Signed-off-by: Chuhong Yuan <hslester96@gmail.com>
---
drivers/bluetooth/btmtkuart.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/bluetooth/btmtkuart.c b/drivers/bluetooth/btmtkuart.c
index e11169ad8247..8a81fbca5c9d 100644
--- a/drivers/bluetooth/btmtkuart.c
+++ b/drivers/bluetooth/btmtkuart.c
@@ -1015,7 +1015,7 @@ static int btmtkuart_probe(struct serdev_device *serdev)
if (btmtkuart_is_standalone(bdev)) {
err = clk_prepare_enable(bdev->osc);
if (err < 0)
- return err;
+ goto err_hci_free_dev;
if (bdev->boot) {
gpiod_set_value_cansleep(bdev->boot, 1);
@@ -1028,10 +1028,8 @@ static int btmtkuart_probe(struct serdev_device *serdev)
/* Power on */
err = regulator_enable(bdev->vcc);
- if (err < 0) {
- clk_disable_unprepare(bdev->osc);
- return err;
- }
+ if (err < 0)
+ goto err_clk_disable_unprepare;
/* Reset if the reset-gpios is available otherwise the board
* -level design should be guaranteed.
@@ -1063,7 +1061,6 @@ static int btmtkuart_probe(struct serdev_device *serdev)
err = hci_register_dev(hdev);
if (err < 0) {
dev_err(&serdev->dev, "Can't register HCI device\n");
- hci_free_dev(hdev);
goto err_regulator_disable;
}
@@ -1072,6 +1069,11 @@ static int btmtkuart_probe(struct serdev_device *serdev)
err_regulator_disable:
if (btmtkuart_is_standalone(bdev))
regulator_disable(bdev->vcc);
+err_clk_disable_unprepare:
+ if (btmtkuart_is_standalone(bdev))
+ clk_disable_unprepare(bdev->osc);
+err_hci_free_dev:
+ hci_free_dev(hdev);
return err;
}
--
2.26.2
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^ permalink raw reply related
* [PATCH v4 2/4] dmaengine: mediatek-cqdma: remove redundant queue structure
From: EastL @ 2020-05-28 9:57 UTC (permalink / raw)
To: Sean Wang
Cc: mark.rutland, devicetree, wsd_upstream, linux-kernel, EastL,
dmaengine, vkoul, robh+dt, linux-mediatek, matthias.bgg,
linux-arm-kernel
In-Reply-To: <1590659832-31476-1-git-send-email-EastL.Lee@mediatek.com>
This patch introduces active_vdec to indicate the virtual descriptor
under processing by the CQDMA dmaengine, and simplify the control logic
by removing redundant queue structure, tasklets, and completion
management.
Signed-off-by: EastL <EastL.Lee@mediatek.com>
---
drivers/dma/mediatek/mtk-cqdma.c | 383 ++++++++++-----------------------------
1 file changed, 93 insertions(+), 290 deletions(-)
diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
index 6bf838e..905bbcb 100644
--- a/drivers/dma/mediatek/mtk-cqdma.c
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -22,6 +22,7 @@
#include <linux/of_dma.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
+#include <linux/preempt.h>
#include <linux/refcount.h>
#include <linux/slab.h>
@@ -47,7 +48,6 @@
#define MTK_CQDMA_SRC 0x1c
#define MTK_CQDMA_DST 0x20
#define MTK_CQDMA_LEN1 0x24
-#define MTK_CQDMA_LEN2 0x28
#define MTK_CQDMA_SRC2 0x60
#define MTK_CQDMA_DST2 0x64
@@ -69,45 +69,32 @@
* descriptor (CVD)
* @vd: An instance for struct virt_dma_desc
* @len: The total data size device wants to move
- * @residue: The remaining data size device will move
* @dest: The destination address device wants to move to
* @src: The source address device wants to move from
* @ch: The pointer to the corresponding dma channel
- * @node: The lise_head struct to build link-list for VDs
- * @parent: The pointer to the parent CVD
*/
struct mtk_cqdma_vdesc {
struct virt_dma_desc vd;
size_t len;
- size_t residue;
dma_addr_t dest;
dma_addr_t src;
struct dma_chan *ch;
-
- struct list_head node;
- struct mtk_cqdma_vdesc *parent;
};
/**
* struct mtk_cqdma_pchan - The struct holding info describing physical
* channel (PC)
- * @queue: Queue for the PDs issued to this PC
+ * @active_vdesc: The pointer to the CVD which is under processing
* @base: The mapped register I/O base of this PC
* @irq: The IRQ that this PC are using
* @refcnt: Track how many VCs are using this PC
- * @tasklet: Tasklet for this PC
* @lock: Lock protect agaisting multiple VCs access PC
*/
struct mtk_cqdma_pchan {
- struct list_head queue;
+ struct mtk_cqdma_vdesc *active_vdesc;
void __iomem *base;
u32 irq;
-
refcount_t refcnt;
-
- struct tasklet_struct tasklet;
-
- /* lock to protect PC */
spinlock_t lock;
};
@@ -116,14 +103,11 @@ struct mtk_cqdma_pchan {
* channel (VC)
* @vc: An instance for struct virt_dma_chan
* @pc: The pointer to the underlying PC
- * @issue_completion: The wait for all issued descriptors completited
- * @issue_synchronize: Bool indicating channel synchronization starts
*/
struct mtk_cqdma_vchan {
struct virt_dma_chan vc;
struct mtk_cqdma_pchan *pc;
- struct completion issue_completion;
- bool issue_synchronize;
+ struct completion cmp;
};
/**
@@ -202,22 +186,22 @@ static void mtk_cqdma_vdesc_free(struct virt_dma_desc *vd)
kfree(to_cqdma_vdesc(vd));
}
-static int mtk_cqdma_poll_engine_done(struct mtk_cqdma_pchan *pc, bool atomic)
+static int mtk_cqdma_poll_engine_done(struct mtk_cqdma_pchan *pc)
{
u32 status = 0;
- if (!atomic)
+ if (in_task())
+ return readl_poll_timeout_atomic(pc->base + MTK_CQDMA_EN,
+ status,
+ !(status & MTK_CQDMA_EN_BIT),
+ MTK_CQDMA_USEC_POLL,
+ MTK_CQDMA_TIMEOUT_POLL);
+ else
return readl_poll_timeout(pc->base + MTK_CQDMA_EN,
status,
!(status & MTK_CQDMA_EN_BIT),
MTK_CQDMA_USEC_POLL,
MTK_CQDMA_TIMEOUT_POLL);
-
- return readl_poll_timeout_atomic(pc->base + MTK_CQDMA_EN,
- status,
- !(status & MTK_CQDMA_EN_BIT),
- MTK_CQDMA_USEC_POLL,
- MTK_CQDMA_TIMEOUT_POLL);
}
static int mtk_cqdma_hard_reset(struct mtk_cqdma_pchan *pc)
@@ -225,20 +209,17 @@ static int mtk_cqdma_hard_reset(struct mtk_cqdma_pchan *pc)
mtk_dma_set(pc, MTK_CQDMA_RESET, MTK_CQDMA_HARD_RST_BIT);
mtk_dma_clr(pc, MTK_CQDMA_RESET, MTK_CQDMA_HARD_RST_BIT);
- return mtk_cqdma_poll_engine_done(pc, true);
+ return mtk_cqdma_poll_engine_done(pc);
}
static void mtk_cqdma_start(struct mtk_cqdma_pchan *pc,
struct mtk_cqdma_vdesc *cvd)
{
- /* wait for the previous transaction done */
- if (mtk_cqdma_poll_engine_done(pc, true) < 0)
- dev_err(cqdma2dev(to_cqdma_dev(cvd->ch)), "cqdma wait transaction timeout\n");
-
/* warm reset the dma engine for the new transaction */
mtk_dma_set(pc, MTK_CQDMA_RESET, MTK_CQDMA_WARM_RST_BIT);
- if (mtk_cqdma_poll_engine_done(pc, true) < 0)
- dev_err(cqdma2dev(to_cqdma_dev(cvd->ch)), "cqdma warm reset timeout\n");
+ if (mtk_cqdma_poll_engine_done(pc) < 0)
+ dev_err(cqdma2dev(to_cqdma_dev(cvd->ch)),
+ "cqdma warm reset timeout\n");
/* setup the source */
mtk_dma_set(pc, MTK_CQDMA_SRC, cvd->src & MTK_CQDMA_ADDR_LIMIT);
@@ -257,7 +238,8 @@ static void mtk_cqdma_start(struct mtk_cqdma_pchan *pc,
#endif
/* setup the length */
- mtk_dma_set(pc, MTK_CQDMA_LEN1, cvd->len);
+ mtk_dma_set(pc, MTK_CQDMA_LEN1, (cvd->len < MTK_CQDMA_MAX_LEN) ?
+ cvd->len : MTK_CQDMA_MAX_LEN);
/* start dma engine */
mtk_dma_set(pc, MTK_CQDMA_EN, MTK_CQDMA_EN_BIT);
@@ -265,30 +247,17 @@ static void mtk_cqdma_start(struct mtk_cqdma_pchan *pc,
static void mtk_cqdma_issue_vchan_pending(struct mtk_cqdma_vchan *cvc)
{
- struct virt_dma_desc *vd, *vd2;
+ struct virt_dma_desc *vd;
struct mtk_cqdma_pchan *pc = cvc->pc;
- struct mtk_cqdma_vdesc *cvd;
- bool trigger_engine = false;
lockdep_assert_held(&cvc->vc.lock);
lockdep_assert_held(&pc->lock);
- list_for_each_entry_safe(vd, vd2, &cvc->vc.desc_issued, node) {
- /* need to trigger dma engine if PC's queue is empty */
- if (list_empty(&pc->queue))
- trigger_engine = true;
-
- cvd = to_cqdma_vdesc(vd);
-
- /* add VD into PC's queue */
- list_add_tail(&cvd->node, &pc->queue);
-
- /* start the dma engine */
- if (trigger_engine)
- mtk_cqdma_start(pc, cvd);
+ vd = vchan_next_desc(&cvc->vc);
- /* remove VD from list desc_issued */
- list_del(&vd->node);
+ if (vd && !pc->active_vdesc) {
+ pc->active_vdesc = to_cqdma_vdesc(vd);
+ mtk_cqdma_start(pc, pc->active_vdesc);
}
}
@@ -298,100 +267,55 @@ static void mtk_cqdma_issue_vchan_pending(struct mtk_cqdma_vchan *cvc)
*/
static bool mtk_cqdma_is_vchan_active(struct mtk_cqdma_vchan *cvc)
{
- struct mtk_cqdma_vdesc *cvd;
-
- list_for_each_entry(cvd, &cvc->pc->queue, node)
- if (cvc == to_cqdma_vchan(cvd->ch))
- return true;
-
- return false;
+ return (!cvc->pc->active_vdesc) ? false :
+ (cvc == to_cqdma_vchan(cvc->pc->active_vdesc->ch));
}
-/*
- * return the pointer of the CVD that is just consumed by the PC
- */
-static struct mtk_cqdma_vdesc
-*mtk_cqdma_consume_work_queue(struct mtk_cqdma_pchan *pc)
+static void mtk_cqdma_complete_vdesc(struct mtk_cqdma_pchan *pc)
{
struct mtk_cqdma_vchan *cvc;
- struct mtk_cqdma_vdesc *cvd, *ret = NULL;
-
- /* consume a CVD from PC's queue */
- cvd = list_first_entry_or_null(&pc->queue,
- struct mtk_cqdma_vdesc, node);
- if (unlikely(!cvd || !cvd->parent))
- return NULL;
+ struct mtk_cqdma_vdesc *cvd;
+ struct virt_dma_desc *vd;
+ size_t tlen;
+ cvd = pc->active_vdesc;
cvc = to_cqdma_vchan(cvd->ch);
- ret = cvd;
-
- /* update residue of the parent CVD */
- cvd->parent->residue -= cvd->len;
- /* delete CVD from PC's queue */
- list_del(&cvd->node);
+ tlen = (cvd->len < MTK_CQDMA_MAX_LEN) ? cvd->len : MTK_CQDMA_MAX_LEN;
+ cvd->len -= tlen;
+ cvd->src += tlen;
+ cvd->dest += tlen;
spin_lock(&cvc->vc.lock);
- /* check whether all the child CVDs completed */
- if (!cvd->parent->residue) {
- /* add the parent VD into list desc_completed */
- vchan_cookie_complete(&cvd->parent->vd);
+ /* check whether the VD completed */
+ if (!cvd->len) {
+ /* delete VD from desc_issued */
+ list_del(&cvd->vd.node);
- /* setup completion if this VC is under synchronization */
- if (cvc->issue_synchronize && !mtk_cqdma_is_vchan_active(cvc)) {
- complete(&cvc->issue_completion);
- cvc->issue_synchronize = false;
- }
- }
-
- spin_unlock(&cvc->vc.lock);
+ /* add the VD into list desc_completed */
+ vchan_cookie_complete(&cvd->vd);
- /* start transaction for next CVD in the queue */
- cvd = list_first_entry_or_null(&pc->queue,
- struct mtk_cqdma_vdesc, node);
- if (cvd)
- mtk_cqdma_start(pc, cvd);
-
- return ret;
-}
-
-static void mtk_cqdma_tasklet_cb(unsigned long data)
-{
- struct mtk_cqdma_pchan *pc = (struct mtk_cqdma_pchan *)data;
- struct mtk_cqdma_vdesc *cvd = NULL;
- unsigned long flags;
-
- spin_lock_irqsave(&pc->lock, flags);
- /* consume the queue */
- cvd = mtk_cqdma_consume_work_queue(pc);
- spin_unlock_irqrestore(&pc->lock, flags);
-
- /* submit the next CVD */
- if (cvd) {
- dma_run_dependencies(&cvd->vd.tx);
-
- /*
- * free child CVD after completion.
- * the parent CVD would be freeed with desc_free by user.
- */
- if (cvd->parent != cvd)
- kfree(cvd);
+ /* get the next active VD */
+ vd = vchan_next_desc(&cvc->vc);
+ pc->active_vdesc = (!vd) ? NULL : to_cqdma_vdesc(vd);
}
- /* re-enable interrupt before leaving tasklet */
- enable_irq(pc->irq);
+ /* start the next transaction */
+ if (pc->active_vdesc)
+ mtk_cqdma_start(pc, pc->active_vdesc);
+
+ spin_unlock(&cvc->vc.lock);
}
static irqreturn_t mtk_cqdma_irq(int irq, void *devid)
{
struct mtk_cqdma_device *cqdma = devid;
irqreturn_t ret = IRQ_NONE;
- bool schedule_tasklet = false;
u32 i;
/* clear interrupt flags for each PC */
- for (i = 0; i < cqdma->dma_channels; ++i, schedule_tasklet = false) {
+ for (i = 0; i < cqdma->dma_channels; ++i) {
spin_lock(&cqdma->pc[i]->lock);
if (mtk_dma_read(cqdma->pc[i],
MTK_CQDMA_INT_FLAG) & MTK_CQDMA_INT_FLAG_BIT) {
@@ -399,72 +323,21 @@ static irqreturn_t mtk_cqdma_irq(int irq, void *devid)
mtk_dma_clr(cqdma->pc[i], MTK_CQDMA_INT_FLAG,
MTK_CQDMA_INT_FLAG_BIT);
- schedule_tasklet = true;
+ mtk_cqdma_complete_vdesc(cqdma->pc[i]);
+
ret = IRQ_HANDLED;
}
spin_unlock(&cqdma->pc[i]->lock);
-
- if (schedule_tasklet) {
- /* disable interrupt */
- disable_irq_nosync(cqdma->pc[i]->irq);
-
- /* schedule the tasklet to handle the transactions */
- tasklet_schedule(&cqdma->pc[i]->tasklet);
- }
}
return ret;
}
-static struct virt_dma_desc *mtk_cqdma_find_active_desc(struct dma_chan *c,
- dma_cookie_t cookie)
-{
- struct mtk_cqdma_vchan *cvc = to_cqdma_vchan(c);
- struct virt_dma_desc *vd;
- unsigned long flags;
-
- spin_lock_irqsave(&cvc->pc->lock, flags);
- list_for_each_entry(vd, &cvc->pc->queue, node)
- if (vd->tx.cookie == cookie) {
- spin_unlock_irqrestore(&cvc->pc->lock, flags);
- return vd;
- }
- spin_unlock_irqrestore(&cvc->pc->lock, flags);
-
- list_for_each_entry(vd, &cvc->vc.desc_issued, node)
- if (vd->tx.cookie == cookie)
- return vd;
-
- return NULL;
-}
-
static enum dma_status mtk_cqdma_tx_status(struct dma_chan *c,
dma_cookie_t cookie,
struct dma_tx_state *txstate)
{
- struct mtk_cqdma_vchan *cvc = to_cqdma_vchan(c);
- struct mtk_cqdma_vdesc *cvd;
- struct virt_dma_desc *vd;
- enum dma_status ret;
- unsigned long flags;
- size_t bytes = 0;
-
- ret = dma_cookie_status(c, cookie, txstate);
- if (ret == DMA_COMPLETE || !txstate)
- return ret;
-
- spin_lock_irqsave(&cvc->vc.lock, flags);
- vd = mtk_cqdma_find_active_desc(c, cookie);
- spin_unlock_irqrestore(&cvc->vc.lock, flags);
-
- if (vd) {
- cvd = to_cqdma_vdesc(vd);
- bytes = cvd->residue;
- }
-
- dma_set_residue(txstate, bytes);
-
- return ret;
+ return dma_cookie_status(c, cookie, txstate);
}
static void mtk_cqdma_issue_pending(struct dma_chan *c)
@@ -473,13 +346,17 @@ static void mtk_cqdma_issue_pending(struct dma_chan *c)
unsigned long pc_flags;
unsigned long vc_flags;
- /* acquire PC's lock before VS's lock for lock dependency in tasklet */
+ /* acquire PC's lock before VC's lock for lock dependency in ISR */
spin_lock_irqsave(&cvc->pc->lock, pc_flags);
spin_lock_irqsave(&cvc->vc.lock, vc_flags);
+ init_completion(&cvc->cmp);
+
if (vchan_issue_pending(&cvc->vc))
mtk_cqdma_issue_vchan_pending(cvc);
+ complete(&cvc->cmp);
+
spin_unlock_irqrestore(&cvc->vc.lock, vc_flags);
spin_unlock_irqrestore(&cvc->pc->lock, pc_flags);
}
@@ -488,125 +365,50 @@ static void mtk_cqdma_issue_pending(struct dma_chan *c)
mtk_cqdma_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dest,
dma_addr_t src, size_t len, unsigned long flags)
{
- struct mtk_cqdma_vdesc **cvd;
- struct dma_async_tx_descriptor *tx = NULL, *prev_tx = NULL;
- size_t i, tlen, nr_vd;
-
- /*
- * In the case that trsanction length is larger than the
- * DMA engine supports, a single memcpy transaction needs
- * to be separated into several DMA transactions.
- * Each DMA transaction would be described by a CVD,
- * and the first one is referred as the parent CVD,
- * while the others are child CVDs.
- * The parent CVD's tx descriptor is the only tx descriptor
- * returned to the DMA user, and it should not be completed
- * until all the child CVDs completed.
- */
- nr_vd = DIV_ROUND_UP(len, MTK_CQDMA_MAX_LEN);
- cvd = kcalloc(nr_vd, sizeof(*cvd), GFP_NOWAIT);
+ struct mtk_cqdma_vdesc *cvd;
+
+ cvd = kzalloc(sizeof(*cvd), GFP_NOWAIT);
if (!cvd)
return NULL;
- for (i = 0; i < nr_vd; ++i) {
- cvd[i] = kzalloc(sizeof(*cvd[i]), GFP_NOWAIT);
- if (!cvd[i]) {
- for (; i > 0; --i)
- kfree(cvd[i - 1]);
- return NULL;
- }
-
- /* setup dma channel */
- cvd[i]->ch = c;
-
- /* setup sourece, destination, and length */
- tlen = (len > MTK_CQDMA_MAX_LEN) ? MTK_CQDMA_MAX_LEN : len;
- cvd[i]->len = tlen;
- cvd[i]->src = src;
- cvd[i]->dest = dest;
-
- /* setup tx descriptor */
- tx = vchan_tx_prep(to_virt_chan(c), &cvd[i]->vd, flags);
- tx->next = NULL;
+ /* setup dma channel */
+ cvd->ch = c;
- if (!i) {
- cvd[0]->residue = len;
- } else {
- prev_tx->next = tx;
- cvd[i]->residue = tlen;
- }
-
- cvd[i]->parent = cvd[0];
-
- /* update the src, dest, len, prev_tx for the next CVD */
- src += tlen;
- dest += tlen;
- len -= tlen;
- prev_tx = tx;
- }
+ /* setup sourece, destination, and length */
+ cvd->len = len;
+ cvd->src = src;
+ cvd->dest = dest;
- return &cvd[0]->vd.tx;
+ return vchan_tx_prep(to_virt_chan(c), &cvd->vd, flags);
}
-static void mtk_cqdma_free_inactive_desc(struct dma_chan *c)
-{
- struct virt_dma_chan *vc = to_virt_chan(c);
- unsigned long flags;
- LIST_HEAD(head);
-
- /*
- * set desc_allocated, desc_submitted,
- * and desc_issued as the candicates to be freed
- */
- spin_lock_irqsave(&vc->lock, flags);
- list_splice_tail_init(&vc->desc_allocated, &head);
- list_splice_tail_init(&vc->desc_submitted, &head);
- list_splice_tail_init(&vc->desc_issued, &head);
- spin_unlock_irqrestore(&vc->lock, flags);
-
- /* free descriptor lists */
- vchan_dma_desc_free_list(vc, &head);
-}
-
-static void mtk_cqdma_free_active_desc(struct dma_chan *c)
+static int mtk_cqdma_terminate_all(struct dma_chan *c)
{
struct mtk_cqdma_vchan *cvc = to_cqdma_vchan(c);
- bool sync_needed = false;
+ struct virt_dma_chan *vc = to_virt_chan(c);
unsigned long pc_flags;
unsigned long vc_flags;
+ LIST_HEAD(head);
+
+ /* wait for the VC to be inactive */
+ if (!wait_for_completion_timeout(&cvc->cmp, msecs_to_jiffies(3000)))
+ return -EAGAIN;
/* acquire PC's lock first due to lock dependency in dma ISR */
spin_lock_irqsave(&cvc->pc->lock, pc_flags);
spin_lock_irqsave(&cvc->vc.lock, vc_flags);
- /* synchronization is required if this VC is active */
- if (mtk_cqdma_is_vchan_active(cvc)) {
- cvc->issue_synchronize = true;
- sync_needed = true;
- }
+ /* get VDs from lists */
+ vchan_get_all_descriptors(vc, &head);
+
+ /* free all the VDs */
+ vchan_dma_desc_free_list(vc, &head);
spin_unlock_irqrestore(&cvc->vc.lock, vc_flags);
spin_unlock_irqrestore(&cvc->pc->lock, pc_flags);
- /* waiting for the completion of this VC */
- if (sync_needed)
- wait_for_completion(&cvc->issue_completion);
-
- /* free all descriptors in list desc_completed */
vchan_synchronize(&cvc->vc);
- WARN_ONCE(!list_empty(&cvc->vc.desc_completed),
- "Desc pending still in list desc_completed\n");
-}
-
-static int mtk_cqdma_terminate_all(struct dma_chan *c)
-{
- /* free descriptors not processed yet by hardware */
- mtk_cqdma_free_inactive_desc(c);
-
- /* free descriptors being processed by hardware */
- mtk_cqdma_free_active_desc(c);
-
return 0;
}
@@ -618,7 +420,7 @@ static int mtk_cqdma_alloc_chan_resources(struct dma_chan *c)
u32 i, min_refcnt = U32_MAX, refcnt;
unsigned long flags;
- /* allocate PC with the minimun refcount */
+ /* allocate PC with the minimum refcount */
for (i = 0; i < cqdma->dma_channels; ++i) {
refcnt = refcount_read(&cqdma->pc[i]->refcnt);
if (refcnt < min_refcnt) {
@@ -671,8 +473,9 @@ static void mtk_cqdma_free_chan_resources(struct dma_chan *c)
mtk_dma_set(cvc->pc, MTK_CQDMA_FLUSH, MTK_CQDMA_FLUSH_BIT);
/* wait for the completion of flush operation */
- if (mtk_cqdma_poll_engine_done(cvc->pc, true) < 0)
- dev_err(cqdma2dev(to_cqdma_dev(c)), "cqdma flush timeout\n");
+ if (mtk_cqdma_poll_engine_done(cvc->pc) < 0)
+ dev_err(cqdma2dev(to_cqdma_dev(c)),
+ "cqdma flush timeout\n");
/* clear the flush bit and interrupt flag */
mtk_dma_clr(cvc->pc, MTK_CQDMA_FLUSH, MTK_CQDMA_FLUSH_BIT);
@@ -816,10 +619,18 @@ static int mtk_cqdma_probe(struct platform_device *pdev)
if (!cqdma->pc[i])
return -ENOMEM;
- INIT_LIST_HEAD(&cqdma->pc[i]->queue);
+ cqdma->pc[i]->active_vdesc = NULL;
spin_lock_init(&cqdma->pc[i]->lock);
refcount_set(&cqdma->pc[i]->refcnt, 0);
- cqdma->pc[i]->base = devm_platform_ioremap_resource(pdev, i);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+ if (!res) {
+ dev_err(&pdev->dev, "No mem resource for %s\n",
+ dev_name(&pdev->dev));
+ return -EINVAL;
+ }
+
+ cqdma->pc[i]->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(cqdma->pc[i]->base))
return PTR_ERR(cqdma->pc[i]->base);
@@ -852,7 +663,6 @@ static int mtk_cqdma_probe(struct platform_device *pdev)
vc = &cqdma->vc[i];
vc->vc.desc_free = mtk_cqdma_vdesc_free;
vchan_init(&vc->vc, dd);
- init_completion(&vc->issue_completion);
}
err = dma_async_device_register(dd);
@@ -876,11 +686,6 @@ static int mtk_cqdma_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, cqdma);
- /* initialize tasklet for each PC */
- for (i = 0; i < cqdma->dma_channels; ++i)
- tasklet_init(&cqdma->pc[i]->tasklet, mtk_cqdma_tasklet_cb,
- (unsigned long)cqdma->pc[i]);
-
dev_info(&pdev->dev, "MediaTek CQDMA driver registered\n");
return 0;
@@ -915,8 +720,6 @@ static int mtk_cqdma_remove(struct platform_device *pdev)
/* Waits for any pending IRQ handlers to complete */
synchronize_irq(cqdma->pc[i]->irq);
-
- tasklet_kill(&cqdma->pc[i]->tasklet);
}
/* disable hardware */
--
1.9.1
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^ permalink raw reply related
* [PATCH v4 4/4] dmaengine: mediatek-cqdma: add dma mask for capability
From: EastL @ 2020-05-28 9:57 UTC (permalink / raw)
To: Sean Wang
Cc: mark.rutland, devicetree, wsd_upstream, linux-kernel, EastL,
dmaengine, vkoul, robh+dt, linux-mediatek, matthias.bgg,
linux-arm-kernel
In-Reply-To: <1590659832-31476-1-git-send-email-EastL.Lee@mediatek.com>
This patch add dma mask for capability.
Change-Id: I31f4622f9541d769702029532e5f5f185815dda2
Signed-off-by: EastL <EastL.Lee@mediatek.com>
---
drivers/dma/mediatek/mtk-cqdma.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
index bca7118..1805a76 100644
--- a/drivers/dma/mediatek/mtk-cqdma.c
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -117,6 +117,7 @@ struct mtk_cqdma_vchan {
* @clk: The clock that device internal is using
* @dma_requests: The number of VCs the device supports to
* @dma_channels: The number of PCs the device supports to
+ * @dma_mask: A mask for DMA capability
* @vc: The pointer to all available VCs
* @pc: The pointer to all the underlying PCs
*/
@@ -126,6 +127,7 @@ struct mtk_cqdma_device {
u32 dma_requests;
u32 dma_channels;
+ u32 dma_mask;
struct mtk_cqdma_vchan *vc;
struct mtk_cqdma_pchan **pc;
};
@@ -549,6 +551,7 @@ static void mtk_cqdma_hw_deinit(struct mtk_cqdma_device *cqdma)
};
MODULE_DEVICE_TABLE(of, mtk_cqdma_match);
+static u64 cqdma_dmamask;
static int mtk_cqdma_probe(struct platform_device *pdev)
{
struct mtk_cqdma_device *cqdma;
@@ -607,6 +610,16 @@ static int mtk_cqdma_probe(struct platform_device *pdev)
cqdma->dma_channels = MTK_CQDMA_NR_PCHANS;
}
+ if (pdev->dev.of_node && of_property_read_u32(pdev->dev.of_node,
+ "dma-channel-mask",
+ &cqdma->dma_mask)) {
+ dev_info(&pdev->dev,
+ "Using 0 as missing dma-channel-mask property\n");
+ } else {
+ cqdma_dmamask = DMA_BIT_MASK(cqdma->dma_mask);
+ pdev->dev.dma_mask = &cqdma_dmamask;
+ }
+
cqdma->pc = devm_kcalloc(&pdev->dev, cqdma->dma_channels,
sizeof(*cqdma->pc), GFP_KERNEL);
if (!cqdma->pc)
--
1.9.1
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^ permalink raw reply related
* [PATCH v4] dmaengine: mediatek-cqdma: add dt-bindings and remove redundant queue
From: EastL @ 2020-05-28 9:57 UTC (permalink / raw)
To: Sean Wang
Cc: mark.rutland, devicetree, wsd_upstream, linux-kernel, dmaengine,
vkoul, robh+dt, linux-mediatek, matthias.bgg, linux-arm-kernel
This patch set adds document the devicetree bindings for MediaTek Command-Queue DMA controller,
and remove redundant queue structure, add dma-channel-mask for DMA capability and fix compatible.
Changes since v3:
- fix dt_binding_check errors
Changes since v2:
- add devicetree bindings for MediaTek Command-Queue DMA controller
Changes since v1:
- remove redundant queue structure
- fix wrong description and tags in the earlier patch
- add dma-channel-mask for DMA capability
- fix compatible for common
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^ permalink raw reply
* [PATCH v4 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
From: EastL @ 2020-05-28 9:57 UTC (permalink / raw)
To: Sean Wang
Cc: mark.rutland, devicetree, wsd_upstream, linux-kernel, EastL,
dmaengine, vkoul, robh+dt, linux-mediatek, matthias.bgg,
linux-arm-kernel
In-Reply-To: <1590659832-31476-1-git-send-email-EastL.Lee@mediatek.com>
Document the devicetree bindings for MediaTek Command-Queue DMA controller
which could be found on MT6779 SoC or other similar Mediatek SoCs.
Signed-off-by: EastL <EastL.Lee@mediatek.com>
---
.../devicetree/bindings/dma/mtk-cqdma.yaml | 100 +++++++++++++++++++++
1 file changed, 100 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
new file mode 100644
index 0000000..045aa0c
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/mtk-cqdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Command-Queue DMA controller Device Tree Binding
+
+maintainers:
+ - EastL <EastL.Lee@mediatek.com>
+
+description:
+ MediaTek Command-Queue DMA controller (CQDMA) on Mediatek SoC
+ is dedicated to memory-to-memory transfer through queue based
+ descriptor management.
+
+properties:
+ "#dma-cells":
+ minimum: 1
+ # Should be enough
+ maximum: 255
+ description:
+ Used to provide DMA controller specific information.
+
+ compatible:
+ const: mediatek,cqdma
+
+ reg:
+ minItems: 1
+ maxItems: 255
+
+ interrupts:
+ minItems: 1
+ maxItems: 255
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: cqdma
+
+ dma-channel-mask:
+ description:
+ Bitmask of available DMA channels in ascending order that are
+ not reserved by firmware and are available to the
+ kernel. i.e. first channel corresponds to LSB.
+ The first item in the array is for channels 0-31, the second is for
+ channels 32-63, etc.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ minItems: 1
+ # Should be enough
+ maxItems: 255
+
+ dma-channels:
+ $ref: /schemas/types.yaml#definitions/uint32
+ description:
+ Number of DMA channels supported by the controller.
+
+ dma-requests:
+ $ref: /schemas/types.yaml#definitions/uint32
+ description:
+ Number of DMA request signals supported by the controller.
+
+required:
+ - "#dma-cells"
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - dma-channel-mask
+ - dma-channels
+ - dma-requests
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt6779-clk.h>
+ cqdma: dma-controller@10212000 {
+ compatible = "mediatek,cqdma";
+ reg = <0 0x10212000 0 0x80>,
+ <0 0x10212080 0 0x80>,
+ <0 0x10212100 0 0x80>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg_ao CLK_INFRA_CQ_DMA>;
+ clock-names = "cqdma";
+ dma-channel-mask = <63>;
+ dma-channels = <3>;
+ dma-requests = <32>;
+ #dma-cells = <1>;
+ };
+
+...
--
1.9.1
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^ permalink raw reply related
* [PATCH v4 3/4] dmaengine: mediatek-cqdma: fix compatible
From: EastL @ 2020-05-28 9:57 UTC (permalink / raw)
To: Sean Wang
Cc: mark.rutland, devicetree, wsd_upstream, linux-kernel, EastL,
dmaengine, vkoul, robh+dt, linux-mediatek, matthias.bgg,
linux-arm-kernel
In-Reply-To: <1590659832-31476-1-git-send-email-EastL.Lee@mediatek.com>
This patch fixes mediatek-cqdma compatible to common.
Signed-off-by: EastL <EastL.Lee@mediatek.com>
---
drivers/dma/mediatek/mtk-cqdma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
index 905bbcb..bca7118 100644
--- a/drivers/dma/mediatek/mtk-cqdma.c
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -544,7 +544,7 @@ static void mtk_cqdma_hw_deinit(struct mtk_cqdma_device *cqdma)
}
static const struct of_device_id mtk_cqdma_match[] = {
- { .compatible = "mediatek,mt6765-cqdma" },
+ { .compatible = "mediatek,cqdma" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mtk_cqdma_match);
--
1.9.1
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