From: "Kevin D. Kissell" <kevink@mips.com>
To: "Florian Lohoff" <flo@rfc822.org>, <linux-mips@oss.sgi.com>
Subject: Re: MIPS32 patches breaking DecStation
Date: Tue, 9 Jan 2001 01:34:47 +0100 [thread overview]
Message-ID: <000501c079d3$fefe1a60$0deca8c0@Ulysses> (raw)
In-Reply-To: 20010109004101.B27674@paradigm.rfc822.org
Florian,
Could you do me a huge favor and try a build that
uses 3 or 4 nops instead of the branch to the instruction
after the delay slot? There was a reason that I eliminated
the branch construct from the MIPS internal Linux source
base - it's a hack that works perfectly on R4000's, but
it's pretty much a coincidence that it does so. Yes,
the code fragment in question is R4K-specific, but
we really need to migrate towards the use of consistent
mechanisms that work across the full range of MIPS
CPUs. Ideally, *all* CP0 hazards should some day be
padded out with "ssnops" (sll $0,$0,1, if I recall), which
force a 1 cycle delay per instruction even on superscalar
MIPS CPUs.
Kevin K.
WARNING: multiple messages have this Message-ID (diff)
From: "Kevin D. Kissell" <kevink@mips.com>
To: Florian Lohoff <flo@rfc822.org>, linux-mips@oss.sgi.com
Subject: Re: MIPS32 patches breaking DecStation
Date: Tue, 9 Jan 2001 01:34:47 +0100 [thread overview]
Message-ID: <000501c079d3$fefe1a60$0deca8c0@Ulysses> (raw)
Message-ID: <20010109003447.gQcRFGX1ReLVpl8ZBcA9dP4-Itflj1n1MfSfDI7x65w@z> (raw)
In-Reply-To: 20010109004101.B27674@paradigm.rfc822.org
Florian,
Could you do me a huge favor and try a build that
uses 3 or 4 nops instead of the branch to the instruction
after the delay slot? There was a reason that I eliminated
the branch construct from the MIPS internal Linux source
base - it's a hack that works perfectly on R4000's, but
it's pretty much a coincidence that it does so. Yes,
the code fragment in question is R4K-specific, but
we really need to migrate towards the use of consistent
mechanisms that work across the full range of MIPS
CPUs. Ideally, *all* CP0 hazards should some day be
padded out with "ssnops" (sll $0,$0,1, if I recall), which
force a 1 cycle delay per instruction even on superscalar
MIPS CPUs.
Kevin K.
next prev parent reply other threads:[~2001-01-09 0:31 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-01-08 23:41 MIPS32 patches breaking DecStation Florian Lohoff
2001-01-08 23:41 ` Florian Lohoff
2001-01-09 0:34 ` Kevin D. Kissell [this message]
2001-01-09 0:34 ` Kevin D. Kissell
2001-01-09 8:54 ` Florian Lohoff
2001-01-09 17:11 ` Harald Koerfgen
2001-01-09 18:28 ` Ralf Baechle
2001-01-09 19:30 ` Kevin D. Kissell
2001-01-09 19:30 ` Kevin D. Kissell
2001-01-09 19:54 ` Ralf Baechle
2001-01-09 19:54 ` Ralf Baechle
2001-01-09 20:33 ` Kevin D. Kissell
2001-01-09 20:33 ` Kevin D. Kissell
2001-01-09 15:09 ` Ralf Baechle
2001-01-09 15:09 ` Ralf Baechle
2001-01-09 15:50 ` Kevin D. Kissell
2001-01-09 15:50 ` Kevin D. Kissell
2001-01-09 16:43 ` Harald Koerfgen
2001-01-09 17:01 ` Ralf Baechle
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