From: "Michael Uhler" <uhler@mips.com>
To: "'Greg Weeks'" <greg.weeks@timesys.com>,
"'Ralf Baechle'" <ralf@linux-mips.org>
Cc: <linux-mips@linux-mips.org>
Subject: RE: memcpy prefetch
Date: Thu, 7 Apr 2005 05:25:15 -0700 [thread overview]
Message-ID: <003901c53b6c$da8938e0$cf14a8c0@MIPS.COM> (raw)
In-Reply-To: <4255240E.4050701@timesys.com>
> What's the performance hit for doing a pref on a cache line that is
> already pref'd? Does it turn into a nop, or do we get some horrible
> degenerate case? Are 64 bit processors always at least 32 byte cache
> line size? I don't really expect anyone to know the answers
> right now. I
> expect I'll need to time code to tell. This makes generating
> them at run
> time look better and better.
As very general rules of thumb:
- A pref to a line which is already in the cache take a cycle in the
load/store unit and does not go back out to the memory subsystem. There are
some possible ships-passing-in-the-night scenarios, but most processors do
what you'd expect.
- Most 64-bit processors are built for high-end applications, and most
high-end processors most likely have at least 32-bit lines. One usually has
smaller line sizes when the processor is intended for lower-end
applications, or where the memory subsystem isn't all that good.
/gmu
---
Michael Uhler, Chief Technology Officer
MIPS Technologies, Inc. Email: uhler at mips.com
1225 Charleston Road
Mountain View, CA 94043
WARNING: multiple messages have this Message-ID (diff)
From: "Michael Uhler" <uhler@mips.com>
To: 'Greg Weeks' <greg.weeks@timesys.com>,
'Ralf Baechle' <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Subject: RE: memcpy prefetch
Date: Thu, 7 Apr 2005 05:25:15 -0700 [thread overview]
Message-ID: <003901c53b6c$da8938e0$cf14a8c0@MIPS.COM> (raw)
Message-ID: <20050407122515.8JawiMYYo8xzqpUywNp3qahn6ebz0887gkaIVXB3Cuk@z> (raw)
In-Reply-To: <4255240E.4050701@timesys.com>
> What's the performance hit for doing a pref on a cache line that is
> already pref'd? Does it turn into a nop, or do we get some horrible
> degenerate case? Are 64 bit processors always at least 32 byte cache
> line size? I don't really expect anyone to know the answers
> right now. I
> expect I'll need to time code to tell. This makes generating
> them at run
> time look better and better.
As very general rules of thumb:
- A pref to a line which is already in the cache take a cycle in the
load/store unit and does not go back out to the memory subsystem. There are
some possible ships-passing-in-the-night scenarios, but most processors do
what you'd expect.
- Most 64-bit processors are built for high-end applications, and most
high-end processors most likely have at least 32-bit lines. One usually has
smaller line sizes when the processor is intended for lower-end
applications, or where the memory subsystem isn't all that good.
/gmu
---
Michael Uhler, Chief Technology Officer
MIPS Technologies, Inc. Email: uhler at mips.com
1225 Charleston Road
Mountain View, CA 94043
next prev parent reply other threads:[~2005-04-07 12:26 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-04-06 12:30 memcpy prefetch Greg Weeks
2005-04-06 20:08 ` Ralf Baechle
2005-04-07 12:14 ` Greg Weeks
2005-04-07 12:25 ` Ralf Baechle
2005-04-07 12:25 ` Michael Uhler [this message]
2005-04-07 12:25 ` Michael Uhler
2005-04-07 12:28 ` Dominic Sweetman
2005-04-07 14:05 ` Ralf Baechle
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