From: Harald Koerfgen <hkoerfg@web.de>
To: Jun Sun <jsun@mvista.com>, "H . J . Lu" <hjl@lucon.org>
Cc: linux-mips@oss.sgi.com
Subject: Re: A new mips toolchain is available
Date: Wed, 13 Jun 2001 22:55:00 +0200 [thread overview]
Message-ID: <01061322550001.00617@intel> (raw)
In-Reply-To: <3B27B56F.65BAE189@mvista.com>
On Wednesday 13 June 2001 20:48, Jun Sun wrote:
> The latest CVS tree removed MIPS_ATOMIC_SET for CPUs without ll/sc. See
> the diff below.
[diff snipped]
> It seems that the checkin is a mistake because apparently it is not what
> linux-vr is doing. They used to have a piece of code for CPUs without
> ll/sc. And recently they moved to ll/sc instruction emulation.
Well, you seem to have a different linux-vr tree than I do :-)
> Ralf, the following patch includes the original vr code for
> MIPS_ATOMIC_SET, no ll/sc case. Although we all know it is buggy (for
> small negative set values), it is still better than nothing.
Anyway, the linux-vr source tree has a partially working ll/sc emulation, at
least enough for glibc, and MIPS_ATOMIC_SET is not neccessarily needed.
In fact, MIPS_ATOMIC_SET has been removed from the vr tree.
Regards,
Harald
next prev parent reply other threads:[~2001-06-14 7:44 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-06-12 4:03 A new mips toolchain is available H . J . Lu
2001-06-12 11:39 ` Ralf Baechle
2001-06-12 16:40 ` H . J . Lu
2001-06-12 19:11 ` Ralf Baechle
2001-06-12 19:38 ` H . J . Lu
2001-06-13 7:57 ` Maciej W. Rozycki
2001-06-13 15:08 ` H . J . Lu
2001-06-13 15:22 ` Maciej W. Rozycki
2001-06-13 15:24 ` H . J . Lu
2001-06-13 15:39 ` Maciej W. Rozycki
2001-06-13 15:44 ` H . J . Lu
2001-06-13 18:48 ` Jun Sun
2001-06-13 20:55 ` Harald Koerfgen [this message]
2001-06-14 10:26 ` Maciej W. Rozycki
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