* [PATCH v3 0/5] Alchemy: Basic Au1300 and DB1300 support @ 2009-04-08 23:36 Kevin Hickey 2009-04-08 23:36 ` [PATCH v3 1/5] Alchemy: Initial Au1300 and DBAu1300 support Kevin Hickey 0 siblings, 1 reply; 10+ messages in thread From: Kevin Hickey @ 2009-04-08 23:36 UTC (permalink / raw) To: linux-mips, ralf This patch series introduces support for the RMI Alchemy Au1300 series of SOCs and the DBAu1300 (or DB1300) development board. With this set the basic CPU and board are supported. I have code for several of the peripherals, including USB, MMC, IDE, and Ethernet and will submit those patches after these have been accepted. Though some of the new code added here could be useful for other boards (the DB1200 in particular), I did my best to limit this patch set to additions only. It should not disturb any other boards. To verify this I built and tested the updated directory for an on a DB1200 board. A future patch set may include some integration of this new code into the DB1200 configuration. This set incorporates feedback I received on v2 of these patches. =Kevin ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3 1/5] Alchemy: Initial Au1300 and DBAu1300 support 2009-04-08 23:36 [PATCH v3 0/5] Alchemy: Basic Au1300 and DB1300 support Kevin Hickey @ 2009-04-08 23:36 ` Kevin Hickey 2009-04-08 23:36 ` [PATCH v3 2/5] Alchemy: Au1300 new interrupt controller Kevin Hickey 0 siblings, 1 reply; 10+ messages in thread From: Kevin Hickey @ 2009-04-08 23:36 UTC (permalink / raw) To: linux-mips, ralf; +Cc: Kevin Hickey This patch introduces the new RMI Alchemy Au1300 series SOC to the kernel, as well as its first development board, the DBAu1300 (or DB1300). This patch is just the basic CPU identification and some resouce constants. Also included are some new Alchemy IO functions and macros, named to match with the current kernel standard. They include au_iowrite32, au_ioread32, etc. These are used heavily in the Au1300/DB1300 code so they need to be included here. Signed-off-by: Kevin Hickey <khickey@rmicorp.com> --- arch/mips/Makefile | 6 + arch/mips/alchemy/Kconfig | 6 + arch/mips/alchemy/devboards/Makefile | 1 + arch/mips/alchemy/devboards/db1300/Makefile | 6 + arch/mips/alchemy/devboards/db1300/board_setup.c | 107 ++++++++++++ arch/mips/include/asm/cpu.h | 10 +- arch/mips/include/asm/mach-au1x00/au1000.h | 45 +++++ arch/mips/include/asm/mach-au1x00/au13xx.h | 201 ++++++++++++++++++++++ arch/mips/include/asm/mach-au1x00/au1xxx.h | 3 + arch/mips/include/asm/mach-au1x00/dev_boards.h | 44 +++++ arch/mips/include/asm/mips-boards/db1300.h | 121 +++++++++++++ arch/mips/kernel/cpu-probe.c | 20 ++ arch/mips/mm/c-r4k.c | 1 + arch/mips/mm/tlbex.c | 1 + 14 files changed, 569 insertions(+), 3 deletions(-) create mode 100644 arch/mips/alchemy/devboards/db1300/Makefile create mode 100644 arch/mips/alchemy/devboards/db1300/board_setup.c create mode 100644 arch/mips/include/asm/mach-au1x00/au13xx.h create mode 100644 arch/mips/include/asm/mach-au1x00/dev_boards.h create mode 100644 arch/mips/include/asm/mips-boards/db1300.h diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 21b00e9..15e1577 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -255,6 +255,12 @@ core-$(CONFIG_MIPS_DB1200) += arch/mips/alchemy/devboards/ cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000 +# RMI Alchemy DBAu1300 development board +# +core-$(CONFIG_MIPS_DB1300) += arch/mips/alchemy/devboards/ +cflags-$(CONFIG_MIPS_DB1300) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 +load-$(CONFIG_MIPS_DB1300) += 0xffffffff80100000 + # # AMD Alchemy Bosporus eval board # diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 7f8ef13..50d426d 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -53,6 +53,12 @@ config MIPS_DB1550 select MIPS_DISABLE_OBSOLETE_IDE select SYS_SUPPORTS_LITTLE_ENDIAN +config MIPS_DB1300 + bool "Alchemy DBAu1300 Development Board" + select SOC_AU13XX + select DMA_COHERENT + select SYS_SUPPORTS_LITTLE_ENDIAN + config MIPS_MIRAGE bool "Alchemy Mirage board" select DMA_NONCOHERENT diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index 730f9f2..0d2d224 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_MIPS_PB1550) += pb1550/ obj-$(CONFIG_MIPS_DB1000) += db1x00/ obj-$(CONFIG_MIPS_DB1100) += db1x00/ obj-$(CONFIG_MIPS_DB1200) += pb1200/ +obj-$(CONFIG_MIPS_DB1300) += db1300/ obj-$(CONFIG_MIPS_DB1500) += db1x00/ obj-$(CONFIG_MIPS_DB1550) += db1x00/ obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/ diff --git a/arch/mips/alchemy/devboards/db1300/Makefile b/arch/mips/alchemy/devboards/db1300/Makefile new file mode 100644 index 0000000..edaff49 --- /dev/null +++ b/arch/mips/alchemy/devboards/db1300/Makefile @@ -0,0 +1,6 @@ +# +# Copyright 2008 RMI Corporation. All rights reserved. +# Author: Kevin Hickey <khickey@rmicorp.com> +# + +obj-y := board_setup.o mmc.o diff --git a/arch/mips/alchemy/devboards/db1300/board_setup.c b/arch/mips/alchemy/devboards/db1300/board_setup.c new file mode 100644 index 0000000..1fdec7d --- /dev/null +++ b/arch/mips/alchemy/devboards/db1300/board_setup.c @@ -0,0 +1,107 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey <khickey@rmicorp.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <linux/init.h> +#include <linux/kernel.h> /* for printk */ + +#include <prom.h> +#include <au1xxx.h> +#include <asm/mach-au1x00/dev_boards.h> + +#define DB1300_SYSTEM_TYPE_STRING "RMI DBAu1300 Development Board" + +struct bcsr_regs *const bcsr = + (struct bcsr_regs *)(DB1300_BCSR_REGS_PHYS_ADDR + KSEG1); + +extern void (*board_irq_dispatch)(unsigned int); + +/* + * Called by plat_irq_dispatch to do board-specific things (i.e. display the + * interrupt on a hex output). This should *not* be used for board-specific + * interrupt handling; for that register a new interrupt handler as a device + * driver would do. + */ +void db1300_board_irq_dispatch(unsigned int irq) +{ + if (irq != AU1300_IRQ_RTCMATCH_2) + db_set_hex((u8)irq); +} + +void __init board_setup(void) +{ + char *argptr = NULL; + + printk(KERN_INFO DB1300_SYSTEM_TYPE_STRING "\n"); + + /* + * Add some text to the command line to point the au1200fb driver to + * the board switch. + */ + argptr = prom_getcmdline(); + strcat(argptr, "console=ttyS0,115200 video=au1200fb:panel:bs"); + + /* + * Enable VBUS to the USB Host port + */ + au_set_bits_16(BCSR_RESETS_USB_HOST, &bcsr->resets); + + board_irq_dispatch = db1300_board_irq_dispatch; +} + +void board_reset(void) +{ + /* KH: TODO - write board_reset() */ +} + +const char *get_system_type(void) +{ + return DB1300_SYSTEM_TYPE_STRING; +} + +/* + * Board specific functions for the Au1200 Framebuffer driver + */ + +int board_au1200fb_panel(void) +{ + u16 switches = (au_ioread16(&db_bcsr->switches) & 0x0f00) >> 8; + + printk(KERN_INFO "Returning LCD switch setting %d\n", switches); + return switches; +} + +int board_au1200fb_panel_init(void) +{ + /* Apply power */ + au_set_bits_16(0x7, &db_bcsr->board); + return 0; +} + +int board_au1200fb_panel_shutdown(void) +{ + /* Remove power */ + au_clear_bits_16(0x7, &db_bcsr->board); + return 0; +} diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index c018727..e3528a7 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -33,9 +33,9 @@ #define PRID_COMP_TOSHIBA 0x070000 #define PRID_COMP_LSI 0x080000 #define PRID_COMP_LEXRA 0x0b0000 +#define PRID_COMP_RMI 0x0c0000 #define PRID_COMP_CAVIUM 0x0d0000 - /* * Assigned values for the product ID register. In order to detect a * certain CPU type exactly eventually additional registers may need to @@ -115,9 +115,13 @@ #define PRID_IMP_BCM3302 0x9000 /* - * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM + * These are the PRID's for when 23:16 == PRID_COMP_RMI */ +#define PRID_IMP_AU13XX 0x8000 +/* + * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM + */ #define PRID_IMP_CAVIUM_CN38XX 0x0000 #define PRID_IMP_CAVIUM_CN31XX 0x0100 #define PRID_IMP_CAVIUM_CN30XX 0x0200 @@ -210,7 +214,7 @@ enum cpu_type_enum { */ CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500, - CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710, + CPU_AU1550, CPU_AU13XX, CPU_PR4450, CPU_BCM3302, CPU_BCM4710, /* * MIPS64 class processors diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 62f91f5..c7fe356 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -6,6 +6,9 @@ * Copyright 2000-2001, 2006-2008 MontaVista Software Inc. * Author: MontaVista Software, Inc. <source@mvista.com> * + * Copyright 2008 RMI Corporation + * Author: Kevin Hickey <khickey@rmicorp.com> + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your @@ -43,6 +46,8 @@ #include <linux/io.h> #include <linux/irq.h> +#include <au13xx.h> + /* cpu pipeline flush */ void static inline au_sync(void) { @@ -130,6 +135,46 @@ static inline int au1xxx_cpu_needs_config_od(void) return 0; } +void static inline au_iowrite16(u16 val, volatile u16 *reg) +{ + *reg = val; +} + +static inline u16 au_ioread16(volatile u16 *reg) +{ + return *reg; +} + +void static inline au_iowrite32(u32 val, volatile u32 *reg) +{ + *reg = val; +} + +static inline u32 au_ioread32(volatile u32 *reg) +{ + return *reg; +} + +static inline void au_set_bits_16(u16 mask, volatile u16 *reg) +{ + au_iowrite16((au_ioread16(reg) | mask), reg); +} + +static inline void au_clear_bits_16(u16 mask, volatile u16 *reg) +{ + au_iowrite16((au_ioread16(reg) & ~mask), reg); +} + +static inline void au_set_bits_32(u32 mask, volatile u32 *reg) +{ + au_iowrite32((au_ioread32(reg) | mask), reg); +} + +static inline void au_clear_bits_32(u32 mask, volatile u32 *reg) +{ + au_iowrite32((au_ioread32(reg) & ~mask), reg); +} + /* arch/mips/au1000/common/clocks.c */ extern void set_au1x00_speed(unsigned int new_freq); extern unsigned int get_au1x00_speed(void); diff --git a/arch/mips/include/asm/mach-au1x00/au13xx.h b/arch/mips/include/asm/mach-au1x00/au13xx.h new file mode 100644 index 0000000..ea05234 --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/au13xx.h @@ -0,0 +1,201 @@ +/* + * Copyright 2008 RMI Corporation + * Author: Kevin Hickey <khickey@rmicorp.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _AU13XX_H +#define _AU13XX_H + +#ifdef CONFIG_SOC_AU13XX +#include <asm/addrspace.h> + +#define UART0_ADDR 0xB0100000 +#define UART1_ADDR 0xB0101000 +#define UART2_ADDR 0xB0102000 +#define UART3_ADDR 0xB0103000 + +#define GPIO_INT_CTRLR_BASE 0x10200000 +/* + * Linux uses IRQ 0-7 for the 8 causes. That means that all of our channel + * bits need to be offset by 8 either when passed to do_IRQ or when received + * through the irq_chip calls + * + * KH: TODO - This is duplicated from gpio_int.h Is that the right thing to do? + */ +#define GPINT_LINUX_IRQ_OFFSET 8 + +#define AU1300_IRQ_UART1 17 +#define AU1300_IRQ_UART2 25 +#define AU1300_IRQ_UART3 27 +#define AU1300_IRQ_SD1 32 +#define AU1300_IRQ_SD2 38 +#define AU1300_IRQ_PSC0 48 +#define AU1300_IRQ_PSC1 52 +#define AU1300_IRQ_PSC2 56 +#define AU1300_IRQ_PSC3 60 +#define AU1300_IRQ_NAND 62 +#define AU1300_IRQ_DDMA 75 +#define AU1300_IRQ_GPU 78 +#define AU1300_IRQ_MPU 77 +#define AU1300_IRQ_MMU 76 +#define AU1300_IRQ_UDMA 79 +#define AU1300_IRQ_TOY_TICK 80 +#define AU1300_IRQ_TOYMATCH_0 81 +#define AU1300_IRQ_TOYMATCH_1 82 +#define AU1300_IRQ_TOYMATCH_2 83 +#define AU1300_IRQ_RTC_TICK 84 +#define AU1300_IRQ_RTCMATCH_0 85 +#define AU1300_IRQ_RTCMATCH_1 86 +#define AU1300_IRQ_RTCMATCH_2 87 +#define AU1300_IRQ_UART0 88 +#define AU1300_IRQ_SD0 89 +#define AU1300_IRQ_USB 90 +#define AU1300_IRQ_LCD 91 +#define AU1300_IRQ_BSA 94 +#define AU1300_IRQ_MPE 93 +#define AU1300_IRQ_ITE 92 +#define AU1300_IRQ_AES 95 +#define AU1300_IRQ_CIM 96 + +#define LCD_PHYS_ADDR 0x15000000 + +#define AU1200_LCD_INT (GPINT_LINUX_IRQ_OFFSET + AU1300_IRQ_LCD) +#define AU1000_RTC_MATCH2_INT (GPINT_LINUX_IRQ_OFFSET + AU1300_IRQ_RTCMATCH_2) + +#define SD0_PHYS_ADDR 0x10600000 +#define SD1_PHYS_ADDR 0x10601000 + + +#define USB_BASE_PHYS_ADDR 0x14021000 +#define USB_EHCI_BASE 0x14020000 +#define USB_EHCI_LEN 0x400 +#define USB_OHCI_BASE 0x14020800 +#define USB_OHCI_LEN 0x400 +#define USB_UOC_BASE 0x14022000 +#define USB_UOC_LEN 0x20 +#define USB_UDC_BASE 0x14022000 +#define USB_UDC_LEN 0x2000 + +struct au13xx_usb_regs { + u32 dwc_ctrl1; + u32 dwc_ctrl2; + u32 reserved0[2]; + + u32 vbus_timer; + u32 sbus_ctrl; + u32 msr_err; + u32 dwc_ctrl3; + + u32 dwc_ctrl4; + u32 reserved1; + u32 otg_status; + u32 dwc_ctrl5; + + u32 dwc_ctrl6; + u32 dwc_ctrl7; + + u32 reserved2[(0xC0-0x38)/4]; + + u32 phy_status; + u32 intr_status; + u32 intr_enable; + +}; + +#define USB_DWC_CTRL1_OTGD (1<<2) +#define USB_DWC_CTRL1_HSTRS (1<<1) +#define USB_DWC_CTRL1_DCRS (1<<0) + +#define USB_DWC_CTRL2_HTBSE1 (1<<11) +#define USB_DWC_CTRL2_HTBSE0 (1<<10) +#define USB_DWC_CTRL2_LTBSE1 (1<<9) +#define USB_DWC_CTRL2_LTBSE0 (1<<8) +#define USB_DWC_CTRL2_LPBKE1 (1<<5) +#define USB_DWC_CTRL2_LPBKE0 (1<<4) +#define USB_DWC_CTRL2_VBUSD (1<<3) +#define USB_DWC_CTRL2_PH1RS (1<<2) +#define USB_DWC_CTRL2_PHY0RS (1<<1) +#define USB_DWC_CTRL2_PHYRS (1<<0) + +#define USB_VBUS_TIMER(n) (n) + +#define USB_SBUS_CTRL_SBCA (1<<2) +#define USB_SBUS_CTRL_HWSZ (1<<1) +#define USB_SBUS_CTRL_BSZ (1<<0) + +#define USB_MSR_ERR_ILLBM (1<<18) +#define USB_MSR_ERR_ILLBRST (1<<17) +#define USB_MSR_ERR_UADDRSTS (1<<16) +#define USB_MSR_ERR_BMMSK (1<<2) +#define USB_MSR_ERR_BRSTMSK (1<<1) +#define USB_MSR_ERR_UADMK (1<<0) + +#define USB_DWC_CTRL3_VATEST_EN (1<<20) +#define USB_DWC_CTRL3_OHC1_CLKEN (1<<19) +#define USB_DWC_CTRL3_OHC0_CLKEN (1<<18) +#define USB_DWC_CTRL3_EHC_CLKEN (1<<17) +#define USB_DWC_CTRL3_OTG_CLKEN (1<<16) +#define USB_DWC_CTRL3_OHCI_SUSP (1<<3) +#define USB_DWC_CTRL3_VBUS_VALID_PORT1 (1<<2) +#define USB_DWC_CTRL3_VBUS_VALID_PORT0 (1<<1) +#define USB_DWC_CTRL3_VBUS_VALID_SEL (1<<0) + +#define USB_DWC_CTRL4_USB_MODE (1<<16) +#define USB_DWC_CTRL4_AHB_CLKDIV(n) ((n&0xF)<<0) + +#define USB_OTG_STATUS_IDPULLUP (1<<8) +#define USB_OTG_STATUS_IDDIG (1<<7) +#define USB_OTG_STATUS_DISCHRGVBUS (1<<6) +#define USB_OTG_STATUS_CHRGVBUS (1<<5) +#define USB_OTG_STATUS_DRVVBUS (1<<4) +#define USB_OTG_STATUS_SESSIONEND (1<<3) +#define USB_OTG_STATUS_VBUSVALID (1<<2) +#define USB_OTG_STATUS_BVALID (1<<1) +#define USB_OTG_STATUS_AVALID (1<<0) + +#define USB_DWC_CTRL5_REFCLK_DIV(n) ((n&3)<<18) +#define USB_DWC_CTRL5_REFCLK_EN(n) ((n&3)<<16) +#define USB_DWC_CTRL5_SIDDQ (1<<1) +#define USB_DWC_CTRL5_COMMONONN (1<<0) + +#define USB_DWC_CTRL6_DMPULLDOWN_PORT1 (1<<3) +#define USB_DWC_CTRL6_DPPULLDOWN_PORT1 (1<<2) +#define USB_DWC_CTRL6_DMPULLDOWN_PORT2 (1<<1) +#define USB_DWC_CTRL6_DPPULLDOWN_PORT2 (1<<0) + +#define USB_DWC_CTRL7_OHC_STARTCLK (1<<0) + +#define USB_PHY_STATUS_VBUS (1<<0) + +#define USB_INTR_S2A (1<<6) +#define USB_INTR_FORCE (1<<5) +#define USB_INTR_PHY (1<<4) +#define USB_INTR_DEVICE (1<<3) +#define USB_INTR_EHCI (1<<2) +#define USB_INTR_OHCI1 (1<<1) +#define USB_INTR_OHCI0 (1<<0) + +#define AU1000_USB_HOST_INT (AU1300_IRQ_USB + GPINT_LINUX_IRQ_OFFSET) + +#endif /* CONFIG_SOC_AU13XX */ +#endif /* _AU13XX_H */ diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx.h b/arch/mips/include/asm/mach-au1x00/au1xxx.h index 1b36550..9a6d9f1 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx.h @@ -38,6 +38,9 @@ #elif defined(CONFIG_MIPS_DB1200) #include <asm/mach-db1x00/db1200.h> +#elif defined(CONFIG_MIPS_DB1300) +#include <asm/mips-boards/db1300.h> + #endif #endif /* _AU1XXX_H_ */ diff --git a/arch/mips/include/asm/mach-au1x00/dev_boards.h b/arch/mips/include/asm/mach-au1x00/dev_boards.h new file mode 100644 index 0000000..27bca17 --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/dev_boards.h @@ -0,0 +1,44 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey <khickey@rmicorp.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _AU_DEV_BOARDS_H +#define _AU_DEV_BOARDS_H + +#ifdef CONFIG_MIPS_DB1300 +#include <asm/mips-boards/db1300.h> +#endif + +#ifdef CONFIG_MIPS_DB1200 +#include <asm/mach-db1x00/db1200.h> +#endif + +void db_set_hex(u8 val); + +/* + * 2 dots use 2 bits + */ +void db_set_hex_dots(u8 val); + +#endif /* _AU_DEV_BOARDS_H */ diff --git a/arch/mips/include/asm/mips-boards/db1300.h b/arch/mips/include/asm/mips-boards/db1300.h new file mode 100644 index 0000000..122432a --- /dev/null +++ b/arch/mips/include/asm/mips-boards/db1300.h @@ -0,0 +1,121 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey <khickey@rmicorp.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef ASM_DB1300_H +#define ASM_DB1300_H +#ifdef CONFIG_MIPS_DB1300 +#include <asm/addrspace.h> +#include <asm/mach-au1x00/au13xx.h> + +struct db1300_hex_regs { + u16 hex; /* Write 8-bit value here */ + u16 reserved; + u16 blank; /* Write 11b to blank */ +}; + + +#define DB1300_HEX_REGS_PHYS_ADDR 0x19C00000 + +/* For alchemy/dev_boards/leds.c */ +typedef struct db1300_hex_regs hex_regs; +#define HEX_REGS_KSEG1_ADDR (DB1300_HEX_REGS_PHYS_ADDR + KSEG1) + +struct bcsr_regs { + /*00*/ u16 whoami; + u16 reserved0; + /*04*/ u16 status; + u16 reserved1; + /*08*/ u16 switches; + u16 reserved2; + /*0C*/ u16 resets; + u16 reserved3; + + /*10*/ u16 pcmcia; + u16 reserved4; + /*14*/ u16 board; + u16 reserved5; + /*18*/ u16 disk_leds; + u16 reserved6; + /*1C*/ u16 system; + u16 reserved7; + + /*20*/ u16 intclr; + u16 reserved8; + /*24*/ u16 intset; + u16 reserved9; + /*28*/ u16 intclr_mask; + u16 reserved10; + /*2C*/ u16 intset_mask; + u16 reserved11; + + /*30*/ u16 sig_status; + u16 reserved12; + /*34*/ u16 int_status; + u16 reserved13; + /*38*/ u16 reserved14; + u16 reserved15; + /*3C*/ u16 reserved16; + u16 reserved17; +}; + +#define DB1300_BCSR_REGS_PHYS_ADDR 0x19800000 +#define BCSR_REGS_KSEG1_ADDR (KSEG1 + DB1300_BCSR_REGS_PHYS_ADDR) + +static volatile struct bcsr_regs *const db_bcsr = + (struct bcsr_regs *)(DB1300_BCSR_REGS_PHYS_ADDR + KSEG1); + +#define BCSR_STATUS_SD1_WP (1<<10) +#define BCSR_INT_SD1_INSERT (1<<12) + +#define BCSR_RESETS_USB_OTG 0x4000 +#define BCSR_RESETS_USB_HOST 0x8000 + +#define CASCADE_IRQ_MIN 129 + +enum db1300_cascade_irqs { + DB1300_IDE_IRQ = CASCADE_IRQ_MIN, + DB1300_ETHERNET_IRQ, + DB1300_AC97_IRQ, + DB1300_AC97_PEN_IRQ, +}; + +#define CASCADE_IRQ_MAX DB1300_AC97_PEN_IRQ + +#define CASCADE_IRQ (5 + GPINT_LINUX_IRQ_OFFSET) +#define CASCADE_IRQ_TYPE_STRING "DB1300 Cascade" + +/* + * Defines for au1xxx-ide + * See the CPLD/BCSR datasheet for details + */ +#define IDE_PHYS_ADDR 0x18800000 +#define IDE_REG_SHIFT 5 +#define IDE_INT DB1300_IDE_IRQ +#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 +#define IDE_RQSIZE 128 +#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT) + + +#endif /* CONFIG_MIPS_DB1300 */ +#endif /* ASM_DB1300_H */ diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index a7162a4..03e0ae7 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -189,6 +189,7 @@ void __init check_wait(void) case CPU_AU1200: case CPU_AU1210: case CPU_AU1250: + case CPU_AU13XX: cpu_wait = au1k_wait; break; case CPU_20KC: @@ -819,6 +820,20 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) } } +static inline void cpu_probe_rmi(struct cpuinfo_mips *c, unsigned int cpu) +{ + decode_configs(c); + switch (c->processor_id & 0xff00) { + case PRID_IMP_AU13XX: + c->cputype = CPU_AU13XX; + __cpu_name[cpu] = "Au13xx"; + break; + default: + panic("Unknown RMI Core!\n"); + break; + } +} + static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); @@ -936,6 +951,11 @@ __cpuinit void cpu_probe(void) case PRID_COMP_CAVIUM: cpu_probe_cavium(c, cpu); break; + case PRID_COMP_RMI: + cpu_probe_rmi(c, cpu); + break; + default: + c->cputype = CPU_UNKNOWN; } BUG_ON(!__cpu_name[cpu]); diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index c43f4b2..2b4736a 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1033,6 +1033,7 @@ static void __cpuinit probe_pcache(void) case CPU_AU1200: case CPU_AU1210: case CPU_AU1250: + case CPU_AU13XX: c->icache.flags |= MIPS_CACHE_IC_F_DC; break; } diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 4294203..ee5e2de 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -299,6 +299,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_AU1200: case CPU_AU1210: case CPU_AU1250: + case CPU_AU13XX: case CPU_PR4450: uasm_i_nop(p); tlbw(p); -- 1.5.4.3 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 2/5] Alchemy: Au1300 new interrupt controller 2009-04-08 23:36 ` [PATCH v3 1/5] Alchemy: Initial Au1300 and DBAu1300 support Kevin Hickey @ 2009-04-08 23:36 ` Kevin Hickey 2009-04-08 23:36 ` [PATCH v3 3/5] Alchemy: Au1300/DB1300 UART support Kevin Hickey 2009-04-09 10:07 ` [PATCH v3 2/5] Alchemy: Au1300 new interrupt controller Manuel Lauss 0 siblings, 2 replies; 10+ messages in thread From: Kevin Hickey @ 2009-04-08 23:36 UTC (permalink / raw) To: linux-mips, ralf; +Cc: Kevin Hickey The Au1300 has a new interrupt controller (relative to the rest of the Alchemy line). The differences were great enough to justify adding a whole new module. Included in this patch is the new interrupt controller, a new implementation of the cascade interrupt controller on the DB1300 board and some code to drive LEDs on the DB1300 that is used by the interrupt controller. Since the cascade interrupt controller is virtually indentical (with the exception of some constants) between the DB1300 and DB1200, a future optimization may be to use the same code for both boards. Signed-off-by: Kevin Hickey <khickey@rmicorp.com> --- arch/mips/alchemy/Kconfig | 16 ++ arch/mips/alchemy/common/Makefile | 5 +- arch/mips/alchemy/common/gpio_int.c | 265 ++++++++++++++++++++++++++ arch/mips/alchemy/devboards/Makefile | 5 + arch/mips/alchemy/devboards/cascade_irq.c | 142 ++++++++++++++ arch/mips/alchemy/devboards/leds.c | 58 ++++++ arch/mips/include/asm/mach-au1x00/gpio_int.h | 237 +++++++++++++++++++++++ arch/mips/include/asm/mach-au1x00/irq.h | 34 ++++ 8 files changed, 761 insertions(+), 1 deletions(-) create mode 100644 arch/mips/alchemy/common/gpio_int.c create mode 100644 arch/mips/alchemy/devboards/cascade_irq.c create mode 100644 arch/mips/alchemy/devboards/leds.c create mode 100644 arch/mips/include/asm/mach-au1x00/gpio_int.h create mode 100644 arch/mips/include/asm/mach-au1x00/irq.h diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 50d426d..2e189c2 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -114,22 +114,32 @@ endchoice config SOC_AU1000 bool select SOC_AU1X00 + select AU_INT_CNTLR config SOC_AU1100 bool select SOC_AU1X00 + select AU_INT_CNTLR config SOC_AU1500 bool select SOC_AU1X00 + select AU_INT_CNTLR config SOC_AU1550 bool select SOC_AU1X00 + select AU_INT_CNTLR config SOC_AU1200 bool select SOC_AU1X00 + select AU_INT_CNTLR + +config SOC_AU13XX + bool + select SOC_AU1X00 + select AU_GPIO_INT_CNTLR config SOC_AU1X00 bool @@ -141,3 +151,9 @@ config SOC_AU1X00 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_APM_EMULATION select GENERIC_HARDIRQS_NO__DO_IRQ + +config AU_INT_CNTLR + bool + +config AU_GPIO_INT_CNTLR + bool diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile index d50d476..faa6afd 100644 --- a/arch/mips/alchemy/common/Makefile +++ b/arch/mips/alchemy/common/Makefile @@ -5,10 +5,13 @@ # Makefile for the Alchemy Au1xx0 CPUs, generic files. # -obj-y += prom.o irq.o puts.o time.o reset.o \ +obj-y += prom.o puts.o time.o reset.o \ clocks.o platform.o power.o setup.o \ sleeper.o dma.o dbdma.o gpio.o obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_AU_GPIO_INT_CNTLR) += gpio_int.o +obj-$(CONFIG_AU_INT_CNTLR) += irq.o + EXTRA_CFLAGS += -Werror diff --git a/arch/mips/alchemy/common/gpio_int.c b/arch/mips/alchemy/common/gpio_int.c new file mode 100644 index 0000000..e6ae8a7 --- /dev/null +++ b/arch/mips/alchemy/common/gpio_int.c @@ -0,0 +1,265 @@ +/* + * Copyright 2008 RMI Corporation + * Author: Kevin Hickey <khickey@rmicorp.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include <linux/irq.h> +#include <linux/init.h> +#include <linux/interrupt.h> /* For functions called by do_IRQ */ +#include <asm/irq_cpu.h> + +#include <asm/mach-au1x00/gpio_int.h> +#include <asm/mach-au1x00/au1000.h> + +struct gpio_int_regs *const gpio_int = + (struct gpio_int_regs *)(GPIO_INT_CTRLR_BASE + KSEG1); + +static struct gpio_int_cfg __initdata basic_irqs[]; + +void (*board_irq_dispatch)(int) = NULL; + +#ifdef CONFIG_SOC_AU13XX +static struct gpio_int_cfg __initdata basic_irqs[] = { + { AU1300_IRQ_DDMA, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_RTC_TICK, 1, RISING, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_TOY_TICK, 1, RISING, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_LCD, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_UART1, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_UART1, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_UART2, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_UART3, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_SD1, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_SD2, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_USB, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_BSA, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_MPE, 1, RISING, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_ITE, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_RTCMATCH_1, 1, RISING, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_RTCMATCH_1, 1, RISING, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_RTCMATCH_2, 0, RISING, HW_INT_0, DEV_CTRL }, + + { AU1300_IRQ_TOYMATCH_1, 1, RISING, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_TOYMATCH_1, 1, RISING, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_TOYMATCH_2, 1, RISING, HW_INT_1, DEV_CTRL }, + + + /* KH: TODO - Move this to the board file. */ + { 5, 0, LEVEL_HIGH, HW_INT_0, GPIO_IN }, +}; + +/* + * KH: TODO - Consider moving to board specific location... + */ +static struct gpio_int_cfg __initdata basic_gpios[] = { + { 32, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 33, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 34, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 35, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 36, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 37, 0, DISABLED, HW_INT_0, DEV_CTRL }, +}; +#endif + +int __initdata nr_basic_irqs = ARRAY_SIZE(basic_irqs); + +/* + **************************************************************************** + * Functions and delcaration for irq_chip + **************************************************************************** + */ +void gpio_int_ack(unsigned int irq) +{ + u32 intr = irq - GPINT_LINUX_IRQ_OFFSET; + u32 bank = GPINT_BANK_FROM_INT(intr); + u32 bit = GPINT_BIT_FROM_INT(bank, intr); + + au_iowrite32(bit, &gpio_int->int_pend[bank]); +} + +void gpio_int_mask(unsigned int irq) +{ + u32 intr = irq - GPINT_LINUX_IRQ_OFFSET; + u32 bank = GPINT_BANK_FROM_INT(intr); + u32 bit = GPINT_BIT_FROM_INT(bank, intr); + + au_iowrite32(bit, &gpio_int->int_maskclr[bank]); +} + +void gpio_int_unmask(unsigned int irq) +{ + u32 intr = irq - GPINT_LINUX_IRQ_OFFSET; + u32 bank = GPINT_BANK_FROM_INT(intr); + u32 bit = GPINT_BIT_FROM_INT(bank, intr); + + au_iowrite32(bit, &gpio_int->int_mask[bank]); +} + +void gpio_int_mask_ack(unsigned int irq) +{ + u32 intr = irq - GPINT_LINUX_IRQ_OFFSET; + u32 bank = GPINT_BANK_FROM_INT(intr); + u32 bit = GPINT_BIT_FROM_INT(bank, intr); + + au_iowrite32(bit, &gpio_int->int_maskclr[bank]); + au_iowrite32(bit, &gpio_int->int_pend[bank]); +} + +static struct irq_chip gpio_int_irq_type = { + .name = "Au GPIO/INT", + .ack = gpio_int_ack, + .mask = gpio_int_mask, + .unmask = gpio_int_unmask, + .mask_ack = gpio_int_mask_ack +}; +/*****************************************************************************/ + +void set_pin_cfg(const struct gpio_int_cfg *cfg) +{ + u32 tmp; + tmp = GPINT_PINCTL_N(cfg->pinctl); + tmp |= GPINT_INTLINE_N(cfg->intline); + tmp |= GPINT_INTCFG_N(cfg->intcfg); + tmp |= cfg->intwake ? GPINT_INTWAKE_ENABLE : 0; + au_iowrite32(tmp, &gpio_int->gp_int[cfg->number]); +} + +void set_gpio(u8 gpio, u8 value) +{ + u32 bank = GPINT_BANK_FROM_GPIO(gpio); + u32 bit = GPINT_BIT_FROM_GPIO(bank, gpio); + + if (value == 0) + au_iowrite32(1 << bit, &gpio_int->pin_valclr[bank]); + else + au_iowrite32(1 << bit, &gpio_int->pin_val[bank]); +} + +u8 get_gpio(u8 gpio) +{ + u32 bank = GPINT_BANK_FROM_GPIO(gpio); + u32 bit = GPINT_BIT_FROM_GPIO(bank, gpio); + u32 tmp; + + tmp = au_ioread32(&gpio_int->pin_val[bank]); + return tmp >> bit; +} + + +void __init arch_init_irq(void) +{ + int i; + + /* + * Initialize the basic MIPS interrupt components. + */ + mips_cpu_irq_init(); + + for (i = 0; i < GPINT_NUM_BANKS; ++i) + gpio_int->int_maskclr[i] = ~0UL; + + + for (i = 0; i < ARRAY_SIZE(basic_gpios); ++i) + set_pin_cfg(&basic_gpios[i]); + + for (i = 0; i < nr_basic_irqs; ++i) { + printk(KERN_DEBUG "Initializing IRQ %d\n", + basic_irqs[i].number); + set_pin_cfg(&basic_irqs[i]); + if (basic_irqs[i].intcfg == LEVEL_LOW) + set_irq_chip_and_handler_name( + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, + &gpio_int_irq_type, + handle_level_irq, + "lowlevel"); + else if (basic_irqs[i].intcfg == LEVEL_HIGH) + set_irq_chip_and_handler_name( + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, + &gpio_int_irq_type, + handle_level_irq, + "highlevel"); + else if (basic_irqs[i].intcfg == FALLING) + set_irq_chip_and_handler_name( + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, + &gpio_int_irq_type, + handle_edge_irq, + "fallingedge"); + else if (basic_irqs[i].intcfg == RISING) + set_irq_chip_and_handler_name( + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, + &gpio_int_irq_type, + handle_edge_irq, + "risingedge"); + else if (basic_irqs[i].intcfg == ANY_CHANGE) + set_irq_chip_and_handler_name( + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, + &gpio_int_irq_type, + handle_edge_irq, + "bothedge"); + else + set_irq_chip( + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, + &gpio_int_irq_type); + } + + set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4); + + board_init_irq(); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int intr; + u32 bank; + u32 reg_msk; + unsigned int pending = read_c0_status() & read_c0_cause(); + /* + * C0 timer tick + */ + if (pending & CAUSEF_IP7) + do_IRQ(MIPS_CPU_IRQ_BASE + 7); + else if (pending & (CAUSEF_IP2 | CAUSEF_IP3)) { + intr = au_ioread32(&gpio_int->pri_enc); + bank = GPINT_BANK_FROM_INT(intr); + reg_msk = GPINT_BIT_FROM_INT(bank, intr); + + if (intr != 127) { + if (board_irq_dispatch) + board_irq_dispatch(intr); + + do_IRQ(GPINT_LINUX_IRQ_OFFSET + intr); + } + } else { + printk(KERN_WARNING + "ALCHEMY GPIO_INT: Unexpected cause was set. %08x\n", + pending); + spurious_interrupt(); + } + +} + diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index 0d2d224..8cce4d0 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -17,3 +17,8 @@ obj-$(CONFIG_MIPS_DB1500) += db1x00/ obj-$(CONFIG_MIPS_DB1550) += db1x00/ obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/ obj-$(CONFIG_MIPS_MIRAGE) += db1x00/ + +# These two files are used only by DB1300 today but will be used by DB1200 and +# possibly others in the future. +obj-$(CONFIG_MIPS_DB1300) += cascade_irq.o +obj-$(CONFIG_MIPS_DB1300) += leds.o diff --git a/arch/mips/alchemy/devboards/cascade_irq.c b/arch/mips/alchemy/devboards/cascade_irq.c new file mode 100644 index 0000000..6d0a965 --- /dev/null +++ b/arch/mips/alchemy/devboards/cascade_irq.c @@ -0,0 +1,142 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey <khickey@rmicorp.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/mutex.h> +#include <linux/semaphore.h> +#include <asm/mach-au1x00/au1000.h> +#include <asm/mips-boards/db1300.h> + +#include <asm/mach-au1x00/dev_boards.h> + +/* + * The following must be declared/defined in an included file: + * - volatile struct bcsr_regs (declared) + * (which much include fields int_status, intset_mask, intclr_mask, intset, + * and intclr) + * - volatile struct bcsr_regs *const bcsr (defined) + * - CASCADE_IRQ_MIN + * - CASCADE_IRQ_MAX + * - CASCADE_IRQ_TYPE_STRING + * - CASCADE_IRQ (System IRQ to which the cascade is connected) + */ + +void __init board_init_irq(void); + +irqreturn_t cascade_handler(int irq, void *dev_id) +{ + u16 int_status = au_ioread16(&db_bcsr->int_status); + int irq_in_service; + + au_iowrite16(int_status, &db_bcsr->int_status); + for ( ; int_status; int_status &= int_status - 1) { + irq_in_service = CASCADE_IRQ_MIN + __ffs(int_status); + db_set_hex((u8)(irq_in_service)); + do_IRQ(irq_in_service); + } + + return IRQ_RETVAL(1); +} + +DEFINE_MUTEX(cascade_use_count_mutex); +static int cascade_use_count; + +static void cascade_mask(unsigned int irq) +{ + au_iowrite16(1 << (irq - CASCADE_IRQ_MIN), &db_bcsr->intclr_mask); +} + +static void cascade_unmask(unsigned int irq) +{ + au_iowrite16(1 << (irq - CASCADE_IRQ_MIN), &db_bcsr->intset_mask); +} + +static void cascade_enable(unsigned int irq) +{ + au_iowrite16(1 << (irq - CASCADE_IRQ_MIN), &db_bcsr->intset); + cascade_unmask(irq); +} + +static void cascade_disable(unsigned int irq) +{ + au_iowrite16(1 << (irq - CASCADE_IRQ_MIN), &db_bcsr->intclr); + cascade_mask(irq); +} + + +static unsigned int cascade_startup(unsigned int irq) +{ + int retval = 0; + + mutex_lock(&cascade_use_count_mutex); + ++cascade_use_count; + if (cascade_use_count == 1) + retval = request_irq(CASCADE_IRQ, + &cascade_handler, 0, "Cascade", + &cascade_handler); + mutex_unlock(&cascade_use_count_mutex); + + cascade_enable(irq); + cascade_unmask(irq); + + return retval; +} + +static void cascade_shutdown(unsigned int irq) +{ + cascade_mask(irq); + cascade_disable(irq); + + mutex_lock(&cascade_use_count_mutex); + --cascade_use_count; + if (cascade_use_count == 0) + free_irq(CASCADE_IRQ, &cascade_handler); + mutex_unlock(&cascade_use_count_mutex); +} + +static struct irq_chip cascade_irq_type = { + .name = CASCADE_IRQ_TYPE_STRING, + .startup = cascade_startup, + .shutdown = cascade_shutdown, + .mask = cascade_mask, + .enable = cascade_enable, + .disable = cascade_disable, + .unmask = cascade_unmask, + .mask_ack = cascade_mask +}; + +void __init board_init_irq(void) +{ + int irq; + + for (irq = CASCADE_IRQ_MIN; + irq < CASCADE_IRQ_MAX; ++irq) { + printk(KERN_DEBUG "Initializing IRQ %d\n", irq); + set_irq_chip_and_handler(irq, &cascade_irq_type, + handle_level_irq); + cascade_disable(irq); + } +} diff --git a/arch/mips/alchemy/devboards/leds.c b/arch/mips/alchemy/devboards/leds.c new file mode 100644 index 0000000..75be345 --- /dev/null +++ b/arch/mips/alchemy/devboards/leds.c @@ -0,0 +1,58 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey <khickey@rmicorp.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <asm/mach-au1x00/au1000.h> +#include <asm/mach-au1x00/dev_boards.h> + +/* + * Requires the following to be defined in the board-specifc .h file: + * - HEX_REGS_KSEG1_ADDR + * - struct hex_regs with members: + * - hex (set the hex value) + * - BCSR_REGS_KSEG1_ADDR + * - struct bcsr_regs + */ + +static hex_regs *const hex = (hex_regs *)(HEX_REGS_KSEG1_ADDR); + +/* + * Takes a u8 because though the register is 16 bits, only 8 appear + */ +void db_set_hex(u8 val) +{ + au_iowrite16((u16)val, &hex->hex); +} + +/* + * 2 dots use the least significant 2 bits + * Setting a bit lights the LED (opposite of the register) + */ +void db_set_hex_dots(u8 val) +{ + u16 leds = au_ioread16(&db_bcsr->disk_leds); + leds |= 0x3; + leds &= (~(val & 0x3)); + au_iowrite16(leds, &db_bcsr->disk_leds); +} diff --git a/arch/mips/include/asm/mach-au1x00/gpio_int.h b/arch/mips/include/asm/mach-au1x00/gpio_int.h new file mode 100644 index 0000000..f1b11fa --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/gpio_int.h @@ -0,0 +1,237 @@ +/* + * Copyright 2008 RMI Corporation + * Author: Kevin Hickey <khickey@rmicorp.com> + * + * Defines and macros for the GPIO and Interrupt controller for Alchemy, + * introduced in the Au13xx series. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef _GPIO_INT_H +#define _GPIO_INT_H + +#include <linux/types.h> + +/* + * There are a total 128 'channels' defined by the Au13xx databook. However, + * this requires 4 sperate 32bit registers for programming. Each register is + * called a 'bank' for ease of use. + */ +#define GPINT_BANK0 0 +#define GPINT_BANK1 1 +#define GPINT_BANK2 2 +#define GPINT_BANK3 3 + +#define GPINT_NUM_BANKS 4 /* 0-3 */ +#define GPINT_MAX_BANK (GPINT_BANK3) + +#define GPINT_GPIO_PER_BANK 32 +#define GPINT_INTS_PER_BANK GPINT_GPIO_PER_BANK + +/* Total number of interrupts our architecture allows */ +#define GPINT_MAX_INTS (GPINT_NUM_BANKS*GPINT_INTS_PER_BANK) + +/* Current maximum supported GPIO/INTERRUPTs */ +#define GPINT_NUM_GPIO GPINT_MAX_INTS +#define GPINT_NUM_INTERRUPTS GPINT_MAX_INTS + +/* Starting GPIO/INTERRUPT for each bank */ +#define GPINT_BANK0_START 0 +#define GPINT_BANK1_START 32 +#define GPINT_BANK2_START 64 +#define GPINT_BANK3_START 96 + +/* divide by 32 to get bank */ +#define GPINT_BANK_FROM_GPIO(n) (n>>5) +#define GPINT_BANK_FROM_INT(n) GPINT_BANK_FROM_GPIO(n) +/* multiply by 32 to get base */ +#define GPINT_BIT_FROM_GPIO(b, n) (1<<(n-(b<<5))) +#define GPINT_BIT_FROM_INT(b, n) GPINT_BIT_FROM_GPIO(b, n) + +struct gpio_int_regs { + /* R/W1S */ + /* u32 pin_val0; 0x00 */ + /* u32 pin_val1; 0x04 */ + /* u32 pin_val2; 0x08 */ + /* u32 pin_val3; 0x0C */ + u32 pin_val[GPINT_NUM_BANKS]; + + /* W1C */ + /* u32 pin_valclr0 0x10 */ + /* u32 pin_valclr1; 0x14 */ + /* u32 pin_valclr2; 0x18 */ + /* u32 pin_valclr3; 0x1C */ + u32 pin_valclr[GPINT_NUM_BANKS]; + + /* R/W1C */ + /* u32 int_pend0; 0x20 */ + /* u32 int_pend1; 0x24 */ + /* u32 int_pend2; 0x28 */ + /* u32 int_pend3; 0x2c */ + u32 int_pend[GPINT_NUM_BANKS]; + + u32 pri_enc; /* 0x30 */ + u32 _resvd0[3]; /* 0x34-0x3c */ + + /* R/W1S */ + /* u32 int_mask0; 0x40 */ + /* u32 int_mask1; 0x44 */ + /* u32 int_mask2; 0x48 */ + /* u32 int_mask3; 0x4c */ + u32 int_mask[GPINT_NUM_BANKS]; + + /* W1C */ + /* u32 int_maskclr0; 0x50 */ + /* u32 int_maskclr1; 0x54 */ + /* u32 int_maskclr2; 0x58 */ + /* u32 int_maskclr3; 0x5C */ + u32 int_maskclr[GPINT_NUM_BANKS]; + + /* R/W */ + u32 dma_sel; /* 0x60 */ + u32 _resvd1[(0x80-0x64)/4]; /* 0x64-0x7C */ + + /* W */ + /* u32 dev_sel0; 0x80 */ + /* u32 dev_sel1; 0x84 */ + /* u32 dev_sel2; 0x88 */ + /* u32 dev_sel3; 0x8C */ + u32 dev_sel[GPINT_NUM_BANKS]; + + /* W */ + /* u32 dev_selclr0; 0x90 */ + /* u32 dev_selclr1; 0x94 */ + /* u32 dev_selclr2; 0x98 */ + /* u32 dev_selclr3; 0x9C */ + u32 dev_selclr[GPINT_NUM_BANKS]; + + /* R */ + /* u32 reset_val0; 0xA0 */ + /* u32 reset_val1; 0xA4 */ + /* u32 reset_val2; 0xA8 */ + /* u32 reset_val3; 0xAC */ + u32 reset_val[GPINT_NUM_BANKS]; + + /* 0xB0 - 0xFFC */ + u32 _resvd2[(0x1000-0xB0)/4]; + + /* R/W -- when interrupt mask is clear */ + /* R -- when interrupt mask is set */ + /* u32 gp_int0; 0x1000 */ + /* u32 gp_int1; 0x1004 */ + /* u32 gp_int2; 0x1008 */ + /* u32 gp_int2; 0x100C */ + /* u32 gp_intN; 0x1000 + (N*4) */ + u32 gp_int[GPINT_MAX_INTS]; +}; + +extern struct gpio_int_regs *const gpio_int; + +#define GPINT_DMASEL_DMA0 (0) +#define GPINT_DMASEL_DMA0_N(n) (((n)&0xFF)<<GPINT_DMASEL_DMA0) +#define GPINT_DMASEL_DMA1 (8) +#define GPINT_DMASEL_DMA1_N(n) (((n)&0xFF)<<GPINT_DMASEL_DMA1) + +#define GPINT_PINCTL (0) +#define GPINT_PINCTL_N(n) (((n)&0x3)<<GPINT_PINCTL) +#define GPINT_PINCTL_GPIOINPUT GPINT_PINCTL_N(0) +#define GPINT_PINCTL_INTERRUPT GPINT_PINCTL_N(1) +#define GPINT_PINCTL_GPIOOUT_0 GPINT_PINCTL_N(2) +#define GPINT_PINCTL_GPIOOUT_1 GPINT_PINCTL_N(3) + +#define GPINT_INTLINE (2) +#define GPINT_INTLINE_N(n) (((n)&0x3)<<GPINT_INTLINE) +#define GPINT_INTLINE_CPUINT_0 GPINT_INTLINE_N(0) +#define GPINT_INTLINE_CPUINT_1 GPINT_INTLINE_N(1) +#define GPINT_INTLINE_CPUINT_2 GPINT_INTLINE_N(2) +#define GPINT_INTLINE_CPUINT_3 GPINT_INTLINE_N(3) + +#define GPINT_INTCFG (4) +#define GPINT_INTCFG_N(n) (((n)&0x7)<<GPINT_INTCFG) +#define GPINT_INTCFG_DISABLE GPINT_INTCFG_N(0) +#define GPINT_INTCFG_LL GPINT_INTCFG_N(1) +#define GPINT_INTCFG_HL GPINT_INTCFG_N(2) +#define GPINT_INTCFG_FE GPINT_INTCFG_N(5) +#define GPINT_INTCFG_RE GPINT_INTCFG_N(6) +#define GPINT_INTCFG_CHANGE GPINT_INTCFG_N(7) + +#define GPINT_INTWAKE (7) +#define GPINT_INTWAKE_ENABLE ((1)<<GPINT_INTWAKE) + +/* GPIO */ +#define GPIO_N(N) (1 << (N)) + +/* + * Take caution when reordering or changing values; used directly in pin + * configuration register + */ +enum intcfg_vals { DISABLED = 0, LEVEL_LOW, LEVEL_HIGH, + FALLING = 5, RISING, ANY_CHANGE }; +enum intline_vals { HW_INT_0 = 0, HW_INT_1, HW_INT_2, HW_INT_3 }; +enum pinctl_vals { GPIO_IN = 0, DEV_CTRL, GPIO_OUT_0, GPIO_OUT_1 }; + +/* + * Defines the settings for a given interrupt "channel" + */ +struct gpio_int_cfg { + int number; + bool intwake; + enum intcfg_vals intcfg; + enum intline_vals intline; + enum pinctl_vals pinctl; +}; + +/* + * Linux uses IRQ 0-7 for the 8 causes. That means that all of our channel + * bits need to be offset by 8 either when passed to do_IRQ or when received + * through the irq_chip calls + */ +#define GPINT_LINUX_IRQ_OFFSET 8 + +/* + * Configure a GPIO/Interrupt pin. Many of the defined interrupt pins as + * decribed in the Au1300 data book are configured during platform + * initialization, however drivers may wish to repurpose those or other GPIO + * pins later. + * + * Changing the behavior of an interrupt pin after a handler has been + * installed is ill advised and should be avoided. + */ +void set_pin_cfg(const struct gpio_int_cfg *cfg); + +/* + * Set the GPIO to the specified value. The value must be 0 or 1. Any other + * value results in a no-op. + * + * This call will implicitly reconfigure the pin to be a GPIO if it is + * configured as a device pin. + */ +void set_gpio(u8 gpio, u8 value); + +/* + * Get the value of any GPIO pin (including those controlled by devices). + * + * This will not change the pin configuration + */ +u8 get_gpio(u8 gpio); + +#endif /* _GPIO_INT_H */ + diff --git a/arch/mips/include/asm/mach-au1x00/irq.h b/arch/mips/include/asm/mach-au1x00/irq.h new file mode 100644 index 0000000..91d06a5 --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/irq.h @@ -0,0 +1,34 @@ +/* + * Copyright 2008 RMI Corporation + * Author: Kevin Hickey <khickey@rmicorp.com> + * + * Defines and macros for the GPIO and Interrupt controller for Alchemy, + * introduced in the Au13xx series. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef _MACH_AU1X00_INT_H +#define _MACH_AU1X00_INT_H + +#define NR_IRQS 255 +#define MIPS_CPU_IRQ_BASE 0 + +#endif /* _MACH_AU1X00_INT_H */ -- 1.5.4.3 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 3/5] Alchemy: Au1300/DB1300 UART support 2009-04-08 23:36 ` [PATCH v3 2/5] Alchemy: Au1300 new interrupt controller Kevin Hickey @ 2009-04-08 23:36 ` Kevin Hickey 2009-04-08 23:36 ` [PATCH v3 4/5] Alchemy: Au1300/DB1300 peripheral resource declarations Kevin Hickey 2009-04-09 10:07 ` [PATCH v3 2/5] Alchemy: Au1300 new interrupt controller Manuel Lauss 1 sibling, 1 reply; 10+ messages in thread From: Kevin Hickey @ 2009-04-08 23:36 UTC (permalink / raw) To: linux-mips, ralf; +Cc: Kevin Hickey Adds support for the UART on the Au1300 SOC and the DB1300 board. This includes enabling EARLY_PRINTK for Alchemy. Signed-off-by: Kevin Hickey <khickey@rmicorp.com> --- arch/mips/Kconfig | 1 + arch/mips/alchemy/common/platform.c | 5 +++++ arch/mips/include/asm/mach-au1x00/au1000.h | 5 +++++ 3 files changed, 11 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e61465a..b030770 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -21,6 +21,7 @@ choice config MACH_ALCHEMY bool "Alchemy processor based machines" + select SYS_HAS_EARLY_PRINTK config BASLER_EXCITE bool "Basler eXcite smart camera" diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 5c76c64..78fd862 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -52,6 +52,11 @@ static struct plat_serial8250_port au1x00_uart_data[] = { #elif defined(CONFIG_SOC_AU1200) PORT(UART0_ADDR, AU1200_UART0_INT), PORT(UART1_ADDR, AU1200_UART1_INT), +#elif defined(CONFIG_SOC_AU13XX) + PORT(UART2_ADDR, AU1300_IRQ_UART2 + GPINT_LINUX_IRQ_OFFSET), + PORT(UART0_ADDR, AU1300_IRQ_UART0 + GPINT_LINUX_IRQ_OFFSET), + PORT(UART1_ADDR, AU1300_IRQ_UART1 + GPINT_LINUX_IRQ_OFFSET), + PORT(UART3_ADDR, AU1300_IRQ_UART3 + GPINT_LINUX_IRQ_OFFSET), #endif #endif /* CONFIG_SERIAL_8250_AU1X00 */ { }, diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index c7fe356..f669556 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -1277,7 +1277,12 @@ enum soc_au1200_ints { #define MAC_RX_BUFF3_ADDR 0x34 /* UARTS 0-3 */ +#ifdef CONFIG_SOC_AU13XX +#define UART_BASE UART2_ADDR +#else #define UART_BASE UART0_ADDR +#endif + #ifdef CONFIG_SOC_AU1200 #define UART_DEBUG_BASE UART1_ADDR #else -- 1.5.4.3 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 4/5] Alchemy: Au1300/DB1300 peripheral resource declarations 2009-04-08 23:36 ` [PATCH v3 3/5] Alchemy: Au1300/DB1300 UART support Kevin Hickey @ 2009-04-08 23:36 ` Kevin Hickey 2009-04-08 23:36 ` [PATCH v3 5/5] Alchemy: Au1300: Add LCD framebuffer support Kevin Hickey 0 siblings, 1 reply; 10+ messages in thread From: Kevin Hickey @ 2009-04-08 23:36 UTC (permalink / raw) To: linux-mips, ralf; +Cc: Kevin Hickey This adds some declarations for peripheral resouces for the first few supported peripherals. This includes USB, LCD, IDE and MMC. Signed-off-by: Kevin Hickey <khickey@rmicorp.com> --- arch/mips/alchemy/common/Makefile | 1 + arch/mips/alchemy/common/au13xx_res.c | 132 ++++++++++++++++++++++ arch/mips/alchemy/common/dbdma.c | 46 ++++++++- arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | 33 ++++++ 4 files changed, 211 insertions(+), 1 deletions(-) create mode 100644 arch/mips/alchemy/common/au13xx_res.c diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile index faa6afd..4e533be 100644 --- a/arch/mips/alchemy/common/Makefile +++ b/arch/mips/alchemy/common/Makefile @@ -9,6 +9,7 @@ obj-y += prom.o puts.o time.o reset.o \ clocks.o platform.o power.o setup.o \ sleeper.o dma.o dbdma.o gpio.o +obj-$(CONFIG_SOC_AU13XX) += au13xx_res.o obj-$(CONFIG_PCI) += pci.o obj-$(CONFIG_AU_GPIO_INT_CNTLR) += gpio_int.o diff --git a/arch/mips/alchemy/common/au13xx_res.c b/arch/mips/alchemy/common/au13xx_res.c new file mode 100644 index 0000000..79b8fb4 --- /dev/null +++ b/arch/mips/alchemy/common/au13xx_res.c @@ -0,0 +1,132 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey <khickey@rmicorp.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> +#include <linux/init.h> + +#include <asm/mach-au1x00/au1000.h> +#include <asm/mach-au1x00/au1xxx.h> +#include <asm/mach-au1x00/au1100_mmc.h> + +/* + * USB Resources for Au13xx + */ +static struct resource au13xx_usb_ehci_resources[] = { + [0] = { + .start = USB_EHCI_BASE, + .end = USB_EHCI_BASE + USB_EHCI_LEN - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_IRQ_USB + GPINT_LINUX_IRQ_OFFSET, + .end = AU1300_IRQ_USB + GPINT_LINUX_IRQ_OFFSET, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ehci_dmamask = DMA_32BIT_MASK; + +static struct platform_device au13xx_usb_ehci_device = { + .name = "au13xx-ehci", + .id = 0, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + }, + .num_resources = ARRAY_SIZE(au13xx_usb_ehci_resources), + .resource = au13xx_usb_ehci_resources, +}; + +static struct resource au1200_lcd_resources[] = { + [0] = { + .start = LCD_PHYS_ADDR, + .end = LCD_PHYS_ADDR + 0x800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_IRQ_LCD + 8, + .end = AU1300_IRQ_LCD + 8, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 au1200_lcd_dmamask = DMA_32BIT_MASK; + +static struct platform_device au1200_lcd_device = { + .name = "au1200-lcd", + .id = 0, + .dev = { + .dma_mask = &au1200_lcd_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + }, + .num_resources = ARRAY_SIZE(au1200_lcd_resources), + .resource = au1200_lcd_resources, +}; + +extern struct platform_device au13xx_mmc1_device; + +extern struct au1xmmc_platform_data au1xmmc_platdata[2]; +static struct resource ide_resources[] = { + [0] = { + .start = IDE_PHYS_ADDR, + .end = IDE_PHYS_ADDR + IDE_PHYS_LEN - 1, + .flags = IORESOURCE_MEM + }, + [1] = { + .start = IDE_INT, + .end = IDE_INT, + .flags = IORESOURCE_IRQ + } +}; + +static u64 ide_dmamask = DMA_32BIT_MASK; + +static struct platform_device ide_device = { + .name = "au1200-ide", + .id = 0, + .dev = { + .dma_mask = &ide_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + }, + .num_resources = ARRAY_SIZE(ide_resources), + .resource = ide_resources +}; + +static struct platform_device *au13xx_platform_devices[] __initdata = { + &au13xx_usb_ehci_device, + &au1200_lcd_device, + &ide_device, + &au13xx_mmc1_device, +}; + + +static int __init au13xx_add_devices(void) +{ + return platform_add_devices(au13xx_platform_devices, + ARRAY_SIZE(au13xx_platform_devices)); +} + +arch_initcall(au13xx_add_devices); diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c index 3ab6d80..7fda56b 100644 --- a/arch/mips/alchemy/common/dbdma.c +++ b/arch/mips/alchemy/common/dbdma.c @@ -38,7 +38,8 @@ #include <asm/mach-au1x00/au1000.h> #include <asm/mach-au1x00/au1xxx_dbdma.h> -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) +#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) || \ + defined(CONFIG_SOC_AU13XX) /* * The Descriptor Based DMA supports up to 16 channels. @@ -150,6 +151,47 @@ static dbdev_tab_t dbdev_tab[] = { #endif /* CONFIG_SOC_AU1200 */ +#ifdef CONFIG_SOC_AU13XX + { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x10100004, 0, 0 }, + { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x10100000, 0, 0 }, + { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x01011004, 0, 0 }, + { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x10101000, 0, 0 }, + { DSCR_CMD0_UART2_TX, DEV_FLAGS_OUT, 0, 8, 0x01012004, 0, 0 }, + { DSCR_CMD0_UART2_RX, DEV_FLAGS_IN, 0, 8, 0x10102000, 0, 0 }, + { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x01013004, 0, 0 }, + { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x10103000, 0, 0 }, + + { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 }, + { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 }, + { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 8, 8, 0x10601000, 0, 0 }, + { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 8, 8, 0x10601004, 0, 0 }, + + { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 }, + { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 }, + + { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0001c, 0, 0 }, + { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x10a0001c, 0, 0 }, + { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0101c, 0, 0 }, + { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x10a0101c, 0, 0 }, + { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0201c, 0, 0 }, + { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 16, 0x10a0201c, 0, 0 }, + { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0301c, 0, 0 }, + { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 16, 0x10a0301c, 0, 0 }, + + { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, + + { DSCR_CMD0_SDMS_TX2, DEV_FLAGS_OUT, 4, 8, 0x10602000, 0, 0 }, + { DSCR_CMD0_SDMS_RX2, DEV_FLAGS_IN, 4, 8, 0x10602004, 0, 0 }, + + { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + + { DSCR_CMD0_UDMA, DEV_FLAGS_ANYUSE, 0, 32, 0x14001810, 0, 0 }, + + { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, +#endif /* CONFIG_SOC_AU13XX */ + { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, @@ -881,6 +923,8 @@ static void au1xxx_dbdma_init(void) irq_nr = AU1550_DDMA_INT; #elif defined(CONFIG_SOC_AU1200) irq_nr = AU1200_DDMA_INT; +#elif defined(CONFIG_SOC_AU13XX) + irq_nr = AU1300_IRQ_DDMA + GPINT_LINUX_IRQ_OFFSET; #else #error Unknown Au1x00 SOC #endif diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h index 06f68f4..1c36b9f 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h @@ -195,6 +195,39 @@ typedef volatile struct au1xxx_ddma_desc { #define DSCR_CMD0_CIM_SYNC 26 #endif /* CONFIG_SOC_AU1200 */ +#ifdef CONFIG_SOC_AU13XX +#define DSCR_CMD0_UART0_TX 0 +#define DSCR_CMD0_UART0_RX 1 +#define DSCR_CMD0_UART1_TX 2 +#define DSCR_CMD0_UART1_RX 3 +#define DSCR_CMD0_UART2_TX 4 +#define DSCR_CMD0_UART2_RX 5 +#define DSCR_CMD0_UART3_TX 6 +#define DSCR_CMD0_UART3_RX 7 +#define DSCR_CMD0_SDMS_TX0 8 +#define DSCR_CMD0_SDMS_RX0 9 +#define DSCR_CMD0_SDMS_TX1 10 +#define DSCR_CMD0_SDMS_RX1 11 +#define DSCR_CMD0_AES_TX 12 +#define DSCR_CMD0_AES_RX 13 +#define DSCR_CMD0_PSC0_TX 14 +#define DSCR_CMD0_PSC0_RX 15 +#define DSCR_CMD0_PSC1_TX 16 +#define DSCR_CMD0_PSC1_RX 17 +#define DSCR_CMD0_PSC2_TX 18 +#define DSCR_CMD0_PSC2_RX 19 +#define DSCR_CMD0_PSC3_TX 20 +#define DSCR_CMD0_PSC3_RX 21 +#define DSCR_CMD0_LCD 22 +#define DSCR_CMD0_NAND_FLASH 23 +#define DSCR_CMD0_SDMS_TX2 24 +#define DSCR_CMD0_SDMS_RX2 25 +#define DSCR_CMD0_CIM_SYNC 26 +#define DSCR_CMD0_UDMA 27 +#define DSCR_CMD0_DMA_REQ0 28 +#define DSCR_CMD0_DMA_REQ1 29 +#endif /* CONFIG_SOC_AU13XX */ + #define DSCR_CMD0_THROTTLE 30 #define DSCR_CMD0_ALWAYS 31 #define DSCR_NDEV_IDS 32 -- 1.5.4.3 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 5/5] Alchemy: Au1300: Add LCD framebuffer support 2009-04-08 23:36 ` [PATCH v3 4/5] Alchemy: Au1300/DB1300 peripheral resource declarations Kevin Hickey @ 2009-04-08 23:36 ` Kevin Hickey 0 siblings, 0 replies; 10+ messages in thread From: Kevin Hickey @ 2009-04-08 23:36 UTC (permalink / raw) To: linux-mips, ralf; +Cc: Kevin Hickey Signed-off-by: Kevin Hickey <khickey@rmicorp.com> --- drivers/video/Kconfig | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index fb19803..9f571df 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -1713,7 +1713,7 @@ config FB_AU1100 config FB_AU1200 bool "Au1200 LCD Driver" - depends on (FB = y) && MIPS && SOC_AU1200 + depends on (FB = y) && MIPS && (SOC_AU1200 || SOC_AU13XX) select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT -- 1.5.4.3 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v3 2/5] Alchemy: Au1300 new interrupt controller 2009-04-08 23:36 ` [PATCH v3 2/5] Alchemy: Au1300 new interrupt controller Kevin Hickey 2009-04-08 23:36 ` [PATCH v3 3/5] Alchemy: Au1300/DB1300 UART support Kevin Hickey @ 2009-04-09 10:07 ` Manuel Lauss 2009-04-09 10:07 ` Manuel Lauss 2009-04-09 14:27 ` Kevin Hickey 1 sibling, 2 replies; 10+ messages in thread From: Manuel Lauss @ 2009-04-09 10:07 UTC (permalink / raw) To: Kevin Hickey; +Cc: linux-mips, ralf, Kevin Hickey Hi Kevin! Some major nits: > --- /dev/null > +++ b/arch/mips/alchemy/common/gpio_int.c > +static struct irq_chip gpio_int_irq_type = { > + .name = "Au GPIO/INT", > + .ack = gpio_int_ack, > + .mask = gpio_int_mask, > + .unmask = gpio_int_unmask, > + .mask_ack = gpio_int_mask_ack > +void __init arch_init_irq(void) > +{ [...] > + for (i = 0; i < nr_basic_irqs; ++i) { > + printk(KERN_DEBUG "Initializing IRQ %d\n", > + basic_irqs[i].number); > + set_pin_cfg(&basic_irqs[i]); > + if (basic_irqs[i].intcfg == LEVEL_LOW) > + set_irq_chip_and_handler_name( > + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, > + &gpio_int_irq_type, > + handle_level_irq, > + "lowlevel"); > + else if (basic_irqs[i].intcfg == LEVEL_HIGH) > + set_irq_chip_and_handler_name( > + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, > + &gpio_int_irq_type, > + handle_level_irq, > + "highlevel"); > + else if (basic_irqs[i].intcfg == FALLING) > + set_irq_chip_and_handler_name( > + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, > + &gpio_int_irq_type, > + handle_edge_irq, > + "fallingedge"); > + else if (basic_irqs[i].intcfg == RISING) > + set_irq_chip_and_handler_name( > + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, > + &gpio_int_irq_type, > + handle_edge_irq, > + "risingedge"); > + else if (basic_irqs[i].intcfg == ANY_CHANGE) > + set_irq_chip_and_handler_name( > + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, > + &gpio_int_irq_type, > + handle_edge_irq, > + "bothedge"); > + else > + set_irq_chip( > + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, > + &gpio_int_irq_type); > + } Please please move this to a irq_chip.set_irq_type hook, and replace LEVEL_LOW and friends with linux' IRQ_TYPE_LEVEL_LOW... constants (So one can pass IRQ flags via platform resource information). > diff --git a/arch/mips/alchemy/devboards/cascade_irq.c b/arch/mips/alchemy/devboards/cascade_irq.c > + * The following must be declared/defined in an included file: > + * - volatile struct bcsr_regs (declared) > + * (which much include fields int_status, intset_mask, intclr_mask, intset, > + * and intclr) > + * - volatile struct bcsr_regs *const bcsr (defined) > + * - CASCADE_IRQ_MIN > + * - CASCADE_IRQ_MAX > + * - CASCADE_IRQ_TYPE_STRING > + * - CASCADE_IRQ (System IRQ to which the cascade is connected) > + */ > + > +void __init board_init_irq(void); > + > +irqreturn_t cascade_handler(int irq, void *dev_id) > +{ > + u16 int_status = au_ioread16(&db_bcsr->int_status); > + int irq_in_service; > + > + au_iowrite16(int_status, &db_bcsr->int_status); > + for ( ; int_status; int_status &= int_status - 1) { > + irq_in_service = CASCADE_IRQ_MIN + __ffs(int_status); > + db_set_hex((u8)(irq_in_service)); > + do_IRQ(irq_in_service); generic_handle_irq() please, > +static unsigned int cascade_startup(unsigned int irq) > +{ > + int retval = 0; > + > + mutex_lock(&cascade_use_count_mutex); > + ++cascade_use_count; > + if (cascade_use_count == 1) > + retval = request_irq(CASCADE_IRQ, > + &cascade_handler, 0, "Cascade", > + &cascade_handler); Use "set_irq_chained_handler" after registering the cascades and the startup/shutdown hooks can go away. Also, "cascade" is too generic, maybe call it "db1300cascade". The Db1200 too has a cascade but works slightly different (I even doubt it makes sense to place this code outside the directory. As it currently is, it's not generic enough to be usable by the Db1200/Pb1200; and the code is rather tiny anyway). (Off topic: why the 2-stage mask/unmask system [the 'enable' and 'mask' bits] I didn't make sense to me on the DB1200 either...) > +/* > + * Set the GPIO to the specified value. The value must be 0 or 1. Any other > + * value results in a no-op. > + * > + * This call will implicitly reconfigure the pin to be a GPIO if it is > + * configured as a device pin. > + */ > +void set_gpio(u8 gpio, u8 value); > + > +/* > + * Get the value of any GPIO pin (including those controlled by devices). > + * > + * This will not change the pin configuration > + */ > +u8 get_gpio(u8 gpio); > + > +#endif /* _GPIO_INT_H */ > + no support for linux' GPIO framework? Thanks! Manuel Lauss ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 2/5] Alchemy: Au1300 new interrupt controller 2009-04-09 10:07 ` [PATCH v3 2/5] Alchemy: Au1300 new interrupt controller Manuel Lauss @ 2009-04-09 10:07 ` Manuel Lauss 2009-04-09 14:27 ` Kevin Hickey 1 sibling, 0 replies; 10+ messages in thread From: Manuel Lauss @ 2009-04-09 10:07 UTC (permalink / raw) To: Kevin Hickey; +Cc: linux-mips, ralf Hi Kevin! Some major nits: > --- /dev/null > +++ b/arch/mips/alchemy/common/gpio_int.c > +static struct irq_chip gpio_int_irq_type = { > + .name = "Au GPIO/INT", > + .ack = gpio_int_ack, > + .mask = gpio_int_mask, > + .unmask = gpio_int_unmask, > + .mask_ack = gpio_int_mask_ack > +void __init arch_init_irq(void) > +{ [...] > + for (i = 0; i < nr_basic_irqs; ++i) { > + printk(KERN_DEBUG "Initializing IRQ %d\n", > + basic_irqs[i].number); > + set_pin_cfg(&basic_irqs[i]); > + if (basic_irqs[i].intcfg == LEVEL_LOW) > + set_irq_chip_and_handler_name( > + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, > + &gpio_int_irq_type, > + handle_level_irq, > + "lowlevel"); > + else if (basic_irqs[i].intcfg == LEVEL_HIGH) > + set_irq_chip_and_handler_name( > + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, > + &gpio_int_irq_type, > + handle_level_irq, > + "highlevel"); > + else if (basic_irqs[i].intcfg == FALLING) > + set_irq_chip_and_handler_name( > + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, > + &gpio_int_irq_type, > + handle_edge_irq, > + "fallingedge"); > + else if (basic_irqs[i].intcfg == RISING) > + set_irq_chip_and_handler_name( > + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, > + &gpio_int_irq_type, > + handle_edge_irq, > + "risingedge"); > + else if (basic_irqs[i].intcfg == ANY_CHANGE) > + set_irq_chip_and_handler_name( > + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, > + &gpio_int_irq_type, > + handle_edge_irq, > + "bothedge"); > + else > + set_irq_chip( > + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, > + &gpio_int_irq_type); > + } Please please move this to a irq_chip.set_irq_type hook, and replace LEVEL_LOW and friends with linux' IRQ_TYPE_LEVEL_LOW... constants (So one can pass IRQ flags via platform resource information). > diff --git a/arch/mips/alchemy/devboards/cascade_irq.c b/arch/mips/alchemy/devboards/cascade_irq.c > + * The following must be declared/defined in an included file: > + * - volatile struct bcsr_regs (declared) > + * (which much include fields int_status, intset_mask, intclr_mask, intset, > + * and intclr) > + * - volatile struct bcsr_regs *const bcsr (defined) > + * - CASCADE_IRQ_MIN > + * - CASCADE_IRQ_MAX > + * - CASCADE_IRQ_TYPE_STRING > + * - CASCADE_IRQ (System IRQ to which the cascade is connected) > + */ > + > +void __init board_init_irq(void); > + > +irqreturn_t cascade_handler(int irq, void *dev_id) > +{ > + u16 int_status = au_ioread16(&db_bcsr->int_status); > + int irq_in_service; > + > + au_iowrite16(int_status, &db_bcsr->int_status); > + for ( ; int_status; int_status &= int_status - 1) { > + irq_in_service = CASCADE_IRQ_MIN + __ffs(int_status); > + db_set_hex((u8)(irq_in_service)); > + do_IRQ(irq_in_service); generic_handle_irq() please, > +static unsigned int cascade_startup(unsigned int irq) > +{ > + int retval = 0; > + > + mutex_lock(&cascade_use_count_mutex); > + ++cascade_use_count; > + if (cascade_use_count == 1) > + retval = request_irq(CASCADE_IRQ, > + &cascade_handler, 0, "Cascade", > + &cascade_handler); Use "set_irq_chained_handler" after registering the cascades and the startup/shutdown hooks can go away. Also, "cascade" is too generic, maybe call it "db1300cascade". The Db1200 too has a cascade but works slightly different (I even doubt it makes sense to place this code outside the directory. As it currently is, it's not generic enough to be usable by the Db1200/Pb1200; and the code is rather tiny anyway). (Off topic: why the 2-stage mask/unmask system [the 'enable' and 'mask' bits] I didn't make sense to me on the DB1200 either...) > +/* > + * Set the GPIO to the specified value. The value must be 0 or 1. Any other > + * value results in a no-op. > + * > + * This call will implicitly reconfigure the pin to be a GPIO if it is > + * configured as a device pin. > + */ > +void set_gpio(u8 gpio, u8 value); > + > +/* > + * Get the value of any GPIO pin (including those controlled by devices). > + * > + * This will not change the pin configuration > + */ > +u8 get_gpio(u8 gpio); > + > +#endif /* _GPIO_INT_H */ > + no support for linux' GPIO framework? Thanks! Manuel Lauss ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 2/5] Alchemy: Au1300 new interrupt controller 2009-04-09 10:07 ` [PATCH v3 2/5] Alchemy: Au1300 new interrupt controller Manuel Lauss 2009-04-09 10:07 ` Manuel Lauss @ 2009-04-09 14:27 ` Kevin Hickey 2009-04-09 15:15 ` Manuel Lauss 1 sibling, 1 reply; 10+ messages in thread From: Kevin Hickey @ 2009-04-09 14:27 UTC (permalink / raw) To: Manuel Lauss; +Cc: linux-mips, ralf On Thu, 2009-04-09 at 12:07 +0200, Manuel Lauss wrote: > Hi Kevin! > > Some major nits: > > > --- /dev/null > > +++ b/arch/mips/alchemy/common/gpio_int.c > > +static struct irq_chip gpio_int_irq_type = { > > + .name = "Au GPIO/INT", > > + .ack = gpio_int_ack, > > + .mask = gpio_int_mask, > > + .unmask = gpio_int_unmask, > > + .mask_ack = gpio_int_mask_ack > > +void __init arch_init_irq(void) > > +{ > [...] > > + for (i = 0; i < nr_basic_irqs; ++i) { > > + printk(KERN_DEBUG "Initializing IRQ %d\n", > > + basic_irqs[i].number); > > + set_pin_cfg(&basic_irqs[i]); > > + if (basic_irqs[i].intcfg == LEVEL_LOW) > > + set_irq_chip_and_handler_name( > > + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, > > + &gpio_int_irq_type, > > + handle_level_irq, > > + "lowlevel"); > > + else if (basic_irqs[i].intcfg == LEVEL_HIGH) > > + set_irq_chip_and_handler_name( > > + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, > > + &gpio_int_irq_type, > > + handle_level_irq, > > + "highlevel"); > > + else if (basic_irqs[i].intcfg == FALLING) > > + set_irq_chip_and_handler_name( > > + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, > > + &gpio_int_irq_type, > > + handle_edge_irq, > > + "fallingedge"); > > + else if (basic_irqs[i].intcfg == RISING) > > + set_irq_chip_and_handler_name( > > + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, > > + &gpio_int_irq_type, > > + handle_edge_irq, > > + "risingedge"); > > + else if (basic_irqs[i].intcfg == ANY_CHANGE) > > + set_irq_chip_and_handler_name( > > + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, > > + &gpio_int_irq_type, > > + handle_edge_irq, > > + "bothedge"); > > + else > > + set_irq_chip( > > + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, > > + &gpio_int_irq_type); > > + } > > Please please move this to a irq_chip.set_irq_type hook, and replace > LEVEL_LOW and friends with linux' IRQ_TYPE_LEVEL_LOW... constants > (So one can pass IRQ flags via platform resource information). > > > > diff --git a/arch/mips/alchemy/devboards/cascade_irq.c b/arch/mips/alchemy/devboards/cascade_irq.c > > + * The following must be declared/defined in an included file: > > + * - volatile struct bcsr_regs (declared) > > + * (which much include fields int_status, intset_mask, intclr_mask, intset, > > + * and intclr) > > + * - volatile struct bcsr_regs *const bcsr (defined) > > + * - CASCADE_IRQ_MIN > > + * - CASCADE_IRQ_MAX > > + * - CASCADE_IRQ_TYPE_STRING > > + * - CASCADE_IRQ (System IRQ to which the cascade is connected) > > + */ > > + > > +void __init board_init_irq(void); > > + > > +irqreturn_t cascade_handler(int irq, void *dev_id) > > +{ > > + u16 int_status = au_ioread16(&db_bcsr->int_status); > > + int irq_in_service; > > + > > + au_iowrite16(int_status, &db_bcsr->int_status); > > + for ( ; int_status; int_status &= int_status - 1) { > > + irq_in_service = CASCADE_IRQ_MIN + __ffs(int_status); > > + db_set_hex((u8)(irq_in_service)); > > + do_IRQ(irq_in_service); > > generic_handle_irq() please, > > > > +static unsigned int cascade_startup(unsigned int irq) > > +{ > > + int retval = 0; > > + > > + mutex_lock(&cascade_use_count_mutex); > > + ++cascade_use_count; > > + if (cascade_use_count == 1) > > + retval = request_irq(CASCADE_IRQ, > > + &cascade_handler, 0, "Cascade", > > + &cascade_handler); > > Use "set_irq_chained_handler" after registering the cascades and the > startup/shutdown hooks can go away. > > Also, "cascade" is too generic, maybe call it "db1300cascade". The > Db1200 too has a cascade but works slightly different (I even doubt it > makes sense to place this code outside the directory. As it currently > is, it's not generic enough to be usable by the Db1200/Pb1200; and > the code is rather tiny anyway). > To address all of your comments, I wrote this code some time ago and have not had time to digest some of the changes that have been posted to the DB1200 interrupt code since then. I have every intention of finding some time down the line to revisit this and merge it with the DB1200 cascade code. The controllers are very similar - in fact in my local tree I am using this same code on both platforms. In the interest of time and schedule, I was hoping to have this version included in 2.6.30 so that I had something to build on for future updates and something to release other driver and peripheral patches against. > (Off topic: why the 2-stage mask/unmask system [the 'enable' and > 'mask' bits] I didn't make sense to me on the DB1200 either...) > I'm not really sure either but I can ask the folks responsible for the CPLD. My guess is that it is just because traditionally interrupt controllers have both enables and masks and that's how it was written. > > > +/* > > + * Set the GPIO to the specified value. The value must be 0 or 1. Any other > > + * value results in a no-op. > > + * > > + * This call will implicitly reconfigure the pin to be a GPIO if it is > > + * configured as a device pin. > > + */ > > +void set_gpio(u8 gpio, u8 value); > > + > > +/* > > + * Get the value of any GPIO pin (including those controlled by devices). > > + * > > + * This will not change the pin configuration > > + */ > > +u8 get_gpio(u8 gpio); > > + > > +#endif /* _GPIO_INT_H */ > > + > > no support for linux' GPIO framework? Again, at the time I was unaware of any GPIO standards. I will probably revise this to use gpiolib or whaterver down the line. > -- Kevin Hickey Alchemy Solutions RMI Corporation khickey@rmicorp.com P: 512.691.8044 ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 2/5] Alchemy: Au1300 new interrupt controller 2009-04-09 14:27 ` Kevin Hickey @ 2009-04-09 15:15 ` Manuel Lauss 0 siblings, 0 replies; 10+ messages in thread From: Manuel Lauss @ 2009-04-09 15:15 UTC (permalink / raw) To: Kevin Hickey; +Cc: linux-mips, ralf On Thu, 09 Apr 2009 09:27:58 -0500 Kevin Hickey <khickey@rmicorp.com> wrote: > To address all of your comments, I wrote this code some time ago and > have not had time to digest some of the changes that have been posted to > the DB1200 interrupt code since then. I have every intention of finding > some time down the line to revisit this and merge it with the DB1200 > cascade code. The controllers are very similar - in fact in my local > tree I am using this same code on both platforms. > > In the interest of time and schedule, I was hoping to have this version > included in 2.6.30 so that I had something to build on for future > updates and something to release other driver and peripheral patches > against. I see. I don't have any objections against inclusion if you're going to fix it later on. Thanks! Manuel Lauss ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2009-04-09 15:15 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2009-04-08 23:36 [PATCH v3 0/5] Alchemy: Basic Au1300 and DB1300 support Kevin Hickey 2009-04-08 23:36 ` [PATCH v3 1/5] Alchemy: Initial Au1300 and DBAu1300 support Kevin Hickey 2009-04-08 23:36 ` [PATCH v3 2/5] Alchemy: Au1300 new interrupt controller Kevin Hickey 2009-04-08 23:36 ` [PATCH v3 3/5] Alchemy: Au1300/DB1300 UART support Kevin Hickey 2009-04-08 23:36 ` [PATCH v3 4/5] Alchemy: Au1300/DB1300 peripheral resource declarations Kevin Hickey 2009-04-08 23:36 ` [PATCH v3 5/5] Alchemy: Au1300: Add LCD framebuffer support Kevin Hickey 2009-04-09 10:07 ` [PATCH v3 2/5] Alchemy: Au1300 new interrupt controller Manuel Lauss 2009-04-09 10:07 ` Manuel Lauss 2009-04-09 14:27 ` Kevin Hickey 2009-04-09 15:15 ` Manuel Lauss
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