From: Ralf Baechle <ralf@oss.sgi.com>
To: Carsten Langgaard <carstenl@mips.com>
Cc: Alice Hennessy <ahennessy@mvista.com>,
Atsushi Nemoto <nemoto@toshiba-tops.co.jp>,
ajob4me@21cn.com, linux-mips@oss.sgi.com
Subject: Re: Toshiba TX3927 board boot problem.
Date: Tue, 30 Oct 2001 15:13:08 +0100 [thread overview]
Message-ID: <20011030151308.B10165@dea.linux-mips.net> (raw)
In-Reply-To: <3BDE6671.7776CB4B@mips.com>; from carstenl@mips.com on Tue, Oct 30, 2001 at 09:36:01AM +0100
On Tue, Oct 30, 2001 at 09:36:01AM +0100, Carsten Langgaard wrote:
> > So, we should not set CU1 generically for FPU-less CPUs especially since a
> > known problem exists
> > for the tx3927? Ie, qualify all setting of CU1 as follows:
> >
> > if (mips_cpu.options & MIPS_CPU_FPU)
> > set_cp0_status(ST0_CU1);
>
> And while we are at it, could we handle the CP0 hazard of 4 nops, between
> setting the CU1 bit in the status register and executing
> the first floating point instruction, on CPU which got a FPU.
Which CPUs actually need four nops?
Just working on a patch; I found a bunch more place where we were playing
with the CU1 bit.
Ralf
next prev parent reply other threads:[~2001-10-30 14:14 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20011026095319.1C4BBB474@topsms.toshiba-tops.co.jp>
2001-10-26 13:58 ` Toshiba TX3927 board boot problem Atsushi Nemoto
2001-10-29 7:02 ` Atsushi Nemoto
2001-10-29 8:32 ` Carsten Langgaard
2001-10-30 0:17 ` Alice Hennessy
2001-10-30 0:32 ` Ralf Baechle
2001-10-30 2:25 ` Alice Hennessy
2001-10-30 8:36 ` Carsten Langgaard
2001-10-30 14:13 ` Ralf Baechle [this message]
2001-10-30 14:17 ` Carsten Langgaard
2001-10-30 3:14 ` Atsushi Nemoto
2001-10-30 8:20 ` Carsten Langgaard
2001-10-30 14:55 ` Ralf Baechle
2001-10-31 2:58 ` Atsushi Nemoto
2001-10-31 4:06 ` Ralf Baechle
2001-10-31 4:30 ` Atsushi Nemoto
2001-10-31 4:31 ` Ralf Baechle
2001-10-31 5:07 ` Daniel Jacobowitz
2001-10-26 9:49 8route
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