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* [PATCH] disable interrupt for non-LLSC atomic set
@ 2002-01-11  1:53 Jun Sun
  2002-01-11 10:54 ` Maciej W. Rozycki
  0 siblings, 1 reply; 4+ messages in thread
From: Jun Sun @ 2002-01-11  1:53 UTC (permalink / raw)
  To: ralf, linux-mips


The current MIPS_ATOMIC set code for no-LLSC case does a load and store with
interrupt open.  This is potentially dangerous as an interrupt could happen
in-between and cause the value changed inside the interrupt handler. 
Therefore the load/store is not atomic anymore.

Does the following patch look good to fix that?

http://linux.junsun.net/patches/oss.sgi.com/submitted/020110.disable-intr-for-nollsc-atomic-set.patch

Jun

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] disable interrupt for non-LLSC atomic set
  2002-01-11  1:53 [PATCH] disable interrupt for non-LLSC atomic set Jun Sun
@ 2002-01-11 10:54 ` Maciej W. Rozycki
  2002-01-11 17:23   ` Jun Sun
  0 siblings, 1 reply; 4+ messages in thread
From: Maciej W. Rozycki @ 2002-01-11 10:54 UTC (permalink / raw)
  To: Jun Sun; +Cc: ralf, linux-mips

On Thu, 10 Jan 2002, Jun Sun wrote:

> The current MIPS_ATOMIC set code for no-LLSC case does a load and store with
> interrupt open.  This is potentially dangerous as an interrupt could happen
> in-between and cause the value changed inside the interrupt handler. 

 No need to -- no sane interrupt handler will ever access a user's atomic
variable. 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] disable interrupt for non-LLSC atomic set
  2002-01-11 10:54 ` Maciej W. Rozycki
@ 2002-01-11 17:23   ` Jun Sun
  2002-01-11 17:40     ` Maciej W. Rozycki
  0 siblings, 1 reply; 4+ messages in thread
From: Jun Sun @ 2002-01-11 17:23 UTC (permalink / raw)
  To: Maciej W. Rozycki; +Cc: ralf, linux-mips

On Fri, Jan 11, 2002 at 11:54:24AM +0100, Maciej W. Rozycki wrote:
> On Thu, 10 Jan 2002, Jun Sun wrote:
> 
> > The current MIPS_ATOMIC set code for no-LLSC case does a load and store with
> > interrupt open.  This is potentially dangerous as an interrupt could happen
> > in-between and cause the value changed inside the interrupt handler. 
> 
>  No need to -- no sane interrupt handler will ever access a user's atomic
> variable. 
>

OK, I have to reveal the secret desire :-).  I have a patch
that makes MIPS kernel preemptible, and that unprotected operation
becomes very volunerable with the preemptible patch.

Jun

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] disable interrupt for non-LLSC atomic set
  2002-01-11 17:23   ` Jun Sun
@ 2002-01-11 17:40     ` Maciej W. Rozycki
  0 siblings, 0 replies; 4+ messages in thread
From: Maciej W. Rozycki @ 2002-01-11 17:40 UTC (permalink / raw)
  To: Jun Sun; +Cc: ralf, linux-mips

On Fri, 11 Jan 2002, Jun Sun wrote:

> >  No need to -- no sane interrupt handler will ever access a user's atomic
> > variable. 
> 
> OK, I have to reveal the secret desire :-).  I have a patch
> that makes MIPS kernel preemptible, and that unprotected operation
> becomes very volunerable with the preemptible patch.

 I see.  But why not to keep the MIPS_ATOMIC update together with the
patch then?  It doesn't look like such a patch is going into the official
kernel anytime soon.

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2002-01-11 18:41 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2002-01-11  1:53 [PATCH] disable interrupt for non-LLSC atomic set Jun Sun
2002-01-11 10:54 ` Maciej W. Rozycki
2002-01-11 17:23   ` Jun Sun
2002-01-11 17:40     ` Maciej W. Rozycki

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