PATCH: Momentum Ocelot (CP7000) fixes

PATCH: Momentum Ocelot (CP7000) fixes

[Matthew Dharm]

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Ralf --

Attached to this message is a patch to make the Momentum Computer
Ocelot (CP7000) SBC port of Linux work.  I made this patch against a
recent (2 days ago) CVS snapshot.  Please apply it to the CVS
repository.

It turns out that the existing code only worked for boards with 512MiB
of SDRAM.  This patch makes all memory configurations work.  While
discontiguous memory configurations seemed to work, there was some
"unusual" behavior.  This patch uses a contiguous memory approach,
which seems much more stable.

BTW, did you ever wind up in the same place as the board we sent you?

Matt

--
Matthew D. Dharm                            Senior Software Designer
Momentum Computer Inc.                      1815 Aston Ave.  Suite 107
(760) 431-8663 X-115                        Carlsbad, CA 92008-7310
Momentum Works For You                      www.momenco.com

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? a.out
? arch/mips/boot/elf2ecoff
? arch/mips/boot/vmlinux.ecoff
? arch/mips/boot/addinitrd
Index: arch/mips/gt64120/momenco_ocelot/setup.c
===================================================================
RCS file: /cvs/linux/arch/mips/gt64120/momenco_ocelot/setup.c,v
retrieving revision 1.5
diff -u -r1.5 setup.c
--- arch/mips/gt64120/momenco_ocelot/setup.c	2001/11/25 09:25:53	1.5
+++ arch/mips/gt64120/momenco_ocelot/setup.c	2002/02/05 02:24:48
@@ -2,11 +2,12 @@
  * setup.c
  *
  * BRIEF MODULE DESCRIPTION
- * Galileo Evaluation Boards - board dependent boot routines
+ * Momentum Computer Ocelot (CP7000) - board dependent boot routines
  *
  * Copyright (C) 1996, 1997, 2001  Ralf Baechle
  * Copyright (C) 2000 RidgeRun, Inc.
  * Copyright (C) 2001 Red Hat, Inc.
+ * Copyright (C) 2002 Momentum Computer
  *
  * Author: RidgeRun, Inc.
  *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
@@ -116,8 +117,7 @@
 
 	/* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
 	   in the CS[012] region. We can't use ioremap() yet. The NVRAM
-	   appears to be one of the variants of ST M48T35 - see 
-	   http://www.st.com/stonline/bin/sftab.exe?table=172&filter0=M48T35
+	   is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
 
 		Ocelot PLD (CS0)	0x2c000000	0xe0020000
 		NVRAM			0x2c800000	0xe0030000
@@ -155,6 +155,7 @@
 	GT_WRITE(GT_PCI1M0LD_OFS, 0x32000000 >> 21);
 	GT_WRITE(GT_PCI1M1LD_OFS, 0x34000000 >> 21);
 
+	/* For the initial programming, we assume 512MB configuration */
 	/* Relocate the CPU's view of the RAM... */
 	GT_WRITE(GT_SCS10LD_OFS, 0);
 	GT_WRITE(GT_SCS10HD_OFS, 0x0fe00000 >> 21);
@@ -207,17 +208,66 @@
 	switch(tmpword &3) {
 	case 3:
 		/* 512MiB */
-		add_memory_region(256<<20, 256<<20, BOOT_MEM_RAM);
+		/* Decoders are allready set -- just add the
+		 * appropriate region */
+		add_memory_region( 0x40<<20,  0xC0<<20, BOOT_MEM_RAM);
+		add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM);
+		break;
 	case 2:
-		/* 256MiB */
-		/* FIXME: Is it actually here, or at 0x10000000? */
-		add_memory_region(128<<20, 128<<20, BOOT_MEM_RAM);
+		/* 256MiB -- two banks of 128MiB */
+		GT_WRITE(GT_SCS10HD_OFS, 0x07e00000 >> 21);
+		GT_WRITE(GT_SCS32LD_OFS, 0x08000000 >> 21);
+		GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21);
+
+		GT_WRITE(GT_SCS0HD_OFS, 0x7f);
+		GT_WRITE(GT_SCS2LD_OFS, 0x80);
+		GT_WRITE(GT_SCS2HD_OFS, 0xff);
+
+		/* reconfigure the PCI0 interface view of memory */
+		GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
+		GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x08000000);
+		GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000);
+		GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000);
+
+		add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
+		add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM);
+		break;
 	case 1:
-		/* 128MiB */
-		add_memory_region(64<<20, 64<<20, BOOT_MEM_RAM);
+		/* 128MiB -- 64MiB per bank */
+		GT_WRITE(GT_SCS10HD_OFS, 0x03e00000 >> 21);
+		GT_WRITE(GT_SCS32LD_OFS, 0x04000000 >> 21);
+		GT_WRITE(GT_SCS32HD_OFS, 0x07e00000 >> 21);
+
+		GT_WRITE(GT_SCS0HD_OFS, 0x3f);
+		GT_WRITE(GT_SCS2LD_OFS, 0x40);
+		GT_WRITE(GT_SCS2HD_OFS, 0x7f);
+
+		/* reconfigure the PCI0 interface view of memory */
+		GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
+		GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000);
+		GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x03fff000);
+		GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x03fff000);
+
+		/* add the appropriate region */
+		add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
+		break;
 	case 0:
 		/* 64MiB */
-		;
+		GT_WRITE(GT_SCS10HD_OFS, 0x01e00000 >> 21);
+		GT_WRITE(GT_SCS32LD_OFS, 0x02000000 >> 21);
+		GT_WRITE(GT_SCS32HD_OFS, 0x03e00000 >> 21);
+
+		GT_WRITE(GT_SCS0HD_OFS, 0x1f);
+		GT_WRITE(GT_SCS2LD_OFS, 0x20);
+		GT_WRITE(GT_SCS2HD_OFS, 0x3f);
+
+		/* reconfigure the PCI0 interface view of memory */
+		GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
+		GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000);
+		GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x01fff000);
+		GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x01fff000);
+
+		break;
 	}
 
 	/* Fix up the DiskOnChip mapping */

Re: PATCH: Momentum Ocelot (CP7000) fixes

[Ralf Baechle]

On Wed, Feb 06, 2002 at 05:21:55PM -0800, Matthew Dharm wrote:

> Attached to this message is a patch to make the Momentum Computer
> Ocelot (CP7000) SBC port of Linux work.  I made this patch against a
> recent (2 days ago) CVS snapshot.  Please apply it to the CVS
> repository.
> 
> It turns out that the existing code only worked for boards with 512MiB
> of SDRAM.  This patch makes all memory configurations work.  While
> discontiguous memory configurations seemed to work, there was some
> "unusual" behavior.  This patch uses a contiguous memory approach,
> which seems much more stable.

Applied,

  Ralf