Re: FPU emulator unsafe for SMP?

[Greg Lindahl <lindahl@conservativecomputer.com>]

On Wed, Feb 20, 2002 at 02:50:23PM +0100, Ralf Baechle wrote:

> These days I assume the difference to be greater for cache reasons.  Our
> stored fp registers take 256 bytes and also tend to be located at a constant
> offset from start of the 8kB (64-bit: 16kB) aligned task_struct.  Combined
> with the usually low degree of cache associativity on MIPS that means
> we'll frequently miss L1.

Ouch. That cache miss is much more expensive than saving the FPU state.

Can we un-align task_struct? I see it is allocated as a whole page,
but it's apparently much smaller. We could add an offset to its start
(hm, should be a multiple of the cache line size), and that ought to
give much nicer L1 usage.

Any other struct which is allocated as a whole page but is much
smaller could be a candidate for this, too. But we should experiment
once to see if it's a win before getting that excited.

greg