From: Ralf Baechle <ralf@linux-mips.org>
To: Richard Hodges <rh@matriplex.com>
Cc: Ranjan Parthasarathy <ranjanp@efi.com>,
"'linux-mips@linux-mips.org'" <linux-mips@linux-mips.org>
Subject: Re: Disabling lwl and lwr instruction generation
Date: Thu, 13 Mar 2003 02:33:45 +0100 [thread overview]
Message-ID: <20030313023344.A7013@linux-mips.org> (raw)
In-Reply-To: <Pine.BSF.4.50.0303121647400.95890-100000@mail.matriplex.com>; from rh@matriplex.com on Wed, Mar 12, 2003 at 04:50:53PM -0800
On Wed, Mar 12, 2003 at 04:50:53PM -0800, Richard Hodges wrote:
> I got lwl and lwr from a memcpy() with two void pointers...
>
> I quickly changed those to the (aligned) structure pointers instead, and
> then memcpy() changed to ordinary word loads and stores.
>
> So, is somebody starting a toolchain for that new Chinese CPU? :-)
Wouldn't be the first processor without lwl/lwr instructions. There have
been a few that didn't implement it for silly bean^Wgate counting issues
others have done it for patent and licensing reasons.
(Afair MIPS's patent is about to expire and IBM's prior art patent in the
same area is even way older but that legalese ...)
Ralf
next prev parent reply other threads:[~2003-03-13 1:33 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-03-12 18:05 Disabling lwl and lwr instruction generation Ranjan Parthasarathy
2003-03-13 0:43 ` Ralf Baechle
2003-03-13 0:50 ` Richard Hodges
2003-03-13 1:33 ` Ralf Baechle [this message]
2003-03-13 15:07 ` Zhang Fuxin
2003-03-13 0:52 ` Thiemo Seufer
2003-03-13 1:18 ` Ralf Baechle
-- strict thread matches above, loose matches on Subject: below --
2003-03-13 18:00 Ranjan Parthasarathy
2003-03-13 18:00 ` Ranjan Parthasarathy
2003-03-13 18:09 Ranjan Parthasarathy
2003-03-13 18:09 ` Ranjan Parthasarathy
2003-03-13 21:35 ` Ralf Baechle
2003-03-14 0:21 ` Alan Cox
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