From: Ralf Baechle <ralf@linux-mips.org>
To: Ranjan Parthasarathy <ranjanp@efi.com>
Cc: Richard Hodges <rh@matriplex.com>, linux-mips@linux-mips.org
Subject: Re: Disabling lwl and lwr instruction generation
Date: Thu, 13 Mar 2003 22:35:29 +0100 [thread overview]
Message-ID: <20030313223529.D30512@linux-mips.org> (raw)
In-Reply-To: <D9F6B9DABA4CAE4B92850252C52383AB07968241@ex-eng-corp.efi.com>; from ranjanp@efi.com on Thu, Mar 13, 2003 at 10:09:03AM -0800
On Thu, Mar 13, 2003 at 10:09:03AM -0800, Ranjan Parthasarathy wrote:
> From the gcc sources, the compiler generates the lwl,lwr etc. in the block
> move code in gcc/config/mips/mips.c ( output_block_move ).
>
> There is an option -mmemcpy which tells gcc to use a memcpy compiled in
> with the sources for this block move instead of gcc genetrating code. The
> problem however with this is that arch/mips/lib/memcpy.S is optimized
> using lwl,lwr,swl,swr. If this can be modified so that lwl,lwr,swl,swr
> is used if enabled as a kernel option, it might work very well.
Replace those unaligned copies with a word-wise or even bytewise copying.
Not good for performance but ...
Ralf
next prev parent reply other threads:[~2003-03-13 21:35 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-03-13 18:09 Disabling lwl and lwr instruction generation Ranjan Parthasarathy
2003-03-13 18:09 ` Ranjan Parthasarathy
2003-03-13 21:35 ` Ralf Baechle [this message]
2003-03-14 0:21 ` Alan Cox
-- strict thread matches above, loose matches on Subject: below --
2003-03-13 18:00 Ranjan Parthasarathy
2003-03-13 18:00 ` Ranjan Parthasarathy
2003-03-12 18:05 Ranjan Parthasarathy
2003-03-13 0:43 ` Ralf Baechle
2003-03-13 0:50 ` Richard Hodges
2003-03-13 1:33 ` Ralf Baechle
2003-03-13 15:07 ` Zhang Fuxin
2003-03-13 0:52 ` Thiemo Seufer
2003-03-13 1:18 ` Ralf Baechle
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