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* Basic cache questions
@ 2003-04-15 22:19 Steve Taylor
  2003-04-15 23:40 ` Jun Sun
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Steve Taylor @ 2003-04-15 22:19 UTC (permalink / raw)
  To: linux-mips

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Hello All,   I am hoping some of you mips-linux gurus will be able to help me give me some tips and help me get started on some cache stuff which I want to do. (I know decently well about caches - but only at a theoretical Hennessy & Patterson level - and have just started looking under arch/mips/mm to familiarize myself with the mips-linux implementation).   Here's what I want to do - I have a CPU with 4 way SA I and D caches, and I want to write a module that will lock a certain memory region in these caches (for example, let's say I want to lock the ISR in the I-cache). So my questions are a) Is the kernel going to crash if I try to mess around with the caches like locking out a particular way of the cache or something like that? b) I'm sure there are many issues and complications involved in this that I probably havent even thought of  - any obvious and/or subtle pitfalls? and c) Do you think locking out, say, an entire way of a 4-way cache for a dedicated frequently used routine improves or degrades overall system performance?   TIA, -Steve.


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^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: Basic cache questions
  2003-04-15 22:19 Basic cache questions Steve Taylor
@ 2003-04-15 23:40 ` Jun Sun
  2003-04-16 10:07 ` Dominic Sweetman
  2003-04-16 11:50 ` Ralf Baechle
  2 siblings, 0 replies; 4+ messages in thread
From: Jun Sun @ 2003-04-15 23:40 UTC (permalink / raw)
  To: Steve Taylor; +Cc: linux-mips, jsun

On Tue, Apr 15, 2003 at 03:19:14PM -0700, Steve Taylor wrote:
> Hello All,   I am hoping some of you mips-linux gurus will be able to help me give me some tips and help me get started on some cache stuff which I want to do. (I know decently well about caches - but only at a theoretical Hennessy & Patterson level - and have just started looking under arch/mips/mm to familiarize myself with the mips-linux implementation).   Here's what I want to do - I have a CPU with 4 way SA I and D caches, and I want to write a module that will lock a certain memory region in these caches (for example, let's say I want to lock the ISR in the I-cache). So my questions are a) Is the kernel going to crash if I try to mess around with the caches like locking out a particular way of the cache or something like that? b) I'm sure there are many issues and complications involved in this that I probably havent even thought of  - any obvious and/or subtle pitfalls? and c) Do you think locking out, say, an entire way of a 4-way cache for a dedicated frequently used !
> !
> routine improves or degrades overall system performance?   TIA, -Steve.

If the cache locking can survive flushing, i.e., locked cache line
remained valid and locked even after cache invalidation ops, I guess
you are probably OK.

I have looked the performance issues with cache locking on a two-way
cache system.  There was not much performance gain.

Jun

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: Basic cache questions
  2003-04-15 22:19 Basic cache questions Steve Taylor
  2003-04-15 23:40 ` Jun Sun
@ 2003-04-16 10:07 ` Dominic Sweetman
  2003-04-16 11:50 ` Ralf Baechle
  2 siblings, 0 replies; 4+ messages in thread
From: Dominic Sweetman @ 2003-04-16 10:07 UTC (permalink / raw)
  To: Steve Taylor; +Cc: linux-mips


Steve

> c) Do you think locking out, say, an entire way of a 4-way cache for
>    a dedicated frequently used routine improves or degrades overall
>    system performance?

It usually degrades performance, and is likely to go horribly wrong.

Look around and I expect you can find a better way to turn your effort
into higher performance!

--
Dominic Sweetman
dom@mips.com

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: Basic cache questions
  2003-04-15 22:19 Basic cache questions Steve Taylor
  2003-04-15 23:40 ` Jun Sun
  2003-04-16 10:07 ` Dominic Sweetman
@ 2003-04-16 11:50 ` Ralf Baechle
  2 siblings, 0 replies; 4+ messages in thread
From: Ralf Baechle @ 2003-04-16 11:50 UTC (permalink / raw)
  To: Steve Taylor; +Cc: linux-mips

On Tue, Apr 15, 2003 at 03:19:14PM -0700, Steve Taylor wrote:

> Hello All,   I am hoping some of you mips-linux gurus will be able to
> help me give me some tips and help me get started on some cache stuff which
> I want to do. (I know decently well about caches - but only at a
> theoretical Hennessy & Patterson level - and have just started looking
> under arch/mips/mm to familiarize myself with the mips-linux
> implementation).   Here's what I want to do - I have a CPU with 4 way SA I
> and D caches, and I want to write a module that will lock a certain memory
> region in these caches (for example, let's say I want to lock the ISR in
> the I-cache). So my questions are

> a) Is the kernel going to crash if I try to mess around with the caches
> like locking out a particular way of the cache or something like that?

> b) I'm sure there are many issues and
> complications involved in this that I probably havent even thought of  -
> any obvious and/or subtle pitfalls? and c) Do you think locking out, say,
> an entire way of a 4-way cache for a dedicated frequently used routine
> improves or degrades overall system performance?

General wisdom says locking is rarely a win but a loss unless you have
particularly pathological access patterns which is not so likely with a
4-way cache.  Cache locking is primarily useful if you are doing hard
realtime stuff and need execution time deterministic to the absolute
technical limit - even if at cost of latency and throughput.  Linux
being a general purpose UNIX clone is hardly the OS for such an
application ...

  Ralf

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2003-04-16 11:50 UTC | newest]

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2003-04-15 22:19 Basic cache questions Steve Taylor
2003-04-15 23:40 ` Jun Sun
2003-04-16 10:07 ` Dominic Sweetman
2003-04-16 11:50 ` Ralf Baechle

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