wired tlb entry?

wired tlb entry?

[Joseph Chiu]

Hi,
Is there a (proper) way to add a page entry in the TLB it's always valid?
Specifically, accesses to memory-mapped hardware (PCMCIA) causes the kernel
to oops under heavy interrupt loading.
It seems to me that the page entry in the TLB is getting flushed out under
the activity; and when the ioremap'd memory region is accesses, the
exception handling for the missing translation does not run.

I'm afraid my two days of googling hasn't turned up the right information.
I think I just don't know the right terminology and I hope someone can at
least point me in the right direction.
Thanks.
Joseph
(I am running 2.4.18-mips)



--
Joseph Chiu, Senior Engineer, Omnilux, Inc.
joseph@omnilux.net  (626) 535-2819
The sun will come up tomorrow.  Bet your bottom dollar that tomorrow,
things'll be back.

Re: wired tlb entry?

[Pete Popov]

On Mon, 2003-06-16 at 17:36, Joseph Chiu wrote:
> Hi,
> Is there a (proper) way to add a page entry in the TLB it's always valid?
> Specifically, accesses to memory-mapped hardware (PCMCIA) causes the kernel
> to oops under heavy interrupt loading.
> It seems to me that the page entry in the TLB is getting flushed out under
> the activity; and when the ioremap'd memory region is accesses, the
> exception handling for the missing translation does not run.
> 
> I'm afraid my two days of googling hasn't turned up the right information.
> I think I just don't know the right terminology and I hope someone can at
> least point me in the right direction.
> Thanks.
> Joseph
> (I am running 2.4.18-mips)

So is this a kernel from linux-mips.org?  Are you using the 36 bit I/O
patch in that kernel, or the pseudo-address translation hack that I
removed later? What pcmcia I/O card are you using and what tests are you
running?

Pete

RE: wired tlb entry?

[Joseph Chiu]

(Sorry for the double-send of the original inquiry to the list -- I actually
got bounce notices from my mailer...)

This is the kernel from almost a year ago with the changes you made to
support the 36-bit phys addr. access on the Au1xxx.
The Au1x00 PCMCIA (CS release 3.1.22) initialization maps phys_mem f80000000
to virt_io c0000000.

I am running HostAP (0.0.3) on top of this PCMCIA support, using a
Prism3-based WiFi card.

During transmit/receive activity, the hardware interrupt invokes the
prism2_interrupt() in hostap_cs.o which, in turn reads and writes from
registers using the virtual i/o address of c0000000.

Under light and moderate loading, there are no problems.  After heavy
traffic loads, the system eventually dies with accesses to address c000xxxx
(one address gets hit 95% of the time - and there were other addresses a few
other times, but always in the c000xxxx address range).

Thanks,
Joseph

-----Original Message-----
From: Pete Popov [mailto:ppopov@mvista.com]
Sent: Tuesday, June 17, 2003 10:19 AM
To: Joseph Chiu
Cc: Linux MIPS mailing list
Subject: Re: wired tlb entry?


On Mon, 2003-06-16 at 17:36, Joseph Chiu wrote:
> Hi,
> Is there a (proper) way to add a page entry in the TLB it's always valid?
> Specifically, accesses to memory-mapped hardware (PCMCIA) causes the
kernel
> to oops under heavy interrupt loading.
> It seems to me that the page entry in the TLB is getting flushed out under
> the activity; and when the ioremap'd memory region is accesses, the
> exception handling for the missing translation does not run.
>
> I'm afraid my two days of googling hasn't turned up the right information.
> I think I just don't know the right terminology and I hope someone can at
> least point me in the right direction.
> Thanks.
> Joseph
> (I am running 2.4.18-mips)

So is this a kernel from linux-mips.org?  Are you using the 36 bit I/O
patch in that kernel, or the pseudo-address translation hack that I
removed later? What pcmcia I/O card are you using and what tests are you
running?

Pete

RE: wired tlb entry?

[Pete Popov]

Any chance you can try 2.4.21-pre4 (latest linux-mips) before we go any
further?

Pete

On Tue, 2003-06-17 at 11:12, Joseph Chiu wrote:
> (Sorry for the double-send of the original inquiry to the list -- I actually
> got bounce notices from my mailer...)
> 
> This is the kernel from almost a year ago with the changes you made to
> support the 36-bit phys addr. access on the Au1xxx.
> The Au1x00 PCMCIA (CS release 3.1.22) initialization maps phys_mem f80000000
> to virt_io c0000000.
> 
> I am running HostAP (0.0.3) on top of this PCMCIA support, using a
> Prism3-based WiFi card.
> 
> During transmit/receive activity, the hardware interrupt invokes the
> prism2_interrupt() in hostap_cs.o which, in turn reads and writes from
> registers using the virtual i/o address of c0000000.
> 
> Under light and moderate loading, there are no problems.  After heavy
> traffic loads, the system eventually dies with accesses to address c000xxxx
> (one address gets hit 95% of the time - and there were other addresses a few
> other times, but always in the c000xxxx address range).
> 
> Thanks,
> Joseph
> 
> -----Original Message-----
> From: Pete Popov [mailto:ppopov@mvista.com]
> Sent: Tuesday, June 17, 2003 10:19 AM
> To: Joseph Chiu
> Cc: Linux MIPS mailing list
> Subject: Re: wired tlb entry?
> 
> 
> On Mon, 2003-06-16 at 17:36, Joseph Chiu wrote:
> > Hi,
> > Is there a (proper) way to add a page entry in the TLB it's always valid?
> > Specifically, accesses to memory-mapped hardware (PCMCIA) causes the
> kernel
> > to oops under heavy interrupt loading.
> > It seems to me that the page entry in the TLB is getting flushed out under
> > the activity; and when the ioremap'd memory region is accesses, the
> > exception handling for the missing translation does not run.
> >
> > I'm afraid my two days of googling hasn't turned up the right information.
> > I think I just don't know the right terminology and I hope someone can at
> > least point me in the right direction.
> > Thanks.
> > Joseph
> > (I am running 2.4.18-mips)
> 
> So is this a kernel from linux-mips.org?  Are you using the 36 bit I/O
> patch in that kernel, or the pseudo-address translation hack that I
> removed later? What pcmcia I/O card are you using and what tests are you
> running?
> 
> Pete
> 
> 
> 

RE: wired tlb entry?

[Joseph Chiu]

Michael Guo suggested add_wired_entry -- I'm giving that a try now.  I'm
trying to stick to "the kernel that we trust" (from the perspective here)
because I'm worried about what I end up breaking trying to take a new
kernel.

I am behind the time, though, so I'll try to test out 2.4.21-pre4 when I get
back (I'm not available to run the tests during the rest of this week).

Thanks,
Joseph

-----Original Message-----
From: Pete Popov [mailto:ppopov@mvista.com]
Sent: Tuesday, June 17, 2003 11:17 AM
To: Joseph Chiu
Cc: Linux MIPS mailing list
Subject: RE: wired tlb entry?



Any chance you can try 2.4.21-pre4 (latest linux-mips) before we go any
further?

Pete

On Tue, 2003-06-17 at 11:12, Joseph Chiu wrote:
> (Sorry for the double-send of the original inquiry to the list -- I
actually
> got bounce notices from my mailer...)
>
> This is the kernel from almost a year ago with the changes you made to
> support the 36-bit phys addr. access on the Au1xxx.
> The Au1x00 PCMCIA (CS release 3.1.22) initialization maps phys_mem
f80000000
> to virt_io c0000000.
>
> I am running HostAP (0.0.3) on top of this PCMCIA support, using a
> Prism3-based WiFi card.
>
> During transmit/receive activity, the hardware interrupt invokes the
> prism2_interrupt() in hostap_cs.o which, in turn reads and writes from
> registers using the virtual i/o address of c0000000.
>
> Under light and moderate loading, there are no problems.  After heavy
> traffic loads, the system eventually dies with accesses to address
c000xxxx
> (one address gets hit 95% of the time - and there were other addresses a
few
> other times, but always in the c000xxxx address range).
>
> Thanks,
> Joseph
>
> -----Original Message-----
> From: Pete Popov [mailto:ppopov@mvista.com]
> Sent: Tuesday, June 17, 2003 10:19 AM
> To: Joseph Chiu
> Cc: Linux MIPS mailing list
> Subject: Re: wired tlb entry?
>
>
> On Mon, 2003-06-16 at 17:36, Joseph Chiu wrote:
> > Hi,
> > Is there a (proper) way to add a page entry in the TLB it's always
valid?
> > Specifically, accesses to memory-mapped hardware (PCMCIA) causes the
> kernel
> > to oops under heavy interrupt loading.
> > It seems to me that the page entry in the TLB is getting flushed out
under
> > the activity; and when the ioremap'd memory region is accesses, the
> > exception handling for the missing translation does not run.
> >
> > I'm afraid my two days of googling hasn't turned up the right
information.
> > I think I just don't know the right terminology and I hope someone can
at
> > least point me in the right direction.
> > Thanks.
> > Joseph
> > (I am running 2.4.18-mips)
>
> So is this a kernel from linux-mips.org?  Are you using the 36 bit I/O
> patch in that kernel, or the pseudo-address translation hack that I
> removed later? What pcmcia I/O card are you using and what tests are you
> running?
>
> Pete
>
>
>

Re: wired tlb entry?

[Ralf Baechle]

On Tue, Jun 17, 2003 at 11:51:13AM -0700, Joseph Chiu wrote:

> Michael Guo suggested add_wired_entry -- I'm giving that a try now.  I'm
> trying to stick to "the kernel that we trust" (from the perspective here)
> because I'm worried about what I end up breaking trying to take a new
> kernel.
> 
> I am behind the time, though, so I'll try to test out 2.4.21-pre4 when I get
> back (I'm not available to run the tests during the rest of this week).

Usual warning - wired entries are almost always a bad idea.  TLB entries
are a scarce resource and wiring will reduce the number available for
random replacement even further raising the amount of CPU burned in the
TLB reload handler.

  Ralf

RE: wired tlb entry?

[Joseph Chiu]

On Tuesday, June 24, 2003 9:59 PM Ralf Baechle wrote:

> Usual warning - wired entries are almost always a bad idea.  TLB entries
> are a scarce resource and wiring will reduce the number available for
> random replacement even further raising the amount of CPU burned in the
> TLB reload handler.

Thanks Ralf.  It is "just one" wired global TLB entry (admiteddly, out of a
paltry 32).   Using the wired entry has fixed the immediate problem at hand,
so I decided it's worth it for now.

Joseph

Re: wired tlb entry?

[Steven J. Hill]

Joseph Chiu wrote:
> 
> Thanks Ralf.  It is "just one" wired global TLB entry (admiteddly, out of a
> paltry 32).   Using the wired entry has fixed the immediate problem at hand,
> so I decided it's worth it for now.
> 
If you can, which board is this on?

-Steve

RE: wired tlb entry?

[Joseph Chiu]

This is on our own board.  We're developing a optical wireless transceiver
system (see www.omnilux.net) and we use the Au1000 as the central
controller.

It's a pretty simple board -- the au1000 static bus interfaces connects to
FLASH, and two external peripheral devices; one of them being a PCMCIA card.
(We put the card directly on the bus -- no "end user proofing" buffers or
any such things).

The non-PCMCIA peripheral sits within the directly accessible low memory
range.  In fact, outside of user pages, the only thing that needs TLB is the
small windows pointing to the PCMCIA card.

Joseph
-----Original Message-----
From: Steven J. Hill [mailto:sjhill@realitydiluted.com]
Sent: Thursday, June 26, 2003 6:02 PM
To: Joseph Chiu
Cc: Ralf Baechle; Pete Popov; Linux MIPS mailing list
Subject: Re: wired tlb entry?


Joseph Chiu wrote:
>
> Thanks Ralf.  It is "just one" wired global TLB entry (admiteddly, out of
a
> paltry 32).   Using the wired entry has fixed the immediate problem at
hand,
> so I decided it's worth it for now.
>
If you can, which board is this on?

-Steve

Re: wired tlb entry?

[Guo Michael]

Hi! You can use add_wired_entry(unsigned long entrylo0, unsigned long 
entrylo1, unsigned long entryhi, unsigned long pagemask);

for more information you can check include/asm-mips/pgtable.h


-Michael

>From: "Joseph Chiu" <joseph@omnilux.net>
>To: "Linux-MIPS" <linux-mips@linux-mips.org>
>Subject: wired tlb entry?
>Date: Mon, 16 Jun 2003 17:36:58 -0700
>
>Hi,
>Is there a (proper) way to add a page entry in the TLB it's always valid?
>Specifically, accesses to memory-mapped hardware (PCMCIA) causes the 
kernel
>to oops under heavy interrupt loading.
>It seems to me that the page entry in the TLB is getting flushed out under
>the activity; and when the ioremap'd memory region is accesses, the
>exception handling for the missing translation does not run.
>
>I'm afraid my two days of googling hasn't turned up the right information.
>I think I just don't know the right terminology and I hope someone can at
>least point me in the right direction.
>Thanks.
>Joseph
>(I am running 2.4.18-mips)
>
>
>
>--
>Joseph Chiu, Senior Engineer, Omnilux, Inc.
>joseph@omnilux.net  (626) 535-2819
>The sun will come up tomorrow.  Bet your bottom dollar that tomorrow,
>things'll be back.
>
>

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bootloader problem

[He Jin]

Hi, everybody,

I met a problem when debuging a bootloader in IT8172G+RM5231A platform, it's like this:

the bootloader had 2 parts, the first part executes in ROM (0xbfc00000-0xbfc0xxxx) and
it move another part from ROM into SDRAM, then jump to the SDRAM entry point to continue.

In the ROM resident code, if I initialized&flushed the cache, it can jump to SDRAM entry
continue normally. However,if I comment out those cache related code and make cache disabled, 
it seems can not jump to SDRAM entry. 

Who can tell me why I must initialize&flush when cache disabled ? 

Thanks a lot!

He Jin	

Wired TLB entry?

[Joseph Chiu]

Hi,
Is there a (proper) way to add a page entry in the TLB it's always valid?
Specifically, accesses to memory-mapped hardware (PCMCIA) causes the kernel
to oops under heavy interrupt loading.
It seems to me that the page entry in the TLB is getting flushed out under
the activity; and when the ioremap'd memory region is accesses, the
exception handling for the missing translation does not run.

I'm afraid my two days of googling hasn't turned up the right information.
I think I just don't know the right terminology and I hope someone can at
least point me in the right direction.
Thanks.
Joseph
(I am running 2.4.18)

Wired TLB entry?

[Joseph Chiu]

Hi,
Is there a (proper) way to add a page entry in the TLB it's always valid?
Specifically, accesses to memory-mapped hardware (PCMCIA) causes the kernel
to oops under heavy interrupt loading.
It seems to me that the page entry in the TLB is getting flushed out under
the activity; and when the ioremap'd memory region is accesses, the
exception handling for the missing translation does not run.

I'm afraid my two days of googling hasn't turned up the right information.
I think I just don't know the right terminology and I hope someone can at
least point me in the right direction.
Thanks.
Joseph
(I am running 2.4.18)