* "sel" field in MTC0 instruction?
@ 2003-10-14 5:46 Babbellapati Syam Krishna (IFIN DC COM)
2003-10-14 5:46 ` Babbellapati Syam Krishna (IFIN DC COM)
2003-10-14 7:13 ` Ralf Baechle
0 siblings, 2 replies; 6+ messages in thread
From: Babbellapati Syam Krishna (IFIN DC COM) @ 2003-10-14 5:46 UTC (permalink / raw)
To: 'linux-mips@linux-mips.org'
[-- Attachment #1: Type: text/plain, Size: 2354 bytes --]
Hi there,
I am running linux on a MIPS64 5kc processor. From the Data Sheet and
Software User's manual, I could see that we can access the various MIPS
Performance Counters (Coprocessor 0, Register 25) by using the "sel" field
of the MTC0 or MFC0 registers.
Format: MTC0 rt, rd
(OR) MTC0 rt, rd, sel
Based on the second format, I have written a new assembly languauge routine:
#define write_32bit_cp0_performance_register(register,value) \
__asm__ __volatile__( \
"mtc0\t%0,"STR(register)",sel\n\t" \
"nop" \
: : "r" (value));
"sel" in the above assembly instruction is a value of either 0, 1, 2 or 3
based on the register which we would like to write.
"sel" in the above code is newly introduced by us and if there is no sel
then the code compiles properly but I guess we would always be accessing one
register only in that case.
(A similar routine is written using "mfc0" also for reading the values
back.)
But this code results in a compilation error:
{standard input}: Assembler messages:
{standard input}:41: Error: illegal operands `mtc0 $3,$25,0'
{standard input}:45: Error: illegal operands `mfc0 $5,$25,1'
where $25 is CP0_PERFORMANCE register.
The command used for compilation is:
mipsel-linux-gcc -c -I /home/syam/linux-2.4.20with095LTT/include/ -Wall -O2
-fomit-frame-pointer -fno-common -finline-limit=5000 -G 0 -mno-abicalls
-fno-pic -mcpu=r4600 -mips2 -pipe -DMODULE -mlong-calls tempCache.c
Could someone help me in making me understand what is wrong here? Is it a
problem with the syntax of the arguments or is there an assembler support
which I am lacking for such an instruction?
Any kind of pointers would be of help.
Thank you,
Syam
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^ permalink raw reply [flat|nested] 6+ messages in thread
* "sel" field in MTC0 instruction?
2003-10-14 5:46 "sel" field in MTC0 instruction? Babbellapati Syam Krishna (IFIN DC COM)
@ 2003-10-14 5:46 ` Babbellapati Syam Krishna (IFIN DC COM)
2003-10-14 7:13 ` Ralf Baechle
1 sibling, 0 replies; 6+ messages in thread
From: Babbellapati Syam Krishna (IFIN DC COM) @ 2003-10-14 5:46 UTC (permalink / raw)
To: 'linux-mips@linux-mips.org'
[-- Attachment #1: Type: text/plain, Size: 2354 bytes --]
Hi there,
I am running linux on a MIPS64 5kc processor. From the Data Sheet and
Software User's manual, I could see that we can access the various MIPS
Performance Counters (Coprocessor 0, Register 25) by using the "sel" field
of the MTC0 or MFC0 registers.
Format: MTC0 rt, rd
(OR) MTC0 rt, rd, sel
Based on the second format, I have written a new assembly languauge routine:
#define write_32bit_cp0_performance_register(register,value) \
__asm__ __volatile__( \
"mtc0\t%0,"STR(register)",sel\n\t" \
"nop" \
: : "r" (value));
"sel" in the above assembly instruction is a value of either 0, 1, 2 or 3
based on the register which we would like to write.
"sel" in the above code is newly introduced by us and if there is no sel
then the code compiles properly but I guess we would always be accessing one
register only in that case.
(A similar routine is written using "mfc0" also for reading the values
back.)
But this code results in a compilation error:
{standard input}: Assembler messages:
{standard input}:41: Error: illegal operands `mtc0 $3,$25,0'
{standard input}:45: Error: illegal operands `mfc0 $5,$25,1'
where $25 is CP0_PERFORMANCE register.
The command used for compilation is:
mipsel-linux-gcc -c -I /home/syam/linux-2.4.20with095LTT/include/ -Wall -O2
-fomit-frame-pointer -fno-common -finline-limit=5000 -G 0 -mno-abicalls
-fno-pic -mcpu=r4600 -mips2 -pipe -DMODULE -mlong-calls tempCache.c
Could someone help me in making me understand what is wrong here? Is it a
problem with the syntax of the arguments or is there an assembler support
which I am lacking for such an instruction?
Any kind of pointers would be of help.
Thank you,
Syam
----------------------------------------------------------------------------
-------------
*Disclaimer*
"This e-mail and any attachments are confidential and may contain trade
secrets or privileged or undisclosed information. They may also be subject
to copyright protection. Please do not copy, distribute or forward this
email to anyone unless authorized. If you are not a named addressee, you
must not use, disclose, retain or reproduce all or any part of the
information contained in this e-mail or any attachments. If you have
received this email by mistake please notify the sender immediately by
return email and destroy/delete all copies of the email."
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: "sel" field in MTC0 instruction?
2003-10-14 5:46 "sel" field in MTC0 instruction? Babbellapati Syam Krishna (IFIN DC COM)
2003-10-14 5:46 ` Babbellapati Syam Krishna (IFIN DC COM)
@ 2003-10-14 7:13 ` Ralf Baechle
2003-10-14 7:13 ` Ralf Baechle
1 sibling, 1 reply; 6+ messages in thread
From: Ralf Baechle @ 2003-10-14 7:13 UTC (permalink / raw)
To: Babbellapati Syam Krishna (IFIN DC COM)
Cc: 'linux-mips@linux-mips.org'
On Tue, Oct 14, 2003 at 11:16:20AM +0530, Babbellapati Syam Krishna (IFIN DC COM) wrote:
> #define write_32bit_cp0_performance_register(register,value) \
> __asm__ __volatile__( \
> "mtc0\t%0,"STR(register)",sel\n\t" \
> "nop" \
> : : "r" (value));
Which seems to be dervied from an old function which was eleminated months
ago. Checkout a current mipsregs.h - which also accesses register with
a non-zero selector value.
> "sel" in the above assembly instruction is a value of either 0, 1, 2 or 3
> based on the register which we would like to write.
> "sel" in the above code is newly introduced by us and if there is no sel
> then the code compiles properly but I guess we would always be accessing one
> register only in that case.
> (A similar routine is written using "mfc0" also for reading the values
> back.)
>
> But this code results in a compilation error:
> {standard input}: Assembler messages:
> {standard input}:41: Error: illegal operands `mtc0 $3,$25,0'
> {standard input}:45: Error: illegal operands `mfc0 $5,$25,1'
> where $25 is CP0_PERFORMANCE register.
>
> The command used for compilation is:
> mipsel-linux-gcc -c -I /home/syam/linux-2.4.20with095LTT/include/ -Wall -O2
> -fomit-frame-pointer -fno-common -finline-limit=5000 -G 0 -mno-abicalls
> -fno-pic -mcpu=r4600 -mips2 -pipe -DMODULE -mlong-calls tempCache.c
The mtc/mfc syntax is MIP32, didn't exist in MIPS III.
> *Disclaimer*
> "This e-mail and any attachments are confidential and may contain trade
> secrets or privileged or undisclosed information. They may also be subject
> to copyright protection. Please do not copy, distribute or forward this
> email to anyone unless authorized. If you are not a named addressee, you
> must not use, disclose, retain or reproduce all or any part of the
> information contained in this e-mail or any attachments. If you have
> received this email by mistake please notify the sender immediately by
> return email and destroy/delete all copies of the email."
Please print a hardcopy of this my answer, then eat it up because it's
confidential ;-)
Any and all email sent to this list will be archived and published
immediately no matter what bullshit disclaimer is attached.
Ralf
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: "sel" field in MTC0 instruction?
2003-10-14 7:13 ` Ralf Baechle
@ 2003-10-14 7:13 ` Ralf Baechle
0 siblings, 0 replies; 6+ messages in thread
From: Ralf Baechle @ 2003-10-14 7:13 UTC (permalink / raw)
To: Babbellapati Syam Krishna (IFIN DC COM)
Cc: 'linux-mips@linux-mips.org'
On Tue, Oct 14, 2003 at 11:16:20AM +0530, Babbellapati Syam Krishna (IFIN DC COM) wrote:
> #define write_32bit_cp0_performance_register(register,value) \
> __asm__ __volatile__( \
> "mtc0\t%0,"STR(register)",sel\n\t" \
> "nop" \
> : : "r" (value));
Which seems to be dervied from an old function which was eleminated months
ago. Checkout a current mipsregs.h - which also accesses register with
a non-zero selector value.
> "sel" in the above assembly instruction is a value of either 0, 1, 2 or 3
> based on the register which we would like to write.
> "sel" in the above code is newly introduced by us and if there is no sel
> then the code compiles properly but I guess we would always be accessing one
> register only in that case.
> (A similar routine is written using "mfc0" also for reading the values
> back.)
>
> But this code results in a compilation error:
> {standard input}: Assembler messages:
> {standard input}:41: Error: illegal operands `mtc0 $3,$25,0'
> {standard input}:45: Error: illegal operands `mfc0 $5,$25,1'
> where $25 is CP0_PERFORMANCE register.
>
> The command used for compilation is:
> mipsel-linux-gcc -c -I /home/syam/linux-2.4.20with095LTT/include/ -Wall -O2
> -fomit-frame-pointer -fno-common -finline-limit=5000 -G 0 -mno-abicalls
> -fno-pic -mcpu=r4600 -mips2 -pipe -DMODULE -mlong-calls tempCache.c
The mtc/mfc syntax is MIP32, didn't exist in MIPS III.
> *Disclaimer*
> "This e-mail and any attachments are confidential and may contain trade
> secrets or privileged or undisclosed information. They may also be subject
> to copyright protection. Please do not copy, distribute or forward this
> email to anyone unless authorized. If you are not a named addressee, you
> must not use, disclose, retain or reproduce all or any part of the
> information contained in this e-mail or any attachments. If you have
> received this email by mistake please notify the sender immediately by
> return email and destroy/delete all copies of the email."
Please print a hardcopy of this my answer, then eat it up because it's
confidential ;-)
Any and all email sent to this list will be archived and published
immediately no matter what bullshit disclaimer is attached.
Ralf
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: "sel" field in MTC0 instruction?
@ 2003-10-14 10:18 Babbellapati Syam Krishna (IFIN DC COM)
2003-10-14 10:18 ` Babbellapati Syam Krishna (IFIN DC COM)
0 siblings, 1 reply; 6+ messages in thread
From: Babbellapati Syam Krishna (IFIN DC COM) @ 2003-10-14 10:18 UTC (permalink / raw)
To: 'Ralf Baechle'; +Cc: 'linux-mips@linux-mips.org'
>> #define write_32bit_cp0_performance_register(register,value)
>\ __asm__
>> __volatile__( \ "mtc0\t%0,"STR(register)",sel\n\t" \
>> "nop" \
>> : : "r" (value));
>
>Which seems to be dervied from an old function which was
>eleminated months ago. Checkout a current mipsregs.h - which
>also accesses register with a non-zero selector value.
>
Thanks Ralf. I could get out of it.
Syam
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: "sel" field in MTC0 instruction?
2003-10-14 10:18 Babbellapati Syam Krishna (IFIN DC COM)
@ 2003-10-14 10:18 ` Babbellapati Syam Krishna (IFIN DC COM)
0 siblings, 0 replies; 6+ messages in thread
From: Babbellapati Syam Krishna (IFIN DC COM) @ 2003-10-14 10:18 UTC (permalink / raw)
To: 'Ralf Baechle'; +Cc: 'linux-mips@linux-mips.org'
>> #define write_32bit_cp0_performance_register(register,value)
>\ __asm__
>> __volatile__( \ "mtc0\t%0,"STR(register)",sel\n\t" \
>> "nop" \
>> : : "r" (value));
>
>Which seems to be dervied from an old function which was
>eleminated months ago. Checkout a current mipsregs.h - which
>also accesses register with a non-zero selector value.
>
Thanks Ralf. I could get out of it.
Syam
^ permalink raw reply [flat|nested] 6+ messages in thread
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2003-10-14 5:46 "sel" field in MTC0 instruction? Babbellapati Syam Krishna (IFIN DC COM)
2003-10-14 5:46 ` Babbellapati Syam Krishna (IFIN DC COM)
2003-10-14 7:13 ` Ralf Baechle
2003-10-14 7:13 ` Ralf Baechle
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2003-10-14 10:18 ` Babbellapati Syam Krishna (IFIN DC COM)
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