* Doubt in timer interrupt
@ 2004-01-22 7:24 karthikeyan natarajan
2004-01-22 7:41 ` Matthew Dharm
2004-01-22 8:43 ` Dominic Sweetman
0 siblings, 2 replies; 5+ messages in thread
From: karthikeyan natarajan @ 2004-01-22 7:24 UTC (permalink / raw)
To: linux-mips
Hi All,
In R4000 & descendent processors, interrupt number 7
is being used for internal timer interrupt. From this
i understand that the timer interrupt is also maskable
when the IE bit in status register is cleared. If
somebody mask this interrupt for a long time
erroneously, then won't there be a problem in
maintaining the system time?
Please correct me if i am wrong..
Does the system time is maintained via NMI?
Thanks in advance,
-karthi
=====
The expert at anything was once a beginner
______________________________
/ \
O / Karthikeyan.N \
O | Chennai, India. |
`\|||/' \ Mobile: +919884104346 /
(o o) \ /
_ ooO (_) Ooo____________________________________
_____|_____|_____|_____|_____|_____|_____|_____|_
__|_____|_____|_____|_____|_____|_____|_____|____
_____|_____|_____|_____|_____|_____|_____|_____|_
________________________________________________________________________
Yahoo! Messenger - Communicate instantly..."Ping"
your friends today! Download Messenger Now
http://uk.messenger.yahoo.com/download/index.html
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: Doubt in timer interrupt
2004-01-22 7:24 Doubt in timer interrupt karthikeyan natarajan
@ 2004-01-22 7:41 ` Matthew Dharm
2004-01-22 8:43 ` Dominic Sweetman
1 sibling, 0 replies; 5+ messages in thread
From: Matthew Dharm @ 2004-01-22 7:41 UTC (permalink / raw)
To: karthikeyan natarajan; +Cc: linux-mips
As with any timer interrupt, if you mask it too long you'll lose time.
Generally, masking interrupts via the IE bit is a bad idea.
Matt
On Thu, Jan 22, 2004 at 07:24:07AM +0000, karthikeyan natarajan wrote:
> Hi All,
>
> In R4000 & descendent processors, interrupt number 7
> is being used for internal timer interrupt. From this
> i understand that the timer interrupt is also maskable
> when the IE bit in status register is cleared. If
> somebody mask this interrupt for a long time
> erroneously, then won't there be a problem in
> maintaining the system time?
> Please correct me if i am wrong..
>
> Does the system time is maintained via NMI?
>
> Thanks in advance,
> -karthi
>
> =====
> The expert at anything was once a beginner
> ______________________________
> / \
> O / Karthikeyan.N \
> O | Chennai, India. |
> `\|||/' \ Mobile: +919884104346 /
> (o o) \ /
> _ ooO (_) Ooo____________________________________
> _____|_____|_____|_____|_____|_____|_____|_____|_
> __|_____|_____|_____|_____|_____|_____|_____|____
> _____|_____|_____|_____|_____|_____|_____|_____|_
>
> ________________________________________________________________________
> Yahoo! Messenger - Communicate instantly..."Ping"
> your friends today! Download Messenger Now
> http://uk.messenger.yahoo.com/download/index.html
--
Matthew Dharm Work: mdharm@momenco.com
Senior Software Designer, Momentum Computer
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: Doubt in timer interrupt
2004-01-22 7:24 Doubt in timer interrupt karthikeyan natarajan
2004-01-22 7:41 ` Matthew Dharm
@ 2004-01-22 8:43 ` Dominic Sweetman
2004-01-22 9:27 ` karthikeyan natarajan
1 sibling, 1 reply; 5+ messages in thread
From: Dominic Sweetman @ 2004-01-22 8:43 UTC (permalink / raw)
To: karthikeyan natarajan; +Cc: linux-mips
Karthi,
> In R4000 & descendent processors, interrupt number 7
> is being used for internal timer interrupt. From this
> i understand that the timer interrupt is also maskable
> when the IE bit in status register is cleared. If
> somebody mask this interrupt for a long time
> erroneously, then won't there be a problem in
> maintaining the system time?
Yes, there may be a long delay. So the standard way of using the
onchip counter to generate a periodic interrupt is that the counter
itself is allowed to free-run, keeping accurate time.
The 'Compare' register is then incremented by a fixed amount.
So long as the interrupt is not delayed by a whole tick, this keeps
perfect time.
I'm sure this is described in "See MIPS Run" - do you have a copy?
--
Dominic Sweetman
MIPS Technologies Inc
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: Doubt in timer interrupt
2004-01-22 8:43 ` Dominic Sweetman
@ 2004-01-22 9:27 ` karthikeyan natarajan
2004-01-23 8:18 ` Dominic Sweetman
0 siblings, 1 reply; 5+ messages in thread
From: karthikeyan natarajan @ 2004-01-22 9:27 UTC (permalink / raw)
To: Dominic Sweetman; +Cc: linux-mips
Hi Dominic Sweetman,
Thanks much for your inputs..
> > In R4000 & descendent processors, interrupt
> number 7
> > is being used for internal timer interrupt. From
> this
> > i understand that the timer interrupt is also
> maskable
> > when the IE bit in status register is cleared. If
> > somebody mask this interrupt for a long time
> > erroneously, then won't there be a problem in
> > maintaining the system time?
>
> Yes, there may be a long delay. So the standard way
> of using the
> onchip counter to generate a periodic interrupt is
> that the counter
> itself is allowed to free-run, keeping accurate
> time.
>
> The 'Compare' register is then incremented by a
> fixed amount.
>
> So long as the interrupt is not delayed by a whole
> tick, this keeps
> perfect time.
>
> I'm sure this is described in "See MIPS Run" - do
> you have a copy?
Yes, i have a copy. Have just started reading
this book.. I yet to get into the deep waters of the
MIPS..
May i know the purpose of the NMI interrupt and
in what way it differ from the timer interrupt.
Thanks much,
-karthi
> --
> Dominic Sweetman
> MIPS Technologies Inc
>
>
>
=====
The expert at anything was once a beginner
______________________________
/ \
O / Karthikeyan.N \
O | Chennai, India. |
`\|||/' \ Mobile: +919884104346 /
(o o) \ /
_ ooO (_) Ooo____________________________________
_____|_____|_____|_____|_____|_____|_____|_____|_
__|_____|_____|_____|_____|_____|_____|_____|____
_____|_____|_____|_____|_____|_____|_____|_____|_
________________________________________________________________________
Yahoo! Messenger - Communicate instantly..."Ping"
your friends today! Download Messenger Now
http://uk.messenger.yahoo.com/download/index.html
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: Doubt in timer interrupt
2004-01-22 9:27 ` karthikeyan natarajan
@ 2004-01-23 8:18 ` Dominic Sweetman
0 siblings, 0 replies; 5+ messages in thread
From: Dominic Sweetman @ 2004-01-23 8:18 UTC (permalink / raw)
To: karthikeyan natarajan; +Cc: Dominic Sweetman, linux-mips
Karthi,
> May i know the purpose of the NMI interrupt and
> in what way it differ from the timer interrupt.
On MIPS CPUs the NMI is a sort of second-class reset. You could use
it for debugging and the kind of last-ditch everything-is-dead
watchdog interrupt you might use in a high-availability system.
Most systems don't connect it to anything.
It's not for use for regular device interrupts at all.
--
Dominic
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2004-01-23 8:18 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2004-01-22 7:24 Doubt in timer interrupt karthikeyan natarajan
2004-01-22 7:41 ` Matthew Dharm
2004-01-22 8:43 ` Dominic Sweetman
2004-01-22 9:27 ` karthikeyan natarajan
2004-01-23 8:18 ` Dominic Sweetman
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox