From: Ralf Baechle <ralf@linux-mips.org>
To: Lijun Chen <chenli@nortelnetworks.com>
Cc: linux-mips@linux-mips.org
Subject: Re: exception priority for BCM1250
Date: Wed, 31 Mar 2004 01:43:42 +0200 [thread overview]
Message-ID: <20040330234342.GB7543@linux-mips.org> (raw)
In-Reply-To: <4069F90D.9060903@americasm01.nt.com>
On Tue, Mar 30, 2004 at 05:47:41PM -0500, Lijun Chen wrote:
> Does anybody know which mips family SB1 core on bcm1250 falls into?
> It is a MIPS64 processor, does it belong to 5K family or 20Kc?
They're all MIPS64.
> What about the exception priorities, such as cache error exception, bus
> error exception, and so on? Are they maskable or non-maskable? It is not
> clear from BCM1250 and sb1 core manuals.
This is explained in the MIPS64 spec.
Ralf
next prev parent reply other threads:[~2004-03-30 23:43 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-03-30 22:47 exception priority for BCM1250 Lijun Chen
2004-03-30 23:38 ` Lijun Chen
2004-03-30 23:41 ` Ralf Baechle
2004-03-30 23:43 ` Ralf Baechle [this message]
2004-03-31 8:35 ` Dominic Sweetman
2004-03-31 15:39 ` Lijun Chen
2004-03-31 18:19 ` Jun Sun
2004-03-31 20:26 ` Lijun Chen
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