IOC3 interrupt management

IOC3 interrupt management

[Stanislaw Skowronek]

Well, there is a problem _again_. This time it's a purely conceptual one.

The IOC3 on Octanes (maybe on Onyx2es, too) controls the Ethernet, 
keyboard, mouse, serial and parallel ports and SGI alone knows what else.

It is also tied to (at least) two bridge interrupts. One is used solely
for Ethernet, and the other one is used for all the SuperIO stuff.

Well, I'm an educated man (when it comes to Octane internals, that is)
and I know that the first interrupt is 2 and the other is 4, and that they
map to IRQ10 and IRQ12, respectively. But how should the poor kernel know
about such arcanes? There is not a word in the IOC3 registers about this
weird connection so the PCI drivers don't know about it at all.

Now this is not a problem - I could simply assume that all IOC3s will have
another IRQ at irq_num+2. But, MENET of course is build of four IOC3s and
is definitely arranged in some other way. And what about the single IOC3
cards? Do they have the other IRQ at all, or don't they allow using
SuperIO?

This will all end in a kludge.

Stanislaw Skowronek

--<=>--
  "You're not as old as the trees, not as young as the leaves.
   Not as free as the breeze, not as open as the seas."

Re: IOC3 interrupt management

[Ralf Baechle]

On Tue, May 11, 2004 at 07:56:40PM +0200, Stanislaw Skowronek wrote:

> Well, there is a problem _again_. This time it's a purely conceptual one.
> 
> The IOC3 on Octanes (maybe on Onyx2es, too) controls the Ethernet, 
> keyboard, mouse, serial and parallel ports and SGI alone knows what else.
> 
> It is also tied to (at least) two bridge interrupts. One is used solely
> for Ethernet, and the other one is used for all the SuperIO stuff.
> 
> Well, I'm an educated man (when it comes to Octane internals, that is)
> and I know that the first interrupt is 2 and the other is 4, and that they
> map to IRQ10 and IRQ12, respectively. But how should the poor kernel know
> about such arcanes? There is not a word in the IOC3 registers about this
> weird connection so the PCI drivers don't know about it at all.
> 
> Now this is not a problem - I could simply assume that all IOC3s will have
> another IRQ at irq_num+2. But, MENET of course is build of four IOC3s and
> is definitely arranged in some other way. And what about the single IOC3
> cards? Do they have the other IRQ at all, or don't they allow using
> SuperIO?

PCI only permits INTA that is a single interrupt for normal devices.  In
good old tradition of violating the PCI spec the IOC3 has two interrupt
pins.  IP27 and IOC3 cards INTA and INTB are wired together, so we're back
to PCI compliance, no problem ...

So, Octane is different ...  I suggest you treat ethernet as a normal PCI
device - the Linux PCI code doesn't know how to handle anything else.  Then
in ioc3-eth.c itself you can register the serial interface with 8250.c
and using the appropriate interrupt number.  Everything along the lines of
MENET - but of course different ;-)

  Ralf

Re: IOC3 interrupt management

[Jan-Benedict Glaw]

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On Thu, 2004-05-13 02:14:05 +0200, Ralf Baechle <ralf@linux-mips.org>
wrote in message <20040513001405.GC18513@linux-mips.org>:
> On Tue, May 11, 2004 at 07:56:40PM +0200, Stanislaw Skowronek wrote:

> So, Octane is different ...  I suggest you treat ethernet as a normal PCI
> device - the Linux PCI code doesn't know how to handle anything else.  Then
> in ioc3-eth.c itself you can register the serial interface with 8250.c

Sig'ed.

MfG, JBG

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