titan code question

titan code question

[Thomas Koeller]

Hi Manish & Ralf,

the code below is from tian_ge.c:

	/*
	 * This is the 1.2 revision of the chip. It has fix for the
	 * IP header alignment. Now, the IP header begins at an
	 * aligned address and this wont need an extra copy in the
	 * driver. This performance drawback existed in the previous
	 * versions of the silicon
	 */
	reg_data_1 = TITAN_GE_READ(0x103c + (port_num << 12));
	reg_data_1 |= 0x40000000;
	TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);

	reg_data_1 |= 0x04000000;
	TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);

	mdelay(5);

	reg_data_1 &= ~(0x04000000);
	TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);

	mdelay(5);


According to the RM9000 user manual, register 0x103c (and 0x203c
and 0x303c), named TTPRI0, contains eight four-bit fields, each
of which is a packet priority value. This would be used to find
the priority for incoming packets.

Given the register description in the cpu manual, I cannot make
any sense of the code above. Whoever did that, would you care to
explain?

thanks,
Thomas
-- 
--------------------------------------------------

Thomas Koeller, Software Development
Basler Vision Technologies

thomas dot koeller at baslerweb dot com
http://www.baslerweb.com

==============================

Re: titan code question

[Manish Lachwani]

Hi Thomas,

This makes sense. Basically, in Titan 1.0 and 1.1, there was no support 
for IP header alignment. As a results, for every incoming packet, there 
had to be an extra copy in the driver. This had to be somehow fixed in 
the chip. So, the chip designers were basically looking for some unused 
registers that can be used to indicate to the chip that IP header needs 
aligning. And the chip designers wanted to implement this framework by 
using minimal possible changes so that 1.2 can be released asap.

Hence, they used this register. I am not sure if this is even 
documented. However, this code has been written based on the feedback 
from the chip designers. If you dont use this code, the MAC subsystem of 
titan will stop aligning IP headers and you will need to implement the 
code in the driver to do the aligning.

Hope this clears things.

Thanks
Manish Lachwani


Thomas Koeller wrote:
> Hi Manish & Ralf,
> 
> the code below is from tian_ge.c:
> 
> 	/*
> 	 * This is the 1.2 revision of the chip. It has fix for the
> 	 * IP header alignment. Now, the IP header begins at an
> 	 * aligned address and this wont need an extra copy in the
> 	 * driver. This performance drawback existed in the previous
> 	 * versions of the silicon
> 	 */
> 	reg_data_1 = TITAN_GE_READ(0x103c + (port_num << 12));
> 	reg_data_1 |= 0x40000000;
> 	TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
> 
> 	reg_data_1 |= 0x04000000;
> 	TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
> 
> 	mdelay(5);
> 
> 	reg_data_1 &= ~(0x04000000);
> 	TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
> 
> 	mdelay(5);
> 
> 
> According to the RM9000 user manual, register 0x103c (and 0x203c
> and 0x303c), named TTPRI0, contains eight four-bit fields, each
> of which is a packet priority value. This would be used to find
> the priority for incoming packets.
> 
> Given the register description in the cpu manual, I cannot make
> any sense of the code above. Whoever did that, would you care to
> explain?
> 
> thanks,
> Thomas

Re: titan code question

[Maciej W. Rozycki]

On Mon, 22 Nov 2004, Manish Lachwani wrote:

> Hence, they used this register. I am not sure if this is even 
> documented. However, this code has been written based on the feedback 
> from the chip designers. If you dont use this code, the MAC subsystem of 
> titan will stop aligning IP headers and you will need to implement the 
> code in the driver to do the aligning.

 That means you should use macros for registers and their contents,
preferably with some nearby documentation in the form of comments to
clarify less obvious bits.  Otherwise you end up with an unmaintainable
mess, especially once other sources of information drain out.

  Maciej

Re: titan code question

[Manish Lachwani]

Maciej W. Rozycki wrote:
> On Mon, 22 Nov 2004, Manish Lachwani wrote:
> 
> 
>>Hence, they used this register. I am not sure if this is even 
>>documented. However, this code has been written based on the feedback 
>>from the chip designers. If you dont use this code, the MAC subsystem of 
>>titan will stop aligning IP headers and you will need to implement the 
>>code in the driver to do the aligning.
> 
> 
>  That means you should use macros for registers and their contents,
> preferably with some nearby documentation in the form of comments to
> clarify less obvious bits.  Otherwise you end up with an unmaintainable
> mess, especially once other sources of information drain out.
> 
>   Maciej

I agree that we need to provide documentation :)

Thanks
Manish Lachwani