[PATCH] IDT Interprise Processor Support for Linux 2.6.x

Linux MIPS Architecture development
 help / color / mirror / Atom feed

* [PATCH] IDT Interprise Processor Support for Linux  2.6.x
@ 2006-03-10  1:08 Tiwari, Rakesh
  2006-03-10  5:15 ` Robin H. Johnson
  2006-03-10 17:45 ` Chris Wedgwood
  0 siblings, 2 replies; 6+ messages in thread
From: Tiwari, Rakesh @ 2006-03-10  1:08 UTC (permalink / raw)
  To: 'Ralf Baechle'; +Cc: linux-mips


[-- Attachment #1.1: Type: text/plain, Size: 362 bytes --]

Hi Ralf,

The attached patch adds support for the IDT Interprise series of processor 
based on the MIPS 4KC and Cronus (RC32300) core.

The patch is against the latest MIPS kernel linux-2.6.16-rc5. 

Look forward for your feedback/comments.

Regards
Rakesh

PS: Additional information regarding IDT's processor can be found at
http://www.idt.com/?catID=58532




[-- Attachment #1.2: Type: text/html, Size: 1038 bytes --]

[-- Attachment #2: idt_processor.patch --]
[-- Type: application/octet-stream, Size: 1461991 bytes --]

diff -uNr linux-2.6.16-rc5/arch/mips/configs/rc32334_defconfig idtlinux/arch/mips/configs/rc32334_defconfig
--- linux-2.6.16-rc5/arch/mips/configs/rc32334_defconfig	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/configs/rc32334_defconfig	2006-03-09 16:25:45.000000000 -0800
@@ -0,0 +1,969 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.16-rc5
+# Thu Mar  9 15:47:19 2006
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MIPS_MTX1 is not set
+# CONFIG_MIPS_BOSPORUS is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1100 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_MIPS_PB1550 is not set
+# CONFIG_MIPS_PB1200 is not set
+# CONFIG_MIPS_DB1000 is not set
+# CONFIG_MIPS_DB1100 is not set
+# CONFIG_MIPS_DB1500 is not set
+# CONFIG_MIPS_DB1550 is not set
+# CONFIG_MIPS_DB1200 is not set
+# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_IVR is not set
+CONFIG_IDT_BOARDS=y
+# CONFIG_MIPS_ITE8172 is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SEAD is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_MOMENCO_JAGUAR_ATX is not set
+# CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_MOMENCO_OCELOT_3 is not set
+# CONFIG_MOMENCO_OCELOT_C is not set
+# CONFIG_MOMENCO_OCELOT_G is not set
+# CONFIG_MIPS_XXS1500 is not set
+# CONFIG_PNX8550_V2PCI is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_DDB5074 is not set
+# CONFIG_DDB5476 is not set
+# CONFIG_DDB5477 is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_QEMU is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_PTSWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SNI_RM200_PCI is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_TOSHIBA_RBTX4927 is not set
+# CONFIG_TOSHIBA_RBTX4938 is not set
+# CONFIG_IDT_EB438 is not set
+# CONFIG_IDT_EB434 is not set
+# CONFIG_IDT_EB365 is not set
+# CONFIG_IDT_EB355 is not set
+CONFIG_IDT_S334=y
+CONFIG_IDT_BOARD_FREQ=75000000
+CONFIG_IDT_ZIMAGE_ADDR=0x80800000
+CONFIG_IDT_BOOT_NVRAM=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_BOOT_ELF32=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+
+#
+# CPU selection
+#
+# CONFIG_CPU_MIPS32_R1 is not set
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+CONFIG_CPU_RC32300=y
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+
+#
+# Kernel type
+#
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_CPU_HAS_PREFETCH=y
+# CONFIG_MIPS_MT is not set
+CONFIG_CPU_ADVANCED=y
+CONFIG_CPU_HAS_LLSC=y
+# CONFIG_CPU_HAS_WB is not set
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+# CONFIG_IKCONFIG_PROC is not set
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_EMBEDDED=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_HOTPLUG is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_BASE_FULL is not set
+# CONFIG_FUTEX is not set
+# CONFIG_EPOLL is not set
+CONFIG_SHMEM=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+# CONFIG_SLAB is not set
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=1
+CONFIG_SLOB=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+
+#
+# Block layer
+#
+# CONFIG_LBD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_LEGACY_PROC=y
+CONFIG_MMU=y
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PCI Hotplug Support
+#
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_TRAD_SIGNALS=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_NETDEBUG is not set
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+
+#
+# IP: Virtual Server Configuration
+#
+CONFIG_IP_VS=m
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_SH=m
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=m
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_IP_NF_CONNTRACK=m
+CONFIG_IP_NF_CT_ACCT=y
+CONFIG_IP_NF_CONNTRACK_MARK=y
+CONFIG_IP_NF_CONNTRACK_EVENTS=y
+CONFIG_IP_NF_CONNTRACK_NETLINK=m
+# CONFIG_IP_NF_CT_PROTO_SCTP is not set
+CONFIG_IP_NF_FTP=m
+CONFIG_IP_NF_IRC=m
+# CONFIG_IP_NF_NETBIOS_NS is not set
+CONFIG_IP_NF_TFTP=m
+CONFIG_IP_NF_AMANDA=m
+CONFIG_IP_NF_PPTP=m
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_IPRANGE=m
+CONFIG_IP_NF_MATCH_MULTIPORT=m
+CONFIG_IP_NF_MATCH_TOS=m
+CONFIG_IP_NF_MATCH_RECENT=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_DSCP=m
+CONFIG_IP_NF_MATCH_AH_ESP=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_MATCH_OWNER=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_HASHLIMIT=m
+CONFIG_IP_NF_MATCH_POLICY=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_IP_NF_TARGET_TCPMSS=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_SAME=m
+CONFIG_IP_NF_NAT_SNMP_BASIC=m
+CONFIG_IP_NF_NAT_IRC=m
+CONFIG_IP_NF_NAT_FTP=m
+CONFIG_IP_NF_NAT_TFTP=m
+CONFIG_IP_NF_NAT_AMANDA=m
+CONFIG_IP_NF_NAT_PPTP=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_TOS=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_DSCP=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# DCCP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+
+#
+# TIPC Configuration (EXPERIMENTAL)
+#
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+CONFIG_NET_SCHED=y
+# CONFIG_NET_SCH_CLK_JIFFIES is not set
+CONFIG_NET_SCH_CLK_GETTIMEOFDAY=y
+# CONFIG_NET_SCH_CLK_CPU is not set
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_INGRESS=m
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+# CONFIG_CLS_U32_PERF is not set
+# CONFIG_CLS_U32_MARK is not set
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_CLS_POLICE=y
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_ESTIMATOR=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_IEEE80211 is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_RAM is not set
+CONFIG_BLK_DEV_RAM_COUNT=16
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# PHY device support
+#
+# CONFIG_PHYLIB is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_DM9000 is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_DGRS is not set
+# CONFIG_EEPRO100 is not set
+CONFIG_E100=y
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_LAN_SAA9730 is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+# CONFIG_TELCLOCK is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Hardware Monitoring support
+#
+# CONFIG_HWMON is not set
+# CONFIG_HWMON_VID is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia Capabilities Port drivers
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
+# SN Devices
+#
+
+#
+# EDAC - error detection and reporting (RAS)
+#
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_RELAYFS_FS is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Hardware crypto devices
+#
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+CONFIG_CRC32=y
+CONFIG_LIBCRC32C=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
diff -uNr linux-2.6.16-rc5/arch/mips/configs/rc32355_defconfig idtlinux/arch/mips/configs/rc32355_defconfig
--- linux-2.6.16-rc5/arch/mips/configs/rc32355_defconfig	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/configs/rc32355_defconfig	2006-03-09 16:25:45.000000000 -0800
@@ -0,0 +1,940 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.16-rc5
+# Thu Mar  9 16:01:25 2006
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MIPS_MTX1 is not set
+# CONFIG_MIPS_BOSPORUS is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1100 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_MIPS_PB1550 is not set
+# CONFIG_MIPS_PB1200 is not set
+# CONFIG_MIPS_DB1000 is not set
+# CONFIG_MIPS_DB1100 is not set
+# CONFIG_MIPS_DB1500 is not set
+# CONFIG_MIPS_DB1550 is not set
+# CONFIG_MIPS_DB1200 is not set
+# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_IVR is not set
+CONFIG_IDT_BOARDS=y
+# CONFIG_MIPS_ITE8172 is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SEAD is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_MOMENCO_JAGUAR_ATX is not set
+# CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_MOMENCO_OCELOT_3 is not set
+# CONFIG_MOMENCO_OCELOT_C is not set
+# CONFIG_MOMENCO_OCELOT_G is not set
+# CONFIG_MIPS_XXS1500 is not set
+# CONFIG_PNX8550_V2PCI is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_DDB5074 is not set
+# CONFIG_DDB5476 is not set
+# CONFIG_DDB5477 is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_QEMU is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_PTSWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SNI_RM200_PCI is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_TOSHIBA_RBTX4927 is not set
+# CONFIG_TOSHIBA_RBTX4938 is not set
+# CONFIG_IDT_EB438 is not set
+# CONFIG_IDT_EB434 is not set
+# CONFIG_IDT_EB365 is not set
+CONFIG_IDT_EB355=y
+# CONFIG_IDT_S334 is not set
+CONFIG_IDT_BOARD_FREQ=75000000
+CONFIG_IDT_ZIMAGE_ADDR=0x8c000000
+# CONFIG_IDT_BOOT_NVRAM is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_BOOT_ELF32=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+
+#
+# CPU selection
+#
+# CONFIG_CPU_MIPS32_R1 is not set
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+CONFIG_CPU_RC32300=y
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+
+#
+# Kernel type
+#
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_CPU_HAS_PREFETCH=y
+# CONFIG_MIPS_MT is not set
+# CONFIG_CPU_ADVANCED is not set
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+# CONFIG_IKCONFIG_PROC is not set
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_EMBEDDED=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_HOTPLUG is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_BASE_FULL is not set
+# CONFIG_FUTEX is not set
+# CONFIG_EPOLL is not set
+CONFIG_SHMEM=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+# CONFIG_SLAB is not set
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=1
+CONFIG_SLOB=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+
+#
+# Block layer
+#
+# CONFIG_LBD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_MMU=y
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PCI Hotplug Support
+#
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_TRAD_SIGNALS=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_NETDEBUG is not set
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+
+#
+# IP: Virtual Server Configuration
+#
+CONFIG_IP_VS=m
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_SH=m
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=m
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_IP_NF_CONNTRACK=m
+CONFIG_IP_NF_CT_ACCT=y
+CONFIG_IP_NF_CONNTRACK_MARK=y
+CONFIG_IP_NF_CONNTRACK_EVENTS=y
+CONFIG_IP_NF_CONNTRACK_NETLINK=m
+# CONFIG_IP_NF_CT_PROTO_SCTP is not set
+CONFIG_IP_NF_FTP=m
+CONFIG_IP_NF_IRC=m
+# CONFIG_IP_NF_NETBIOS_NS is not set
+CONFIG_IP_NF_TFTP=m
+CONFIG_IP_NF_AMANDA=m
+CONFIG_IP_NF_PPTP=m
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_IPRANGE=m
+CONFIG_IP_NF_MATCH_MULTIPORT=m
+CONFIG_IP_NF_MATCH_TOS=m
+CONFIG_IP_NF_MATCH_RECENT=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_DSCP=m
+CONFIG_IP_NF_MATCH_AH_ESP=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_MATCH_OWNER=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_HASHLIMIT=m
+CONFIG_IP_NF_MATCH_POLICY=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_IP_NF_TARGET_TCPMSS=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_SAME=m
+CONFIG_IP_NF_NAT_SNMP_BASIC=m
+CONFIG_IP_NF_NAT_IRC=m
+CONFIG_IP_NF_NAT_FTP=m
+CONFIG_IP_NF_NAT_TFTP=m
+CONFIG_IP_NF_NAT_AMANDA=m
+CONFIG_IP_NF_NAT_PPTP=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_TOS=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_DSCP=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# DCCP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+
+#
+# TIPC Configuration (EXPERIMENTAL)
+#
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+CONFIG_NET_SCHED=y
+# CONFIG_NET_SCH_CLK_JIFFIES is not set
+CONFIG_NET_SCH_CLK_GETTIMEOFDAY=y
+# CONFIG_NET_SCH_CLK_CPU is not set
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_INGRESS=m
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+# CONFIG_CLS_U32_PERF is not set
+# CONFIG_CLS_U32_MARK is not set
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_CLS_POLICE=y
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_ESTIMATOR=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_IEEE80211 is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+CONFIG_BLK_DEV_RAM_COUNT=16
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# I2O device support
+#
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# PHY device support
+#
+CONFIG_PHYLIB=m
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_IDT_RC32355_ETH=y
+# CONFIG_DM9000 is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+
+#
+# Ethernet (10000 Mbit)
+#
+
+#
+# Token Ring devices
+#
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+# CONFIG_TELCLOCK is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_PCA_ISA is not set
+CONFIG_I2C_RC32355=y
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_RTC_X1205_I2C is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Hardware Monitoring support
+#
+# CONFIG_HWMON is not set
+# CONFIG_HWMON_VID is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia Capabilities Port drivers
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB_ARCH_HAS_HCD is not set
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# InfiniBand support
+#
+
+#
+# SN Devices
+#
+
+#
+# EDAC - error detection and reporting (RAS)
+#
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_RELAYFS_FS is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Hardware crypto devices
+#
+
+#
+# Library routines
+#
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=m
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
diff -uNr linux-2.6.16-rc5/arch/mips/configs/rc32365_defconfig idtlinux/arch/mips/configs/rc32365_defconfig
--- linux-2.6.16-rc5/arch/mips/configs/rc32365_defconfig	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/configs/rc32365_defconfig	2006-03-09 16:25:45.000000000 -0800
@@ -0,0 +1,1029 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.16-rc5
+# Thu Mar  9 16:13:13 2006
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MIPS_MTX1 is not set
+# CONFIG_MIPS_BOSPORUS is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1100 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_MIPS_PB1550 is not set
+# CONFIG_MIPS_PB1200 is not set
+# CONFIG_MIPS_DB1000 is not set
+# CONFIG_MIPS_DB1100 is not set
+# CONFIG_MIPS_DB1500 is not set
+# CONFIG_MIPS_DB1550 is not set
+# CONFIG_MIPS_DB1200 is not set
+# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_IVR is not set
+CONFIG_IDT_BOARDS=y
+# CONFIG_MIPS_ITE8172 is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SEAD is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_MOMENCO_JAGUAR_ATX is not set
+# CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_MOMENCO_OCELOT_3 is not set
+# CONFIG_MOMENCO_OCELOT_C is not set
+# CONFIG_MOMENCO_OCELOT_G is not set
+# CONFIG_MIPS_XXS1500 is not set
+# CONFIG_PNX8550_V2PCI is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_DDB5074 is not set
+# CONFIG_DDB5476 is not set
+# CONFIG_DDB5477 is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_QEMU is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_PTSWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SNI_RM200_PCI is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_TOSHIBA_RBTX4927 is not set
+# CONFIG_TOSHIBA_RBTX4938 is not set
+# CONFIG_IDT_EB438 is not set
+# CONFIG_IDT_EB434 is not set
+CONFIG_IDT_EB365=y
+# CONFIG_IDT_EB355 is not set
+# CONFIG_IDT_S334 is not set
+CONFIG_IDT_BOARD_FREQ=90000000
+CONFIG_IDT_ZIMAGE_ADDR=0x88000000
+# CONFIG_IDT_BOOT_NVRAM is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_BOOT_ELF32=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+
+#
+# CPU selection
+#
+# CONFIG_CPU_MIPS32_R1 is not set
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+CONFIG_CPU_RC32300=y
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+
+#
+# Kernel type
+#
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_CPU_HAS_PREFETCH=y
+# CONFIG_MIPS_MT is not set
+CONFIG_CPU_ADVANCED=y
+CONFIG_CPU_HAS_LLSC=y
+# CONFIG_CPU_HAS_WB is not set
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+# CONFIG_IKCONFIG_PROC is not set
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_EMBEDDED=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_HOTPLUG is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_BASE_FULL is not set
+# CONFIG_FUTEX is not set
+# CONFIG_EPOLL is not set
+CONFIG_SHMEM=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+# CONFIG_SLAB is not set
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=1
+CONFIG_SLOB=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+
+#
+# Block layer
+#
+# CONFIG_LBD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_LEGACY_PROC=y
+CONFIG_MMU=y
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PCI Hotplug Support
+#
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_TRAD_SIGNALS=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_NETDEBUG is not set
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+
+#
+# IP: Virtual Server Configuration
+#
+CONFIG_IP_VS=m
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_SH=m
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=m
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_IP_NF_CONNTRACK=m
+CONFIG_IP_NF_CT_ACCT=y
+CONFIG_IP_NF_CONNTRACK_MARK=y
+CONFIG_IP_NF_CONNTRACK_EVENTS=y
+CONFIG_IP_NF_CONNTRACK_NETLINK=m
+# CONFIG_IP_NF_CT_PROTO_SCTP is not set
+CONFIG_IP_NF_FTP=m
+CONFIG_IP_NF_IRC=m
+# CONFIG_IP_NF_NETBIOS_NS is not set
+CONFIG_IP_NF_TFTP=m
+CONFIG_IP_NF_AMANDA=m
+CONFIG_IP_NF_PPTP=m
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_IPRANGE=m
+CONFIG_IP_NF_MATCH_MULTIPORT=m
+CONFIG_IP_NF_MATCH_TOS=m
+CONFIG_IP_NF_MATCH_RECENT=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_DSCP=m
+CONFIG_IP_NF_MATCH_AH_ESP=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_MATCH_OWNER=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_HASHLIMIT=m
+CONFIG_IP_NF_MATCH_POLICY=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_IP_NF_TARGET_TCPMSS=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_SAME=m
+CONFIG_IP_NF_NAT_SNMP_BASIC=m
+CONFIG_IP_NF_NAT_IRC=m
+CONFIG_IP_NF_NAT_FTP=m
+CONFIG_IP_NF_NAT_TFTP=m
+CONFIG_IP_NF_NAT_AMANDA=m
+CONFIG_IP_NF_NAT_PPTP=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_TOS=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_DSCP=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# DCCP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+
+#
+# TIPC Configuration (EXPERIMENTAL)
+#
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+CONFIG_NET_SCHED=y
+# CONFIG_NET_SCH_CLK_JIFFIES is not set
+CONFIG_NET_SCH_CLK_GETTIMEOFDAY=y
+# CONFIG_NET_SCH_CLK_CPU is not set
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_INGRESS=m
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+# CONFIG_CLS_U32_PERF is not set
+# CONFIG_CLS_U32_MARK is not set
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_CLS_POLICE=y
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_ESTIMATOR=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_IEEE80211 is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_RAM is not set
+CONFIG_BLK_DEV_RAM_COUNT=16
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# PHY device support
+#
+CONFIG_PHYLIB=m
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_IDT_RC32365_ETH=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_DM9000 is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_DGRS is not set
+# CONFIG_EEPRO100 is not set
+CONFIG_E100=y
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_LAN_SAA9730 is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+# CONFIG_TELCLOCK is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_SCx200_ACB is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_ISA is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_RTC_X1205_I2C is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Hardware Monitoring support
+#
+# CONFIG_HWMON is not set
+# CONFIG_HWMON_VID is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia Capabilities Port drivers
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
+# SN Devices
+#
+
+#
+# EDAC - error detection and reporting (RAS)
+#
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_RELAYFS_FS is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Hardware crypto devices
+#
+
+#
+# Library routines
+#
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=m
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
diff -uNr linux-2.6.16-rc5/arch/mips/configs/rc32434_defconfig idtlinux/arch/mips/configs/rc32434_defconfig
--- linux-2.6.16-rc5/arch/mips/configs/rc32434_defconfig	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/configs/rc32434_defconfig	2006-03-09 16:25:45.000000000 -0800
@@ -0,0 +1,1032 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.16-rc5
+# Thu Mar  9 11:35:54 2006
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MIPS_MTX1 is not set
+# CONFIG_MIPS_BOSPORUS is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1100 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_MIPS_PB1550 is not set
+# CONFIG_MIPS_PB1200 is not set
+# CONFIG_MIPS_DB1000 is not set
+# CONFIG_MIPS_DB1100 is not set
+# CONFIG_MIPS_DB1500 is not set
+# CONFIG_MIPS_DB1550 is not set
+# CONFIG_MIPS_DB1200 is not set
+# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_IVR is not set
+CONFIG_IDT_BOARDS=y
+# CONFIG_MIPS_ITE8172 is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SEAD is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_MOMENCO_JAGUAR_ATX is not set
+# CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_MOMENCO_OCELOT_3 is not set
+# CONFIG_MOMENCO_OCELOT_C is not set
+# CONFIG_MOMENCO_OCELOT_G is not set
+# CONFIG_MIPS_XXS1500 is not set
+# CONFIG_PNX8550_V2PCI is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_DDB5074 is not set
+# CONFIG_DDB5476 is not set
+# CONFIG_DDB5477 is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_QEMU is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_PTSWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SNI_RM200_PCI is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_TOSHIBA_RBTX4927 is not set
+# CONFIG_TOSHIBA_RBTX4938 is not set
+# CONFIG_IDT_EB438 is not set
+CONFIG_IDT_EB434=y
+# CONFIG_IDT_EB365 is not set
+# CONFIG_IDT_EB355 is not set
+# CONFIG_IDT_S334 is not set
+CONFIG_IDT_BOARD_FREQ=200000000
+CONFIG_IDT_ZIMAGE_ADDR=0x9b000000
+# CONFIG_IDT_BOOT_NVRAM is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_BOOT_ELF32=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+
+#
+# CPU selection
+#
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPSR1=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+
+#
+# Kernel type
+#
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_CPU_HAS_PREFETCH=y
+# CONFIG_MIPS_MT is not set
+# CONFIG_64BIT_PHYS_ADDR is not set
+CONFIG_CPU_ADVANCED=y
+CONFIG_CPU_HAS_LLSC=y
+# CONFIG_CPU_HAS_WB is not set
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+# CONFIG_IKCONFIG_PROC is not set
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_EMBEDDED=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_HOTPLUG is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_BASE_FULL is not set
+# CONFIG_FUTEX is not set
+# CONFIG_EPOLL is not set
+CONFIG_SHMEM=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+# CONFIG_SLAB is not set
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=1
+CONFIG_SLOB=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+
+#
+# Block layer
+#
+# CONFIG_LBD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_LEGACY_PROC=y
+CONFIG_MMU=y
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PCI Hotplug Support
+#
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_TRAD_SIGNALS=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_NETDEBUG is not set
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+
+#
+# IP: Virtual Server Configuration
+#
+CONFIG_IP_VS=m
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_SH=m
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=m
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_IP_NF_CONNTRACK=m
+CONFIG_IP_NF_CT_ACCT=y
+CONFIG_IP_NF_CONNTRACK_MARK=y
+CONFIG_IP_NF_CONNTRACK_EVENTS=y
+CONFIG_IP_NF_CONNTRACK_NETLINK=m
+# CONFIG_IP_NF_CT_PROTO_SCTP is not set
+CONFIG_IP_NF_FTP=m
+CONFIG_IP_NF_IRC=m
+# CONFIG_IP_NF_NETBIOS_NS is not set
+CONFIG_IP_NF_TFTP=m
+CONFIG_IP_NF_AMANDA=m
+CONFIG_IP_NF_PPTP=m
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_IPRANGE=m
+CONFIG_IP_NF_MATCH_MULTIPORT=m
+CONFIG_IP_NF_MATCH_TOS=m
+CONFIG_IP_NF_MATCH_RECENT=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_DSCP=m
+CONFIG_IP_NF_MATCH_AH_ESP=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_MATCH_OWNER=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_HASHLIMIT=m
+CONFIG_IP_NF_MATCH_POLICY=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_IP_NF_TARGET_TCPMSS=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_SAME=m
+CONFIG_IP_NF_NAT_SNMP_BASIC=m
+CONFIG_IP_NF_NAT_IRC=m
+CONFIG_IP_NF_NAT_FTP=m
+CONFIG_IP_NF_NAT_TFTP=m
+CONFIG_IP_NF_NAT_AMANDA=m
+CONFIG_IP_NF_NAT_PPTP=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_TOS=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_DSCP=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# DCCP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+
+#
+# TIPC Configuration (EXPERIMENTAL)
+#
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+CONFIG_NET_SCHED=y
+# CONFIG_NET_SCH_CLK_JIFFIES is not set
+CONFIG_NET_SCH_CLK_GETTIMEOFDAY=y
+# CONFIG_NET_SCH_CLK_CPU is not set
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_INGRESS=m
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+# CONFIG_CLS_U32_PERF is not set
+# CONFIG_CLS_U32_MARK is not set
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_CLS_POLICE=y
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_ESTIMATOR=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_IEEE80211 is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_RAM is not set
+CONFIG_BLK_DEV_RAM_COUNT=16
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# PHY device support
+#
+CONFIG_PHYLIB=m
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_IDT_RC32434_ETH=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_DM9000 is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_DGRS is not set
+# CONFIG_EEPRO100 is not set
+CONFIG_E100=y
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_LAN_SAA9730 is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+# CONFIG_TELCLOCK is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_SCx200_ACB is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_ISA is not set
+CONFIG_I2C_RC32434=y
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_RTC_X1205_I2C is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Hardware Monitoring support
+#
+# CONFIG_HWMON is not set
+# CONFIG_HWMON_VID is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia Capabilities Port drivers
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
+# SN Devices
+#
+
+#
+# EDAC - error detection and reporting (RAS)
+#
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_RELAYFS_FS is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Hardware crypto devices
+#
+
+#
+# Library routines
+#
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=m
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
diff -uNr linux-2.6.16-rc5/arch/mips/configs/rc32438_defconfig idtlinux/arch/mips/configs/rc32438_defconfig
--- linux-2.6.16-rc5/arch/mips/configs/rc32438_defconfig	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/configs/rc32438_defconfig	2006-03-09 16:25:45.000000000 -0800
@@ -0,0 +1,982 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.16-rc5
+# Thu Mar  9 10:57:39 2006
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MIPS_MTX1 is not set
+# CONFIG_MIPS_BOSPORUS is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1100 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_MIPS_PB1550 is not set
+# CONFIG_MIPS_PB1200 is not set
+# CONFIG_MIPS_DB1000 is not set
+# CONFIG_MIPS_DB1100 is not set
+# CONFIG_MIPS_DB1500 is not set
+# CONFIG_MIPS_DB1550 is not set
+# CONFIG_MIPS_DB1200 is not set
+# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_IVR is not set
+CONFIG_IDT_BOARDS=y
+# CONFIG_MIPS_ITE8172 is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SEAD is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_MOMENCO_JAGUAR_ATX is not set
+# CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_MOMENCO_OCELOT_3 is not set
+# CONFIG_MOMENCO_OCELOT_C is not set
+# CONFIG_MOMENCO_OCELOT_G is not set
+# CONFIG_MIPS_XXS1500 is not set
+# CONFIG_PNX8550_V2PCI is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_DDB5074 is not set
+# CONFIG_DDB5476 is not set
+# CONFIG_DDB5477 is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_QEMU is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_PTSWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SNI_RM200_PCI is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_TOSHIBA_RBTX4927 is not set
+# CONFIG_TOSHIBA_RBTX4938 is not set
+CONFIG_IDT_EB438=y
+# CONFIG_RC32438_REVISION_ZA is not set
+# CONFIG_IDT_EB434 is not set
+# CONFIG_IDT_EB365 is not set
+# CONFIG_IDT_EB355 is not set
+# CONFIG_IDT_S334 is not set
+CONFIG_IDT_BOARD_FREQ=150000000
+CONFIG_IDT_ZIMAGE_ADDR=0x91000000
+# CONFIG_IDT_BOOT_NVRAM is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_BOOT_ELF32=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+
+#
+# CPU selection
+#
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPSR1=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+
+#
+# Kernel type
+#
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_CPU_HAS_PREFETCH=y
+# CONFIG_MIPS_MT is not set
+# CONFIG_64BIT_PHYS_ADDR is not set
+CONFIG_CPU_ADVANCED=y
+CONFIG_CPU_HAS_LLSC=y
+# CONFIG_CPU_HAS_WB is not set
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+# CONFIG_IKCONFIG_PROC is not set
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_EMBEDDED=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_HOTPLUG is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_BASE_FULL is not set
+# CONFIG_FUTEX is not set
+# CONFIG_EPOLL is not set
+CONFIG_SHMEM=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+# CONFIG_SLAB is not set
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=1
+CONFIG_SLOB=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+
+#
+# Block layer
+#
+# CONFIG_LBD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_LEGACY_PROC=y
+CONFIG_MMU=y
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PCI Hotplug Support
+#
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_TRAD_SIGNALS=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_NETDEBUG is not set
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+
+#
+# IP: Virtual Server Configuration
+#
+CONFIG_IP_VS=m
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_SH=m
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=m
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_IP_NF_CONNTRACK=m
+CONFIG_IP_NF_CT_ACCT=y
+CONFIG_IP_NF_CONNTRACK_MARK=y
+CONFIG_IP_NF_CONNTRACK_EVENTS=y
+CONFIG_IP_NF_CONNTRACK_NETLINK=m
+# CONFIG_IP_NF_CT_PROTO_SCTP is not set
+CONFIG_IP_NF_FTP=m
+CONFIG_IP_NF_IRC=m
+# CONFIG_IP_NF_NETBIOS_NS is not set
+CONFIG_IP_NF_TFTP=m
+CONFIG_IP_NF_AMANDA=m
+CONFIG_IP_NF_PPTP=m
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_IPRANGE=m
+CONFIG_IP_NF_MATCH_MULTIPORT=m
+CONFIG_IP_NF_MATCH_TOS=m
+CONFIG_IP_NF_MATCH_RECENT=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_DSCP=m
+CONFIG_IP_NF_MATCH_AH_ESP=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_MATCH_OWNER=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_HASHLIMIT=m
+CONFIG_IP_NF_MATCH_POLICY=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_IP_NF_TARGET_TCPMSS=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_SAME=m
+CONFIG_IP_NF_NAT_SNMP_BASIC=m
+CONFIG_IP_NF_NAT_IRC=m
+CONFIG_IP_NF_NAT_FTP=m
+CONFIG_IP_NF_NAT_TFTP=m
+CONFIG_IP_NF_NAT_AMANDA=m
+CONFIG_IP_NF_NAT_PPTP=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_TOS=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_DSCP=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# DCCP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+
+#
+# TIPC Configuration (EXPERIMENTAL)
+#
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+CONFIG_NET_SCHED=y
+# CONFIG_NET_SCH_CLK_JIFFIES is not set
+CONFIG_NET_SCH_CLK_GETTIMEOFDAY=y
+# CONFIG_NET_SCH_CLK_CPU is not set
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_INGRESS=m
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+# CONFIG_CLS_U32_PERF is not set
+# CONFIG_CLS_U32_MARK is not set
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_CLS_POLICE=y
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_ESTIMATOR=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_IEEE80211 is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_RAM is not set
+CONFIG_BLK_DEV_RAM_COUNT=16
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# PHY device support
+#
+CONFIG_PHYLIB=m
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_IDT_RC32438_ETH=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_DM9000 is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_DGRS is not set
+# CONFIG_EEPRO100 is not set
+CONFIG_E100=y
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_LAN_SAA9730 is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+# CONFIG_TELCLOCK is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Hardware Monitoring support
+#
+# CONFIG_HWMON is not set
+# CONFIG_HWMON_VID is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia Capabilities Port drivers
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
+# SN Devices
+#
+
+#
+# EDAC - error detection and reporting (RAS)
+#
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_RELAYFS_FS is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Hardware crypto devices
+#
+
+#
+# Library routines
+#
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=m
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/Kconfig idtlinux/arch/mips/idt-boards/Kconfig
--- linux-2.6.16-rc5/arch/mips/idt-boards/Kconfig	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/Kconfig	2006-03-09 16:25:51.000000000 -0800
@@ -0,0 +1,107 @@
+config IDT_EB438
+	bool " Support for the IDT 79EB438 evaluation board"
+	depends on IDT_BOARDS
+	select DMA_NONCOHERENT
+	select IRQ_CPU
+	select HW_HAS_PCI
+	select SWAP_IO_SPACE
+	select SYS_HAS_CPU_MIPS32_R1
+	select SYS_SUPPORTS_LITTLE_ENDIAN
+	select BOOT_ELF32
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_BIG_ENDIAN
+	help
+	 IDT evaluation board based on RC32438 Interprise Processor
+
+config RC32438_REVISION_ZA
+	bool " Support for ZA version"
+	depends on IDT_EB438
+	help
+	 Enable this option for enabling the workaround for the bugs
+	 in the ZA part.
+
+config IDT_EB434
+        bool " Support for the IDT 79EB434/435 evaluation board"
+        depends on IDT_BOARDS
+        select DMA_NONCOHERENT
+        select IRQ_CPU
+        select HW_HAS_PCI
+        select SWAP_IO_SPACE
+        select SYS_HAS_CPU_MIPS32_R1
+        select SYS_SUPPORTS_LITTLE_ENDIAN
+        select BOOT_ELF32
+        select SYS_SUPPORTS_32BIT_KERNEL
+        select SYS_SUPPORTS_BIG_ENDIAN
+        help
+         IDT evaluation board based on RC32434/435 Interprise Processor
+
+config IDT_EB365
+        bool " Support for the IDT 79EB365/336 based evaluation boards"
+        depends on IDT_BOARDS
+        select DMA_NONCOHERENT
+        select IRQ_CPU
+        select HW_HAS_PCI
+	select SYS_HAS_CPU_MIPS32_R1
+        select SYS_SUPPORTS_LITTLE_ENDIAN
+        select BOOT_ELF32
+        select SYS_SUPPORTS_32BIT_KERNEL
+        select SYS_SUPPORTS_BIG_ENDIAN
+        select SWAP_IO_SPACE
+        help
+         IDT evaluation boards based RC32300 core.
+
+config IDT_EB355
+        bool " Support for the IDT 79EB355 based evaluation boards"
+        depends on IDT_BOARDS
+        select DMA_NONCOHERENT
+        select IRQ_CPU
+        select SYS_HAS_CPU_MIPS32_R1
+        select SYS_SUPPORTS_LITTLE_ENDIAN
+        select BOOT_ELF32
+        select SYS_SUPPORTS_32BIT_KERNEL
+        select SYS_SUPPORTS_BIG_ENDIAN
+        select SWAP_IO_SPACE
+        help
+         IDT evaluation boards based RC32300 core.
+
+config IDT_S334
+        bool " Support for the IDT 79EB334 based evaluation boards"
+        depends on IDT_BOARDS
+        select DMA_NONCOHERENT
+        select IRQ_CPU
+        select HW_HAS_PCI
+        select SYS_SUPPORTS_LITTLE_ENDIAN
+	select SYS_HAS_CPU_MIPS32_R1
+        select BOOT_ELF32
+        select SYS_SUPPORTS_32BIT_KERNEL
+        select SYS_SUPPORTS_BIG_ENDIAN
+        select SWAP_IO_SPACE
+        help
+         IDT evaluation boards based RC32300 core.
+
+
+config  IDT_BOARD_FREQ
+        int "  Board Frequency (HZ)"
+        depends on IDT_EB438 || IDT_EB365 || IDT_EB434 || IDT_S334 || IDT_EB355
+        default 100000000 if IDT_EB434 || IDT_EB438
+        default 75000000 if IDT_EB355 || IDT_S334
+        default 90000000 if IDT_EB365
+        help
+         Specify the board frequency in Hz.
+
+config  IDT_ZIMAGE_ADDR
+        hex "  zImage Address"
+        depends on IDT_EB438 || IDT_EB355 || IDT_EB365 || IDT_EB434 || IDT_S334
+        default "0x88000000" if IDT_EB365 || IDT_EB438
+        default "0x9b000000" if IDT_EB434
+        default "0x8c000000" if IDT_EB355
+        default "0x80800000" if IDT_S334
+        help
+         You may create a compressed image by running 'make zImage' that can
+         either be loaded using the bootloader, or can be burned into the flash.
+         Specify the address where zImage will be loaded. The default address
+         is that of flash.
+
+config  IDT_BOOT_NVRAM
+        depends on IDT_EB438 || IDT_EB365 || IDT_EB434 || IDT_S334 || IDT_EB355
+        bool "  Enable reading environment variables from NVRAM"
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/csu_idt.S idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/csu_idt.S
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/csu_idt.S	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/csu_idt.S	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,285 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Board initialization code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+		
+
+#include <linux/config.h>
+#include <linux/threads.h>
+
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/asm-offsets.h>
+#include <asm/cachectl.h>
+#include "iregdef.h"
+#include "idtcpu.h"
+#include "idthdr.h"
+	
+#define  MHZ CONFIG_IDT_BOARD_FREQ
+
+#include "s364.h"		
+#include "s355ram.h"
+
+#define IndexInvalidate_I       0x00
+		
+/*--------------------------------------------------------------
+* prom entry point table
+*-------------------------------------------------------------*/
+
+FRAME(start,sp,0,ra)
+
+	j idtstart  /* begin monitor from start |00| */
+	
+idtstart:
+
+	.set noreorder
+	
+	mtc0  zero, C0_CAUSE
+	li    v0, 0x0
+	or    v0, (SR_CU0 | SR_BEV | SR_DE)
+	mtc0  v0, C0_SR
+
+	mfc0  v1, C0_CONFIG
+	li    v0, CFG_C_NCHRNT_WB  /* CFG_C_NCHRNT_WB  CFG_C_NCHRNT_WT_NWA CFG_C_UNCACHED */
+	and   v1, ~(0x7)
+	or    v1, v1, v0
+	mtc0  v1, C0_CONFIG
+	nop
+	nop
+	li    t0, ERR_CNTL_STATUS
+	lw    t1, 0(t0) 
+	li    t2, ERR_CNTL_VALUE
+	and   t1, t2  
+	sw    t1, 0(t0)  
+
+/* ------------------- Setup Device Controller -------------------------------*/
+	li    t0, DEV_CTL_BASE    /* load 2 base address registers' base */
+
+	lw    t2, 0x8(t0)
+	andi  t2, t2, 0x3
+	li    t1, MCR_CS0_BS      /* device0 control parameter */
+	or    t1, t1, t2
+	sw    t1, 0x8(t0)         /* set the control register for CS 1 - SRAM */
+	li    t1, MCR_CS0_TC      /* device0 timing config. parameter */
+	sw    t1, 0xC(t0)
+
+	li    t1, 0x0
+	sw    t1, 0x14(t0)
+	sw    t1, 0x24(t0)
+	sw    t1, 0x34(t0)
+	sw    t1, 0x44(t0)
+	sw    t1, 0x54(t0)
+
+	li    t1, MBA_REG1
+	sw    t1, 0x10(t0)
+	li    t1, MCR_CS1_BS
+	sw    t1, 0x18(t0)
+	li    t1, MCR_CS1_TC
+	sw    t1, 0x1C(t0)
+	li    t1, MBM_REG1
+	sw    t1, 0x14(t0)
+
+	li    t1, MBA_REG2
+	sw    t1, 0x20(t0)
+	li    t1, MCR_CS2_BS
+	sw    t1, 0x28(t0)
+	li    t1, MCR_CS2_TC
+	sw    t1, 0x2C(t0)
+	li    t1, MBM_REG2
+	sw    t1, 0x24(t0)
+
+	li    t1, MBA_REG3
+	sw    t1, 0x30(t0)
+	li    t1, MCR_CS3_BS
+	sw    t1, 0x38(t0)
+	li    t1, MCR_CS3_TC
+	sw    t1, 0x3C(t0)
+	li    t1, MBM_REG3
+	sw    t1, 0x34(t0)
+
+	li    t1, MBA_REG4
+	sw    t1, 0x40(t0)
+	li    t1, MCR_CS4_BS
+	sw    t1, 0x48(t0)
+	li    t1, MCR_CS4_TC
+	sw    t1, 0x4C(t0)
+	li    t1, MBM_REG4
+	sw    t1, 0x44(t0)
+
+	li    t1, MBA_REG5
+	sw    t1, 0x50(t0)
+	li    t1, MCR_CS5_BS
+	sw    t1, 0x58(t0)
+	li    t1, MCR_CS5_TC
+	sw    t1, 0x5C(t0)
+	li    t1, MBM_REG5
+	sw    t1, 0x54(t0)
+
+/* USB fix for RP355 - set GPIO_26 as GPIO output low */
+	li    t0, GPIO_BASE
+	li    t1, 0xf9ffffff      /* All alternate functions for GPIO pins except GPIO_26*/
+	sw    t1, 0x0(t0)
+
+	lw    t1, 0x8(t0)         /* Reset GPIOD bit */
+	and   t1, ~0x04000000
+	sw    t1, 0x8(t0)
+
+	lw    t2, 0x4(t0)         /* Set as output */
+	or    t2, 0x04000000
+	sw    t2, 0x4(t0)
+
+	sw    t1, 0x8(t0)         /* Once again reset output */
+
+/*------------ load all R32355 internal registers' base address ----------*/
+	li    t0, TIMER_BASE  
+
+/* ------------------- Disable WatchDog Timer --------------------------------- */
+	li    t1, DISABLE_TIMER
+	sw    t1, 0x40(t0)
+
+/* ------------------- Reduce Bus Timeout Count -----------------------------*/
+	li    t1, TIMEOUT_COUNT
+	sw    t1, 0x34(t0)
+
+/*-------------- Initialize SDRAM  Base and Mask Registers ----------*/
+
+	li    t0, SDRAM_CTL_BASE
+	li    t1, SDRAM_CR_BS
+	li    t2, 0x7FFFFFFF
+	and   t1, t1, t2
+	sw    t1, 0x10(t0)        /* disable SDRAM refresh */
+
+	li    t1, 0x0             /* Disable Bank0 */
+	sw    t1, 0x4(t0)
+	li    t1, 0x0             /* Disable Bank1 */
+	sw    t1, 0xC(t0)         /* set DRAM bank 1 mask */
+
+	li    t1, DRAM_BNK0_BASE  /* load DRAM bank 0 physical address in t1 */
+	sw    t1, 0x0(t0)         /* set DRAM bank 0 base */
+	li    t1, DRAM_BNK0_MASK  /* load DRAM bank 0 size in t1 */
+	sw    t1, 0x4(t0)         /* set DRAM bank 0 mask */
+
+/*-------------- Enable SDRAM Controller ---------------------------*/
+	li    t0, SDRAM_CTL_BASE
+
+/*-------------- Setup Precharge Command ---------------------------*/
+	li    t2, 2
+	li    t3, 0
+1:  
+	li    t1, SDRAM_PC_VAL
+	sw    t1, 0x10(t0)
+	nop
+	nop
+	lw    t7, 0x10(t0)
+	nop
+	li    t4, APATTERN
+	li    t5, 0xA0000000 | DRAM_BNK0_BASE
+	sw    t4, 0x0(t5)
+	addu  t3, 1
+	bne   t3, t2, 1b
+	nop
+/*--------------- Setup Refresh Command ----------------------------*/
+	li    t2, 8
+	li    t3, 0
+1:      
+	li    t1, SDRAM_RFRSH_CMD
+	sw    t1, 0x10(t0)
+	sw    t4, 0x0(t5)
+	addu  t3, 1
+	bne   t3, t2, 1b
+	nop
+/*-------------- Setup up to write to Mode Register ----------------*/
+	li    t1, SDRAM_MODE_REG
+	sw    t1, 0x10(t0)
+	addu  t5, 0x80            /* Kasi addu  t5,0xC0 (CL=3)*/
+	sw    t4, 0x0(t5)         /* note: same old t5 */
+
+/*-------------- Setup and Enable Refresh Timer --------------------*/
+
+	li    t0, TIMER_BASE      /* load timer register set base */
+
+	li    t1, DISABLE_TIMER   /* load diable timer bit settings into t1 */
+	sw    t1, 0x2c(t0)        /* disable timer */
+
+	li    t1, 0               /* load DRAM refresh timer count register bit settings in t1 */
+	sw    t1, 0x24(t0)        /* set DRAM refresh timer count register bit settings */
+	li    t1, DRAM_RF_CMPR_SE_BS  /* load refresh timer compare value for slower expiration */
+	sw    t1, 0x28(t0)        /* set compare register again */
+
+	li    t1, ENABLE_TIMER    /* load timer enable bit */
+	sw    t1, 0x2c(t0)        /* enable refresh timer */
+
+	li    t0, SDRAM_CTL_BASE
+	li    t1, SDRAM_CR_BS
+	sw    t1, 0x10(t0)
+/* the memory system may need up to 120us to start up... */
+	li    v0, 128             /* ~256us */
+1:  
+	bne   v0, zero, 1b
+	subu  v0, 1               /* BDSLOT  */
+	nop
+	nop
+
+/************************************************************************
+** before doing anything
+** initialize the section of memory used by cache initialization
+** whenever you boot out of ROM or reset-vector
+** This assumed to be 1MB.
+** --Sugan (11-22-96)
+************************************************************************/
+	
+	li    t0, 0xa0000000
+	li    t1, 0xa0100000
+1:
+	sw    zero, 0x00(t0)
+	sw    zero, 0x04(t0)
+	sw    zero, 0x08(t0)
+	sw    zero, 0x0c(t0)
+	addiu t0, 16
+	nop
+	blt   t0, t1, 1b
+	nop
+	nop
+	nop
+3:
+	mfc0  t0, C0_SR
+	nop
+	nop
+	and   t0, ~SR_BEV
+	mtc0  t0, C0_SR
+	nop
+	nop
+
+	la      k0, zstartup
+	j      k0
+	nop
+	nop
+			
+ENDFRAME(start)
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/head.S idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/head.S
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/head.S	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/head.S	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,138 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Board initialisation code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+		
+
+#include <linux/config.h>
+#include <linux/threads.h>
+
+#include <asm/asm.h>
+#include <asm/cacheops.h>
+#include <asm/mipsregs.h>
+#include <asm/asm-offsets.h>
+#include <asm/cachectl.h>
+#include <asm/regdef.h>
+
+#define IndexInvalidate_I       0x00
+
+	.set noreorder
+	.cprestore
+	LEAF(zstartup)
+zstartup:
+
+        la      sp, .stack
+	move	s0, a0
+	move	s1, a1
+	move	s2, a2
+	move	s3, a3
+
+	/* Clear BSS */
+	/* Note: when zImage is in ROM, _edata and _bss point to
+	 * ROM space even when using -Tbss on the linker command line;
+	 * maybe ld.script needs to be corrected.
+	 */
+	la	a0, .stack
+	la	a2, _end
+1:	sw	zero, 0(a0)
+	bne	a2, a0, 1b
+	addu	a0, 4
+
+#if 1
+	/* flush the I-Cache */
+	li	k0, 0x80000000  # start address
+	li	k1, 0x80002000  # end address (8KB I-Cache)
+	subu	k1, 128
+2:
+	.set mips3
+	cache	IndexInvalidate_I, 0(k0)
+	cache	IndexInvalidate_I, 16(k0)
+	cache	IndexInvalidate_I, 32(k0)
+	cache	IndexInvalidate_I, 48(k0)
+	cache	IndexInvalidate_I, 64(k0)
+	cache	IndexInvalidate_I, 80(k0)
+	cache	IndexInvalidate_I, 96(k0)
+	cache	IndexInvalidate_I, 112(k0)
+	.set mips0
+
+	bne	k0, k1, 2b
+	addu	k0, k0, 128
+	/* done */
+#endif
+#if 1
+	/* flush the D-Cache */
+	li	k0, 0x80000000  # start address
+	li	k1, 0x80000400  # end address (2KB I-Cache)
+	subu	k1, 128
+3:	
+	.set mips3
+	/* First way */
+	cache	Index_Writeback_Inv_D, 0(k0)
+	cache	Index_Writeback_Inv_D, 16(k0)
+	cache	Index_Writeback_Inv_D, 32(k0)
+	cache	Index_Writeback_Inv_D, 48(k0)
+	cache	Index_Writeback_Inv_D, 64(k0)
+	cache	Index_Writeback_Inv_D, 80(k0)
+	cache	Index_Writeback_Inv_D, 96(k0)
+	cache	Index_Writeback_Inv_D, 112(k0)
+	/* Second way */
+	cache	Index_Writeback_Inv_D, 1024(k0)
+	cache	Index_Writeback_Inv_D, 1040(k0)
+	cache	Index_Writeback_Inv_D, 1056(k0)
+	cache	Index_Writeback_Inv_D, 1072(k0)
+	cache	Index_Writeback_Inv_D, 1088(k0)
+	cache	Index_Writeback_Inv_D, 1104(k0)
+	cache	Index_Writeback_Inv_D, 1120(k0)
+	cache	Index_Writeback_Inv_D, 1136(k0)
+	.set mips0
+
+	bne	k0, k1, 3b
+	addu	k0, k0, 128
+	/* done */
+#endif
+
+	la	ra, 3f
+	la	k0, decompress_kernel
+	jr	k0
+	nop
+3:
+
+	move	a0, s0
+	move	a1, s1
+	move	a2, s2
+	move	a3, s3
+	li	k0, KERNEL_ENTRY
+	jr	k0
+	nop
+4:
+	b 4b
+	END(zstartup)
+
+	.bss
+	.fill 0x2000
+	EXPORT(.stack)
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/idtcpu.h idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/idtcpu.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/idtcpu.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/idtcpu.h	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,614 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   IDT CPU register definitions. Though the registers are already defined
+ *   under asm directory, they are once again declared here for the ease of
+ *   syncing up with IDT bootloader code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#if defined(__IDTCPU_H__)
+#else
+#define __IDTCPU_H__
+
+
+/*
+** memory configuration and mapping
+*/
+#define K0BASE	0x80000000
+#define K0SIZE	0x20000000
+#define K1BASE	0xa0000000
+#define K1SIZE	0x20000000
+#define K2BASE	0xc0000000
+#if defined(S364)
+#define K2SIZE	0x3e000000
+#define ICEBASE	0xff000000
+#define ICESIZE	0x01000000
+#else
+#define K2SIZE	0x20000000
+#endif
+#if defined(CPU_R4000)
+#define KSBASE	0xe0000000
+#define KSSIZE	0x20000000
+#endif
+
+#define KUBASE	0
+#define KUSIZE	0x80000000
+
+/*
+** Exception Vectors
+*/
+#if defined(CPU_R3000)
+#define	UT_VEC	K0BASE			/* utlbmiss vector */
+#define E_VEC	(K0BASE+0x80)		/* exception vevtor */
+#endif
+#if defined(CPU_R4000) || defined S364  /*(CPU_R32364)      */
+#define	T_VEC	(K0BASE+0x000)		/* tlbmiss vector */
+#define X_VEC	(K0BASE+0x080)		/* xtlbmiss vector */
+#define C_VEC	(K1BASE+0x100)		/* cache error vector */
+#define E_VEC	(K0BASE+0x180)		/* exception vector */
+#define I_VEC	(K0BASE+0X200)		/* interrupt vector */
+#endif
+#define	R_VEC	(K1BASE+0x1fc00000)	/* reset vector */
+
+/*
+** Address conversion macros
+*/
+#ifdef CLANGUAGE
+#define	CAST(as) (as)
+#else
+#define	CAST(as)
+#endif
+#define	K0_TO_K1(x)	(CAST(unsigned)(x)|0xA0000000)	/* kseg0 to kseg1 */
+#define	K1_TO_K0(x)	(CAST(unsigned)(x)&0x9FFFFFFF)	/* kseg1 to kseg0 */
+#define	K0_TO_PHYS(x)	(CAST(unsigned)(x)&0x1FFFFFFF)	/* kseg0 to physical */
+#define	K1_TO_PHYS(x)	(CAST(unsigned)(x)&0x1FFFFFFF)	/* kseg1 to physical */
+#define	PHYS_TO_K0(x)	(CAST(unsigned)(x)|0x80000000)	/* physical to kseg0 */
+#define	PHYS_TO_K1(x)	(CAST(unsigned)(x)|0xA0000000)	/* physical to kseg1 */
+
+/*
+**	Cache size constants
+*/
+/* Sugan changed so that MINCACHE is 0x200 instead of 0x800 */
+#define	MINCACHE	0x200		/* 512 bytes  */
+#define	MAXCACHE	0x40000		/* 256*1024   256k */	
+
+#if defined CPU_R32364                  /* Includes RC32364, RC32332, RC32334 */
+#define	CFG_ICE		0x80000000	/* ICE detect */
+#define	CFG_ECMASK	0x70000000	/* System Clock Ratio */
+#define	CFG_ECBY2	0x00000000 	/* divide by 2 */
+#define	CFG_ECBY3	0x10000000 	/* divide by 3 */
+#define	CFG_ECBY4	0x20000000 	/* divide by 4 */
+#define	CFG_NBL		0x00800000	/* Non-Blocking load pending */
+#define	CFG_BE		0x00008000	/* Big Endian */
+#define	CFG_ICMASK	0x00000e00	/* Instruction cache size */
+#define	CFG_ICSHIFT	9
+#define	CFG_DCMASK	0x000001c0	/* Data cache size */
+#define	CFG_DCSHIFT	6
+#define	CFG_IB		0x00000020	/* Instruction cache line size */
+#define	CFG_DB		0x00000010	/* Data cache line size */
+#define	CFG_K0MASK	0x00000007	/* KSEG0 coherency algorithm */
+
+/*
+ * R32364 primary cache mode
+ */
+#define CFG_C_NCHRNT_WT_NWA	0
+#define CFG_C_NCHRNT_WT		1
+#define CFG_C_UNCACHED		2
+#define CFG_C_NCHRNT_WB		3
+
+/* Cache Operations */
+#define Index_Invalidate_I               0x0         /* 0       0 */
+#define Index_Writeback_Inv_D            0x1         /* 0       1 */
+#define Index_Invalidate_SI              0x2         /* 0       2 */
+#define Index_Writeback_Inv_SD           0x3         /* 0       3 */
+#define Index_Load_Tag_I                 0x4         /* 1       0 */
+#define Index_Load_Tag_D                 0x5         /* 1       1 */
+#define Index_Load_Tag_SI                0x6         /* 1       2 */
+#define Index_Load_Tag_SD                0x7         /* 1       3 */
+#define Index_Store_Tag_I                0x8         /* 2       0 */
+#define Index_Store_Tag_D                0x9         /* 2       1 */
+#define Index_Store_Tag_SI               0xA         /* 2       2 */
+#define Index_Store_Tag_SD               0xB         /* 2       3 */
+#define Create_Dirty_Exc_D               0xD         /* 3       1 */
+#define Create_Dirty_Exc_SD              0xF         /* 3       3 */
+#define Hit_Invalidate_I                 0x10        /* 4       0 */
+#define Hit_Invalidate_D                 0x11        /* 4       1 */
+#define Hit_Invalidate_SI                0x12        /* 4       2 */
+#define Hit_Invalidate_SD                0x13        /* 4       3 */
+#define Hit_Writeback_Inv_D              0x15        /* 5       1 */
+#define Hit_Writeback_Inv_SD             0x17        /* 5       3 */
+#define Fill_I                           0x14        /* 5       0 */
+#define Hit_Writeback_D                  0x19        /* 6       1 */
+#define Hit_Writeback_SD                 0x1B        /* 6       3 */
+#define Hit_Writeback_I                  0x18        /* 6       0 */
+#define Hit_Set_Virtual_SI               0x1E        /* 7       2 */
+#define Hit_Set_Virtual_SD               0x1F        /* 7       3 */
+#define CFG_EW32        0x00040000      /* 32 bit */
+#endif /* CPU_R32364 */
+
+#if defined(CPU_R4000)
+/* R4000 configuration register definitions */
+#define CFG_CM		0x80000000	/* Master-Checker mode */
+#define CFG_ECMASK	0x70000000	/* System Clock Ratio */
+#define CFG_ECBY2	0x00000000 	/* divide by 2 */
+#define CFG_ECBY3	0x10000000 	/* divide by 3 */
+#define CFG_ECBY4	0x20000000 	/* divide by 4 */
+#define CFG_EPMASK	0x0f000000	/* Transmit data pattern */
+#define CFG_EPD		0x00000000	/* D */
+#define CFG_EPDDX	0x01000000	/* DDX */
+#define CFG_EPDDXX	0x02000000	/* DDXX */
+#define CFG_EPDXDX	0x03000000	/* DXDX */
+#define CFG_EPDDXXX	0x04000000	/* DDXXX */
+#define CFG_EPDDXXXX	0x05000000	/* DDXXXX */
+#define CFG_EPDXXDXX	0x06000000	/* DXXDXX */
+#define CFG_EPDDXXXXX	0x07000000	/* DDXXXXX */
+#define CFG_EPDXXXDXXX	0x08000000	/* DXXXDXXX */
+#define CFG_SBMASK	0x00c00000	/* Secondary cache block size */
+#define CFG_SBSHIFT	22
+#define CFG_SB4		0x00000000	/* 4 words */
+#define CFG_SB8		0x00400000	/* 8 words */
+#define CFG_SB16	0x00800000	/* 16 words */
+#define CFG_SB32	0x00c00000	/* 32 words */
+#define CFG_SS		0x00200000	/* Split secondary cache */
+#define CFG_SW		0x00100000	/* Secondary cache port width */
+#define CFG_EWMASK	0x000c0000	/* System port width */
+#define CFG_EWSHIFT	18
+#define CFG_EW64	0x00000000	/* 64 bit */
+#define CFG_EW32	0x00040000	/* 32 bit */
+/* #if defined(CPU_R5000) */
+/* Sugan added for R5000 L2 cache 07-17-96 */
+#define L2_PAGESIZE	0x1000
+#define SIZE256K	0x00040000 /* 256KB in Hex */
+#define CFG_HARDL2	0x00020000 /* Hardware bit that enables/disables
+				      L2 cache */
+#define CFG_SE		0x1000
+#define CFG_SIZE512K	0x00000000 /* size of Scache is 512k */
+#define CFG_SIZE1MB 	0x00100000 /* size of Scache is 1MB */
+#define CFG_SIZE2MB 	0x00200000 /* size of Scache is 2MB */
+#define CFG_SIZEMASK	0x00300000 /* size mask */
+/* #endif */
+#define CFG_SC		0x00020000	/* Secondary cache absent */
+#define CFG_SM		0x00010000	/* Dirty Shared mode disabled */
+#define CFG_BE		0x00008000	/* Big Endian */
+#define CFG_EM		0x00004000	/* ECC mode enable */
+#define CFG_EB		0x00002000	/* Block ordering */
+#define CFG_ICMASK	0x00000e00	/* Instruction cache size */
+#define CFG_ICSHIFT	9
+#define CFG_DCMASK	0x000001c0	/* Data cache size */
+#define CFG_DCSHIFT	6
+#define CFG_IB		0x00000020	/* Instruction cache block size */
+#define CFG_DB		0x00000010	/* Data cache block size */
+#define CFG_CU		0x00000008	/* Update on Store Conditional */
+#define CFG_K0MASK	0x00000007	/* KSEG0 coherency algorithm */
+
+/*
+ * R4000 primary cache mode
+ */
+#define CFG_C_WRITETHROUGH_CACHE		0
+#define CFG_C_UNCACHED		2
+#define CFG_C_NONCOHERENT	3
+#define CFG_C_COHERENTXCL	4
+#define CFG_C_COHERENTXCLW	5
+#define CFG_C_COHERENTUPD	6
+
+/*
+ * R4000 cache operations (should be in assembler...?)
+ */
+#if defined(CPU_R5000)
+#define InvAllScache			 0x03	     /* 0	3 */
+#define IndexLoadTagScache		 0x07	     /* 1	3 */
+#define IndexStoreTagScache		 0x0b	     /* 2	3 */
+#define PageInvScache			 0x17	     /* 5	3 */
+#endif
+#define Index_Invalidate_I               0x0         /* 0       0 */
+#define Index_Writeback_Inv_D            0x1         /* 0       1 */
+#define Index_Invalidate_SI              0x2         /* 0       2 */
+#define Index_Writeback_Inv_SD           0x3         /* 0       3 */
+#define Index_Load_Tag_I                 0x4         /* 1       0 */
+#define Index_Load_Tag_D                 0x5         /* 1       1 */
+#define Index_Load_Tag_SI                0x6         /* 1       2 */
+#define Index_Load_Tag_SD                0x7         /* 1       3 */
+#define Index_Store_Tag_I                0x8         /* 2       0 */
+#define Index_Store_Tag_D                0x9         /* 2       1 */
+#define Index_Store_Tag_SI               0xA         /* 2       2 */
+#define Index_Store_Tag_SD               0xB         /* 2       3 */
+#define Create_Dirty_Exc_D               0xD         /* 3       1 */
+#define Create_Dirty_Exc_SD              0xF         /* 3       3 */
+#define Hit_Invalidate_I                 0x10        /* 4       0 */
+#define Hit_Invalidate_D                 0x11        /* 4       1 */
+#define Hit_Invalidate_SI                0x12        /* 4       2 */
+#define Hit_Invalidate_SD                0x13        /* 4       3 */
+#define Hit_Writeback_Inv_D              0x15        /* 5       1 */
+#define Hit_Writeback_Inv_SD             0x17        /* 5       3 */
+#define Fill_I                           0x14        /* 5       0 */
+#define Hit_Writeback_D                  0x19        /* 6       1 */
+#define Hit_Writeback_SD                 0x1B        /* 6       3 */
+#define Hit_Writeback_I                  0x18        /* 6       0 */
+#define Hit_Set_Virtual_SI               0x1E        /* 7       2 */
+#define Hit_Set_Virtual_SD               0x1F        /* 7       3 */
+
+#endif
+
+/*
+** TLB resource defines
+*/
+
+#if defined(CPU_R32364)  
+#define	N_TLB_ENTRIES	16
+#endif 
+
+#if defined(CPU_R4000)
+#define N_TLB_ENTRIES  48
+#endif
+
+#if defined (CPU_R32364)
+#define	TLBHI_VPN2MASK	0xffffe000
+#define	TLBHI_PIDMASK	0x000000ff
+#define	TLBHI_NPID	256
+
+#define	TLBLO_PFNMASK	0x03ffffc0
+#define	TLBLO_PFNSHIFT	6
+#define	TLBLO_D		0x00000004	/* writeable */
+#define	TLBLO_V		0x00000002	/* valid bit */
+#define	TLBLO_G		0x00000001	/* global access bit */
+#define	TLBLO_CMASK	0x00000038	/* cache algorithm mask */
+#define	TLBLO_CSHIFT	3
+
+#define	TLBLO_UNCACHED		(CFG_C_UNCACHED<<TLBLO_CSHIFT)
+#define	TLBLO_NCHRNT_WT_NWA	(CFG_C_NCHRNT_WT_NWA<<TLBLO_CSHIFT)
+#define	TLBLO_NCHRNT_WT		(CFG_C_NCHRNT_WT<<TLBLO_CSHIFT)
+#define	TLBLO_NCHRNT_WB		(CFG_C_NCHRNT_WB<<TLBLO_CSHIFT)
+
+#elif defined(CPU_R4000)
+#define	TLBHI_VPN2MASK	0xffffe000
+#define	TLBHI_PIDMASK	0x000000ff
+#define	TLBHI_NPID	256
+
+#define	TLBLO_PFNMASK	0x3fffffc0
+#define	TLBLO_PFNSHIFT	6
+#define	TLBLO_D		0x00000004	/* writeable */
+#define	TLBLO_V		0x00000002	/* valid bit */
+#define	TLBLO_G		0x00000001	/* global access bit */
+#define	TLBLO_CMASK	0x00000038	/* cache algorithm mask */
+#define	TLBLO_CSHIFT	3
+
+#define	TLBLO_UNCACHED		(CFG_C_UNCACHED<<TLBLO_CSHIFT)
+#define	TLBLO_NONCOHERENT	(CFG_C_NONCOHERENT<<TLBLO_CSHIFT)
+#define	TLBLO_COHERENTXCL	(CFG_C_COHERENTXCL<<TLBLO_CSHIFT)
+#define	TLBLO_COHERENTXCLW	(CFG_C_COHERENTXCLW<<TLBLO_CSHIFT)
+#define	TLBLO_COHERENTUPD	(CFG_C_COHERENTUPD<<TLBLO_CSHIFT)
+#endif
+#if defined(CPU_R4000)||defined(S364)
+#define	TLBINX_PROBE	0x80000000
+#define	TLBINX_INXMASK	0x0000003f
+
+#define	TLBRAND_RANDMASK	0x0000003f
+
+#define	TLBCTXT_BASEMASK	0xff800000
+#define	TLBCTXT_BASESHIFT	23
+
+#define	TLBCTXT_VPN2MASK	0x007ffff0
+#define	TLBCTXT_VPN2SHIFT	4
+
+#define	TLBPGMASK_MASK		0x01ffe000
+#endif
+
+#define	SR_PE		0x00100000	/* cache parity error */
+#if defined(CPU_R3000)
+#define	SR_CUMASK	0xf0000000	/* coproc usable bits */
+#define	SR_CU3		0x80000000	/* Coprocessor 3 usable */
+#define	SR_CU2		0x40000000	/* Coprocessor 2 usable */
+#define	SR_CU1		0x20000000	/* Coprocessor 1 usable */
+#define	SR_CU0		0x10000000	/* Coprocessor 0 usable */
+
+#define	SR_BEV		0x00400000	/* use boot exception vectors */
+
+/* Cache control bits */
+#define	SR_TS		0x00200000	/* TLB shutdown */
+#define	SR_CM		0x00080000	/* cache miss */
+#define	SR_PZ		0x00040000	/* cache parity zero */
+#define	SR_SWC		0x00020000	/* swap cache */
+#define	SR_ISC		0x00010000	/* Isolate data cache */
+
+/*
+**	status register interrupt masks and bits
+*/
+
+#define	SR_IMASK	0x0000ff00	/* Interrupt mask */
+#define	SR_IMASK8	0x00000000	/* mask level 8 */
+#define	SR_IMASK7	0x00008000	/* mask level 7 */
+#define	SR_IMASK6	0x0000c000	/* mask level 6 */
+#define	SR_IMASK5	0x0000e000	/* mask level 5 */
+#define	SR_IMASK4	0x0000f000	/* mask level 4 */
+#define	SR_IMASK3	0x0000f800	/* mask level 3 */
+#define	SR_IMASK2	0x0000fc00	/* mask level 2 */
+#define	SR_IMASK1	0x0000fe00	/* mask level 1 */
+#define	SR_IMASK0	0x0000ff00	/* mask level 0 */
+
+#define	SR_IMASKSHIFT	8
+
+#define	SR_IBIT8	0x00008000	/* bit level 8 */
+#define	SR_IBIT7	0x00004000	/* bit level 7 */
+#define	SR_IBIT6	0x00002000	/* bit level 6 */
+#define	SR_IBIT5	0x00001000	/* bit level 5 */
+#define	SR_IBIT4	0x00000800	/* bit level 4 */
+#define	SR_IBIT3	0x00000400	/* bit level 3 */
+#define	SR_IBIT2	0x00000200	/* bit level 2 */
+#define	SR_IBIT1	0x00000100	/* bit level 1 */
+
+#define	SR_KUO		0x00000020	/* old kernel/user, 0 => k, 1 => u */
+#define	SR_IEO		0x00000010	/* old interrupt enable, 1 => enable */
+#define	SR_KUP		0x00000008	/* prev kernel/user, 0 => k, 1 => u */
+#define	SR_IEP		0x00000004	/* prev interrupt enable, 1 => enable */
+#define	SR_KUC		0x00000002	/* cur kernel/user, 0 => k, 1 => u */
+#define	SR_IEC		0x00000001	/* cur interrupt enable, 1 => enable */
+#endif
+
+#if defined S364                        /* (CPU_R32364)        */
+#define	SR_CUMASK	0xf0000000	/* coproc usable bits */
+#define	SR_CU3		0x80000000	/* Coprocessor 3 usable */
+#define	SR_CU2		0x40000000	/* Coprocessor 2 usable */
+#define	SR_CU1		0x20000000	/* Coprocessor 1 usable */
+#define	SR_CU0		0x10000000	/* Coprocessor 0 usable */
+
+/* defines for R32364 processor */
+#define	SR_NBL		0x08000000	/* Non Blocking Load */
+#define	SR_RE		0X02000000	/* Reverse Endianness */
+#define	SR_DL		0x01000000	/* Data Cache Locking */
+#define	SR_IL		0x00800000	/* Instruction Cache Locking */
+
+#define	SR_BEV		0x00400000	/* Use boot exception vectors */
+#define	SR_SR		0x00100000	/* Soft reset */
+#define	SR_CH		0x00040000	/* Cache hit */
+#define	SR_CE		0x00020000	/* Use cache ECC  */
+#define	SR_DE		0x00010000	/* Disable cache exceptions */
+
+/*
+**	status register interrupt masks and bits
+*/
+
+#define	SR_IMASK	0x0000ff00	/* Interrupt mask */
+#define	SR_IMASK8	0x00000000	/* mask level 8 */
+#define	SR_IMASK7	0x00008000	/* mask level 7 */
+#define	SR_IMASK6	0x0000c000	/* mask level 6 */
+#define	SR_IMASK5	0x0000e000	/* mask level 5 */
+#define	SR_IMASK4	0x0000f000	/* mask level 4 */
+#define	SR_IMASK3	0x0000f800	/* mask level 3 */
+#define	SR_IMASK2	0x0000fc00	/* mask level 2 */
+#define	SR_IMASK1	0x0000fe00	/* mask level 1 */
+#define	SR_IMASK0	0x0000ff00	/* mask level 0 */
+
+#define	SR_IMASKSHIFT	8
+
+#define	SR_IBIT8	0x00008000	/* bit level 8 */
+#define	SR_IBIT7	0x00004000	/* bit level 7 */
+#define	SR_IBIT6	0x00002000	/* bit level 6 */
+#define	SR_IBIT5	0x00001000	/* bit level 5 */
+#define	SR_IBIT4	0x00000800	/* bit level 4 */
+#define	SR_IBIT3	0x00000400	/* bit level 3 */
+#define	SR_IBIT2	0x00000200	/* bit level 2 */
+#define	SR_IBIT1	0x00000100	/* bit level 1 */
+
+#define	SR_KSMASK	0x00000016	/* Kernel mode mask */
+#define	SR_KSUSER	0x00000000	/* User Mode */
+#define	SR_KSKERNEL	0x00000016	/* Kernel Mode */
+
+#define	SR_ERL		0x00000004	/* Error level */
+#define	SR_EXL		0x00000002	/* Exception level */
+#define	SR_IE		0x00000001	/* Interrupts enabled */
+#define	NOT_SR_IEC      0xfffffffe      /* assembler problem with li
+~SR_IEC */
+
+/* R32364 Cache locking bits */
+#define SR_ICACHELOCK 0x00800000
+#define SR_DCACHELOCK 0x01000000
+
+#endif /* CPU_R32364 */
+
+#if defined(CPU_R4000)
+#define	SR_CUMASK	0xf0000000	/* coproc usable bits */
+#define	SR_CU3		0x80000000	/* Coprocessor 3 usable */
+#define	SR_CU2		0x40000000	/* Coprocessor 2 usable */
+#define	SR_CU1		0x20000000	/* Coprocessor 1 usable */
+#define	SR_CU0		0x10000000	/* Coprocessor 0 usable */
+
+#define	SR_RP		0x08000000      /* Reduced power operation */
+#define	SR_FR		0x04000000	/* Additional floating pt registers */
+#define	SR_RE		0x02000000	/* Reverse endian in user mode */
+
+#define	SR_BEV		0x00400000	/* Use boot exception vectors */
+#define	SR_TS		0x00200000	/* TLB shutdown */
+#define	SR_SR		0x00100000	/* Soft reset */
+#define	SR_CH		0x00040000	/* Cache hit */
+#define	SR_CE		0x00020000	/* Use cache ECC  */
+#define	SR_DE		0x00010000	/* Disable cache exceptions */
+
+/*
+**	status register interrupt masks and bits
+*/
+
+#define	SR_IMASK	0x0000ff00	/* Interrupt mask */
+#define	SR_IMASK8	0x00000000	/* mask level 8 */
+#define	SR_IMASK7	0x00008000	/* mask level 7 */
+#define	SR_IMASK6	0x0000c000	/* mask level 6 */
+#define	SR_IMASK5	0x0000e000	/* mask level 5 */
+#define	SR_IMASK4	0x0000f000	/* mask level 4 */
+#define	SR_IMASK3	0x0000f800	/* mask level 3 */
+#define	SR_IMASK2	0x0000fc00	/* mask level 2 */
+#define	SR_IMASK1	0x0000fe00	/* mask level 1 */
+#define	SR_IMASK0	0x0000ff00	/* mask level 0 */
+
+#define	SR_IMASKSHIFT	8
+
+#define	SR_IBIT8	0x00008000	/* bit level 8 */
+#define	SR_IBIT7	0x00004000	/* bit level 7 */
+#define	SR_IBIT6	0x00002000	/* bit level 6 */
+#define	SR_IBIT5	0x00001000	/* bit level 5 */
+#define	SR_IBIT4	0x00000800	/* bit level 4 */
+#define	SR_IBIT3	0x00000400	/* bit level 3 */
+#define	SR_IBIT2	0x00000200	/* bit level 2 */
+#define	SR_IBIT1	0x00000100	/* bit level 1 */
+
+#define	SR_KSMASK	0x00000018	/* Kernel mode mask */
+#define	SR_KSUSER	0x00000010	/* User mode */
+#define	SR_KSSUPER	0x00000008	/* Supervisor mode */
+#define	SR_KSKERNEL	0x00000000	/* Kernel mode */
+#define	SR_ERL		0x00000004	/* Error level */
+#define	SR_EXL		0x00000002	/* Exception level */
+#define	SR_IE		0x00000001	/* Interrupts enabled */
+
+/* R4650 Cache locking bits */
+#define	SR_ICACHELOCK 0x00800000
+#define	SR_DCACHELOCK 0x01000000
+
+
+#endif
+#if defined(CPU_R3000)
+#define	SR_FR		0x04000000	/* Additional floating point registers */
+#endif
+
+
+
+/*
+ * Cause Register
+ */
+#define	CAUSE_BD	0x80000000	/* Branch delay slot */
+#define	CAUSE_CEMASK	0x30000000	/* coprocessor error */
+#define	CAUSE_CESHIFT	28
+#define	CAUSE_IW	0x01000000	/* Instruction watch */
+#define	CAUSE_DW	0x02000000	/* Data watch */
+#define	CAUSE_IPE	0x04000000	/* Imprecise exception */
+
+
+#define	CAUSE_IPMASK	0x0000FF00	/* Pending interrupt mask */
+#define	CAUSE_IPSHIFT	8
+
+/* Notice: Watch Exception if Exc. Code is 23 is not included in the mask
+ *	   for R32364.
+ */
+#define	CAUSE_EXCMASK	0x0000003C	/* Cause code bits */
+#define	CAUSE_EXCSHIFT	2
+
+#ifndef XDS
+/*
+**  Coprocessor 0 registers
+*/
+
+/* Evelyn, 12/12/94, for P3 	*/
+#define C0_IBASE        $0		/* I base */
+#define C0_IBOUND       $1		/* I bound */
+
+#define	C0_INX			$0		/* tlb index */
+#define	C0_RAND			$1		/* tlb random */
+#if defined(CPU_R3000)
+#define	C0_TLBLO	$2				/* tlb entry low */
+#define	C0_BUSCTRL		$2		/* bus control R3041 specific */
+#define	C0_CONFIG		$3		/* cache config */
+#define	C0_CTXT			$4		/* tlb context */
+#define	C0_BADVADDR		$8		/* bad virtual address */
+#define	C0_COUNT			$9		/* count R3041 specific */
+#define	C0_PORTSIZE		$10	/* port size R3041 specific */
+#define	C0_TLBHI			$10	/* tlb entry hi */
+#define	C0_COMPARE		$11	/* compare R3041 specific */
+#define	C0_SR				$12	/* status register */
+#define	C0_CAUSE			$13	/* exception cause */
+#define	C0_EPC			$14	/* exception pc */
+#define	C0_PRID			$15	/* revision identifier */
+#endif
+
+#if defined(S364)					/*(CPU_R32364)      */
+#define	C0_RANDOM		$1
+#define	C0_TLBLO0		$2		/* tlb entry low 0 */
+#define	C0_TLBLO1		$3		/* tlb entry low 1 */
+#define	C0_CTXT			$4		/* tlb context */
+#define	C0_PAGEMASK		$5		/* tlb page mask */
+#define	C0_WIRED			$6		/* number of wired tlb entries */
+
+#define	C0_INX			$0		/* tlb index */
+#define	C0_BADVADDR		$8		/* bad virtual address */
+#define	C0_COUNT			$9		/* timer count */
+#define	C0_TLBHI			$10	/* tlb entry hi */
+#define	C0_COMPARE		$11	/* timer comparator  */
+#define	C0_SR				$12	/* status register */
+#define	C0_CAUSE			$13	/* exception cause */
+#define	C0_EPC			$14	/* exception pc */
+#define	C0_PRID			$15	/* revision identifier */
+#define	C0_CONFIG		$16	/* configuration register */
+
+#define	C0_IWATCH		$18	/* Instr brk pt Virtual add. */
+#define	C0_DWATCH		$19	/* Data brk pt Virtual add. */
+
+#define	C0_IEPC			$22	/* Imprecise Exception pc */
+#define	C0_DEPC			$23	/* Debug Exception pc */
+#define	C0_DEBUG			$24	/* Debug control/status reg */
+
+#define	C0_ECC			$26	/* primary cache Parity control */
+#define	C0_CACHEERR		$27	/* cache error status */
+#define	C0_TAGLO			$28	/* cache tag lo */
+#define	C0_TAGHI			$29
+#define	C0_ERRPC			$30	/* cache error pc */
+#endif /* CPU_R32364 			*/
+
+#if defined(CPU_R4000)
+
+/* Evelyn, 12/12/94, for P3 	*/
+#define	C0_DBASE			$2		/* D base */
+#define	C0_DBOUND		$3		/* D bound */
+
+#define	C0_TLBLO0		$2		/* tlb entry low 0 */
+#define	C0_TLBLO1		$3		/* tlb entry low 1 */
+#define	C0_CTXT			$4		/* tlb context */
+#define	C0_PAGEMASK		$5		/* tlb page mask */
+#define	C0_WIRED			$6		/* number of wired tlb entries */
+
+#define	C0_BADVADDR		$8		/* bad virtual address */
+#define	C0_COUNT			$9		/* cycle count */
+#define	C0_TLBHI			$10	/* tlb entry hi */
+#define	C0_COMPARE		$11	/* cyccle count comparator  */
+#define	C0_SR				$12	/* status register */
+#define	C0_CAUSE			$13	/* exception cause */
+#define	C0_EPC			$14	/* exception pc */
+#define	C0_PRID			$15	/* revision identifier */
+#define	C0_CONFIG		$16	/* configuration register */
+
+/* Evelyn, 12/12/94, for P3   */
+#define	C0_CALG			$17	/* Calg rigister */
+#define	C0_IWATCH		$18	/* IWatch register */
+#define	C0_DWATCH		$19	/* DWatch register */
+
+#define	C0_LLADDR		$17	/* linked load address */
+#define	C0_WATCHLO		$18	/* watchpoint trap register */
+#define	C0_WATCHHI		$19	/* watchpoint trap register */
+#define	C0_XCTXT			$20 	/* extended tlb context */
+#define	C0_ECC			$26	/* secondary cache ECC control */
+#define	C0_CACHEERR		$27	/* cache error status */
+#define	C0_TAGLO			$28	/* cache tag lo */
+#define	C0_TAGHI			$29	/* cache tag hi */
+#define	C0_ERRPC			$30	/* cache error pc */
+#endif
+#endif 
+#endif /* defined(__IDTCPU_H__) */
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/idthdr.h idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/idthdr.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/idthdr.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/idthdr.h	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,53 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Some macros. Though they are already defined else where in the linux
+ *   tree, they are once again declared here for the ease of syncing up with
+ *    IDT bootloader code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#ifndef XDS
+
+#define	FRAME(name,frm_reg,offset,ret_reg)	\
+	.globl	name;				\
+	.ent	name;				\
+name:;						\
+	.frame	frm_reg,offset,ret_reg
+
+#define ENDFRAME(name) 	.end name
+
+#else
+
+#define FRAME(name,frm_reg,offset,ret_reg)      \
+name:
+
+#define ENDFRAME(name)
+
+#endif
+
+
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/image.lds.in idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/image.lds.in
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/image.lds.in	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/image.lds.in	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,31 @@
+OUTPUT_ARCH(mips)
+ENTRY(zstartup)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = IMSTART;
+  .init          : { *(.init)		} =0
+  .text      :
+  {
+    _ftext = . ;
+    *(.text)
+    *(.rodata)
+    *(.rodata1)
+   . = ALIGN(4096);
+    input_data = .;
+    arch/mips/idt-boards/rc32300/EB355/boot/piggy.o
+    input_data_end = .;
+   . = ALIGN(4096);
+    *(.gnu.warning)
+  } =0
+
+  .reginfo : { *(.reginfo) }
+
+   . = BSS_START;
+  __bss_start = .;
+  .bss       :
+  {
+   *(.bss)
+  _end = . ;
+  }
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/iregdef.h idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/iregdef.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/iregdef.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/iregdef.h	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,284 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   IDT CPU register definitions. Though the registers are already defined
+ *   under asm directory, they are once again declared here for the ease of
+ *   syncing up with IDT bootloader code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#define r0	$0
+#define r1	$1 /*at assembler temp */
+#define r2	$2 /*v0 return value */
+#define r3	$3 /*v1 return value */
+#define r4	$4 /*a0 argument 0 */
+#define r5	$5 /*a1 argument 1 */
+#define r6	$6
+#define r7	$7
+#define r8	$8
+#define r9	$9
+#define r10	$10
+#define r11	$11
+#define r12	$12
+#define r13	$13
+
+#define r14	$14
+#define r15	$15
+#define r16	$16 /*s0 called saved */
+#define r17	$17
+#define r18	$18
+#define r19	$19
+#define r20	$20
+#define r21	$21
+#define r22	$22
+#define r23	$23 /*s7 called saved */
+#define r24	$24
+#define r25	$25
+#define r26	$26 /*k0 kernel temp. */
+#define r27	$27 /*k1   ""    ""   */
+#define r28	$28 /*gp global pointer */
+#define r29	$29 /*sp stack pointer */
+#define r30	$30 /*fp frame pointer */
+#define r31	$31 /*ra return address */
+
+#define fp0	$f0
+#define fp1	$f1
+#define fp2	$f2
+#define fp3	$f3
+#define fp4	$f4
+#define fp5	$f5
+#define fp6	$f6
+#define fp7	$f7
+#define fp8	$f8
+#define fp9	$f9
+#define fp10	$f10
+#define fp11	$f11
+#define fp12	$f12
+#define fp13	$f13
+#define fp14	$f14
+#define fp15	$f15
+#define fp16	$f16
+#define fp17	$f17
+#define fp18	$f18
+#define fp19	$f19
+#define fp20	$f20
+#define fp21	$f21
+#define fp22	$f22
+#define fp23	$f23
+#define fp24	$f24
+#define fp25	$f25
+#define fp26	$f26
+#define fp27	$f27
+#define fp28	$f28
+#define fp29	$f29
+#define fp30	$f30
+#define fp31	$f31
+
+#define fcr0	$0
+#define fcr30	$30
+#define fcr31	$31
+
+#define zero	$0	/* wired zero */
+#define AT	$at	/* assembler temp */
+#define v0	$2	/* return value */
+#define v1	$3
+#define a0	$4	/* argument registers */
+#define a1	$5
+#define a2	$6
+#define a3	$7
+#define t0	$8	/* caller saved */
+#define t1	$9
+#define t2	$10
+#define t3	$11
+#define t4	$12
+#define t5	$13
+#define t6	$14
+#define t7	$15
+#define s0	$16	/* callee saved */
+#define s1	$17
+#define s2	$18
+#define s3	$19
+#define s4	$20
+#define s5	$21
+#define s6	$22
+#define s7	$23
+#define t8	$24	/* code generator */
+#define t9	$25
+#define k0	$26	/* kernel temporary */
+#define k1	$27
+#define gp	$28	/* global pointer */
+#define sp	$29	/* stack pointer */
+#define s8	$30	/* yet another saved reg for the callee */
+#define fp	$30	/* frame pointer - this is being phased out by MIPS */
+#define ra	$31	/* return address */
+
+
+/*
+ * register names
+ */
+#define	R_R0		0
+#define	R_R1		1
+#define	R_R2		2
+#define	R_R3		3
+#define	R_R4		4
+#define	R_R5		5
+#define	R_R6		6
+#define	R_R7		7
+#define	R_R8		8
+#define	R_R9		9
+#define	R_R10		10
+#define	R_R11		11
+#define	R_R12		12
+#define	R_R13		13
+#define	R_R14		14
+#define	R_R15		15
+#define	R_R16		16
+#define	R_R17		17
+#define	R_R18		18
+#define	R_R19		19
+#define	R_R20		20
+#define	R_R21		21
+#define	R_R22		22
+#define	R_R23		23
+#define	R_R24		24
+#define	R_R25		25
+#define	R_R26		26
+#define	R_R27		27
+#define	R_R28		28
+#define	R_R29		29
+#define	R_R30		30
+#define	R_R31		31
+#define	R_F0		32
+#define	R_F1		33
+#define	R_F2		34
+#define	R_F3		35
+#define	R_F4		36
+#define	R_F5		37
+#define	R_F6		38
+#define	R_F7		39
+#define	R_F8		40
+#define	R_F9		41
+#define	R_F10		42
+#define	R_F11		43
+#define	R_F12		44
+#define	R_F13		45
+#define	R_F14		46
+#define	R_F15		47
+#define	R_F16		48
+#define	R_F17		49
+#define	R_F18		50
+#define	R_F19		51
+#define	R_F20		52
+#define	R_F21		53
+#define	R_F22		54
+#define	R_F23		55
+#define	R_F24		56
+#define	R_F25		57
+#define	R_F26		58
+#define	R_F27		59
+#define	R_F28		60
+#define	R_F29		61
+#define	R_F30		62
+#define	R_F31		63
+#define NCLIENTREGS	64
+#define	R_EPC		64
+#define	R_MDHI		65
+#define	R_MDLO		66
+#define	R_SR		67
+#define	R_CAUSE		68
+#define	R_TLBHI		69
+#ifdef CPU_R4000
+#define	R_TLBLO0	70
+#else
+#define	R_TLBLO		70
+#endif
+#define	R_BADVADDR	71
+#define	R_INX		72
+#define	R_RAND		73
+#define	R_CTXT		74
+#define	R_EXCTYPE	75
+#define R_MODE		76
+#define	R_PRID		77
+#define R_FCSR		78
+#define R_FEIR		79
+#ifdef CPU_R4000
+#define	R_TLBLO1	80
+#define R_PAGEMASK	81
+#define R_WIRED		82
+#define R_COUNT		83
+#define R_COMPARE	84
+#define R_CONFIG	85
+#define R_LLADDR	86
+#define R_WATCHLO	87
+#define R_WATCHHI	88
+#define R_ECC		89
+#define R_CACHEERR	90
+#define R_TAGLO		91
+#define R_TAGHI		92
+#define R_ERRPC		93
+#endif
+
+#ifdef CPU_R4000
+#define	NREGS		94
+#else
+#define NREGS		80
+#endif
+
+/*
+ * compiler defined bindings
+ */
+#define	R_ZERO		R_R0
+#define	R_AT		R_R1
+#define	R_V0		R_R2
+#define	R_V1		R_R3
+#define	R_A0		R_R4
+#define	R_A1		R_R5
+#define	R_A2		R_R6
+#define	R_A3		R_R7
+#define	R_T0		R_R8
+#define	R_T1		R_R9
+#define	R_T2		R_R10
+#define	R_T3		R_R11
+#define	R_T4		R_R12
+#define	R_T5		R_R13
+#define	R_T6		R_R14
+#define	R_T7		R_R15
+#define	R_S0		R_R16
+#define	R_S1		R_R17
+#define	R_S2		R_R18
+#define	R_S3		R_R19
+#define	R_S4		R_R20
+#define	R_S5		R_R21
+#define	R_S6		R_R22
+#define	R_S7		R_R23
+#define	R_T8		R_R24
+#define	R_T9		R_R25
+#define	R_K0		R_R26
+#define	R_K1		R_R27
+#define	R_GP		R_R28
+#define	R_SP		R_R29
+#define	R_FP		R_R30
+#define	R_RA		R_R31
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/Makefile idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/Makefile
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/Makefile	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/Makefile	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,134 @@
+###############################################################################
+#
+#  BRIEF MODULE DESCRIPTION
+#     Makefile create a compressed zImage or Rommable rImage
+#
+#  Copyright 2006 IDT Inc. (rischelp@idt.com)
+#
+#  This program is free software; you can redistribute  it and/or modify it
+#  under  the terms of  the GNU General  Public License as published by the
+#  Free Software Foundation;  either version 2 of the  License, or (at your
+#  option) any later version.
+#
+#  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+#  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+#   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+#   NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+#   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+#   NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+#   USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+#   ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+#   THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#   You should have received a copy of the  GNU General Public License along
+#   with this program; if not, write  to the Free Software Foundation, Inc.,
+#   675 Mass Ave, Cambridge, MA 02139, USA.
+# 
+# 
+###############################################################################
+
+###############################################################################
+# The following is taken from IDT/Sim Makefile
+#############################################################################
+TARGET=355
+
+# following refers to size of the DRAM space.
+# These are values for the switch DRAMSZ.
+SRAM_ONLY=1
+SDRAM_ONLY=2
+SRAM_N_SDRAM=3
+SDRAM_N_SRAM=4
+
+MB16=1
+MB32=2
+MB64=3
+MB128=4
+MB32SO=5
+
+FLASH_2M=0
+FLASH_4M=1
+FLASH_8M=2
+
+MACH= -DS$(TARGET) -DEB355 -DS364 -DCPU_R32364 -DMEMCFG=$(SDRAM_ONLY) -DDRAMSZ=$(MB32SO) -DFLASHSZ=$(FLASH_8M)
+COMMSWITCHES = $(INCDIRS) $(MACH)
+#***************** END IDT/Sim Makefile #####################################
+ZDEBUG=0
+export ZDEBUG
+
+# working space for gunzip:
+FREE_RAM      := 0x80C00000
+END_RAM       := 0x80E00000
+
+KERNELCONFIG  := $(TOPDIR)/.config
+include $(KERNELCONFIG)
+
+SIZE = $(CROSS_COMPILE)size
+
+O_FORMAT = $(shell $(OBJDUMP) -i | head -2 | grep elf32)
+
+SYSTEM	      := $(TOPDIR)/vmlinux
+ZBSS          := 0x800A0000
+
+ZIMSTART      := $(CONFIG_IDT_ZIMAGE_ADDR)
+RIMSTART      := 0x9FC00000
+
+LOADADDR      := 0x$(shell $(NM) $(SYSTEM) | grep "A _text" |cut -f1 -d' ')
+KERNEL_ENTRY  := $(shell $(OBJDUMP) -f $(SYSTEM) | sed -n -e 's/^start address //p')
+
+####################################################################################
+ZIMFLAGS        = s/IMSTART/$(ZIMSTART)/;s/BSS_START/$(ZBSS)/
+RIMFLAGS        = s/IMSTART/$(RIMSTART)/;s/BSS_START/$(ZBSS)/
+CFLAGS	:= -fno-pic -nostdinc -G 0 -mno-abicalls -fno-pic -pipe -I$(TOPDIR)/include
+AFLAGS	:= -D__ASSEMBLY__ $(CFLAGS)
+
+####################################################################################
+OBJECTS= $(obj)/piggy.o $(obj)/head.o $(obj)/misc.o
+ifneq ($(ZDEBUG),0)
+OBJECTS += $(obj)/uart16550.o
+endif
+
+$(obj)/zImage.lds: $(obj)/image.lds.in $(KERNELCONFIG)
+	@sed "$(ZIMFLAGS)" < $< > $@
+
+$(obj)/rImage.lds: $(obj)/image.lds.in $(KERNELCONFIG)
+	@sed "$(RIMFLAGS)" < $< > $@
+
+$(obj)/piggy.o: $(SYSTEM) $(obj)/Makefile
+	$(OBJCOPY) -S -O binary -R .note -R .comment $(SYSTEM) $(SYSTEM).bin
+	gzip -f -9 < $(SYSTEM).bin > $(SYSTEM).gz
+	echo "O_FORMAT:  " $(O_FORMAT); 
+	$(LD) -r -b binary --oformat $(O_FORMAT) -o $(obj)/piggy.o $(SYSTEM).gz
+	rm -f $(SYSTEM).bin $(SYSTEM).gz
+
+$(obj)/head.o: $(obj)/head.S $(SYSTEM) $(obj)/Makefile
+	$(CC) $(AFLAGS) -DKERNEL_ENTRY=$(KERNEL_ENTRY) -c $(obj)/head.S -o $(obj)/head.o
+
+$(obj)/misc.o: $(obj)/misc.c $(obj)/Makefile
+	$(CC) $(CFLAGS) -DLOADADDR=$(LOADADDR) -DFREE_RAM=$(FREE_RAM) -DEND_RAM=$(END_RAM) \
+		-c $< -DZDEBUG=$(ZDEBUG) -o $(obj)/misc.o
+
+$(obj)/uart16550.o: $(obj)/uart16550.c $(KERNELCONFIG)
+	$(CC) $(CFLAGS) -c $< -o $(obj)/uart16550.o
+
+$(obj)/csu_idt.o: $(obj)/csu_idt.S Makefile $(SYSTEM)
+	$(CC) $(AFLAGS) $(COMMSWITCHES) -c $< -o $(obj)/csu_idt.o
+
+zImage: $(obj)/zImage.lds $(SYSTEM) $(OBJECTS)
+	$(LD) -T$(obj)/zImage.lds -o $(TOPDIR)/zImage $(OBJECTS)
+	$(OBJCOPY) -S -O binary -R .note -R .comment $(TOPDIR)/zImage $(TOPDIR)/zImage.bin
+	$(OBJCOPY) -I binary -S -O srec --srec-forceS3 --srec-len=32 --change-start=0x00000000 \
+		 $(TOPDIR)/zImage.bin $(TOPDIR)/zImage.prm
+	$(SIZE) $(TOPDIR)/zImage |awk -F" " '{ print $$4 "\t" $$5 }' > $(TOPDIR)/zImage.size
+	rm -f *.o
+
+rImage: $(obj)/rImage.lds $(OBJECTS) $(obj)/csu_idt.o $(SYSTEM)
+	@rm -f $(TOPDIR)/*.prm
+	$(LD) -T$(obj)/rImage.lds -o $(TOPDIR)/rImage $(obj)/csu_idt.o $(OBJECTS) 
+	$(OBJCOPY) -S -O binary -R .note -R .comment $(TOPDIR)/rImage $(TOPDIR)/rImage.bin
+	$(OBJCOPY) -I binary -S -O srec --srec-forceS3 --srec-len=32 --change-start=0x00000000 \
+		 $(TOPDIR)/rImage.bin $(TOPDIR)/rImage.prm
+	$(SIZE) $(TOPDIR)/rImage |awk -F" " '{ print $$4 "\t" $$5 }' > $(TOPDIR)/rImage.size
+	rm -f *.o
+clean:
+	rm -f *.o $(TOPDIR)/zImage $(TOPDIR)/rImage $(TOPDIR)/*.prm $(TOPDIR)/rImage.size $(TOPDIR)/zImage.size
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/misc.c idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/misc.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/misc.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/misc.c	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,341 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Code to un-compress linux image
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/types.h>
+
+/*
+ * gzip declarations
+ */
+#define OF(args)  args
+#define STATIC static
+#define memzero(s, n)     memset ((s), 0, (n))
+typedef unsigned char uch;
+typedef unsigned short ush;
+typedef unsigned long ulg;
+#define WSIZE 0x8000		/* Window size must be at least 32k, */
+				/* and a power of two */
+static uch *inbuf;		/* input buffer */
+static uch window[WSIZE];	/* Sliding window buffer */
+
+/* gzip flag byte */
+#define ASCII_FLAG   0x01	/* bit 0 set: file probably ASCII text */
+#define CONTINUATION 0x02	/* bit 1 set: continuation of multi-part gzip file */
+#define EXTRA_FIELD  0x04	/* bit 2 set: extra field present */
+#define ORIG_NAME    0x08	/* bit 3 set: original file name present */
+#define COMMENT      0x10	/* bit 4 set: file comment present */
+#define ENCRYPTED    0x20	/* bit 5 set: file is encrypted */
+#define RESERVED     0xC0	/* bit 6,7:   reserved */
+
+
+static unsigned insize;	/* valid bytes in inbuf */
+static unsigned inptr;	/* index of next byte to be processed in inbuf */
+static unsigned outcnt;	/* bytes in output buffer */
+
+void variable_init(void);
+#if ZDEBUG > 0
+static void puts(const char *);
+extern void putc_init(void);
+extern void putc(unsigned char c);
+#endif
+static int fill_inbuf(void);
+static void flush_window(void);
+static void error(char *m);
+static void gzip_mark(void **);
+static void gzip_release(void **);
+
+extern char input_data[];
+//extern int input_len;
+extern char input_data_end[];
+
+
+#if ZDEBUG > 0
+void int2hex(unsigned long val)
+{
+        unsigned char buf[10];
+        int i;
+        for (i = 7;  i >= 0;  i--)
+        {
+                buf[i] = "0123456789ABCDEF"[val & 0x0F];
+                val >>= 4;
+        }
+        buf[8] = '\0';
+        puts(buf);
+}
+#endif
+
+static unsigned long byte_count;
+
+int get_byte(void)
+{
+#if ZDEBUG > 1
+	static int printCnt;
+#endif
+	unsigned char c = (inptr < insize ? inbuf[inptr++] : fill_inbuf());
+	byte_count++;
+
+#if ZDEBUG > 1
+	if (printCnt++ < 32)
+	{
+	  puts("byte count = ");
+	  int2hex(byte_count);
+	  puts(" byte val = ");
+	  int2hex(c);
+	  puts("\n");
+	}
+#endif
+	return c;
+}
+
+/* Diagnostic functions */
+#ifdef DEBUG
+#  define Assert(cond,msg) {if(!(cond)) error(msg);}
+#  define Trace(x) fprintf x
+#  define Tracev(x) {if (verbose) fprintf x ;}
+#  define Tracevv(x) {if (verbose>1) fprintf x ;}
+#  define Tracec(c,x) {if (verbose && (c)) fprintf x ;}
+#  define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}
+#else
+#  define Assert(cond,msg)
+#  define Trace(x)
+#  define Tracev(x)
+#  define Tracevv(x)
+#  define Tracec(c,x)
+#  define Tracecv(c,x)
+#endif
+
+/*
+ * This is set up by the setup-routine at boot-time
+ */
+
+static long bytes_out;
+static uch *output_data;
+static unsigned long output_ptr;
+
+
+static void *malloc(int size);
+static void free(void *where);
+static void error(char *m);
+static void gzip_mark(void **);
+static void gzip_release(void **);
+
+static unsigned long free_mem_ptr;
+static unsigned long free_mem_end_ptr;
+
+#include "../../../../../../lib/inflate.c"
+
+static void *malloc(int size)
+{
+	void *p;
+
+	if (size < 0)
+		error("Malloc error\n");
+	if (free_mem_ptr <= 0) error("Memory error\n");
+
+	free_mem_ptr = (free_mem_ptr + 3) & ~3;	/* Align */
+
+	p = (void *) free_mem_ptr;
+	free_mem_ptr += size;
+
+	if (free_mem_ptr >= free_mem_end_ptr)
+		error("\nOut of memory\n");
+
+	return p;
+}
+
+static void free(void *where)
+{				/* Don't care */
+}
+
+static void gzip_mark(void **ptr)
+{
+	*ptr = (void *) free_mem_ptr;
+}
+
+static void gzip_release(void **ptr)
+{
+	free_mem_ptr = (long) *ptr;
+}
+#if ZDEBUG > 0
+static void puts(const char *s)
+{
+	while (*s) {
+		if (*s == 10)
+			putc(13);
+		putc(*s++);
+	}
+}
+#endif
+void *memset(void *s, int c, size_t n)
+{
+	int i;
+	char *ss = (char *) s;
+
+	for (i = 0; i < n; i++)
+		ss[i] = c;
+	return s;
+}
+
+void *memcpy(void *__dest, __const void *__src, size_t __n)
+{
+	int i;
+	char *d = (char *) __dest, *s = (char *) __src;
+
+	for (i = 0; i < __n; i++)
+		d[i] = s[i];
+	return __dest;
+}
+
+/* ===========================================================================
+ * Fill the input buffer. This is called only when the buffer is empty
+ * and at least one byte is really needed.
+ */
+static int fill_inbuf(void)
+{
+	if (insize != 0) {
+		error("ran out of input data\n");
+	}
+
+	inbuf = input_data;
+	//	insize = input_len;
+	insize = &input_data_end[0] - &input_data[0];	
+	inptr = 1;
+	return inbuf[0];
+}
+
+/* ===========================================================================
+ * Write the output window window[0..outcnt-1] and update crc and bytes_out.
+ * (Used for the decompressed data only.)
+ */
+static void flush_window(void)
+{
+	ulg c = crc;		/* temporary variable */
+	unsigned n;
+	uch *in, *out, ch;
+
+	in = window;
+	out = &output_data[output_ptr];
+	for (n = 0; n < outcnt; n++) {
+		ch = *out++ = *in++;
+		c = crc_32_tab[((int) c ^ ch) & 0xff] ^ (c >> 8);
+	}
+	crc = c;
+	bytes_out += (ulg) outcnt;
+	output_ptr += (ulg) outcnt;
+	outcnt = 0;
+}
+
+#if ZDEBUG > 0
+void check_mem(void)
+{
+	int i;
+
+	puts("\ncplens = ");
+	for (i = 0; i < 10; i++) {
+		int2hex(cplens[i]);
+		puts(" ");
+	}
+	puts("\ncplext = ");
+	for (i = 0; i < 10; i++) {
+		int2hex(cplext[i]);
+		puts(" ");
+	}
+	puts("\nborder = ");
+	for (i = 0; i < 10; i++) {
+		int2hex(border[i]);
+		puts(" ");
+	}
+	puts("\n");
+}
+#endif
+static void error(char *x)
+{
+#if ZDEBUG > 1
+	check_mem();
+	puts("\n\n");
+	puts(x);
+	puts("byte_count = ");
+	int2hex(byte_count);
+	puts("\n");
+	puts("\n\n -- Error. System halted");
+#endif
+	while (1);		/* Halt */
+}
+
+void variable_init(void)
+{
+	byte_count = 0;
+	//	output_data = (char *) LOADADDR;
+	free_mem_ptr = FREE_RAM;
+	free_mem_end_ptr = END_RAM;
+#if ZDEBUG > 1
+	puts("output_data      0x");
+	int2hex((unsigned long)output_data); puts("\n");
+	puts("free_mem_ptr     0x");
+	int2hex(free_mem_ptr); puts("\n");
+	puts("free_mem_end_ptr 0x");
+	int2hex(free_mem_end_ptr); puts("\n");
+	puts("input_data       0x");
+	int2hex((unsigned long)input_data); puts("\n");
+#endif
+}
+
+int decompress_kernel(void)
+{
+#if ZDEBUG > 0
+  putc_init();
+#if ZDEBUG > 2
+  check_mem();
+#endif
+#endif
+
+  variable_init();
+
+  makecrc();
+#if ZDEBUG > 0
+  puts("\n");
+  puts("Uncompressing Linux... \n");
+#endif
+  gunzip();		// ...see inflate.c
+#if ZDEBUG > 0
+  puts("Ok, booting the kernel.\n");
+#endif
+
+#if ZDEBUG > 1
+ {
+  unsigned long *p = (unsigned long *)LOADADDR;
+  int2hex(p[0]); puts("\n");
+  int2hex(p[1]); puts("\n");
+  int2hex(p[2]); puts("\n");
+  int2hex(p[3]); puts("\n");
+ }
+#endif
+
+  return 0;
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/rImage.lds idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/rImage.lds
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/rImage.lds	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/rImage.lds	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,31 @@
+OUTPUT_ARCH(mips)
+ENTRY(zstartup)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = 0x9FC00000;
+  .init          : { *(.init)		} =0
+  .text      :
+  {
+    _ftext = . ;
+    *(.text)
+    *(.rodata)
+    *(.rodata1)
+   . = ALIGN(4096);
+    input_data = .;
+    arch/mips/idt-boards/rc32300/EB355/boot/piggy.o
+    input_data_end = .;
+   . = ALIGN(4096);
+    *(.gnu.warning)
+  } =0
+
+  .reginfo : { *(.reginfo) }
+
+   . = 0x800A0000;
+  __bss_start = .;
+  .bss       :
+  {
+   *(.bss)
+  _end = . ;
+  }
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/s355ram.h idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/s355ram.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/s355ram.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/s355ram.h	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,613 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   IDT EB355 SDRAM setup values.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+
+#ifndef __S355RAM__
+#define __S355RAM__
+
+#define SRAM_ONLY     1
+#define SDRAM_ONLY    2
+#define SRAM_N_SDRAM  3
+#define SDRAM_N_SRAM  4
+ 
+#define MB16	1
+#define MB32	2
+#define MB64	3
+#define MB128	4
+#define MB32SO	5
+
+
+#define EXTU  1
+#define INTU  2
+
+#define RST_CTL_BASE      PHYS_TO_K1(0x18008000)  /* base address of reset controller register */
+#define DEV_CTL_BASE      PHYS_TO_K1(0x18010000)  /* base address of device controller Registers */
+#define SDRAM_CTL_BASE    PHYS_TO_K1(0x18018000)  /* base address of SDRAM controller Registers */
+#define BANYAN_IREG_BASE  PHYS_TO_K1(0x18000000)  /* all Banyan internal registers' base address */
+#define GPIO_BASE         PHYS_TO_K1(0x18040000)
+#define ERR_CNTL_STATUS   0xb8028030
+#define ERR_CNTL_VALUE    0x000000bf
+
+/*
+** b14:13=>01=PROM;b12=>1= do not assert CS during writes; b11:10=>00=8 bit port
+** b09:05=>0A=10 wait states; b04:00=>0A= 10 wait states
+*/
+
+
+/********  Chip Select 0 Control Register settings ***********/
+#if defined(EB355)
+#define MCR_CS0_BS    0x028A2204
+#define MCR_CS0_TC    0x00000A44
+#else
+#define MCR_CS0_BS    0x01CA333C
+#define MCR_CS0_TC    0x00001FFF
+#endif
+
+/*
+** b14:13=>00=SRAM;b12=>0= assert CS during writes; b11:10=>10=32 bit port
+** b09:05=>FF=31 wait states; b04:00=>FF= 31 wait states.
+** NOTE: wait states should be tuned.
+*/
+
+
+/*#define MCR_CS1_BS    0x28e728e7*/
+#if defined(EB355)
+#define MCR_CS1_BS    0x01C73336
+#define MCR_CS1_TC    0x00000A44
+#else
+#define MCR_CS1_BS    0x01C73336
+#define MCR_CS1_TC    0x00001fff
+#endif
+
+/*
+** b14:13=>01=I Type;b12=>0= assert CS during writes; b11:10=>00=8 bit port
+** b09:05=>FF=31 wait states; b04:00=>FF= 31 wait states
+*/
+#if defined(EB355)
+#define MCR_CS2_BS    0x028A2204
+#ifdef FLASHSZ
+#define MCR_CS2_TC    (0x00000A44 | FLASHSZ)
+#else
+#define MCR_CS2_TC    0x00000A46
+#endif
+#else
+#define MCR_CS2_BS    0x0ffffff4
+#define MCR_CS2_TC    0x00001fff
+#endif
+
+#if defined(EB355)
+#define MCR_CS3_BS    0x0ffffff4
+#define MCR_CS3_TC    0x00001fff
+#endif
+
+#define MCR_CS4_BS    0x0ffffff4
+#define MCR_CS4_TC    0x00001fff
+
+#define MCR_CS5_BS    0x0ffffff4
+#define MCR_CS5_TC    0x00001fff
+
+/*
+** physical memory base address register value for Chip Select 0 - EPROM
+** NOTE: for starters see if you can just set the default value: 0x1FC00000 Banyan
+*/
+#define MBA_REG0    0x1FC00000
+
+/*
+** memory base mask register value for Chip Select 0 - EPROM - 4MB Banyan
+*/
+#define MBM_REG0    0xFFC00000
+
+#ifdef EB355
+#define MBA_REG2    0x0C000000
+#ifdef FLASHSZ
+#define MBM_REG2    (~(0x200000 * FLASHSZ - 1))
+#else
+#define MBM_REG2    0xFFC00000
+#endif
+#else
+#define MBA_REG2    0x0C000000
+#define MBM_REG2    0xFC000000
+#endif
+
+#ifdef EB355
+#define MBA_REG3    0x1A000000
+#define MBM_REG3    0xFFFF0000
+#endif
+
+#define MBA_REG4    0x14000000
+#define MBM_REG4    0xFC000000
+
+#define MBA_REG5    0x00000000
+#ifdef EB355
+#define MBM_REG5    0x00000000
+#else
+#define MBM_REG5    0xFC000000
+#endif
+
+#define CPU_BERR_BS   0xFF
+#define IP_BERR_BS    0xFF
+
+
+
+#if MEMCFG == SRAM_ONLY
+/*
+** physical memory base address register value for Chip Select 1 - SRAM
+*/
+#define MBA_REG1    0x00000000
+
+/*
+** memory base mask register value for Chip Select 1 - SRAM - 1MB
+*/
+#define MBM_REG1    0xFFF00000
+
+#elif MEMCFG == SDRAM_ONLY || MEMCFG == SDRAM_N_SRAM
+/*
+*************************************
+** SDRAM_ONLY or SDRAM_N_SRAM section
+*************************************
+*/
+
+#define APATTERN 0xa5a5a5a5
+
+#if DRAMSZ == MB64
+/*
+===============================
+== 128MB section
+===============================
+*/
+/*
+** DRAM BANK0 BASE.  Starting Bank at 0MB:
+*/
+#define DRAM_BNK0_BASE    0x00000000
+/*
+** DRAM BANK1 BASE. 2nd bank at 64MB:
+*/
+#define DRAM_BNK1_BASE    0x04000000
+/*
+** DRAM Bank 0 Mask
+*/
+#define DRAM_BNK0_MASK    0xFFF00000
+/*
+** DRAM Bank 1 Mask
+*/
+#define DRAM_BNK1_MASK    DRAM_BNK0_MASK
+/*
+** SDRAM ENABLE Settings
+*/
+#define SDRAM_CR_BS   0xb95500FF  /* old: 0x9EFBOOFF */
+/*
+** SDRAM DISABLE Settings
+*/
+#define SDRAM_DS_BS   0x2AF800FF
+/*
+** Precharge Value
+*/
+#define SDRAM_PC_VAL    0xb95501a0
+/*
+** Refresh Cmd
+*/
+#define SDRAM_RFRSH_CMD   0xb9550090
+/*
+** Mode Register
+*/
+#define SDRAM_MODE_REG    0xAAF80080
+
+#if MEMCFG == SDRAM_N_SRAM
+/*
+** physical memory base address register value for Chip Select 1 - SRAM
+** at 128MB:
+*/
+#define MBA_REG1    0x08000000
+
+/*
+** memory base mask register value for Chip Select 1 - SRAM - 1MB
+*/
+#define MBM_REG1    0xFFF00000
+
+#endif /* #if MEMCFG == SDRAM_N_SRAM */
+
+#elif DRAMSZ == MB32
+/*
+===============================
+== 32MB section
+===============================
+*/
+/*
+** DRAM BANK0 BASE.  Starting Bank at 0MB:
+*/
+#define DRAM_BNK0_BASE    0x00000000
+/*
+** DRAM BANK1 BASE. 2nd bank at 8MB:
+*/
+#define DRAM_BNK1_BASE    0x00800000
+/*
+** DRAM Bank 0 Mask
+*/
+#define DRAM_BNK0_MASK    0xFF800000
+/*
+** DRAM Bank 1 Mask
+*/
+#define DRAM_BNK1_MASK    DRAM_BNK0_MASK
+/*
+** SDRAM ENABLE Settings
+*/
+#define SDRAM_CR_BS   0xB95500FF  /* 11:18:99 0xBAF800FF */
+/*
+** SDRAM DISABLE Settings
+*/
+#define SDRAM_DS_BS   0x395500FF  /* 11:18:99 0x3AF800FF */
+/*
+** Precharge Value
+*/
+#define SDRAM_PC_VAL    0xB95501A0  /* 11:18:99 0xBAF801A0 */
+/*
+** Refresh Cmd
+*/
+#define SDRAM_RFRSH_CMD   0xB9550090  /* 11:18:99 0xBAF80090 */
+/*
+** Mode Register
+*/
+#define SDRAM_MODE_REG    0xB9550080  /* 11:18:99 0xBAF80080 */
+/*
+** Refresh Count Register Bit Settings
+*/
+#define DRAM_RF_CNT_BS    0x00000000
+/*
+** Refresh Compare Register Bit Settings
+*/
+#define DRAM_RF_CMPR_BS   0x00000040
+/*
+** Refresh Compare Register Bit Settings for Slow Expiration
+*/
+#define DRAM_RF_CMPR_SE_BS  0x000002A0
+
+#if MEMCFG == SDRAM_N_SRAM
+/*
+** physical memory base address register value for Chip Select 1 - SRAM
+** at 32MB:
+*/
+#define MBA_REG1    0x04000000
+
+/*
+** memory base mask register value for Chip Select 1 - SRAM - 1MB
+*/
+#define MBM_REG1    0xFFF00000
+#endif /* MEMCFG == SDRAM_N_SRAM */
+#elif DRAMSZ == MB32SO
+/*
+===============================
+== 32MB SODIMM section
+===============================
+*/
+/*
+** DRAM BANK0 BASE.  Starting Bank at 0MB:
+*/
+#define DRAM_BNK0_BASE    0x00000000
+/*
+** DRAM BANK1 BASE. 2nd bank at 8MB:
+*/
+#define DRAM_BNK1_BASE    0x02000000
+/*
+** DRAM Bank 0 Mask
+*/
+#define DRAM_BNK0_MASK    0xFE000000
+/*
+** DRAM Bank 1 Mask
+*/
+#define DRAM_BNK1_MASK          0xFE000000
+/*
+** SDRAM ENABLE Settings
+*/
+/* for other boards such as S355, EB355
+*/
+#define SDRAM_CR_BS             0x9a281080
+/*
+** SDRAM DISABLE Settings
+*/
+#define SDRAM_DS_BS   0x1a681080
+/*
+** Precharge Value
+*/
+#define SDRAM_PC_VAL    0x1a6810c3
+/*
+** Refresh Cmd
+*/
+
+#define SDRAM_RFRSH_CMD         0x1a681093
+/*
+** Mode Register
+*/
+#define SDRAM_MODE_REG          0x1a681083
+
+/*
+** Refresh Count Register Bit Settings
+*/
+#define DRAM_RF_CNT_BS    0x00000000
+/*
+** Refresh Compare Register Bit Settings
+*/
+#define DRAM_RF_CMPR_BS   0x00000040
+/*
+** Refresh Compare Register Bit Settings for Slow Expiration
+*/
+#define DRAM_RF_CMPR_SE_BS  0x00000271
+
+//#if MEMCFG == SDRAM_N_SRAM
+/*
+** physical memory base address register value for Chip Select 1 - SRAM
+** at 32MB:
+*/
+#define MBA_REG1    0x02000000
+
+/*
+** memory base mask register value for Chip Select 1 - SRAM - 1MB
+*/
+#define MBM_REG1    0xFFF00000
+#endif /* MEMCFG == SDRAM_N_SRAM */
+
+//#endif /* DRAMSZ == MB32SO */
+
+#elif MEMCFG == SRAM_N_SDRAM
+
+#define APATTERN 0xa5a5a5a5
+
+/*
+*******************************
+** SRAM and SDRAM section
+*******************************
+*/
+#if DRAMSZ == MB128
+/*
+===============================
+== 128MB section
+===============================
+*/
+/*
+** physical memory base address register value for Chip Select 1 - SRAM
+*/
+#define MBA_REG1    0x00000000
+
+/*
+** memory base mask register value for Chip Select 1 - SRAM - 1MB
+*/
+#define MBM_REG1    0xFFF00000
+
+/*
+** DRAM BANK0 BASE.  Starting Bank at 32MB:
+*/
+#define DRAM_BNK0_BASE    0x02000000
+/*
+** DRAM BANK1 BASE. 2nd bank at 64MB:
+*/
+#define DRAM_BNK1_BASE    0x04000000
+/*
+** DRAM BANK2 BASE. 3rd bank at 96MB:
+*/
+#define DRAM_BNK2_BASE    0x06000000
+/*
+** DRAM BANK3 BASE. 4th bank at 128MB:
+*/
+#define DRAM_BNK3_BASE    0x08000000
+/*
+** DRAM Bank 0 Mask
+*/
+#define DRAM_BNK0_MASK    0xFE000000
+/*
+** DRAM Bank 1 Mask
+*/
+#define DRAM_BNK1_MASK    DRAM_BNK0_MASK
+/*
+** DRAM Bank 2 Mask
+*/
+#define DRAM_BNK2_MASK    DRAM_BNK0_MASK
+/*
+** DRAM Bank 3 Mask
+*/
+#define DRAM_BNK3_MASK    DRAM_BNK0_MASK
+/*
+** SDRAM ENABLE Settings
+*/
+#define SDRAM_CR_BS   0xAAF800FF  /* old: 0x9EFBOOFF */
+/*
+** SDRAM DISABLE Settings
+*/
+#define SDRAM_DS_BS   0x2AF800FF
+/*
+** Precharge Value
+*/
+#define SDRAM_PC_VAL    0xAAF801A0
+/*
+** Refresh Cmd
+*/
+#define SDRAM_RFRSH_CMD   0xAAF80090
+/*
+** Mode Register
+*/
+#define SDRAM_MODE_REG    0xAAF80080
+/*
+** Refresh Count Register Bit Settings
+*/
+#define DRAM_RF_CNT_BS    0x00000000
+/*
+** Refresh Compare Register Bit Settings
+*/
+#define DRAM_RF_CMPR_BS   0x00000040
+/*
+** Refresh Compare Register Bit Settings for Slow Expiration
+*/
+#define DRAM_RF_CMPR_SE_BS  0x000000A0
+
+#elif DRAMSZ == MB32
+/*
+===============================
+== 32MB section
+===============================
+*/
+
+/*
+** physical memory base address register value for Chip Select 1 - SRAM
+*/
+#define MBA_REG1    0x00000000
+
+/*
+** memory base mask register value for Chip Select 1 - SRAM - 1MB
+*/
+#define MBM_REG1    0xFFF00000
+
+/*
+** DRAM BANK0 BASE.  Starting Bank at 8MB:
+*/
+#define DRAM_BNK0_BASE    0x00800000
+/*
+** DRAM BANK1 BASE. 2nd bank at 16MB:
+*/
+#define DRAM_BNK1_BASE    0x01000000
+
+/*
+** DRAM Bank 0 Mask
+*/
+#define DRAM_BNK0_MASK    0xFF800000
+/*
+** DRAM Bank 1 Mask
+*/
+#define DRAM_BNK1_MASK    DRAM_BNK0_MASK
+/*
+** SDRAM ENABLE Settings
+*/
+#define SDRAM_CR_BS   0xB95500FF  /* 11:18:99 0xBAF800FF */
+/*
+** SDRAM DISABLE Settings
+*/
+#define SDRAM_DS_BS   0x395500FF  /* 11:18:99 0x3AF800FF */
+/*
+** Precharge Value
+*/
+#define SDRAM_PC_VAL    0xB95501A0  /* 11:18:99 0xBAF801A0 */
+/*
+** Refresh Cmd
+*/
+#define SDRAM_RFRSH_CMD   0xB9550090  /* 11:18:99 0xBAF80090 */
+/*
+** Mode Register
+*/
+#define SDRAM_MODE_REG    0xB9550080  /* 11:18:99 0xBAF80080 */
+/*
+** Refresh Count Register Bit Settings
+*/
+#define DRAM_RF_CNT_BS    0x00000000
+/*
+** Refresh Compare Register Bit Settings
+*/
+#define DRAM_RF_CMPR_BS   0x00000040
+/*
+** Refresh Compare Register Bit Settings for Slow Expiration
+*/
+#define DRAM_RF_CMPR_SE_BS  0x000002A0  /* 11:18:99 0x000000A0 */
+
+#elif DRAMSZ == MB32SO
+/*
+===============================
+== 32MB section
+===============================
+*/
+
+/*
+** physical memory base address register value for Chip Select 1 - SRAM
+*/
+#define MBA_REG1    0x00000000
+
+/*
+** memory base mask register value for Chip Select 1 - SRAM - 1MB
+*/
+#define MBM_REG1    0xFFF00000
+
+/*
+** DRAM BANK0 BASE.  Starting Bank at 32MB:
+*/
+#define DRAM_BNK0_BASE    0x02000000
+/*
+** DRAM BANK1 BASE. 2nd bank at 16MB:
+*/
+#define DRAM_BNK1_BASE    0x02100000
+/*
+** DRAM Bank 0 Mask
+*/
+#define DRAM_BNK0_MASK    0xFE000000
+/*
+** DRAM Bank 1 Mask
+*/
+#define DRAM_BNK1_MASK    0xFE000000
+/*
+** SDRAM ENABLE Settings
+*/
+#define SDRAM_CR_BS   0x9a281080
+/*
+** SDRAM DISABLE Settings
+*/
+#define SDRAM_DS_BS   0x1a681080
+/*
+** Precharge Value
+*/
+#define SDRAM_PC_VAL    0x1a6810c3
+/*
+** Refresh Cmd
+*/
+
+#define SDRAM_RFRSH_CMD         0x1a681093
+/*
+** Mode Register
+*/
+
+#define SDRAM_MODE_REG          0x1a681083
+/*
+** Refresh Count Register Bit Settings
+*/
+#define DRAM_RF_CNT_BS    0x00000000
+/*
+** Refresh Compare Register Bit Settings
+*/
+#define DRAM_RF_CMPR_BS   0x00000040
+/*
+** Refresh Compare Register Bit Settings for Slow Expiration
+*/
+#define DRAM_RF_CMPR_SE_BS  0x00000271  /* 11:18:99 0x000000A0 */
+
+
+#else
+#error "unrecognized dram size"
+#endif /* DRAMSZ */
+
+#else
+#error "unrecogized memory configuration parameter"
+#endif /* error */
+
+#endif /* __S355RAM__ */
+
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/s364.h idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/s364.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/s364.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/s364.h	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,156 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   LCD Display routines
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef __S364134__
+#define __S364134__
+/******************************** D E F I N E S *******************************/
+#ifndef GPIO_BASE
+#ifdef S355
+#define GPIO_BASE PHYS_TO_K1(0x18040000)
+#else
+#define GPIO_BASE PHYS_TO_K1(0x18000600)
+#endif
+#endif
+/*
+** following defines simple and uniform to save and restore context
+** when enrtering and leaving as assemblu language program when memory
+** and registers are both premiunm.
+*/
+#define SAVE_CNTXT    \
+  subu  sp,64;    \
+  sw  t0,60(sp);  \
+  sw  t1,56(sp);  \
+  sw  t2,52(sp);  \
+  sw  t3,48(sp);  \
+  sw  t4,44(sp);  \
+  sw  t5,40(sp);  \
+  sw  t6,36(sp);  \
+  sw  t7,32(sp);  \
+  sw  t8,28(sp);  \
+  sw  t9,24(sp);  \
+  sw  a0,20(sp);  \
+  sw  a1,16(sp);  \
+  sw  a2,12(sp);  \
+  sw  a3,8(sp); \
+  sw  ra,4(sp)
+
+#define RSTR_CNTXT    \
+  lw  t0,60(sp);  \
+  lw  t1,56(sp);  \
+  lw  t2,52(sp);  \
+  lw  t3,48(sp);  \
+  lw  t4,44(sp);  \
+  lw  t5,40(sp);  \
+  lw  t6,36(sp);  \
+  lw  t7,32(sp);  \
+  lw  t8,28(sp);  \
+  lw  t9,24(sp);  \
+  lw  a0,20(sp);  \
+  lw  a1,16(sp);  \
+  lw  a2,12(sp);  \
+  lw  a3,8(sp); \
+  lw  ra,4(sp); \
+  add sp,64
+
+/*
+** Following define is to specify a maximum value for a software
+** busy wait counter.
+*/
+
+#define LP_CNT_100NS  1000      /* set this based on processor speed */
+#define LP_CNT_3S     1000000   /* set this based on processor speed */
+
+/*
+** Following are other common timer definitions.
+*/
+#ifdef S355
+#define TIMER_BASE    PHYS_TO_K1(0x18028000)  
+#define TIMEOUT_COUNT 0x00000FFF
+#else
+#define TIMER_BASE    PHYS_TO_K1(0x18000700)  
+#endif
+#define ENABLE_TIMER  0x1
+#define DISABLE_TIMER 0x0
+#define BIG_VALUE     0xFFFFFFFF
+
+#ifdef S355
+/* There is no DISPLAY on 355 boards*/
+#elif defined(S334)
+/*
+** following few lines define a macro DISPLAY
+** which is used to write a set of 4 characters
+** onto the S334 LED.
+*/
+
+#if defined(EB332)
+#define LED_BASE      PHYS_TO_K1(0x10000000)
+#define LED_DIGIT0    0xc
+#define LED_DIGIT1    0x8
+#define LED_DIGIT2    0x4
+#define LED_DIGIT3    0x0
+
+#define LED_CLEAR     0x400
+
+#else
+#define LED_BASE      PHYS_TO_K1(0x14000000)
+#define LED_DIGIT0    0xf
+#define LED_DIGIT1    0xb
+#define LED_DIGIT2    0x7
+#define LED_DIGIT3    0x3
+
+#define LED_CLEAR     0x400
+
+#endif
+
+#define DISPLAY(d0, d1, d2, d3)     \
+        li    t6, LED_BASE                    ;\
+        lb    t7, LED_CLEAR(t6)               ;\
+              nop                             ;\
+        li    t7, (d0) & 0xff                 ;\
+        sb    t7, LED_DIGIT0(t6)              ;\
+        li    t7, (d1) & 0xff                 ;\
+        sb    t7, LED_DIGIT1(t6)              ;\
+        li    t7, (d2) & 0xff                 ;\
+        sb    t7, LED_DIGIT2(t6)              ;\
+        li    t7, (d3) & 0xff                 ;\
+        sb    t7, LED_DIGIT3(t6)
+
+#define LEDCLEAR()              \
+        li    t6, LED_BASE                    ;\
+        lb    t7, LED_CLEAR(t6)               ;\
+              nop
+
+#endif
+
+#define DESTRUCTIVE     1
+#define NONDESTRUCTIVE  0
+
+#endif
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/uart16550.c idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/uart16550.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/uart16550.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/uart16550.c	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,180 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   UART code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+
+#define RC32355_REG_BASE   0xb8000000
+#ifdef __MIPSEB__
+#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50003)
+#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50023)
+#else
+#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50000)
+#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50020)
+#endif
+
+#define BASE		   RC32300_UART0_BASE
+
+#define MAX_BAUD		(CONFIG_IDT_BOARD_FREQ / 16)
+#define REG_OFFSET		0x4
+
+/* === CONFIG === */
+
+/*
+ * #define BASE			0xb2001000
+ * #define MAX_BAUD		1152000
+ * #define REG_OFFSET		0x10
+ */
+#if (!defined(BASE) || !defined(MAX_BAUD) || !defined(REG_OFFSET))
+#error You must define BASE, MAX_BAUD and REG_OFFSET in the Makefile.
+#endif
+
+#ifndef INIT_SERIAL_PORT
+#define INIT_SERIAL_PORT	1
+#endif
+
+#ifndef DEFAULT_BAUD
+//#define DEFAULT_BAUD		UART16550_BAUD_115200
+#define DEFAULT_BAUD		UART16550_BAUD_9600
+#endif
+#ifndef DEFAULT_PARITY
+#define DEFAULT_PARITY		UART16550_PARITY_NONE
+#endif
+#ifndef DEFAULT_DATA
+#define DEFAULT_DATA		UART16550_DATA_8BIT
+#endif
+#ifndef DEFAULT_STOP
+#define DEFAULT_STOP		UART16550_STOP_1BIT
+#endif
+
+/* === END OF CONFIG === */
+
+typedef         unsigned char uint8;
+typedef         unsigned int  uint32;
+
+#define         UART16550_BAUD_2400             2400
+#define         UART16550_BAUD_4800             4800
+#define         UART16550_BAUD_9600             9600
+#define         UART16550_BAUD_19200            19200
+#define         UART16550_BAUD_38400            38400
+#define         UART16550_BAUD_57600            57600
+#define         UART16550_BAUD_115200           115200
+
+#define         UART16550_PARITY_NONE           0
+#define         UART16550_PARITY_ODD            0x08
+#define         UART16550_PARITY_EVEN           0x18
+#define         UART16550_PARITY_MARK           0x28
+#define         UART16550_PARITY_SPACE          0x38
+
+#define         UART16550_DATA_5BIT             0x0
+#define         UART16550_DATA_6BIT             0x1
+#define         UART16550_DATA_7BIT             0x2
+#define         UART16550_DATA_8BIT             0x3
+
+#define         UART16550_STOP_1BIT             0x0
+#define         UART16550_STOP_2BIT             0x4
+
+/* register offset */
+#define		OFS_RCV_BUFFER		(0*REG_OFFSET)
+#define		OFS_TRANS_HOLD		(0*REG_OFFSET)
+#define		OFS_SEND_BUFFER		(0*REG_OFFSET)
+#define		OFS_INTR_ENABLE		(1*REG_OFFSET)
+#define		OFS_INTR_ID		(2*REG_OFFSET)
+#define		OFS_DATA_FORMAT		(3*REG_OFFSET)
+#define		OFS_LINE_CONTROL	(3*REG_OFFSET)
+#define		OFS_MODEM_CONTROL	(4*REG_OFFSET)
+#define		OFS_RS232_OUTPUT	(4*REG_OFFSET)
+#define		OFS_LINE_STATUS		(5*REG_OFFSET)
+#define		OFS_MODEM_STATUS	(6*REG_OFFSET)
+#define		OFS_RS232_INPUT		(6*REG_OFFSET)
+#define		OFS_SCRATCH_PAD		(7*REG_OFFSET)
+
+#define		OFS_DIVISOR_LSB		(0*REG_OFFSET)
+#define		OFS_DIVISOR_MSB		(1*REG_OFFSET)
+
+#define		UART16550_READ(y)    (*((volatile uint8*)(BASE + y)))
+#define		UART16550_WRITE(y, z)  ((*((volatile uint8*)(BASE + y))) = z)
+
+static void Uart16550Init(uint32 baud, uint8 data, uint8 parity, uint8 stop)
+{
+	/* disable interrupts */
+	UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
+	UART16550_WRITE(OFS_INTR_ENABLE, 0);
+
+	/* set up baud rate */
+	{
+		uint32 divisor;
+
+		/* set DIAB bit */
+		UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
+
+		/* set divisor */
+		divisor = MAX_BAUD / baud;
+		UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
+		UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00)>>8);
+
+		/* clear DIAB bit */
+		UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
+	}
+
+	/* set data format */
+	UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
+}
+
+
+void
+putc_init(void)
+{
+#if INIT_SERIAL_PORT
+	Uart16550Init(DEFAULT_BAUD, DEFAULT_DATA, DEFAULT_PARITY, DEFAULT_STOP);
+#endif
+}
+
+void
+putc(unsigned char c)
+{
+	while ((UART16550_READ(OFS_LINE_STATUS) &0x20) == 0);
+	UART16550_WRITE(OFS_SEND_BUFFER, c);
+}
+
+#if 0
+unsigned char
+getc(void)
+{
+	while((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
+	return UART16550_READ(OFS_RCV_BUFFER);
+}
+
+int
+tstc(void)
+{
+	return((UART16550_READ(OFS_LINE_STATUS) & 0x01) != 0);
+}
+#endif
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/zImage.lds idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/zImage.lds
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/zImage.lds	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/zImage.lds	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,31 @@
+OUTPUT_ARCH(mips)
+ENTRY(zstartup)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = 0x8c000000;
+  .init          : { *(.init)		} =0
+  .text      :
+  {
+    _ftext = . ;
+    *(.text)
+    *(.rodata)
+    *(.rodata1)
+   . = ALIGN(4096);
+    input_data = .;
+    arch/mips/idt-boards/rc32300/EB355/boot/piggy.o
+    input_data_end = .;
+   . = ALIGN(4096);
+    *(.gnu.warning)
+  } =0
+
+  .reginfo : { *(.reginfo) }
+
+   . = 0x800A0000;
+  __bss_start = .;
+  .bss       :
+  {
+   *(.bss)
+  _end = . ;
+  }
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/idtIRQ.S idtlinux/arch/mips/idt-boards/rc32300/EB355/idtIRQ.S
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/idtIRQ.S	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/idtIRQ.S	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,75 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Interrupt dispatcher for IDT EB355 boards
+ *
+ *  Copyright 2006 IDT Inc.
+ *  Author: Integrated Device Technology Inc. rischelp@idt.com
+ *
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+	
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
+
+	.text
+	.set	noreorder
+	.set	noat
+	.align	5
+	NESTED(rc32300_IRQ, PT_SIZE, sp)
+	SAVE_ALL
+	CLI
+
+	.set	at
+	.set	noreorder
+
+	/* Get the pending interrupts */
+	mfc0    t0, CP0_CAUSE
+	nop
+			 
+	/* Isolate the allowed ones by anding the irq mask */
+	mfc0    t2, CP0_STATUS 
+	move	a1, sp		/* need a nop here, hence we anticipate */
+	andi	t0, CAUSEF_IP 
+	and     t0, t2
+								  
+	/* check for r4k counter/timer IRQ. */
+	
+	andi    t1, t0, CAUSEF_IP7
+	beqz    t1, 1f
+	nop
+
+	jal     idt_timer_interrupt	/* bypass rc32300_irqdispatch */
+	li	a0, 7
+	j	ret_from_irq
+	nop
+1:
+	jal	rc32300_irqdispatch
+	move	a0, t0
+	j	ret_from_irq
+	nop
+
+	END(rc32300_IRQ)
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/irq.c idtlinux/arch/mips/idt-boards/rc32300/EB355/irq.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/irq.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/irq.c	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,287 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     RC32355 interrupt routines.
+ *
+ *  Copyright 2006 IDT Inc.
+ *  Author: Integrated Device Technology Inc. rischelp@idt.com
+ *
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/delay.h>
+
+#include <asm/bitops.h>
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+#include <asm/idt-boards/rc32300/rc32300.h>
+
+#undef DEBUG_IRQ
+#ifdef DEBUG_IRQ
+/* note: prints function name for you */
+#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
+#else
+#define DPRINTK(fmt, args...)
+#endif
+
+extern asmlinkage void rc32300_IRQ(void);
+extern irq_cpustat_t irq_stat [NR_CPUS];
+unsigned int local_bh_count[NR_CPUS];
+unsigned int local_irq_count[NR_CPUS];
+
+static unsigned int startup_irq(unsigned int irq);
+static void end_irq(unsigned int irq_nr);
+static void mask_and_ack_irq(unsigned int irq_nr);
+static void rc32355_enable_irq(unsigned int irq_nr);
+static void rc32355_disable_irq(unsigned int irq_nr);
+
+extern void __init init_generic_irq(void);
+
+#ifdef CONFIG_PM
+extern void counter0_irq(int irq, void *dev_id, struct pt_regs *regs);
+#endif
+
+typedef struct {
+	u32 mask;       /* mask of valid bits in pending/mask registers */
+	volatile u32 *base_addr;
+} intr_group_t;
+
+static const intr_group_t intr_group[NUM_INTR_GROUPS] = {
+	{ 0x0000003f, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET) },
+	{ 0x0000ffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET) },
+	{ 0x000003ff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET) },
+	{ 0x00ffffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET) },
+	{ 0xffffffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET) }
+};
+
+#define READ_PEND(base) (*(base))
+#define READ_MASK(base) (*(base + 1))
+#define WRITE_MASK(base, val) (*(base + 1) = (val))
+
+static inline int irq_to_group(unsigned int irq_nr)
+{
+	return ((irq_nr - GROUP0_IRQ_BASE) >> 5);
+}
+
+static inline int group_to_ip(unsigned int group)
+{
+	return group + 2;
+}
+
+static inline void enable_local_irq(unsigned int ip)
+{
+	int ipnum = 0x100 << ip;
+	clear_c0_cause(ipnum);
+	set_c0_status(ipnum);
+}
+
+static inline void disable_local_irq(unsigned int ip)
+{
+	int ipnum = 0x100 << ip;
+	clear_c0_status(ipnum);
+}
+
+static inline void ack_local_irq(unsigned int ip)
+{
+	int ipnum = 0x100 << ip;
+	clear_c0_cause(ipnum);
+}
+
+static void rc32355_enable_irq(unsigned int irq_nr)
+{
+	unsigned long flags;
+	int           ip = irq_nr - GROUP0_IRQ_BASE;
+	unsigned int  group, intr_bit;
+	volatile unsigned int  *addr;
+	
+	local_irq_save(flags);
+	if (ip < 0)
+		enable_local_irq(irq_nr);
+	else {
+		// calculate group
+		group = ip >> 5;
+		
+		// calc interrupt bit within group
+		ip -= (group << 5);
+		intr_bit = 1 << ip;
+		
+		// first enable the IP mapped to this IRQ
+		enable_local_irq(group_to_ip(group));
+		
+		addr = intr_group[group].base_addr;
+		// unmask intr within group
+		WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
+	}
+	
+	local_irq_restore(flags);
+}
+
+static void rc32355_disable_irq(unsigned int irq_nr)
+{
+	unsigned long flags;
+	int           ip = irq_nr - GROUP0_IRQ_BASE;
+	unsigned int  group, intr_bit, mask;
+	volatile unsigned int  *addr;
+	
+	local_irq_save(flags);
+	if (ip < 0)
+		disable_local_irq(irq_nr);
+	else {
+		// calculate group
+		group = ip >> 5;
+		
+		// calc interrupt bit within group
+		ip -= group << 5;
+		intr_bit = 1 << ip;
+		
+		addr = intr_group[group].base_addr;
+		// mask intr within group
+		mask = READ_MASK(addr);
+		mask |= intr_bit;
+		WRITE_MASK(addr, mask);
+		
+		/*
+		  if there are no more interrupts enabled in this
+		  group, disable corresponding IP
+		*/
+		if (mask == intr_group[group].mask)
+			disable_local_irq(group_to_ip(group));
+	}
+	
+	local_irq_restore(flags);
+}
+
+static unsigned int startup_irq(unsigned int irq_nr)
+{
+	rc32355_enable_irq(irq_nr);
+	return 0; 
+}
+
+static void shutdown_irq(unsigned int irq_nr)
+{
+	rc32355_disable_irq(irq_nr);
+	return;
+}
+
+static void mask_and_ack_irq(unsigned int irq_nr)
+{
+	rc32355_disable_irq(irq_nr);
+	ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
+}
+
+static void end_irq(unsigned int irq_nr)
+{
+	int ip = irq_nr - GROUP0_IRQ_BASE;
+	unsigned int intr_bit, group;
+	volatile unsigned int *addr;
+	
+	if (!(irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
+		if (ip < 0)
+			enable_local_irq(irq_nr);
+		else {
+			
+			group = ip >> 5;
+			
+			// calc interrupt bit within group
+			ip -= (group << 5);
+			intr_bit = 1 << ip;
+			
+			// first enable the IP mapped to this IRQ
+			enable_local_irq(group_to_ip(group));
+			
+			addr = intr_group[group].base_addr;
+			// unmask intr within group
+			WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
+		}
+	} 
+	else {
+		printk("warning: end_irq %d did not enable (%x)\n", 
+		       irq_nr, irq_desc[irq_nr].status);
+	}
+}
+
+static struct hw_interrupt_type rc32355_irq_type = {
+	"RC32355",
+	startup_irq,
+	shutdown_irq,
+	rc32355_enable_irq,
+	rc32355_disable_irq,
+	mask_and_ack_irq,
+	end_irq,
+	NULL
+};
+
+
+void __init arch_init_irq(void)
+{
+	int i;
+	
+	printk("Initializing IRQ's: %d\n", RC32355_NR_IRQS);
+	memset(irq_desc, 0, sizeof(irq_desc));
+	set_except_vector(0, rc32300_IRQ);
+	
+	for (i = 0; i < RC32355_NR_IRQS; i++) {
+		irq_desc[i].status = IRQ_DISABLED;
+		irq_desc[i].action = NULL;
+		irq_desc[i].depth = 1;
+		irq_desc[i].handler = &rc32355_irq_type;
+                spin_lock_init(&irq_desc[i].lock);
+	}
+}
+
+/* Main Interrupt dispatcher */
+void rc32300_irqdispatch(unsigned long cp0_cause, struct pt_regs *regs)
+{
+	unsigned int ip, pend, group;
+	volatile unsigned int *addr;
+	
+	if ((ip = (cp0_cause & 0x7c00))) {
+		group = 21 - rc32300_clz(ip);
+		
+		addr = intr_group[group].base_addr;
+		
+		pend = READ_PEND(addr);
+		pend &= ~READ_MASK(addr); // only unmasked interrupts
+		pend = 39 - rc32300_clz(pend);
+		do_IRQ((group << 5) + pend, regs);
+		return;
+	} 
+	else 
+		return; //spurious interrupt, do nothing....
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/lcd.c idtlinux/arch/mips/idt-boards/rc32300/EB355/lcd.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/lcd.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/lcd.c	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,144 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     IDT 79EB355 lcd support.
+ *
+ *  Copyright 2006 IDT Inc.
+ *  Author: Integrated Device Technology Inc. rischelp@idt.com
+ *
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/ioport.h>
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/idt-boards/rc32300/rc32300.h>
+#include <asm/idt-boards/rc32300/rc32355.h>
+
+#define LCD_FUNC_SET    	0x38
+#define	LCD_ENT_MODE    	0x06
+#define	LCD_DISP_ON_CURS_OFF 	0x0C 
+#define	LCD_DISP_ON_CURS_ON 	0x0E 
+#define	LCD_DISP_CLEAR  	0x01
+#define	LCD_DDRAM_ADR_SET_0	0x80
+#define	LCD_DDRAM_ADR_SET_1	0xC0
+
+#define	LCD_MAX_CHAR_PER_LINE 	16
+#define	LCD_MAX_LINES	 	2
+
+
+static void delay_lcd_long(void)
+{
+	int ii ;
+	for (ii = 0 ; ii < 0x5FFFF ; ii++)
+		;
+}
+
+
+static void delay_lcd_short(void)
+{
+	int ii ;
+	for (ii = 0 ; ii < 0x1FFFF ; ii++)
+		;
+}
+
+
+int init_lcd(void)
+{
+	u8* chLcdBase = (u8*)KSEG1ADDR(LCD_BASE);
+	
+	/*-------------- Reset LCD ---------------------------*/
+	
+	delay_lcd_long() ;
+	
+	/* send function select 4 times */
+	rc32300_writeb(LCD_FUNC_SET, (unsigned long)chLcdBase);
+	delay_lcd_long() ;
+	rc32300_writeb(LCD_FUNC_SET, (unsigned long)chLcdBase);
+	delay_lcd_long() ;
+	rc32300_writeb(LCD_FUNC_SET, (unsigned long)chLcdBase);
+	delay_lcd_long() ;
+	rc32300_writeb(LCD_FUNC_SET, (unsigned long)chLcdBase);
+	delay_lcd_long() ;  	
+	
+	
+	rc32300_writeb(LCD_ENT_MODE, (unsigned long)chLcdBase);
+	delay_lcd_long() ;
+
+	rc32300_writeb(LCD_DISP_ON_CURS_OFF, (unsigned long)chLcdBase);
+	delay_lcd_long() ;
+	
+	rc32300_writeb(LCD_DISP_CLEAR, (unsigned long)chLcdBase);
+	delay_lcd_long() ;
+	
+	/* set it to row-0, column-0 */
+	rc32300_writeb(LCD_DDRAM_ADR_SET_0, (unsigned long)chLcdBase);
+	delay_lcd_long() ;
+	
+	return 0;
+}
+
+
+int idtprintf(const char *fmt, ...)
+{
+	va_list args;
+	u8* chLcdData = (u8*)KSEG1ADDR((LCD_BASE+1));
+	u8* chLcdBase = (u8*)KSEG1ADDR(LCD_BASE);
+	char str[LCD_MAX_CHAR_PER_LINE * LCD_MAX_LINES];
+	int iNumChars, iCharsSent;
+	
+	va_start(args, fmt);
+	vsprintf(str, fmt, args);
+	va_end(args);
+	
+	iNumChars = strlen(str);
+	
+	/* Can't have more characters than what will fit on the display */
+	if (iNumChars > (LCD_MAX_CHAR_PER_LINE * LCD_MAX_LINES))
+		iNumChars = (LCD_MAX_CHAR_PER_LINE * LCD_MAX_LINES) ;
+	
+	/* first blank out the whole display */
+	rc32300_writeb(LCD_DISP_CLEAR, (unsigned long)chLcdBase);
+	delay_lcd_long() ;
+	
+	/* set it to row-0, column-0 */
+	rc32300_writeb(LCD_DDRAM_ADR_SET_0, (unsigned long)chLcdBase);
+	delay_lcd_long() ;
+	
+	/* Now display characters one by one*/
+	for(iCharsSent = 0 ; iCharsSent < iNumChars ; iCharsSent++) {
+		if (iCharsSent == LCD_MAX_CHAR_PER_LINE ) {
+			/* move over to the next line */
+			rc32300_writeb(LCD_DDRAM_ADR_SET_1, (unsigned long)chLcdBase); 
+			delay_lcd_long() ;
+		}
+		rc32300_writeb(str[iCharsSent], (unsigned long)chLcdData);
+		delay_lcd_short() ;
+	}
+
+	return iNumChars;
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/Makefile idtlinux/arch/mips/idt-boards/rc32300/EB355/Makefile
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/Makefile	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/Makefile	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,41 @@
+#**************************************************************************
+#
+#  BRIEF MODULE DESCRIPTION
+#     Makefile for EB355 BSP
+#
+#  Copyright 2006 IDT Inc. (rischelp@idt.com)
+#         
+#  This program is free software; you can redistribute  it and/or modify it
+#  under  the terms of  the GNU General  Public License as published by the
+#  Free Software Foundation;  either version 2 of the  License, or (at your
+#  option) any later version.
+#
+#  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+#  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+#  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+#  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+#  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+#  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+#  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+#  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+#  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+#  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#  You should have received a copy of the  GNU General Public License along
+#  with this program; if not, write  to the Free Software Foundation, Inc.,
+#  675 Mass Ave, Cambridge, MA 02139, USA.
+#
+#**************************************************************************
+#
+
+.S.s:
+	$(CPP) $(CFLAGS) $< -o $*.s
+.S.o:
+	$(CC) $(CFLAGS) -c $< -o $*.o
+
+obj-y	 := irq.o lcd.o setup.o idtIRQ.o reset.o prom.o time.o
+obj-$(CONFIG_KGDB)			+= serial_gdb.o
+obj-$(CONFIG_SERIAL_8250)		+= serial.o
+subdir-$(CONFIG_IDT_BOOT_NVRAM)		+= nvram
+obj-$(CONFIG_IDT_BOOT_NVRAM)		+= nvram/built-in.o
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/nvram/Makefile idtlinux/arch/mips/idt-boards/rc32300/EB355/nvram/Makefile
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/nvram/Makefile	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/nvram/Makefile	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,40 @@
+#**************************************************************************
+#
+#  BRIEF MODULE DESCRIPTION
+#     Makefile for nvram driver
+#
+#  Copyright 2006 IDT Inc.
+#  Author: Integrated Device Technology Inc. rischelp@idt.com
+#
+#         
+#  This program is free software; you can redistribute  it and/or modify it
+#  under  the terms of  the GNU General  Public License as published by the
+#  Free Software Foundation;  either version 2 of the  License, or (at your
+#  option) any later version.
+#
+#  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+#  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+#  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+#  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+#  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+#  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+#  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+#  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+#  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+#  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#  You should have received a copy of the  GNU General Public License along
+#  with this program; if not, write  to the Free Software Foundation, Inc.,
+#  675 Mass Ave, Cambridge, MA 02139, USA.
+#
+#
+#*************************************************************************
+#/
+
+.S.s:   
+	$(CPP) $(CFLAGS) $< -o $*.s
+.S.o:   
+	$(CC) $(CFLAGS) -c $< -o $*.o
+
+
+obj-y   := nvram355.o
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/nvram/nvram355.c idtlinux/arch/mips/idt-boards/rc32300/EB355/nvram/nvram355.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/nvram/nvram355.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/nvram/nvram355.c	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,423 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     nvram API
+ *
+ *  Copyright 2006 IDT Inc.
+ *  Author: Integrated Device Technology Inc. rischelp@idt.com
+ *
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include "nvram355.h"
+
+void setenv (char *e, char *v, int rewrite);
+char *getenv (char *e);
+void unsetenv (char *e);
+void mapenv (int (*func)(char *, char *));
+void purgeenv(void);
+extern char *getenv (char *s);
+unsigned int  is_valid = 0;
+static void nvram_initenv(void);
+
+/*
+ * The *env routines provide wrappers to the nvram_*env
+ * routines to allow any special processing of the environment
+ * to be carried out
+ * Yes this is a bit naff
+ */
+#define WAIT(x) { int i=0; while (++i < (x)) ; }
+
+static unsigned char
+nvram_getbyte(int offs)
+{
+	int i = 0;
+
+	unsigned char* nvramAddrPointer = (unsigned char*)(NVRAM_BASE + 0x10);
+	unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + 0x13);
+	
+	*nvramAddrPointer = (unsigned char) offs;
+	
+	while (++i < 0x100);
+	
+	return ((unsigned int)(*nvramDataPointer));
+}
+
+static void
+nvram_setbyte(int offs, unsigned char val)
+{
+	int i = 0;
+	unsigned char* nvramAddrPointer=(unsigned char*)(NVRAM_BASE + 0x10);
+	unsigned char* nvramDataPointer=(unsigned char*)(NVRAM_BASE + 0x13);
+	
+	*nvramAddrPointer=(unsigned char)offs;
+	
+	while(++i < 0x100);
+	
+	*nvramDataPointer = val;
+	
+	i = 0;
+	while(++i < 0x100);
+}
+
+/*
+ * BigEndian!
+ */
+static unsigned short
+nvram_getshort(int offs)
+{
+	return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
+}
+
+static void
+nvram_setshort(int offs, unsigned short val)
+{
+	nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
+	nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
+}
+
+#if 0
+static unsigned int
+nvram_getint(int offs)
+{
+	unsigned int val;
+	val = nvram_getbyte(offs) << 24;
+	val |= nvram_getbyte(offs + 1) << 16;
+	val |= nvram_getbyte(offs + 2) << 8;
+	val |= nvram_getbyte(offs + 3);
+	return(val);
+}
+
+static void
+nvram_setint(int offs, unsigned int val)
+{
+	nvram_setbyte(offs, val >> 24);
+	nvram_setbyte(offs + 1, val >> 16);
+	nvram_setbyte(offs + 2, val >> 8);
+	nvram_setbyte(offs + 3, val);
+}
+#endif
+/*
+ * calculate NVRAM checksum
+ */
+static unsigned short
+nvram_calcsum(void)
+{
+	unsigned short sum = NV_MAGIC;
+	int i;
+	
+	for (i = ENV_BASE; i < ENV_TOP; i += 2)
+		sum += nvram_getshort(i);
+	return(sum);
+}
+
+/*
+ * update the nvram checksum
+ */
+static void
+nvram_updatesum(void)
+{
+	nvram_setshort(NVOFF_CSUM, nvram_calcsum());
+}
+
+/*
+ * test validity of nvram by checksumming it
+ */
+static int
+nvram_isvalid(void)
+{
+#if defined(PRETEND_NVRAM) || defined(NO_NVRAM)
+	is_valid = 1;
+	return(1);
+#else
+	
+	if (is_valid)
+		return(1);
+	
+	if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC) {
+		nvram_initenv();
+		return(0);
+	}
+	
+	is_valid = 1;
+	return(1);
+#endif
+}
+
+/* return nvram address of environment string */
+static int
+nvram_matchenv(char *s)
+{
+	int envsize, envp, n, i, varsize;
+	char *var;
+	
+	envsize = nvram_getshort(NVOFF_ENVSIZE);
+	if (envsize > ENV_AVAIL)
+		return(0);     /* sanity */
+	envp = ENV_BASE;
+	
+	if ((n = strlen (s)) > 255)
+		return(0);
+	
+	while (envsize > 0) {
+		varsize = nvram_getbyte(envp);
+		if (varsize == 0 || (envp + varsize) > ENV_TOP)
+			return(0);   /* sanity */
+		for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
+			char c1 = nvram_getbyte(i);
+			char c2 = *var;
+			if (islower(c1))
+				c1 = toupper(c1);
+			if (islower(c2))
+				c2 = toupper(c2);
+			if (c1 != c2)
+				break;
+		}
+		if (i > envp + n) {   /* match so far */
+			if (n == varsize - 1) /* match on boolean */
+				return(envp);
+			if (nvram_getbyte(i) == '=')  /* exact match on variable */
+				return(envp);
+		}
+		envsize -= varsize;
+		envp += varsize;
+	}
+	return(0);
+}
+
+static void nvram_initenv(void)
+{
+  nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
+  nvram_setshort(NVOFF_ENVSIZE, 0);
+  nvram_updatesum();
+}
+
+static void
+nvram_delenv(char *s)
+{
+	int nenvp, envp, envsize, nbytes;
+	
+	envp = nvram_matchenv(s);
+	if (envp == 0)
+		return;
+	
+	nenvp = envp + nvram_getbyte(envp);
+	envsize = nvram_getshort(NVOFF_ENVSIZE);
+	nbytes = envsize - (nenvp - ENV_BASE);
+	nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
+	while (nbytes--) {
+		nvram_setbyte(envp, nvram_getbyte(nenvp));
+		envp++;
+		nenvp++;
+	}
+	nvram_updatesum();
+}
+
+static int
+nvram_setenv(char *s, char *v)
+{
+	int ns, nv, total;
+	int envp;
+	
+	if (!nvram_isvalid())
+		return(-1);
+	
+	nvram_delenv(s);
+	ns = strlen(s);
+	if (ns == 0)
+		return (-1);
+	if (v && *v) {
+		nv = strlen(v);
+		total = ns + nv + 2;
+	}
+	else {
+		nv = 0;
+		total = ns + 1;
+	}
+	if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
+		return(-1);
+	
+	envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
+	
+	nvram_setbyte(envp, (unsigned char)total);
+	envp++;
+	
+	while (ns--) {
+		nvram_setbyte(envp, *s);
+		envp++;
+		s++;
+	}
+	
+	if (nv) {
+		nvram_setbyte(envp, '=');
+		envp++;
+		while (nv--) {
+			nvram_setbyte(envp, *v);
+			envp++;
+			v++;
+		}
+	}
+	nvram_setshort(NVOFF_ENVSIZE, envp - ENV_BASE);
+	nvram_updatesum();
+	return(0);
+}
+
+static char *
+nvram_getenv(char *s)
+{
+	static char buf[256];
+	int envp, ns, nbytes, i;
+	
+	if (!nvram_isvalid())
+		return((char *)0);
+	
+	envp = nvram_matchenv(s);
+	if (envp == 0)
+		return((char *)0);
+	ns = strlen(s);
+	if (nvram_getbyte(envp) == ns + 1)  /* boolean */
+		buf[0] = '\0';
+	else {
+		nbytes = nvram_getbyte(envp) - (ns + 2);
+		envp += ns + 2;
+		for (i = 0; i < nbytes; i++)
+			buf[i] = nvram_getbyte(envp++);
+		buf[i] = '\0';
+	}
+	return(buf);
+}
+
+static void
+nvram_unsetenv(char *s)
+{
+	if (!nvram_isvalid())
+		return;
+	
+	nvram_delenv(s);
+}
+
+void
+purgeenv()
+{
+	int i;
+	unsigned char temp;
+	
+	unsigned char* nvramAddrPointer = (unsigned char*)(NVRAM_BASE + 0x10);
+	unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + 0x13);
+	
+	/* enable burst mode for DS1511*/
+	unsigned char* controlB = (unsigned char*)(NVRAM_BASE + 0x0F);
+	temp = *controlB;
+	*controlB = temp | 0x20;
+	*nvramAddrPointer = (unsigned char)ENV_BASE;
+	for (i = ENV_BASE; i < ENV_TOP; i++)
+		*nvramDataPointer= 0;
+	*controlB = temp;
+	nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
+	nvram_setshort(NVOFF_ENVSIZE, 0);
+	nvram_setshort(NVOFF_CSUM, NV_MAGIC);
+}
+
+/*
+ * apply func to each string in environment
+ */
+static void
+nvram_mapenv(int (*func)(char *, char *))
+{
+	int envsize, envp, n, i, seeneql;
+	char name[256], value[256];
+	char c, *s;
+	
+	if (!nvram_isvalid())
+		return;
+	
+	envsize = nvram_getshort(NVOFF_ENVSIZE);
+	envp = ENV_BASE;
+	
+	while (envsize > 0) {
+		value[0] = '\0';
+		seeneql = 0;
+		s = name;
+		n = nvram_getbyte(envp);
+		for (i = envp + 1; i < envp + n; i++) {
+			c = nvram_getbyte(i);
+			if ((c == '=') && !seeneql) {
+				*s = '\0';
+				s = value;
+				seeneql = 1;
+				continue;
+			}
+			*s++ = c;
+		}
+		*s = '\0';
+		(*func)(name, value);
+		envsize -= n;
+		envp += n;
+	}
+}
+#if 0
+static unsigned int
+digit(char c)
+{
+	if ('0' <= c && c <= '9')
+		return(c - '0');
+	if ('A' <= c && c <= 'Z')
+		return(10 + c - 'A');
+	if ('a' <= c && c <= 'z')
+		return(10 + c - 'a');
+	return(~0);
+}
+#endif
+
+/*
+ * Wrappers to allow 'special' environment variables to get processed
+ */
+void
+setenv(char *e, char *v, int rewrite)
+{
+	if (nvram_getenv(e) && !rewrite)
+		return;
+	nvram_setenv(e, v);
+}
+
+char *
+getenv(char *e)
+{
+	return(nvram_getenv(e));
+}
+
+void
+unsetenv(char *e)
+{
+	nvram_unsetenv(e);
+}
+
+void
+mapenv(int (*func)(char *, char *))
+{
+	nvram_mapenv(func);
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/nvram/nvram355.h idtlinux/arch/mips/idt-boards/rc32300/EB355/nvram/nvram355.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/nvram/nvram355.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/nvram/nvram355.h	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,72 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     nvram.h: NVRAM layout definitions
+ *
+ *  Copyright 2006 IDT Inc.
+ *  Author: Integrated Device Technology Inc. rischelp@idt.com
+ *
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+
+#ifndef _NVRAM_
+#define _NVRAM_
+/*
+ * defining ALGCOMPAT provides backward compatibility
+ * with Algorithmics derived PROM monitors
+ */
+#define ALGCOMPAT
+#ifdef ALGCOMPAT
+#define NVOFFSET  0   /* use all of NVRAM */
+#else
+#define NVOFFSET  128   /* first 1Kb reserved for DECelx */
+#endif
+
+/* Offsets to reserved locations */
+/* size description */
+#define NVOFF_MAGIC   (NVOFFSET + 0)  /* 2 magic value */
+#define NVOFF_CSUM    (NVOFFSET + 2)  /* 2 NVRAM environment checksum */
+#define NVOFF_ENVSIZE (NVOFFSET + 4)  /* 2 size of 'environment' */
+#define NVOFF_TEST    (NVOFFSET + 5)  /* 1 cold start test byte */
+#define NVOFF_ETHADDR (NVOFFSET + 6)  /* 6 decoded ethernet address */
+#define NVOFF_UNUSED  (NVOFFSET + 12) /* 0 current end of table */
+
+#define NV_MAGIC      0xdeaf          /* nvram magic number */
+#define NV_RESERVED   32              /* number of reserved bytes */
+
+#ifdef ALGCOMPAT
+/* ho hum... */
+#undef NVOFF_ETHADDR
+#define NVOFF_ETHADDR (NVOFFSET + NV_RESERVED - 6)
+#endif
+
+/* number of bytes available for environment */
+#define ENV_BASE      (NVOFFSET + NV_RESERVED)
+#define ENV_TOP       TD_NVRAM_SIZE
+#define ENV_AVAIL     (ENV_TOP - ENV_BASE)
+#endif /* _NVRAM_ */
+
+#define NVRAM_BASE 0xba004000
+#define TD_NVRAM_SIZE 0x100
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/nvram/nvramproc.c idtlinux/arch/mips/idt-boards/rc32300/EB355/nvram/nvramproc.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/nvram/nvramproc.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/nvram/nvramproc.c	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,219 @@
+/******************************************************************************
+  We provide a /proc interface to the nvram. We make an entry
+  for 'nvram' and under which 'boot'. 'boot' is a deivce that
+  is read/write. Together with nvram365.c, we provide an interface for
+  the user to set and modify the environment variables stored in NVRAM.
+ *******************************************************************************
+  Examples
+  
+  #cat /proc/nvram/boot
+     will display the boot environment variables, like netaddr0,bootaddr etc.
+  #echo "netaddr0 192.168.1.3" >/proc/nvram/boot
+     will modify the boot environment variable netaddr0.
+  #echo "netaddr0" >/proc/nvram/boot
+     will erase the "netaddr0" environment variable
+  #echo >/proc/nvram/boot
+     will erase all environment variables stored in nvram
+
+******************************************************************************/
+	
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/proc_fs.h>
+#include <linux/sched.h>
+#include <asm/uaccess.h>
+#include <linux/string.h>
+
+//#define DEBUG 1
+#define MODULE_VERSION "1.0"
+#define MODULE_NAME "nvram"
+#define BOOT_MAJOR 240
+#define BUF_LEN 8192
+
+extern void setenv (char *e, char *v, int rewrite);
+extern char *getenv (char *e);
+extern void unsetenv (char *e);
+extern void mapenv (int (*func)(char *, char *));
+extern void purgeenv(void);
+extern char *getenv (char *s);
+
+static struct proc_dir_entry *nvram, *boot;
+
+static int boot_open(struct inode *, struct file *);
+static int boot_release(struct inode *, struct file *);
+static ssize_t boot_read(struct file *, char *, size_t, loff_t *);
+static ssize_t boot_write(struct file *, const char *, size_t, loff_t *);
+
+static struct file_operations boot_fops = {
+	.read = boot_read, 
+	.write = boot_write,
+	.open = boot_open,
+	.release = boot_release
+};
+
+static char msg[BUF_LEN];
+static char *msg_Ptr;
+const char delimiters[] = " \n";
+
+static int printVal(char *name,char *val)
+{
+	strcat(msg,name);
+	strcat(msg," ");
+	strcat(msg,val);
+	strcat(msg,"\n");
+	return 0;
+}
+
+static int boot_open(struct inode *inode, struct file *file)
+{
+	MOD_INC_USE_COUNT;
+	memset(msg,0,BUF_LEN);
+	msg_Ptr = msg;
+	return 0;
+}
+static int boot_release(struct inode *inode, struct file *file)
+{
+	MOD_DEC_USE_COUNT;
+	return 0;
+}
+
+static ssize_t boot_read(struct file *filp,
+			 char *buffer,    /* The buffer to fill with data */
+			 size_t length,   /* The length of the buffer     */
+			 off_t *offset)  /* Our offset in the file       */
+{
+	int bytes_read = 0;
+	if(msg_Ptr == msg)
+	{
+		mapenv(&printVal);
+	}
+	if (*msg_Ptr == 0){
+		msg_Ptr = msg;
+		return 0;
+	}
+	while (length && *msg_Ptr)
+	{
+		put_user(*(msg_Ptr++), buffer++);
+		length--;
+		bytes_read++;
+	}
+	return bytes_read;
+}
+
+static ssize_t boot_write(struct file *filp,
+			  const char *buffer,
+			  size_t length,
+			  loff_t *offset)
+{
+	int bytes_written = 0;
+	char *token1,*token2;
+	
+	memset(msg,0,BUF_LEN);
+	
+	while(length && *buffer)
+	{
+		get_user(msg[bytes_written],buffer++);
+		length--;
+		bytes_written++;
+	}
+	
+	token1 = strsep(&msg_Ptr,delimiters);
+	token2 = strsep(&msg_Ptr,delimiters);
+	
+	if((*token1 !='\0') && (*token2 != '\0'))
+	{
+#ifdef DEBUG
+		printk(__FILE__": setting environment %s to %s\n",token1,token2);
+#endif
+		setenv(token1,token2,1);
+	}
+	else if(*token1 != '\0')
+	{
+#ifdef DEBUG
+		printk(__FILE__": pugring environment variable %s\n",token1);
+#endif
+		unsetenv(token1);
+	}
+	else
+	{
+#ifdef DEBUG
+		printk(__FILE__": purging all environment variables\n");
+#endif
+		purgeenv();
+	}
+	
+	return bytes_written;
+}
+
+
+static int __init init_procfs_nvram(void)
+{
+	int rv = 0;
+	
+	/* create directory */
+	nvram = proc_mkdir(MODULE_NAME, NULL);
+	if(nvram == NULL) {
+#ifdef DEBUG
+		printk(__FILE__": Cannot make proc entry for 'nvram'\n");
+#endif
+		rv = -ENOMEM;
+		goto out1;
+	}
+#ifdef DEBUG
+	printk(__FILE__": module %s %s initialised\n", MODULE_NAME, MODULE_VERSION);
+#endif
+	if (register_chrdev(BOOT_MAJOR,"boot", &boot_fops) <0)
+	{
+#ifdef DEBUG     
+		printk(__FILE__": Cannot register 'boot' device.\n");
+#endif
+		rv = -EINVAL;
+		goto out2;
+	}
+	
+#ifdef DEBUG     
+	printk(__FILE__": device 'boot' (major %d) registered\n",BOOT_MAJOR);
+#endif
+        
+	boot = proc_mknod("boot", S_IFCHR | 0644, nvram, MKDEV(BOOT_MAJOR, 0));
+	if(boot == NULL) {
+#ifdef DEBUG
+		printk(__FILE__": Cannot make proc entry for boot.\n");
+#endif
+		rv = -ENOMEM;
+		goto out3;
+	}
+	
+	boot->owner = THIS_MODULE;
+	
+	return 0;
+	
+ out3:
+	unregister_chrdev(BOOT_MAJOR,"boot");
+ out2:
+	remove_proc_entry(MODULE_NAME, NULL);
+ out1:
+	return rv;
+}
+
+
+static void __exit cleanup_procfs_nvram(void)
+{
+	remove_proc_entry("boot", nvram);
+	unregister_chrdev(BOOT_MAJOR,"boot");
+	remove_proc_entry(MODULE_NAME, NULL);
+#ifdef DEBUG
+	printk("%s %s removed\n", MODULE_NAME, MODULE_VERSION);
+#endif
+}
+
+
+module_init(init_procfs_nvram);
+module_exit(cleanup_procfs_nvram);
+
+MODULE_AUTHOR("idt");
+MODULE_DESCRIPTION("proc interface for nvram");
+MODULE_LICENSE("GPL");
+
+EXPORT_NO_SYMBOLS;
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/prom.c idtlinux/arch/mips/idt-boards/rc32300/EB355/prom.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/prom.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/prom.c	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,141 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     IDT EB32355 kernel boot-parameters setup
+ *
+ *  Copyright 2006 IDT Inc.
+ *  Author: Integrated Device Technology Inc. rischelp@idt.com
+ *
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/console.h>
+#include <asm/bootinfo.h>
+#include <linux/bootmem.h>
+#include <linux/ioport.h>
+#include <linux/serial.h>
+#include <linux/serialP.h>
+#include <asm/serial.h>
+#include <linux/ioport.h>
+
+#include <asm/idt-boards/rc32300/rc32300.h>
+#include <asm/idt-boards/rc32300/rc32355.h>
+
+unsigned int idt_cpu_freq = CONFIG_IDT_BOARD_FREQ;
+EXPORT_SYMBOL(idt_cpu_freq);
+extern void setup_serial_port(int);
+
+
+#ifdef CONFIG_IDT_BOOT_NVRAM
+extern void mapenv(int (*func)(char *, char *));
+static int make_bootparm(char *name,char *val)
+{ 
+	if (strncmp(name, "bootparm", 8) == 0) {
+		strcat(arcs_cmdline,val);
+		strcat(arcs_cmdline," ");
+	}
+	else if(strncmp(name, "HZ", 2) == 0) {
+		idt_cpu_freq = simple_strtoul(val, 0, 10);
+		printk("CPU Clock at %d Hz (from HZ environment variable)\n",
+		       idt_cpu_freq);
+	}
+	return 0;
+}
+
+
+/*
+ * Parses environment variable strings in NVRAM, copying strings
+ * beginning with "bootparm?=" to arcs_cmdline[]. For example,
+ *
+ *    netaddr=10.0.1.95
+ *    bootaddr=10.0.0.139
+ *    bootfile=vmlinus
+ *    bootparm1=root=/dev/nfs
+ *    bootparm2=ip=10.0.1.95
+ *
+ * is parsed to:
+ *
+ *      root=/dev/nfs ip=10.0.1.95
+ *
+ * in arcs_cmdline[].
+ */
+static void prom_init_cmdline(void)
+{ 
+	memset(arcs_cmdline,0,sizeof(arcs_cmdline));
+	mapenv(&make_bootparm);
+}
+#else
+/* Kernel Boot parameters */
+static unsigned char bootparm[]="console=ttyS0,9600";
+#endif
+extern unsigned long mips_machgroup;
+extern unsigned long mips_machtype;
+
+const char *get_system_type(void)
+{
+	return "IDT 79EB355";
+}
+
+struct resource rc32300_res_ram = {
+	"RAM",
+	0,
+	RAM_SIZE,
+	IORESOURCE_MEM
+};
+
+char * __init prom_getcmdline(void)
+{
+	return &(arcs_cmdline[0]);
+}
+
+void __init prom_init(void)
+{
+#ifdef CONFIG_IDT_BOOT_NVRAM
+	/* set up command line */
+	prom_init_cmdline();
+#else
+	sprintf(arcs_cmdline,"%s",bootparm);
+#endif
+	
+	setup_serial_port(0);     // UART0
+	setup_serial_port(1);     // UART1
+	
+	/* set our arch type */
+	mips_machgroup = MACH_GROUP_IDT;
+	mips_machtype = MACH_IDT_EB355;
+	add_memory_region(0,
+			  rc32300_res_ram.end - rc32300_res_ram.start,
+			  BOOT_MEM_RAM);
+	
+}
+
+void prom_free_prom_memory(void)
+{
+}
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/reset.c idtlinux/arch/mips/idt-boards/rc32300/EB355/reset.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/reset.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/reset.c	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,70 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     IDT EB32355 reset/power-off routines
+ *
+ *  Copyright 2006 IDT Inc.
+ *  Author: Integrated Device Technology Inc. rischelp@idt.com
+ *
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/pm.h>
+#include <linux/slab.h>
+#include <linux/sysctl.h>
+
+#include <asm/string.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/cacheflush.h>
+
+#include <asm/idt-boards/rc32300/rc32300.h>
+#include <asm/idt-boards/rc32300/rc32355.h>
+
+void rc32300_restart(char *command)
+{
+	set_c0_status((ST0_BEV | ST0_ERL));
+	set_c0_config(CONF_CM_UNCACHED);
+	flush_cache_all();
+	write_c0_wired(0);
+	
+	rc32300_writel(0x80000001, RESET_CNTL);
+}
+
+void rc32300_halt(void)
+{
+	printk(KERN_NOTICE "\n** You can safely turn off the power\n");
+	while (1)
+		__asm__(".set\tmips3\n\t"
+	                "wait\n\t"
+			".set\tmips0");
+}
+
+void rc32300_power_off(void)
+{
+	rc32300_halt();
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/serial.c idtlinux/arch/mips/idt-boards/rc32300/EB355/serial.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/serial.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/serial.c	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,82 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Serial Port Setup (2 UART)
+ *
+ *  Copyright 2006 IDT Inc.
+ *  Author: Integrated Device Technology Inc. rischelp@idt.com
+ *
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <asm/time.h>
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/serial.h>
+#include <asm/idt-boards/rc32300/rc32300.h>
+
+
+extern int __init early_serial_setup(struct uart_port *port);
+extern unsigned int idt_cpu_freq;
+
+
+extern int __init setup_serial_port(int port)
+{ 
+	static struct uart_port serial_req[2];
+	memset(serial_req, 0, sizeof(serial_req));
+	if(port == 0){
+		serial_req[0].type       = PORT_16550A;
+		serial_req[0].line       = 0;
+		serial_req[0].irq        = RC32300_UART0_IRQ;
+		serial_req[0].flags      = STD_COM_FLAGS;
+		serial_req[0].uartclk    = idt_cpu_freq;
+		serial_req[0].iotype     = SERIAL_IO_MEM;
+		serial_req[0].membase    = (char *) KSEG1ADDR(RC32300_UART0_BASE);
+		serial_req[0].mapbase   = KSEG1ADDR(RC32300_UART0_BASE);
+		serial_req[0].regshift   = 2;
+		early_serial_setup(&serial_req[0]);
+	}
+	else if (port == 1){
+		serial_req[1].type       = PORT_16550A;
+		serial_req[1].line       = 1;
+		serial_req[1].irq        = RC32300_UART1_IRQ;
+		serial_req[1].flags      = STD_COM_FLAGS;
+		serial_req[1].uartclk    = idt_cpu_freq;
+		serial_req[1].iotype     = SERIAL_IO_MEM;
+		serial_req[1].membase    = (char *) KSEG1ADDR(RC32300_UART1_BASE);
+		serial_req[1].mapbase   = KSEG1ADDR(RC32300_UART1_BASE);
+		serial_req[1].regshift   = 2;
+		early_serial_setup(&serial_req[1]);
+	}
+	return(0);
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/serial_gdb.c idtlinux/arch/mips/idt-boards/rc32300/EB355/serial_gdb.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/serial_gdb.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/serial_gdb.c	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,273 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *      EB355 specific polling driver for 16550 UART.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/serial_reg.h>
+
+/* set remote gdb baud rate at 115200 */
+
+#define GDB_BAUD 115200
+#define CONS_BAUD 9600
+
+extern unsigned int idt_cpu_freq;
+
+
+/* turn this on to watch the debug protocol echoed on the console port */
+#undef DEBUG_REMOTE_DEBUG
+
+#ifdef __MIPSEB__
+#define CONS_PORT 0xb8050003u
+#define GDB_PORT  0xb8050023u
+#else
+#define CONS_PORT 0xb8050000u
+#define GDB_PORT  0xb8050020u
+#endif
+           
+volatile unsigned char *ports[2] = {
+	(volatile unsigned char *)CONS_PORT,
+	(volatile unsigned char *)GDB_PORT
+};
+
+
+void reset_gdb_port(void);
+void cons_putc(char c);
+int port_getc(int port);
+void port_putc(int port, char c);
+
+int cons_getc(void)
+{
+	return port_getc(0);
+}
+
+void cons_putc(char c)
+{
+	port_putc(0, c);
+}
+
+void cons_puts(char *s)
+{
+	while(*s) {
+		if(*s == '\n') cons_putc('\r');
+		cons_putc(*s);
+		s++;
+	}
+}
+
+void cons_do_putn(int n)
+{
+	if(n) {
+		cons_do_putn(n / 10);
+		cons_putc(n % 10 + '0');
+	}
+}
+
+void cons_putn(int n)
+{
+	if(n < 0) {
+		cons_putc('-');
+		n = -n;
+	}
+
+	if (n == 0) {
+		cons_putc('0');
+	} else {
+		cons_do_putn(n);
+	}
+}
+
+#ifdef DEBUG_REMOTE_DEBUG
+static enum {HUH, SENDING, GETTING} state;
+
+static void sent(int c)
+{
+	switch(state) {
+	case HUH:
+	case GETTING:
+		cons_puts("\nSNT ");
+		state = SENDING;
+		/* fall through */
+	case SENDING:
+		cons_putc(c);
+		break;
+	}       
+}
+
+static void got(int c)
+{
+	switch(state) {
+	case HUH:
+	case SENDING:
+		cons_puts("\nGOT ");
+		state = GETTING;
+		/* fall through */
+	case GETTING:
+		cons_putc(c);
+		break;
+	}       
+}
+#endif /* DEBUG_REMOTE_DEBUG */
+
+static int first = 1;
+
+int getDebugChar(void)
+{
+	int c;
+
+	if(first) reset_gdb_port();
+
+	c = port_getc(1);
+
+#ifdef DEBUG_REMOTE_DEBUG
+	got(c);
+#endif
+
+	return c;
+}
+
+int port_getc(int p)
+{
+	volatile unsigned char *port = ports[p];
+	int c;
+
+	while((*(port + UART_LSR * 4) & UART_LSR_DR) == 0) {
+		continue;
+	}       	
+
+	c = *(port + UART_RX * 4);
+
+	return c;
+}
+
+int port_getc_ready(int p)
+{
+	volatile unsigned char *port = ports[p];
+
+	return *(port + UART_LSR * 4) & UART_LSR_DR;
+}
+
+int isDebugReady(void)
+{
+	return port_getc_ready(1);
+}
+
+void putDebugChar(char c)
+{
+	if(first) reset_gdb_port();
+
+#ifdef DEBUG_REMOTE_DEBUG
+	sent(c);
+#endif
+
+	port_putc(1, c);
+}
+
+#define OK_TO_XMT (UART_LSR_TEMT | UART_LSR_THRE)
+
+void port_putc(int p, char c)
+{
+	volatile unsigned char *port = ports[p];
+	volatile unsigned char *lsr = port + UART_LSR * 4;
+
+	while((*lsr & OK_TO_XMT) != OK_TO_XMT) {
+		continue;
+	}
+
+	*(port + UART_TX * 4) = c;
+}
+
+void reset_gdb_port(void)
+{
+	volatile unsigned char *port = ports[1];
+	unsigned int DIVISOR = (idt_cpu_freq / 16 / GDB_BAUD);
+
+	first = 0;
+
+#ifdef DEBUG_REMOTE_DEBUG
+	cons_puts("reset_gdb_port: initializing remote debug serial port (internal UART 1, ");
+	cons_putn(GDB_BAUD);
+	cons_puts("baud, MHz=");
+	cons_putn(idt_cpu_freq);
+	cons_puts(", divisor=");
+	cons_putn(DIVISOR);
+	cons_puts(")\n");
+#endif
+
+	/* reset the port */
+	*(port + UART_CSR * 4) = 0;
+
+	/* clear and enable the FIFOs */
+	*(port + UART_FCR * 4) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | 
+		UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;
+
+	/* set the baud rate */
+	*(port + UART_LCR * 4) = UART_LCR_DLAB;		/* enable DLL, DLM registers */
+	*(port + UART_DLL * 4) = DIVISOR;
+	*(port + UART_DLM * 4) = DIVISOR >> 8;
+
+	/* set the line control stuff and disable DLL, DLM regs */
+
+	*(port + UART_LCR * 4) = UART_LCR_STOP | 	/* 2 stop bits */
+		UART_LCR_WLEN8;				/* 8 bit word length */
+	
+	/* leave interrupts off */
+	*(port + UART_IER * 4) = 0;
+
+	/* the modem controls don't leave the chip on this port, so leave them alone */
+	*(port + UART_MCR * 4) = 0;
+}
+
+void reset_cons_port(void)
+{
+	volatile unsigned char *port = ports[0];
+	  unsigned int DIVISOR = (idt_cpu_freq / 16 / CONS_BAUD);
+
+	/* reset the port */
+	*(port + UART_CSR * 4) = 0;
+
+	/* clear and enable the FIFOs */
+	*(port + UART_FCR * 4) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | 
+		UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;
+
+	/* set the baud rate */
+	*(port + UART_LCR * 4) = UART_LCR_DLAB;		/* enable DLL, DLM registers */
+
+	*(port + UART_DLL * 4) = DIVISOR;
+	*(port + UART_DLM * 4) = DIVISOR >> 8;
+	/* set the line control stuff and disable DLL, DLM regs */
+
+	*(port + UART_LCR * 4) = UART_LCR_STOP | 	/* 2 stop bits */
+		UART_LCR_WLEN8;				/* 8 bit word length */
+	
+	/* leave interrupts off */
+	*(port + UART_IER * 4) = 0;
+
+	/* the modem controls don't leave the chip on this port, so leave them alone */
+	*(port + UART_MCR * 4) = 0;
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/setup.c idtlinux/arch/mips/idt-boards/rc32300/EB355/setup.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/setup.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/setup.c	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,138 @@
+/**************************************************************************
+*
+*  BRIEF MODULE DESCRIPTION
+*     IDT EB32355 board setup
+*
+*  Copyright 2006 IDT Inc.
+*  Author: Integrated Device Technology Inc. rischelp@idt.com
+*
+*         
+*  This program is free software; you can redistribute  it and/or modify it
+*  under  the terms of  the GNU General  Public License as published by the
+*  Free Software Foundation;  either version 2 of the  License, or (at your
+*  option) any later version.
+*
+*  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+*  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+*  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+*  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+*  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+*  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+*  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+*  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*  You should have received a copy of the  GNU General Public License along
+*  with this program; if not, write  to the Free Software Foundation, Inc.,
+*  675 Mass Ave, Cambridge, MA 02139, USA.
+*
+**************************************************************************
+*/
+
+#include <linux/config.h>
+#include <linux/pm.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+
+#include <linux/config.h>
+#include <linux/eisa.h>
+#include <linux/hdreg.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/mc146818rtc.h>
+#include <linux/console.h>
+#include <linux/fb.h>
+#include <linux/tty.h>
+
+#include <asm/reboot.h>
+
+#include <asm/idt-boards/rc32300/rc32300.h>
+#include <asm/idt-boards/rc32300/rc32355.h>
+
+extern void (*board_time_init)(void);
+extern void (*board_timer_setup)(struct irqaction *irq);
+extern void rc32300_time_init(void);
+extern void rc32300_timer_setup(struct irqaction *irq);
+extern char * __init prom_getcmdline(void);
+extern void rc32300_restart(char *);
+extern void rc32300_halt(void);
+extern void rc32300_power_off(void);
+extern int init_lcd(void);
+extern int idtprintf(const char *fmt, ...);
+
+static int __init idt_setup(void)
+{
+	char* argptr;
+	argptr = prom_getcmdline();
+	
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+	if ((argptr = strstr(argptr, "console=")) == NULL) {
+		argptr = prom_getcmdline();
+		strcat(argptr, " console=ttyS0,9600");
+	}
+#endif
+	
+	board_time_init = rc32300_time_init;
+	board_timer_setup = rc32300_timer_setup;
+	
+	_machine_restart = rc32300_restart;
+	_machine_halt = rc32300_halt;
+	pm_power_off = rc32300_power_off;
+	
+	set_io_port_base(KSEG1);
+	
+	// clear out any wired entries
+	write_c0_wired(0);
+	
+	/*
+	 * Setup Device 3. The EPLD (U13) splits device 3 chip-select
+	 * into seperate chip selects for the TDM, LCD, and RTC
+	 * devices. Timings are from IDT-SIM source.
+	 */
+	rc32300_writel(0x00000000, DEV0_MASK   + 3*DEV_REG_OFFSET);
+	rc32300_writel(TDM_BASE,   DEV0_BASE   + 3*DEV_REG_OFFSET);
+	rc32300_writel(0x0FFFFF84, DEV0_CNTL   + 3*DEV_REG_OFFSET);
+	rc32300_writel(0x00001FFF, DEV0_TIMING + 3*DEV_REG_OFFSET);
+	rc32300_writel(0xFFFF0000, DEV0_MASK   + 3*DEV_REG_OFFSET);
+	
+	init_lcd();
+	idtprintf("IDT-Linux 2.6");
+	
+	
+#ifdef CONFIG_MTD
+	/*
+	 * Setup device 2 for flash devices. Set for
+	 * 32-bit databus size, write-enable.
+	 */
+	rc32300_writel(0x00000000, DEV0_MASK   + 2*DEV_REG_OFFSET);
+	rc32300_writel(FLASH_BASE, DEV0_BASE   + 2*DEV_REG_OFFSET);
+	/* timings are from IDT/sim source */
+	rc32300_writel(0x03CF3316, DEV0_CNTL   + 2*DEV_REG_OFFSET);
+	rc32300_writel(0x00001133, DEV0_TIMING + 2*DEV_REG_OFFSET);
+	rc32300_writel(0xFF800000, DEV0_MASK   + 2*DEV_REG_OFFSET);
+#endif
+	
+	
+	/* Disable Watchdog timer */
+	rc32300_writel(0, 0xb8028040);
+	
+	return 0;
+}
+
+//early_initcall(idt_setup);
+
+void __init plat_setup(void){
+  idt_setup();
+}
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/time.c idtlinux/arch/mips/idt-boards/rc32300/EB355/time.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/time.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB355/time.c	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,133 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *    IDT EB32355 timer routines
+ *
+ *  Copyright 2006 IDT Inc.
+ *  Author: Integrated Device Technology Inc. rischelp@idt.com
+ *
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * 
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/mc146818rtc.h>
+#include <linux/irq.h>
+#include <linux/timex.h>
+
+#include <linux/param.h>
+#include <asm/mipsregs.h>
+#include <asm/ptrace.h>
+#include <asm/time.h>
+#include <asm/hardirq.h>
+#include <asm/mipsregs.h>
+#include <asm/ptrace.h>
+#include <asm/debug.h>
+#include <asm/time.h>
+#include <asm/idt-boards/rc32300/rc32300.h>
+#include <asm/idt-boards/rc32300/rc32355.h>
+
+static unsigned long r4k_offset; /* Amount to incr compare reg each time */
+static unsigned long r4k_cur;    /* What counter should be at next timer irq */
+
+extern unsigned int idt_cpu_freq;
+#if defined(CONFIG_IDT_79EB355) && defined(CONFIG_MIPS_RTC)
+extern void rtc_ds1501_init(void);
+#endif
+
+
+/* 
+ * Figure out the r4k offset, the amount to increment the compare
+ * register for each time tick. There is no RTC available.
+ *
+ * The RC32300 counts at half the CPU *core* speed.
+ */
+
+static unsigned long __init cal_r4koff(void)
+{
+	mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
+	return (mips_hpt_frequency / HZ);
+}
+
+
+void __init rc32300_time_init(void)
+{
+	unsigned int est_freq, flags;
+	
+	local_irq_save(flags);
+	
+	printk("calculating r4koff... ");
+	r4k_offset = cal_r4koff();
+	printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
+	
+	est_freq = 2*r4k_offset*HZ;	
+	est_freq += 5000;    /* round */
+	est_freq -= est_freq%10000;
+	printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, 
+	       (est_freq%1000000)*100/1000000);
+	local_irq_restore(flags);
+	
+#if defined(CONFIG_IDT_79EB355) && defined(CONFIG_MIPS_RTC)
+	rtc_ds1501_init();
+#endif
+	
+}
+
+
+void __init rc32300_timer_setup(struct irqaction *irq)
+{
+	/* we are using the cpu counter for timer interrupts */
+	setup_irq(MIPS_CPU_TIMER_IRQ, irq);
+	
+	/* to generate the first timer interrupt */
+	r4k_cur = (read_c0_count() + r4k_offset);
+	write_c0_compare(r4k_cur);
+}
+
+static inline void ack_r4ktimer(unsigned long newval)
+{
+	write_c0_compare(newval);
+}
+
+
+asmlinkage void idt_timer_interrupt(int irq,struct pt_regs *regs)
+{ 
+#ifdef CONFIG_KGDB
+	void kgdb_check(void);
+#endif
+
+	irq_enter();
+	kstat_this_cpu.irqs[irq]++;
+	timer_interrupt(irq, NULL, regs);
+	irq_exit();
+
+#ifdef CONFIG_KGDB
+	kgdb_check();
+#endif
+}
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/csu_idt.S idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/csu_idt.S
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/csu_idt.S	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/csu_idt.S	2006-03-09 16:25:47.000000000 -0800
@@ -0,0 +1,320 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Board initialization code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/threads.h>
+
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/asm-offsets.h>
+#include <asm/cachectl.h>
+#include "iregdef.h"
+#include "idtcpu.h"
+#include "idthdr.h"
+	
+#define  MHZ (CONFIG_IDT_BOARD_FREQ/(1000*1000))
+	
+#include "s365led.h"	
+#include "s365ram.h"
+
+	
+/*--------------------------------------------------------------
+* prom entry point table
+*-------------------------------------------------------------*/
+
+FRAME(start,sp,0,ra)
+
+	j	idtstart  /* begin monitor from start |00| */
+	
+idtstart:
+
+	.set noreorder
+	
+	mtc0	zero, C0_CAUSE
+	li	v0, 0x0
+	or	v0, (SR_CU0 | SR_BEV | SR_DE)
+	mtc0	v0, C0_SR
+
+	mfc0	v1, C0_CONFIG
+	li	v0, CFG_C_NCHRNT_WB  /* CFG_C_NCHRNT_WB  CFG_C_NCHRNT_WT_NWA CFG_C_UNCACHED */
+	and	v1, ~(0x7)
+	or	v1, v1, v0
+	mtc0	v1, C0_CONFIG
+	nop
+	nop
+	li	t0, ERR_CNTL_STATUS  
+	sw	zero, 0(t0)
+
+/* ------------------- Setup Device Controller ---------------------------- */
+	li	t0, DEV_CTL_BASE      	/* load 2 base address registers' base    */
+
+	lui	t2, 0xB800
+	lw	t1, 0x8004(t2)        	/* get BCV                                */
+	li	t2, 0x60              	/* check width of boot device 16/32 bit   */
+	and	t1, t1, t2
+	li	t2, 0x20
+	bne	t1, t2, 1f
+	nop
+/* 16 bit device - boot from PROM - CS1 is FLASH                      	*/
+	li	t1, DEV_PROM_CTRL     	/* device0 control parameter              */
+	sw	t1, 0x8(t0)           	/* set the control register  CS0          */
+	li	t1, DEV_PROM_TC       	/* device0 timing config parameter        */
+	sw	t1, 0xC(t0)
+
+	li	t1, DEV1_BASE         	/* set the device base register for CS1   */
+	sw	t1, 0x10(t0)
+	li	t1, DEV_FLASH_MASK    	/* set the device mask register for CS1   */
+	sw	t1, 0x14(t0) 
+	li	t1, DEV_FLASH_CTRL    	/* set the device control register for CS1*/
+	sw	t1, 0x18(t0)
+	li	t1, DEV_FLASH_TC      	/* set the device timing register for CS1 */
+	sw	t1, 0x1C(t0) 
+	b	2f                    
+        nop
+1:
+/* 32 bit device - boot from FLASH - CS1 is PROM                      	*/
+	li	t1, DEV_FLASH_CTRL    	/* device0 control parameter              */
+	sw	t1, 0x8(t0)           	/* set the control register  CS0          */
+	li	t1, DEV_FLASH_TC      	/* device0 timing config parameter        */
+	sw	t1, 0xC(t0)
+	li	t1, DEV1_BASE		/* set the device base register for CS1   */
+	sw	t1, 0x10(t0)
+	li	t1, DEV_PROM_MASK     	/* set the device mask register for CS1   */
+	sw	t1, 0x14(t0) 
+	li	t1, DEV_PROM_CTRL     	/* set the device control register for CS1*/
+	sw	t1, 0x18(t0)
+	li	t1, DEV_PROM_TC       	/* set the device timing register for CS1 */
+	sw	t1, 0x1C(t0) 
+2:
+	li	t1, DEV2_BASE         	/* set the device base register for CS2   */
+	sw	t1, 0x20(t0)
+	li	t1, DEV2_MASK         	/* set the device mask register for CS2   */
+	sw	t1, 0x24(t0) 
+	li	t1, DEV2_CTRL         	/* set the device control register for CS2*/
+	sw	t1, 0x28(t0) 
+	li	t1, DEV2_TC           	/* set the device timing register for CS2 */
+	sw	t1, 0x2C(t0) 
+
+	li	t1, DEV3_BASE	        /* set the device base register for CS3   */
+	sw	t1, 0x30(t0)
+	li	t1, DEV3_MASK         	/* set the device mask register for CS3   */
+	sw	t1, 0x34(t0) 
+	li	t1, DEV3_CTRL         	/* set the device control register for CS3*/
+	sw	t1, 0x38(t0)
+	li	t1, DEV3_TC           	/* set the device timing register for CS3 */
+	sw	t1, 0x3C(t0) 
+
+	li	t1, DEV4_BASE         	/* set the device base register for CS4   */
+	sw	t1, 0x40(t0)
+	li	t1, DEV4_MASK         	/* set the device mask register for CS4   */
+	sw	t1, 0x44(t0) 
+	li	t1, DEV4_CTRL         	/* set the device control register for CS4*/
+	sw	t1, 0x48(t0)
+	li	t1, DEV4_TC           	/* set the device timing register for CS4 */
+	sw	t1, 0x4C(t0) 
+
+	li	t1, DEV5_BASE         	/* set the device base register for CS5   */
+	sw	t1, 0x50(t0)
+	li	t1, DEV5_MASK         	/* set the device mask register for CS5   */
+	sw	t1, 0x54(t0) 
+	li	t1, DEV5_CTRL         	/* set the device control register for CS5*/
+	sw	t1, 0x58(t0)
+	li	t1, DEV5_TC		/* set the device timing register for CS5 */
+	sw	t1, 0x5C(t0)
+
+/* ------------------ Initialize GPIO ------------------------------------- */
+	li	t0, GPIO_BASE
+	li	t1, GPIO_FUNC
+	sw	t1, 0x0(t0)
+  	li	t1, GPIO_CFG
+	sw	t1, 0x4(t0)
+  	li	t1, GPIO_OUT
+	sw	t1, 0x8(t0)
+
+/* ------------- Clear PCI Local Base Control registers ------------------- */
+	li    t0, 0xb8068000
+	sw    zero, 0x18(t0)
+	sw    zero, 0x24(t0)
+	sw    zero, 0x30(t0)
+	sw    zero, 0x3c(t0)
+/* ------------------- Assert PCI reset ----------------------------------- */
+	lw    t1, (t0)
+	andi  t2, t1, 0x1
+	beqz  t2, 2f
+	      nop
+	andi  t2, t1, 0x3fe
+	sw    t2, (t0)
+	li    t2, 0x1000
+1:
+	addi  t2, -1
+	bnez  t2, 1b
+	      nop
+2:
+	ori   t2, t1, 0x1
+	sw    t2, (t0)
+	lui   t2, 0x2
+rip:
+	lw    t1, 4(t0)
+	and   t1, t1, t2
+	bnez  t1, rip
+	      nop
+
+	DISPLAY('I','S','D','R')
+
+	li	t0, SDRAM_BASE 		/* load t0 with internal registers' base address */
+
+/*-------------- Initialize SDRAM Base and Mask Registers ----------*/
+
+	li	t1, SDRAM_BNK0_BASE	/* load SDRAM bank 0 physical address in t1 */
+	sw	t1, 0x0(t0)		/* set SDRAM bank 0 base */
+	li	t1, SDRAM_BNK1_BASE	/* load SDRAM bank 1 physical address in t1 */
+	sw	t1, 0x8(t0)		/* set SDRAM bank 1 base */
+	li	t1, SDRAM_BNK0_ABASE	/* load Alternate SDRAM bank 0 physical address in t1 */
+	sw	t1, 0x20(t0)		/* set Alternate SDRAM bank 0 base */
+
+	li	t1, SDRAM_BNK0_MASK	/* load SDRAM bank 0 size in t1 */
+	sw	t1, 0x4(t0)		/* set SDRAM bank 0 mask */
+	li	t1, SDRAM_BNK1_MASK	/* load SDRAM bank 1 size in t1 */
+	sw	t1, 0xC(t0)		/* set SDRAM bank 1 mask */
+	li	t1, SDRAM_BNK0_AMASK	/* load Alternate SDRAM bank 0 size in t1 */
+	sw	t1, 0x24(t0)		/* set Alternate SDRAM bank 0 mask */
+
+/*-------------- Setup and Enable Refresh Timer --------------------*/
+	li	t1, DISABLE_TIMER 	/* load diable timer bit settings into t1 */
+	sw	t1, 0x1C(t0)    		/* disable timer */
+        nop
+
+/*-------------- Enable SDRAM Controller ---------------------------*/
+	li	t1, SDRAM_CR_BS
+	sw	t1, 0x10(t0)
+        nop
+          
+/*-------------- Delay Loop ----------------------------------------*/
+	li	v0, 10000 /* 8x256us */
+1:  
+	bne	v0, zero,1b
+	subu	v0, 1   /* BDSLOT  */
+        nop
+        nop
+/*-------------- Setup Precharge Command ---------------------------*/
+	li	t2, 2
+	li	t3, 0
+1:  
+	li	t1, SDRAM_PC_VAL
+	sw	t1, 0x10(t0)
+        nop
+        nop
+	lw	t7, 0x10(t0)
+        nop
+	li	t4, DATA_PATTERN
+	li	t5, 0xA0000000 | SDRAM_BNK0_BASE
+	sw	t4, 0x0(t5)
+	addu	t3, 1
+	bne	t3, t2, 1b
+        nop
+/*-------------- Setup Refresh Command -----------------------------*/
+	li	t2, 8
+	li	t3, 0
+1:  
+	li	t1, SDRAM_RFRSH_CMD
+	sw	t1, 0x10(t0)
+	sw	t4, 0x0(t5) 		/* note: t5 not disturbed */
+	addu	t3, 1
+	bne	t3, t2, 1b
+        nop
+/*-------------- Setup up to write to Mode Register ----------------*/
+	li	t1, SDRAM_MODE_REG
+	sw	t1, 0x10(t0)
+	addu	t5, 0x80
+	sw	t4, 0x0(t5)
+
+/*-------------- Setup and Enable Refresh Timer --------------------*/
+
+	li	t1, DISABLE_TIMER   	/* load diable timer bit settings into t1 */
+	sw	t1, 0x1c(t0)        	/* disable timer */
+	sw	zero, 0x14(t0)    	/* set SDRAM refresh timer count register bit settings */
+
+	li	t1, SDRAM_RF_CMPR_SE_BS   /* load SDRAM refresh timer compare register bit settings in t1 */
+	sw	t1, 0x18(t0)    		/* set SDRAM refresh timer compare register bit settings */
+
+	li	t1, ENABLE_TIMER    	/* load timer enable bit */
+	sw	t1, 0x1c(t0)    		/* enable refresh timer */
+
+	li	t1, SDRAM_CR_BS
+	sw	t1, 0x10(t0)
+
+  /* the memory system may need some time to start up... */
+	li	v0, 10000 		/* 8x256us */
+1:  
+	bne	v0, zero, 1b
+	subu	v0, 1
+        nop
+        nop
+
+/************************************************************************
+** before doing anything
+** initialize the section of memory used by cache initialization
+** whenever you boot out of ROM or reset-vector
+** This assumed to be 1MB.
+** --Sugan (11-22-96)
+************************************************************************/
+	
+	li	t0, 0xa0000000
+	li	t1, 0xa0100000
+1:
+	sw	zero, 0x00(t0)
+	sw	zero, 0x04(t0)
+	sw	zero, 0x08(t0)
+	sw	zero, 0x0c(t0)
+	addiu	t0, 16
+	nop
+	blt	t0, t1, 1b
+	nop
+	nop
+	nop
+3:
+	mfc0	t0, C0_SR
+	nop
+	nop
+	and	t0, ~SR_BEV
+	mtc0	t0, C0_SR
+	nop
+	nop
+
+	DISPLAY('U','N','Z','P')
+
+/* Jump to zImage start */
+	
+	la      k0, zstartup
+	j       k0
+	nop
+	nop
+			
+ENDFRAME(start)
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/head.S idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/head.S
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/head.S	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/head.S	2006-03-09 16:25:47.000000000 -0800
@@ -0,0 +1,134 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Board initialisation code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+
+#include <linux/config.h>
+#include <linux/threads.h>
+
+#include <asm/asm.h>
+#include <asm/cacheops.h>
+#include <asm/mipsregs.h>
+#include <asm/asm-offsets.h>
+#include <asm/cachectl.h>
+#include <asm/regdef.h>
+
+#define IndexInvalidate_I       0x00
+
+	.set noreorder
+	.cprestore
+	LEAF(zstartup)
+zstartup:
+
+        la      sp, .stack
+	move	s0, a0
+	move	s1, a1
+	move	s2, a2
+	move	s3, a3
+
+	/* Clear BSS */
+	la	a0, .stack
+	la	a2, _end
+1:	sw	zero, 0(a0)
+	bne	a2, a0, 1b
+	addu	a0, 4
+#if 1
+	/* flush the I-Cache */
+	li	k0, 0x80000000  # start address
+	li	k1, 0x80002000  # end address (8KB I-Cache)
+	subu	k1, 128
+2:
+	.set mips3
+	cache	IndexInvalidate_I, 0(k0)
+	cache	IndexInvalidate_I, 16(k0)
+	cache	IndexInvalidate_I, 32(k0)
+	cache	IndexInvalidate_I, 48(k0)
+	cache	IndexInvalidate_I, 64(k0)
+	cache	IndexInvalidate_I, 80(k0)
+	cache	IndexInvalidate_I, 96(k0)
+	cache	IndexInvalidate_I, 112(k0)
+	.set mips0
+
+	bne	k0, k1, 2b
+	addu	k0, k0, 128
+	/* done */
+#endif
+#if 1
+	/* flush the D-Cache */
+	li	k0, 0x80000000  # start address
+	li	k1, 0x80000400  # end address (2KB I-Cache)
+	subu	k1, 128
+3:	
+	.set mips3
+	/* First way */
+	cache	Index_Writeback_Inv_D, 0(k0)
+	cache	Index_Writeback_Inv_D, 16(k0)
+	cache	Index_Writeback_Inv_D, 32(k0)
+	cache	Index_Writeback_Inv_D, 48(k0)
+	cache	Index_Writeback_Inv_D, 64(k0)
+	cache	Index_Writeback_Inv_D, 80(k0)
+	cache	Index_Writeback_Inv_D, 96(k0)
+	cache	Index_Writeback_Inv_D, 112(k0)
+	/* Second way */
+	cache	Index_Writeback_Inv_D, 1024(k0)
+	cache	Index_Writeback_Inv_D, 1040(k0)
+	cache	Index_Writeback_Inv_D, 1056(k0)
+	cache	Index_Writeback_Inv_D, 1072(k0)
+	cache	Index_Writeback_Inv_D, 1088(k0)
+	cache	Index_Writeback_Inv_D, 1104(k0)
+	cache	Index_Writeback_Inv_D, 1120(k0)
+	cache	Index_Writeback_Inv_D, 1136(k0)
+	.set mips0
+
+	bne	k0, k1, 3b
+	addu	k0, k0, 128
+	/* done */
+#endif
+	
+
+	la	ra, 4f
+	la	k0, decompress_kernel
+	jr	k0
+	nop
+4:
+
+	move	a0, s0
+	move	a1, s1
+	move	a2, s2
+	move	a3, s3
+	li	k0, KERNEL_ENTRY
+	jr	k0
+	nop
+5:
+	b 5b
+	END(zstartup)
+
+	.bss
+	.fill 0x2000
+	EXPORT(.stack)
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/idtcpu.h idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/idtcpu.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/idtcpu.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/idtcpu.h	2006-03-09 16:25:47.000000000 -0800
@@ -0,0 +1,614 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   IDT CPU register definitions. Though the registers are already defined
+ *   under asm directory, they are once again declared here for the ease of
+ *   syncing up with IDT bootloader code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#if defined(__IDTCPU_H__)
+#else
+#define __IDTCPU_H__
+
+
+/*
+** memory configuration and mapping
+*/
+#define K0BASE	0x80000000
+#define K0SIZE	0x20000000
+#define K1BASE	0xa0000000
+#define K1SIZE	0x20000000
+#define K2BASE	0xc0000000
+#if defined(S364)
+#define K2SIZE	0x3e000000
+#define ICEBASE	0xff000000
+#define ICESIZE	0x01000000
+#else
+#define K2SIZE	0x20000000
+#endif
+#if defined(CPU_R4000)
+#define KSBASE	0xe0000000
+#define KSSIZE	0x20000000
+#endif
+
+#define KUBASE	0
+#define KUSIZE	0x80000000
+
+/*
+** Exception Vectors
+*/
+#if defined(CPU_R3000)
+#define	UT_VEC	K0BASE			/* utlbmiss vector */
+#define E_VEC	(K0BASE+0x80)		/* exception vevtor */
+#endif
+#if defined(CPU_R4000) || defined S364  /*(CPU_R32364)      */
+#define	T_VEC	(K0BASE+0x000)		/* tlbmiss vector */
+#define X_VEC	(K0BASE+0x080)		/* xtlbmiss vector */
+#define C_VEC	(K1BASE+0x100)		/* cache error vector */
+#define E_VEC	(K0BASE+0x180)		/* exception vector */
+#define I_VEC	(K0BASE+0X200)		/* interrupt vector */
+#endif
+#define	R_VEC	(K1BASE+0x1fc00000)	/* reset vector */
+
+/*
+** Address conversion macros
+*/
+#ifdef CLANGUAGE
+#define	CAST(as) (as)
+#else
+#define	CAST(as)
+#endif
+#define	K0_TO_K1(x)	(CAST(unsigned)(x)|0xA0000000)	/* kseg0 to kseg1 */
+#define	K1_TO_K0(x)	(CAST(unsigned)(x)&0x9FFFFFFF)	/* kseg1 to kseg0 */
+#define	K0_TO_PHYS(x)	(CAST(unsigned)(x)&0x1FFFFFFF)	/* kseg0 to physical */
+#define	K1_TO_PHYS(x)	(CAST(unsigned)(x)&0x1FFFFFFF)	/* kseg1 to physical */
+#define	PHYS_TO_K0(x)	(CAST(unsigned)(x)|0x80000000)	/* physical to kseg0 */
+#define	PHYS_TO_K1(x)	(CAST(unsigned)(x)|0xA0000000)	/* physical to kseg1 */
+
+/*
+**	Cache size constants
+*/
+/* Sugan changed so that MINCACHE is 0x200 instead of 0x800 */
+#define	MINCACHE	0x200		/* 512 bytes  */
+#define	MAXCACHE	0x40000		/* 256*1024   256k */	
+
+#if defined CPU_R32364                  /* Includes RC32364, RC32332, RC32334 */
+#define	CFG_ICE		0x80000000	/* ICE detect */
+#define	CFG_ECMASK	0x70000000	/* System Clock Ratio */
+#define	CFG_ECBY2	0x00000000 	/* divide by 2 */
+#define	CFG_ECBY3	0x10000000 	/* divide by 3 */
+#define	CFG_ECBY4	0x20000000 	/* divide by 4 */
+#define	CFG_NBL		0x00800000	/* Non-Blocking load pending */
+#define	CFG_BE		0x00008000	/* Big Endian */
+#define	CFG_ICMASK	0x00000e00	/* Instruction cache size */
+#define	CFG_ICSHIFT	9
+#define	CFG_DCMASK	0x000001c0	/* Data cache size */
+#define	CFG_DCSHIFT	6
+#define	CFG_IB		0x00000020	/* Instruction cache line size */
+#define	CFG_DB		0x00000010	/* Data cache line size */
+#define	CFG_K0MASK	0x00000007	/* KSEG0 coherency algorithm */
+
+/*
+ * R32364 primary cache mode
+ */
+#define CFG_C_NCHRNT_WT_NWA	0
+#define CFG_C_NCHRNT_WT		1
+#define CFG_C_UNCACHED		2
+#define CFG_C_NCHRNT_WB		3
+
+/* Cache Operations */
+#define Index_Invalidate_I               0x0         /* 0       0 */
+#define Index_Writeback_Inv_D            0x1         /* 0       1 */
+#define Index_Invalidate_SI              0x2         /* 0       2 */
+#define Index_Writeback_Inv_SD           0x3         /* 0       3 */
+#define Index_Load_Tag_I                 0x4         /* 1       0 */
+#define Index_Load_Tag_D                 0x5         /* 1       1 */
+#define Index_Load_Tag_SI                0x6         /* 1       2 */
+#define Index_Load_Tag_SD                0x7         /* 1       3 */
+#define Index_Store_Tag_I                0x8         /* 2       0 */
+#define Index_Store_Tag_D                0x9         /* 2       1 */
+#define Index_Store_Tag_SI               0xA         /* 2       2 */
+#define Index_Store_Tag_SD               0xB         /* 2       3 */
+#define Create_Dirty_Exc_D               0xD         /* 3       1 */
+#define Create_Dirty_Exc_SD              0xF         /* 3       3 */
+#define Hit_Invalidate_I                 0x10        /* 4       0 */
+#define Hit_Invalidate_D                 0x11        /* 4       1 */
+#define Hit_Invalidate_SI                0x12        /* 4       2 */
+#define Hit_Invalidate_SD                0x13        /* 4       3 */
+#define Hit_Writeback_Inv_D              0x15        /* 5       1 */
+#define Hit_Writeback_Inv_SD             0x17        /* 5       3 */
+#define Fill_I                           0x14        /* 5       0 */
+#define Hit_Writeback_D                  0x19        /* 6       1 */
+#define Hit_Writeback_SD                 0x1B        /* 6       3 */
+#define Hit_Writeback_I                  0x18        /* 6       0 */
+#define Hit_Set_Virtual_SI               0x1E        /* 7       2 */
+#define Hit_Set_Virtual_SD               0x1F        /* 7       3 */
+#define CFG_EW32        0x00040000      /* 32 bit */
+#endif /* CPU_R32364 */
+
+#if defined(CPU_R4000)
+/* R4000 configuration register definitions */
+#define CFG_CM		0x80000000	/* Master-Checker mode */
+#define CFG_ECMASK	0x70000000	/* System Clock Ratio */
+#define CFG_ECBY2	0x00000000 	/* divide by 2 */
+#define CFG_ECBY3	0x10000000 	/* divide by 3 */
+#define CFG_ECBY4	0x20000000 	/* divide by 4 */
+#define CFG_EPMASK	0x0f000000	/* Transmit data pattern */
+#define CFG_EPD		0x00000000	/* D */
+#define CFG_EPDDX	0x01000000	/* DDX */
+#define CFG_EPDDXX	0x02000000	/* DDXX */
+#define CFG_EPDXDX	0x03000000	/* DXDX */
+#define CFG_EPDDXXX	0x04000000	/* DDXXX */
+#define CFG_EPDDXXXX	0x05000000	/* DDXXXX */
+#define CFG_EPDXXDXX	0x06000000	/* DXXDXX */
+#define CFG_EPDDXXXXX	0x07000000	/* DDXXXXX */
+#define CFG_EPDXXXDXXX	0x08000000	/* DXXXDXXX */
+#define CFG_SBMASK	0x00c00000	/* Secondary cache block size */
+#define CFG_SBSHIFT	22
+#define CFG_SB4		0x00000000	/* 4 words */
+#define CFG_SB8		0x00400000	/* 8 words */
+#define CFG_SB16	0x00800000	/* 16 words */
+#define CFG_SB32	0x00c00000	/* 32 words */
+#define CFG_SS		0x00200000	/* Split secondary cache */
+#define CFG_SW		0x00100000	/* Secondary cache port width */
+#define CFG_EWMASK	0x000c0000	/* System port width */
+#define CFG_EWSHIFT	18
+#define CFG_EW64	0x00000000	/* 64 bit */
+#define CFG_EW32	0x00040000	/* 32 bit */
+/* #if defined(CPU_R5000) */
+/* Sugan added for R5000 L2 cache 07-17-96 */
+#define L2_PAGESIZE	0x1000
+#define SIZE256K	0x00040000 /* 256KB in Hex */
+#define CFG_HARDL2	0x00020000 /* Hardware bit that enables/disables
+				      L2 cache */
+#define CFG_SE		0x1000
+#define CFG_SIZE512K	0x00000000 /* size of Scache is 512k */
+#define CFG_SIZE1MB 	0x00100000 /* size of Scache is 1MB */
+#define CFG_SIZE2MB 	0x00200000 /* size of Scache is 2MB */
+#define CFG_SIZEMASK	0x00300000 /* size mask */
+/* #endif */
+#define CFG_SC		0x00020000	/* Secondary cache absent */
+#define CFG_SM		0x00010000	/* Dirty Shared mode disabled */
+#define CFG_BE		0x00008000	/* Big Endian */
+#define CFG_EM		0x00004000	/* ECC mode enable */
+#define CFG_EB		0x00002000	/* Block ordering */
+#define CFG_ICMASK	0x00000e00	/* Instruction cache size */
+#define CFG_ICSHIFT	9
+#define CFG_DCMASK	0x000001c0	/* Data cache size */
+#define CFG_DCSHIFT	6
+#define CFG_IB		0x00000020	/* Instruction cache block size */
+#define CFG_DB		0x00000010	/* Data cache block size */
+#define CFG_CU		0x00000008	/* Update on Store Conditional */
+#define CFG_K0MASK	0x00000007	/* KSEG0 coherency algorithm */
+
+/*
+ * R4000 primary cache mode
+ */
+#define CFG_C_WRITETHROUGH_CACHE		0
+#define CFG_C_UNCACHED		2
+#define CFG_C_NONCOHERENT	3
+#define CFG_C_COHERENTXCL	4
+#define CFG_C_COHERENTXCLW	5
+#define CFG_C_COHERENTUPD	6
+
+/*
+ * R4000 cache operations (should be in assembler...?)
+ */
+#if defined(CPU_R5000)
+#define InvAllScache			 0x03	     /* 0	3 */
+#define IndexLoadTagScache		 0x07	     /* 1	3 */
+#define IndexStoreTagScache		 0x0b	     /* 2	3 */
+#define PageInvScache			 0x17	     /* 5	3 */
+#endif
+#define Index_Invalidate_I               0x0         /* 0       0 */
+#define Index_Writeback_Inv_D            0x1         /* 0       1 */
+#define Index_Invalidate_SI              0x2         /* 0       2 */
+#define Index_Writeback_Inv_SD           0x3         /* 0       3 */
+#define Index_Load_Tag_I                 0x4         /* 1       0 */
+#define Index_Load_Tag_D                 0x5         /* 1       1 */
+#define Index_Load_Tag_SI                0x6         /* 1       2 */
+#define Index_Load_Tag_SD                0x7         /* 1       3 */
+#define Index_Store_Tag_I                0x8         /* 2       0 */
+#define Index_Store_Tag_D                0x9         /* 2       1 */
+#define Index_Store_Tag_SI               0xA         /* 2       2 */
+#define Index_Store_Tag_SD               0xB         /* 2       3 */
+#define Create_Dirty_Exc_D               0xD         /* 3       1 */
+#define Create_Dirty_Exc_SD              0xF         /* 3       3 */
+#define Hit_Invalidate_I                 0x10        /* 4       0 */
+#define Hit_Invalidate_D                 0x11        /* 4       1 */
+#define Hit_Invalidate_SI                0x12        /* 4       2 */
+#define Hit_Invalidate_SD                0x13        /* 4       3 */
+#define Hit_Writeback_Inv_D              0x15        /* 5       1 */
+#define Hit_Writeback_Inv_SD             0x17        /* 5       3 */
+#define Fill_I                           0x14        /* 5       0 */
+#define Hit_Writeback_D                  0x19        /* 6       1 */
+#define Hit_Writeback_SD                 0x1B        /* 6       3 */
+#define Hit_Writeback_I                  0x18        /* 6       0 */
+#define Hit_Set_Virtual_SI               0x1E        /* 7       2 */
+#define Hit_Set_Virtual_SD               0x1F        /* 7       3 */
+
+#endif
+
+/*
+** TLB resource defines
+*/
+
+#if defined(CPU_R32364)  
+#define	N_TLB_ENTRIES	16
+#endif 
+
+#if defined(CPU_R4000)
+#define N_TLB_ENTRIES  48
+#endif
+
+#if defined (CPU_R32364)
+#define	TLBHI_VPN2MASK	0xffffe000
+#define	TLBHI_PIDMASK	0x000000ff
+#define	TLBHI_NPID	256
+
+#define	TLBLO_PFNMASK	0x03ffffc0
+#define	TLBLO_PFNSHIFT	6
+#define	TLBLO_D		0x00000004	/* writeable */
+#define	TLBLO_V		0x00000002	/* valid bit */
+#define	TLBLO_G		0x00000001	/* global access bit */
+#define	TLBLO_CMASK	0x00000038	/* cache algorithm mask */
+#define	TLBLO_CSHIFT	3
+
+#define	TLBLO_UNCACHED		(CFG_C_UNCACHED<<TLBLO_CSHIFT)
+#define	TLBLO_NCHRNT_WT_NWA	(CFG_C_NCHRNT_WT_NWA<<TLBLO_CSHIFT)
+#define	TLBLO_NCHRNT_WT		(CFG_C_NCHRNT_WT<<TLBLO_CSHIFT)
+#define	TLBLO_NCHRNT_WB		(CFG_C_NCHRNT_WB<<TLBLO_CSHIFT)
+
+#elif defined(CPU_R4000)
+#define	TLBHI_VPN2MASK	0xffffe000
+#define	TLBHI_PIDMASK	0x000000ff
+#define	TLBHI_NPID	256
+
+#define	TLBLO_PFNMASK	0x3fffffc0
+#define	TLBLO_PFNSHIFT	6
+#define	TLBLO_D		0x00000004	/* writeable */
+#define	TLBLO_V		0x00000002	/* valid bit */
+#define	TLBLO_G		0x00000001	/* global access bit */
+#define	TLBLO_CMASK	0x00000038	/* cache algorithm mask */
+#define	TLBLO_CSHIFT	3
+
+#define	TLBLO_UNCACHED		(CFG_C_UNCACHED<<TLBLO_CSHIFT)
+#define	TLBLO_NONCOHERENT	(CFG_C_NONCOHERENT<<TLBLO_CSHIFT)
+#define	TLBLO_COHERENTXCL	(CFG_C_COHERENTXCL<<TLBLO_CSHIFT)
+#define	TLBLO_COHERENTXCLW	(CFG_C_COHERENTXCLW<<TLBLO_CSHIFT)
+#define	TLBLO_COHERENTUPD	(CFG_C_COHERENTUPD<<TLBLO_CSHIFT)
+#endif
+#if defined(CPU_R4000)||defined(S364)
+#define	TLBINX_PROBE	0x80000000
+#define	TLBINX_INXMASK	0x0000003f
+
+#define	TLBRAND_RANDMASK	0x0000003f
+
+#define	TLBCTXT_BASEMASK	0xff800000
+#define	TLBCTXT_BASESHIFT	23
+
+#define	TLBCTXT_VPN2MASK	0x007ffff0
+#define	TLBCTXT_VPN2SHIFT	4
+
+#define	TLBPGMASK_MASK		0x01ffe000
+#endif
+
+#define	SR_PE		0x00100000	/* cache parity error */
+#if defined(CPU_R3000)
+#define	SR_CUMASK	0xf0000000	/* coproc usable bits */
+#define	SR_CU3		0x80000000	/* Coprocessor 3 usable */
+#define	SR_CU2		0x40000000	/* Coprocessor 2 usable */
+#define	SR_CU1		0x20000000	/* Coprocessor 1 usable */
+#define	SR_CU0		0x10000000	/* Coprocessor 0 usable */
+
+#define	SR_BEV		0x00400000	/* use boot exception vectors */
+
+/* Cache control bits */
+#define	SR_TS		0x00200000	/* TLB shutdown */
+#define	SR_CM		0x00080000	/* cache miss */
+#define	SR_PZ		0x00040000	/* cache parity zero */
+#define	SR_SWC		0x00020000	/* swap cache */
+#define	SR_ISC		0x00010000	/* Isolate data cache */
+
+/*
+**	status register interrupt masks and bits
+*/
+
+#define	SR_IMASK	0x0000ff00	/* Interrupt mask */
+#define	SR_IMASK8	0x00000000	/* mask level 8 */
+#define	SR_IMASK7	0x00008000	/* mask level 7 */
+#define	SR_IMASK6	0x0000c000	/* mask level 6 */
+#define	SR_IMASK5	0x0000e000	/* mask level 5 */
+#define	SR_IMASK4	0x0000f000	/* mask level 4 */
+#define	SR_IMASK3	0x0000f800	/* mask level 3 */
+#define	SR_IMASK2	0x0000fc00	/* mask level 2 */
+#define	SR_IMASK1	0x0000fe00	/* mask level 1 */
+#define	SR_IMASK0	0x0000ff00	/* mask level 0 */
+
+#define	SR_IMASKSHIFT	8
+
+#define	SR_IBIT8	0x00008000	/* bit level 8 */
+#define	SR_IBIT7	0x00004000	/* bit level 7 */
+#define	SR_IBIT6	0x00002000	/* bit level 6 */
+#define	SR_IBIT5	0x00001000	/* bit level 5 */
+#define	SR_IBIT4	0x00000800	/* bit level 4 */
+#define	SR_IBIT3	0x00000400	/* bit level 3 */
+#define	SR_IBIT2	0x00000200	/* bit level 2 */
+#define	SR_IBIT1	0x00000100	/* bit level 1 */
+
+#define	SR_KUO		0x00000020	/* old kernel/user, 0 => k, 1 => u */
+#define	SR_IEO		0x00000010	/* old interrupt enable, 1 => enable */
+#define	SR_KUP		0x00000008	/* prev kernel/user, 0 => k, 1 => u */
+#define	SR_IEP		0x00000004	/* prev interrupt enable, 1 => enable */
+#define	SR_KUC		0x00000002	/* cur kernel/user, 0 => k, 1 => u */
+#define	SR_IEC		0x00000001	/* cur interrupt enable, 1 => enable */
+#endif
+
+#if defined S364                        /* (CPU_R32364)        */
+#define	SR_CUMASK	0xf0000000	/* coproc usable bits */
+#define	SR_CU3		0x80000000	/* Coprocessor 3 usable */
+#define	SR_CU2		0x40000000	/* Coprocessor 2 usable */
+#define	SR_CU1		0x20000000	/* Coprocessor 1 usable */
+#define	SR_CU0		0x10000000	/* Coprocessor 0 usable */
+
+/* defines for R32364 processor */
+#define	SR_NBL		0x08000000	/* Non Blocking Load */
+#define	SR_RE		0X02000000	/* Reverse Endianness */
+#define	SR_DL		0x01000000	/* Data Cache Locking */
+#define	SR_IL		0x00800000	/* Instruction Cache Locking */
+
+#define	SR_BEV		0x00400000	/* Use boot exception vectors */
+#define	SR_SR		0x00100000	/* Soft reset */
+#define	SR_CH		0x00040000	/* Cache hit */
+#define	SR_CE		0x00020000	/* Use cache ECC  */
+#define	SR_DE		0x00010000	/* Disable cache exceptions */
+
+/*
+**	status register interrupt masks and bits
+*/
+
+#define	SR_IMASK	0x0000ff00	/* Interrupt mask */
+#define	SR_IMASK8	0x00000000	/* mask level 8 */
+#define	SR_IMASK7	0x00008000	/* mask level 7 */
+#define	SR_IMASK6	0x0000c000	/* mask level 6 */
+#define	SR_IMASK5	0x0000e000	/* mask level 5 */
+#define	SR_IMASK4	0x0000f000	/* mask level 4 */
+#define	SR_IMASK3	0x0000f800	/* mask level 3 */
+#define	SR_IMASK2	0x0000fc00	/* mask level 2 */
+#define	SR_IMASK1	0x0000fe00	/* mask level 1 */
+#define	SR_IMASK0	0x0000ff00	/* mask level 0 */
+
+#define	SR_IMASKSHIFT	8
+
+#define	SR_IBIT8	0x00008000	/* bit level 8 */
+#define	SR_IBIT7	0x00004000	/* bit level 7 */
+#define	SR_IBIT6	0x00002000	/* bit level 6 */
+#define	SR_IBIT5	0x00001000	/* bit level 5 */
+#define	SR_IBIT4	0x00000800	/* bit level 4 */
+#define	SR_IBIT3	0x00000400	/* bit level 3 */
+#define	SR_IBIT2	0x00000200	/* bit level 2 */
+#define	SR_IBIT1	0x00000100	/* bit level 1 */
+
+#define	SR_KSMASK	0x00000016	/* Kernel mode mask */
+#define	SR_KSUSER	0x00000000	/* User Mode */
+#define	SR_KSKERNEL	0x00000016	/* Kernel Mode */
+
+#define	SR_ERL		0x00000004	/* Error level */
+#define	SR_EXL		0x00000002	/* Exception level */
+#define	SR_IE		0x00000001	/* Interrupts enabled */
+#define	NOT_SR_IEC      0xfffffffe      /* assembler problem with li
+~SR_IEC */
+
+/* R32364 Cache locking bits */
+#define SR_ICACHELOCK 0x00800000
+#define SR_DCACHELOCK 0x01000000
+
+#endif /* CPU_R32364 */
+
+#if defined(CPU_R4000)
+#define	SR_CUMASK	0xf0000000	/* coproc usable bits */
+#define	SR_CU3		0x80000000	/* Coprocessor 3 usable */
+#define	SR_CU2		0x40000000	/* Coprocessor 2 usable */
+#define	SR_CU1		0x20000000	/* Coprocessor 1 usable */
+#define	SR_CU0		0x10000000	/* Coprocessor 0 usable */
+
+#define	SR_RP		0x08000000      /* Reduced power operation */
+#define	SR_FR		0x04000000	/* Additional floating pt registers */
+#define	SR_RE		0x02000000	/* Reverse endian in user mode */
+
+#define	SR_BEV		0x00400000	/* Use boot exception vectors */
+#define	SR_TS		0x00200000	/* TLB shutdown */
+#define	SR_SR		0x00100000	/* Soft reset */
+#define	SR_CH		0x00040000	/* Cache hit */
+#define	SR_CE		0x00020000	/* Use cache ECC  */
+#define	SR_DE		0x00010000	/* Disable cache exceptions */
+
+/*
+**	status register interrupt masks and bits
+*/
+
+#define	SR_IMASK	0x0000ff00	/* Interrupt mask */
+#define	SR_IMASK8	0x00000000	/* mask level 8 */
+#define	SR_IMASK7	0x00008000	/* mask level 7 */
+#define	SR_IMASK6	0x0000c000	/* mask level 6 */
+#define	SR_IMASK5	0x0000e000	/* mask level 5 */
+#define	SR_IMASK4	0x0000f000	/* mask level 4 */
+#define	SR_IMASK3	0x0000f800	/* mask level 3 */
+#define	SR_IMASK2	0x0000fc00	/* mask level 2 */
+#define	SR_IMASK1	0x0000fe00	/* mask level 1 */
+#define	SR_IMASK0	0x0000ff00	/* mask level 0 */
+
+#define	SR_IMASKSHIFT	8
+
+#define	SR_IBIT8	0x00008000	/* bit level 8 */
+#define	SR_IBIT7	0x00004000	/* bit level 7 */
+#define	SR_IBIT6	0x00002000	/* bit level 6 */
+#define	SR_IBIT5	0x00001000	/* bit level 5 */
+#define	SR_IBIT4	0x00000800	/* bit level 4 */
+#define	SR_IBIT3	0x00000400	/* bit level 3 */
+#define	SR_IBIT2	0x00000200	/* bit level 2 */
+#define	SR_IBIT1	0x00000100	/* bit level 1 */
+
+#define	SR_KSMASK	0x00000018	/* Kernel mode mask */
+#define	SR_KSUSER	0x00000010	/* User mode */
+#define	SR_KSSUPER	0x00000008	/* Supervisor mode */
+#define	SR_KSKERNEL	0x00000000	/* Kernel mode */
+#define	SR_ERL		0x00000004	/* Error level */
+#define	SR_EXL		0x00000002	/* Exception level */
+#define	SR_IE		0x00000001	/* Interrupts enabled */
+
+/* R4650 Cache locking bits */
+#define	SR_ICACHELOCK 0x00800000
+#define	SR_DCACHELOCK 0x01000000
+
+
+#endif
+#if defined(CPU_R3000)
+#define	SR_FR		0x04000000	/* Additional floating point registers */
+#endif
+
+
+
+/*
+ * Cause Register
+ */
+#define	CAUSE_BD	0x80000000	/* Branch delay slot */
+#define	CAUSE_CEMASK	0x30000000	/* coprocessor error */
+#define	CAUSE_CESHIFT	28
+#define	CAUSE_IW	0x01000000	/* Instruction watch */
+#define	CAUSE_DW	0x02000000	/* Data watch */
+#define	CAUSE_IPE	0x04000000	/* Imprecise exception */
+
+
+#define	CAUSE_IPMASK	0x0000FF00	/* Pending interrupt mask */
+#define	CAUSE_IPSHIFT	8
+
+/* Notice: Watch Exception if Exc. Code is 23 is not included in the mask
+ *	   for R32364.
+ */
+#define	CAUSE_EXCMASK	0x0000003C	/* Cause code bits */
+#define	CAUSE_EXCSHIFT	2
+
+#ifndef XDS
+/*
+**  Coprocessor 0 registers
+*/
+
+/* Evelyn, 12/12/94, for P3 	*/
+#define C0_IBASE        $0		/* I base */
+#define C0_IBOUND       $1		/* I bound */
+
+#define	C0_INX			$0		/* tlb index */
+#define	C0_RAND			$1		/* tlb random */
+#if defined(CPU_R3000)
+#define	C0_TLBLO	$2				/* tlb entry low */
+#define	C0_BUSCTRL		$2		/* bus control R3041 specific */
+#define	C0_CONFIG		$3		/* cache config */
+#define	C0_CTXT			$4		/* tlb context */
+#define	C0_BADVADDR		$8		/* bad virtual address */
+#define	C0_COUNT			$9		/* count R3041 specific */
+#define	C0_PORTSIZE		$10	/* port size R3041 specific */
+#define	C0_TLBHI			$10	/* tlb entry hi */
+#define	C0_COMPARE		$11	/* compare R3041 specific */
+#define	C0_SR				$12	/* status register */
+#define	C0_CAUSE			$13	/* exception cause */
+#define	C0_EPC			$14	/* exception pc */
+#define	C0_PRID			$15	/* revision identifier */
+#endif
+
+#if defined(S364)					/*(CPU_R32364)      */
+#define	C0_RANDOM		$1
+#define	C0_TLBLO0		$2		/* tlb entry low 0 */
+#define	C0_TLBLO1		$3		/* tlb entry low 1 */
+#define	C0_CTXT			$4		/* tlb context */
+#define	C0_PAGEMASK		$5		/* tlb page mask */
+#define	C0_WIRED			$6		/* number of wired tlb entries */
+
+#define	C0_INX			$0		/* tlb index */
+#define	C0_BADVADDR		$8		/* bad virtual address */
+#define	C0_COUNT			$9		/* timer count */
+#define	C0_TLBHI			$10	/* tlb entry hi */
+#define	C0_COMPARE		$11	/* timer comparator  */
+#define	C0_SR				$12	/* status register */
+#define	C0_CAUSE			$13	/* exception cause */
+#define	C0_EPC			$14	/* exception pc */
+#define	C0_PRID			$15	/* revision identifier */
+#define	C0_CONFIG		$16	/* configuration register */
+
+#define	C0_IWATCH		$18	/* Instr brk pt Virtual add. */
+#define	C0_DWATCH		$19	/* Data brk pt Virtual add. */
+
+#define	C0_IEPC			$22	/* Imprecise Exception pc */
+#define	C0_DEPC			$23	/* Debug Exception pc */
+#define	C0_DEBUG			$24	/* Debug control/status reg */
+
+#define	C0_ECC			$26	/* primary cache Parity control */
+#define	C0_CACHEERR		$27	/* cache error status */
+#define	C0_TAGLO			$28	/* cache tag lo */
+#define	C0_TAGHI			$29
+#define	C0_ERRPC			$30	/* cache error pc */
+#endif /* CPU_R32364 			*/
+
+#if defined(CPU_R4000)
+
+/* Evelyn, 12/12/94, for P3 	*/
+#define	C0_DBASE			$2		/* D base */
+#define	C0_DBOUND		$3		/* D bound */
+
+#define	C0_TLBLO0		$2		/* tlb entry low 0 */
+#define	C0_TLBLO1		$3		/* tlb entry low 1 */
+#define	C0_CTXT			$4		/* tlb context */
+#define	C0_PAGEMASK		$5		/* tlb page mask */
+#define	C0_WIRED			$6		/* number of wired tlb entries */
+
+#define	C0_BADVADDR		$8		/* bad virtual address */
+#define	C0_COUNT			$9		/* cycle count */
+#define	C0_TLBHI			$10	/* tlb entry hi */
+#define	C0_COMPARE		$11	/* cyccle count comparator  */
+#define	C0_SR				$12	/* status register */
+#define	C0_CAUSE			$13	/* exception cause */
+#define	C0_EPC			$14	/* exception pc */
+#define	C0_PRID			$15	/* revision identifier */
+#define	C0_CONFIG		$16	/* configuration register */
+
+/* Evelyn, 12/12/94, for P3   */
+#define	C0_CALG			$17	/* Calg rigister */
+#define	C0_IWATCH		$18	/* IWatch register */
+#define	C0_DWATCH		$19	/* DWatch register */
+
+#define	C0_LLADDR		$17	/* linked load address */
+#define	C0_WATCHLO		$18	/* watchpoint trap register */
+#define	C0_WATCHHI		$19	/* watchpoint trap register */
+#define	C0_XCTXT			$20 	/* extended tlb context */
+#define	C0_ECC			$26	/* secondary cache ECC control */
+#define	C0_CACHEERR		$27	/* cache error status */
+#define	C0_TAGLO			$28	/* cache tag lo */
+#define	C0_TAGHI			$29	/* cache tag hi */
+#define	C0_ERRPC			$30	/* cache error pc */
+#endif
+#endif 
+#endif /* defined(__IDTCPU_H__) */
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/idthdr.h idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/idthdr.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/idthdr.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/idthdr.h	2006-03-09 16:25:47.000000000 -0800
@@ -0,0 +1,54 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Some macros. Though they are already defined else where in the linux
+ *   tree, they are once again declared here for the ease of syncing up with
+ *    IDT bootloader code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef XDS
+
+#define	FRAME(name,frm_reg,offset,ret_reg)	\
+	.globl	name;				\
+	.ent	name;				\
+name:;						\
+	.frame	frm_reg,offset,ret_reg
+
+#define ENDFRAME(name) 	.end name
+
+#else
+
+#define FRAME(name,frm_reg,offset,ret_reg)      \
+name:
+
+#define ENDFRAME(name)
+
+#endif
+
+
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/image.lds.in idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/image.lds.in
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/image.lds.in	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/image.lds.in	2006-03-09 16:25:47.000000000 -0800
@@ -0,0 +1,31 @@
+OUTPUT_ARCH(mips)
+ENTRY(zstartup)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = IMSTART;
+  .init          : { *(.init)		} =0
+  .text      :
+  {
+    _ftext = . ;
+    *(.text)
+    *(.rodata)
+    *(.rodata1)
+   . = ALIGN(4096);
+    input_data = .;
+    arch/mips/idt-boards/rc32300/EB365/boot/piggy.o
+    input_data_end = .;
+   . = ALIGN(4096);
+    *(.gnu.warning)
+  } =0
+
+  .reginfo : { *(.reginfo) }
+
+   . = BSS_START;
+  __bss_start = .;
+  .bss       :
+  {
+   *(.bss)
+  _end = . ;
+  }
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/iregdef.h idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/iregdef.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/iregdef.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/iregdef.h	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,285 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   IDT CPU register definitions. Though the registers are already defined
+ *   under asm directory, they are once again declared here for the ease of
+ *   syncing up with IDT bootloader code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#define r0	$0
+#define r1	$1 /*at assembler temp */
+#define r2	$2 /*v0 return value */
+#define r3	$3 /*v1 return value */
+#define r4	$4 /*a0 argument 0 */
+#define r5	$5 /*a1 argument 1 */
+#define r6	$6
+#define r7	$7
+#define r8	$8
+#define r9	$9
+#define r10	$10
+#define r11	$11
+#define r12	$12
+#define r13	$13
+
+#define r14	$14
+#define r15	$15
+#define r16	$16 /*s0 called saved */
+#define r17	$17
+#define r18	$18
+#define r19	$19
+#define r20	$20
+#define r21	$21
+#define r22	$22
+#define r23	$23 /*s7 called saved */
+#define r24	$24
+#define r25	$25
+#define r26	$26 /*k0 kernel temp. */
+#define r27	$27 /*k1   ""    ""   */
+#define r28	$28 /*gp global pointer */
+#define r29	$29 /*sp stack pointer */
+#define r30	$30 /*fp frame pointer */
+#define r31	$31 /*ra return address */
+
+#define fp0	$f0
+#define fp1	$f1
+#define fp2	$f2
+#define fp3	$f3
+#define fp4	$f4
+#define fp5	$f5
+#define fp6	$f6
+#define fp7	$f7
+#define fp8	$f8
+#define fp9	$f9
+#define fp10	$f10
+#define fp11	$f11
+#define fp12	$f12
+#define fp13	$f13
+#define fp14	$f14
+#define fp15	$f15
+#define fp16	$f16
+#define fp17	$f17
+#define fp18	$f18
+#define fp19	$f19
+#define fp20	$f20
+#define fp21	$f21
+#define fp22	$f22
+#define fp23	$f23
+#define fp24	$f24
+#define fp25	$f25
+#define fp26	$f26
+#define fp27	$f27
+#define fp28	$f28
+#define fp29	$f29
+#define fp30	$f30
+#define fp31	$f31
+
+#define fcr0	$0
+#define fcr30	$30
+#define fcr31	$31
+
+#define zero	$0	/* wired zero */
+#define AT	$at	/* assembler temp */
+#define v0	$2	/* return value */
+#define v1	$3
+#define a0	$4	/* argument registers */
+#define a1	$5
+#define a2	$6
+#define a3	$7
+#define t0	$8	/* caller saved */
+#define t1	$9
+#define t2	$10
+#define t3	$11
+#define t4	$12
+#define t5	$13
+#define t6	$14
+#define t7	$15
+#define s0	$16	/* callee saved */
+#define s1	$17
+#define s2	$18
+#define s3	$19
+#define s4	$20
+#define s5	$21
+#define s6	$22
+#define s7	$23
+#define t8	$24	/* code generator */
+#define t9	$25
+#define k0	$26	/* kernel temporary */
+#define k1	$27
+#define gp	$28	/* global pointer */
+#define sp	$29	/* stack pointer */
+#define s8	$30	/* yet another saved reg for the callee */
+#define fp	$30	/* frame pointer - this is being phased out by MIPS */
+#define ra	$31	/* return address */
+
+
+/*
+ * register names
+ */
+#define	R_R0		0
+#define	R_R1		1
+#define	R_R2		2
+#define	R_R3		3
+#define	R_R4		4
+#define	R_R5		5
+#define	R_R6		6
+#define	R_R7		7
+#define	R_R8		8
+#define	R_R9		9
+#define	R_R10		10
+#define	R_R11		11
+#define	R_R12		12
+#define	R_R13		13
+#define	R_R14		14
+#define	R_R15		15
+#define	R_R16		16
+#define	R_R17		17
+#define	R_R18		18
+#define	R_R19		19
+#define	R_R20		20
+#define	R_R21		21
+#define	R_R22		22
+#define	R_R23		23
+#define	R_R24		24
+#define	R_R25		25
+#define	R_R26		26
+#define	R_R27		27
+#define	R_R28		28
+#define	R_R29		29
+#define	R_R30		30
+#define	R_R31		31
+#define	R_F0		32
+#define	R_F1		33
+#define	R_F2		34
+#define	R_F3		35
+#define	R_F4		36
+#define	R_F5		37
+#define	R_F6		38
+#define	R_F7		39
+#define	R_F8		40
+#define	R_F9		41
+#define	R_F10		42
+#define	R_F11		43
+#define	R_F12		44
+#define	R_F13		45
+#define	R_F14		46
+#define	R_F15		47
+#define	R_F16		48
+#define	R_F17		49
+#define	R_F18		50
+#define	R_F19		51
+#define	R_F20		52
+#define	R_F21		53
+#define	R_F22		54
+#define	R_F23		55
+#define	R_F24		56
+#define	R_F25		57
+#define	R_F26		58
+#define	R_F27		59
+#define	R_F28		60
+#define	R_F29		61
+#define	R_F30		62
+#define	R_F31		63
+#define NCLIENTREGS	64
+#define	R_EPC		64
+#define	R_MDHI		65
+#define	R_MDLO		66
+#define	R_SR		67
+#define	R_CAUSE		68
+#define	R_TLBHI		69
+#ifdef CPU_R4000
+#define	R_TLBLO0	70
+#else
+#define	R_TLBLO		70
+#endif
+#define	R_BADVADDR	71
+#define	R_INX		72
+#define	R_RAND		73
+#define	R_CTXT		74
+#define	R_EXCTYPE	75
+#define R_MODE		76
+#define	R_PRID		77
+#define R_FCSR		78
+#define R_FEIR		79
+#ifdef CPU_R4000
+#define	R_TLBLO1	80
+#define R_PAGEMASK	81
+#define R_WIRED		82
+#define R_COUNT		83
+#define R_COMPARE	84
+#define R_CONFIG	85
+#define R_LLADDR	86
+#define R_WATCHLO	87
+#define R_WATCHHI	88
+#define R_ECC		89
+#define R_CACHEERR	90
+#define R_TAGLO		91
+#define R_TAGHI		92
+#define R_ERRPC		93
+#endif
+
+#ifdef CPU_R4000
+#define	NREGS		94
+#else
+#define NREGS		80
+#endif
+
+/*
+ * compiler defined bindings
+ */
+#define	R_ZERO		R_R0
+#define	R_AT		R_R1
+#define	R_V0		R_R2
+#define	R_V1		R_R3
+#define	R_A0		R_R4
+#define	R_A1		R_R5
+#define	R_A2		R_R6
+#define	R_A3		R_R7
+#define	R_T0		R_R8
+#define	R_T1		R_R9
+#define	R_T2		R_R10
+#define	R_T3		R_R11
+#define	R_T4		R_R12
+#define	R_T5		R_R13
+#define	R_T6		R_R14
+#define	R_T7		R_R15
+#define	R_S0		R_R16
+#define	R_S1		R_R17
+#define	R_S2		R_R18
+#define	R_S3		R_R19
+#define	R_S4		R_R20
+#define	R_S5		R_R21
+#define	R_S6		R_R22
+#define	R_S7		R_R23
+#define	R_T8		R_R24
+#define	R_T9		R_R25
+#define	R_K0		R_R26
+#define	R_K1		R_R27
+#define	R_GP		R_R28
+#define	R_SP		R_R29
+#define	R_FP		R_R30
+#define	R_RA		R_R31
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/Makefile idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/Makefile
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/Makefile	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/Makefile	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,126 @@
+###############################################################################
+#
+#  BRIEF MODULE DESCRIPTION
+#     Makefile create a compressed zImage or Rommable rImage
+#
+#  Copyright 2006 IDT Inc. (rischelp@idt.com)
+#
+#  This program is free software; you can redistribute  it and/or modify it
+#  under  the terms of  the GNU General  Public License as published by the
+#  Free Software Foundation;  either version 2 of the  License, or (at your
+#  option) any later version.
+#
+#  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+#  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+#   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+#   NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+#   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+#   NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+#   USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+#   ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+#   THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#   You should have received a copy of the  GNU General Public License along
+#   with this program; if not, write  to the Free Software Foundation, Inc.,
+#   675 Mass Ave, Cambridge, MA 02139, USA.
+# 
+# 
+###############################################################################
+
+###############################################################################
+# The following is taken from IDT/Sim Makefile
+#############################################################################
+TARGET=365
+
+# following refers to size of the DRAM space.
+# These are values for the switch DRAMSZ.
+
+MB16=1
+MB32=2
+MB64=3
+MB128=4
+MB32SO=5
+
+MACH= -DS$(TARGET) -DEB365 -DS364 -DCPU_R32364 -DDRAMSZ=$(MB32SO)
+COMMSWITCHES = $(INCDIRS) $(MACH)
+#***************** END IDT/Sim Makefile #####################################
+ZDEBUG=1
+export ZDEBUG
+
+# working space for gunzip:
+FREE_RAM      := 0x80C00000
+END_RAM       := 0x80E00000
+
+KERNELCONFIG  := $(TOPDIR)/.config
+include $(KERNELCONFIG)
+
+SIZE = $(CROSS_COMPILE)size
+
+O_FORMAT = $(shell $(OBJDUMP) -i | head -2 | grep elf32)
+
+SYSTEM	      := $(TOPDIR)/vmlinux
+ZBSS          := 0x800A0000
+
+ZIMSTART      := $(CONFIG_IDT_ZIMAGE_ADDR)
+RIMSTART      := 0x9FC00000
+
+LOADADDR      := 0x$(shell $(NM) $(SYSTEM) | grep "A _text" |cut -f1 -d' ')
+KERNEL_ENTRY  := $(shell $(OBJDUMP) -f $(SYSTEM) | sed -n -e 's/^start address //p')
+
+####################################################################################
+ZIMFLAGS        = s/IMSTART/$(ZIMSTART)/;s/BSS_START/$(ZBSS)/
+RIMFLAGS        = s/IMSTART/$(RIMSTART)/;s/BSS_START/$(ZBSS)/
+CFLAGS	:= -fno-pic -nostdinc -G 0 -mno-abicalls -fno-pic -pipe -I$(TOPDIR)/include
+AFLAGS	:= -D__ASSEMBLY__ $(CFLAGS)
+
+####################################################################################
+OBJECTS= $(obj)/piggy.o $(obj)/head.o $(obj)/misc.o
+ifneq ($(ZDEBUG),0)
+OBJECTS += $(obj)/uart16550.o
+endif
+
+$(obj)/zImage.lds: $(obj)/image.lds.in $(KERNELCONFIG)
+	@sed "$(ZIMFLAGS)" < $< > $@
+
+$(obj)/rImage.lds: $(obj)/image.lds.in $(KERNELCONFIG)
+	@sed "$(RIMFLAGS)" < $< > $@
+
+$(obj)/piggy.o: $(SYSTEM) $(obj)/Makefile
+	$(OBJCOPY) -S -O binary -R .note -R .comment $(SYSTEM) $(SYSTEM).bin
+	gzip -f -9 < $(SYSTEM).bin > $(SYSTEM).gz
+	echo "O_FORMAT:  " $(O_FORMAT); 
+	$(LD) -r -b binary --oformat $(O_FORMAT) -o $(obj)/piggy.o $(SYSTEM).gz
+	rm -f $(SYSTEM).bin $(SYSTEM).gz
+
+$(obj)/head.o: $(obj)/head.S $(SYSTEM) $(obj)/Makefile
+	$(CC) $(AFLAGS) -DKERNEL_ENTRY=$(KERNEL_ENTRY) -c $(obj)/head.S -o $(obj)/head.o
+
+$(obj)/misc.o: $(obj)/misc.c $(obj)/Makefile
+	$(CC) $(CFLAGS) -DLOADADDR=$(LOADADDR) -DFREE_RAM=$(FREE_RAM) -DEND_RAM=$(END_RAM) \
+		-c $< -DZDEBUG=$(ZDEBUG) -o $(obj)/misc.o
+
+$(obj)/uart16550.o: $(obj)/uart16550.c $(KERNELCONFIG)
+	$(CC) $(CFLAGS) -c $< -o $(obj)/uart16550.o
+
+$(obj)/csu_idt.o: $(obj)/csu_idt.S Makefile $(SYSTEM)
+	$(CC) $(AFLAGS) $(COMMSWITCHES) -c $< -o $(obj)/csu_idt.o
+
+zImage: $(obj)/zImage.lds $(SYSTEM) $(OBJECTS)
+	$(LD) -T$(obj)/zImage.lds -o $(TOPDIR)/zImage $(OBJECTS)
+	$(OBJCOPY) -S -O binary -R .note -R .comment $(TOPDIR)/zImage $(TOPDIR)/zImage.bin
+	$(OBJCOPY) -I binary -S -O srec --srec-forceS3 --srec-len=32 --change-start=0x00000000 \
+		 $(TOPDIR)/zImage.bin $(TOPDIR)/zImage.prm
+	$(SIZE) $(TOPDIR)/zImage |awk -F" " '{ print $$4 "\t" $$5 }' > $(TOPDIR)/zImage.size
+	rm -f *.o
+
+rImage: $(obj)/rImage.lds $(OBJECTS) $(obj)/csu_idt.o $(SYSTEM)
+	@rm -f $(TOPDIR)/*.prm
+	$(LD) -T$(obj)/rImage.lds -o $(TOPDIR)/rImage $(obj)/csu_idt.o $(OBJECTS) 
+	$(OBJCOPY) -S -O binary -R .note -R .comment $(TOPDIR)/rImage $(TOPDIR)/rImage.bin
+	$(OBJCOPY) -I binary -S -O srec --srec-forceS3 --srec-len=32 --change-start=0x00000000 \
+		 $(TOPDIR)/rImage.bin $(TOPDIR)/rImage.prm
+	$(SIZE) $(TOPDIR)/rImage |awk -F" " '{ print $$4 "\t" $$5 }' > $(TOPDIR)/rImage.size
+	rm -f *.o
+clean:
+	rm -f *.o $(TOPDIR)/zImage $(TOPDIR)/rImage $(TOPDIR)/*.prm $(TOPDIR)/rImage.size $(TOPDIR)/zImage.size
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/misc.c idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/misc.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/misc.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/misc.c	2006-03-09 16:25:47.000000000 -0800
@@ -0,0 +1,340 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Code to un-compress linux image
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/types.h>
+
+/*
+ * gzip declarations
+ */
+#define OF(args)  args
+#define STATIC static
+#define memzero(s, n)     memset ((s), 0, (n))
+typedef unsigned char uch;
+typedef unsigned short ush;
+typedef unsigned long ulg;
+#define WSIZE 0x8000		/* Window size must be at least 32k, */
+				/* and a power of two */
+static uch *inbuf;		/* input buffer */
+static uch window[WSIZE];	/* Sliding window buffer */
+
+/* gzip flag byte */
+#define ASCII_FLAG   0x01	/* bit 0 set: file probably ASCII text */
+#define CONTINUATION 0x02	/* bit 1 set: continuation of multi-part gzip file */
+#define EXTRA_FIELD  0x04	/* bit 2 set: extra field present */
+#define ORIG_NAME    0x08	/* bit 3 set: original file name present */
+#define COMMENT      0x10	/* bit 4 set: file comment present */
+#define ENCRYPTED    0x20	/* bit 5 set: file is encrypted */
+#define RESERVED     0xC0	/* bit 6,7:   reserved */
+
+
+static unsigned insize;	/* valid bytes in inbuf */
+static unsigned inptr;	/* index of next byte to be processed in inbuf */
+static unsigned outcnt;	/* bytes in output buffer */
+
+void variable_init(void);
+#if ZDEBUG > 0
+static void puts(const char *);
+extern void putc_init(void);
+extern void putc(unsigned char c);
+#endif
+static int fill_inbuf(void);
+static void flush_window(void);
+static void error(char *m);
+static void gzip_mark(void **);
+static void gzip_release(void **);
+
+extern char input_data[];
+
+extern char input_data_end[];
+
+#if ZDEBUG > 0
+void int2hex(unsigned long val)
+{
+        unsigned char buf[10];
+        int i;
+        for (i = 7;  i >= 0;  i--)
+        {
+                buf[i] = "0123456789ABCDEF"[val & 0x0F];
+                val >>= 4;
+        }
+        buf[8] = '\0';
+        puts(buf);
+}
+#endif
+
+static unsigned long byte_count;
+
+int get_byte(void)
+{
+#if ZDEBUG > 1
+	static int printCnt;
+#endif
+	unsigned char c = (inptr < insize ? inbuf[inptr++] : fill_inbuf());
+	byte_count++;
+
+#if ZDEBUG > 1
+	if (printCnt++ < 32)
+	{
+	  puts("byte count = ");
+	  int2hex(byte_count);
+	  puts(" byte val = ");
+	  int2hex(c);
+	  puts("\n");
+	}
+#endif
+	return c;
+}
+
+/* Diagnostic functions */
+#ifdef DEBUG
+#  define Assert(cond,msg) {if(!(cond)) error(msg);}
+#  define Trace(x) fprintf x
+#  define Tracev(x) {if (verbose) fprintf x ;}
+#  define Tracevv(x) {if (verbose>1) fprintf x ;}
+#  define Tracec(c,x) {if (verbose && (c)) fprintf x ;}
+#  define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}
+#else
+#  define Assert(cond,msg)
+#  define Trace(x)
+#  define Tracev(x)
+#  define Tracevv(x)
+#  define Tracec(c,x)
+#  define Tracecv(c,x)
+#endif
+
+/*
+ * This is set up by the setup-routine at boot-time
+ */
+
+static long bytes_out;
+static uch *output_data;
+static unsigned long output_ptr;
+
+
+static void *malloc(int size);
+static void free(void *where);
+static void error(char *m);
+static void gzip_mark(void **);
+static void gzip_release(void **);
+
+static unsigned long free_mem_ptr;
+static unsigned long free_mem_end_ptr;
+
+#include "../../../../../../lib/inflate.c"
+
+static void *malloc(int size)
+{
+	void *p;
+
+	if (size < 0)
+		error("Malloc error\n");
+	if (free_mem_ptr <= 0) error("Memory error\n");
+
+	free_mem_ptr = (free_mem_ptr + 3) & ~3;	/* Align */
+
+	p = (void *) free_mem_ptr;
+	free_mem_ptr += size;
+
+	if (free_mem_ptr >= free_mem_end_ptr)
+		error("\nOut of memory\n");
+
+	return p;
+}
+
+static void free(void *where)
+{				/* Don't care */
+}
+
+static void gzip_mark(void **ptr)
+{
+	*ptr = (void *) free_mem_ptr;
+}
+
+static void gzip_release(void **ptr)
+{
+	free_mem_ptr = (long) *ptr;
+}
+#if ZDEBUG > 0
+static void puts(const char *s)
+{
+	while (*s) {
+		if (*s == 10)
+			putc(13);
+		putc(*s++);
+	}
+}
+#endif
+void *memset(void *s, int c, size_t n)
+{
+	int i;
+	char *ss = (char *) s;
+
+	for (i = 0; i < n; i++)
+		ss[i] = c;
+	return s;
+}
+
+void *memcpy(void *__dest, __const void *__src, size_t __n)
+{
+	int i;
+	char *d = (char *) __dest, *s = (char *) __src;
+
+	for (i = 0; i < __n; i++)
+		d[i] = s[i];
+	return __dest;
+}
+
+/* ===========================================================================
+ * Fill the input buffer. This is called only when the buffer is empty
+ * and at least one byte is really needed.
+ */
+static int fill_inbuf(void)
+{
+	if (insize != 0) {
+		error("ran out of input data\n");
+	}
+
+	inbuf = input_data;
+	insize = &input_data_end[0] - &input_data[0];
+	inptr = 1;
+	return inbuf[0];
+}
+
+/* ===========================================================================
+ * Write the output window window[0..outcnt-1] and update crc and bytes_out.
+ * (Used for the decompressed data only.)
+ */
+static void flush_window(void)
+{
+	ulg c = crc;		/* temporary variable */
+	unsigned n;
+	uch *in, *out, ch;
+
+	in = window;
+	out = &output_data[output_ptr];
+	for (n = 0; n < outcnt; n++) {
+		ch = *out++ = *in++;
+		c = crc_32_tab[((int) c ^ ch) & 0xff] ^ (c >> 8);
+	}
+	crc = c;
+	bytes_out += (ulg) outcnt;
+	output_ptr += (ulg) outcnt;
+	outcnt = 0;
+}
+
+#if ZDEBUG > 0
+void check_mem(void)
+{
+	int i;
+
+	puts("\ncplens = ");
+	for (i = 0; i < 10; i++) {
+		int2hex(cplens[i]);
+		puts(" ");
+	}
+	puts("\ncplext = ");
+	for (i = 0; i < 10; i++) {
+		int2hex(cplext[i]);
+		puts(" ");
+	}
+	puts("\nborder = ");
+	for (i = 0; i < 10; i++) {
+		int2hex(border[i]);
+		puts(" ");
+	}
+	puts("\n");
+}
+#endif
+static void error(char *x)
+{
+#if ZDEBUG > 1
+	check_mem();
+	puts("\n\n");
+	puts(x);
+	puts("byte_count = ");
+	int2hex(byte_count);
+	puts("\n");
+	puts("\n\n -- Error. System halted");
+#endif
+	while (1);		/* Halt */
+}
+
+void variable_init(void)
+{
+	byte_count = 0;
+	output_data = (char *) LOADADDR;
+	free_mem_ptr = FREE_RAM;
+	free_mem_end_ptr = END_RAM;
+#if ZDEBUG > 1
+	puts("output_data      0x");
+	int2hex((unsigned long)output_data); puts("\n");
+	puts("free_mem_ptr     0x");
+	int2hex(free_mem_ptr); puts("\n");
+	puts("free_mem_end_ptr 0x");
+	int2hex(free_mem_end_ptr); puts("\n");
+	puts("input_data       0x");
+	int2hex((unsigned long)input_data); puts("\n");
+#endif
+}
+
+int decompress_kernel(void)
+{
+#if ZDEBUG > 0
+  putc_init();
+#if ZDEBUG > 2
+  check_mem();
+#endif
+#endif
+
+  variable_init();
+
+  makecrc();
+#if ZDEBUG > 0
+  puts("\n");
+  puts("Uncompressing Linux... \n");
+#endif
+  gunzip();		// ...see inflate.c
+#if ZDEBUG > 0
+  puts("Ok, booting the kernel.\n");
+#endif
+
+#if ZDEBUG > 1
+ {
+  unsigned long *p = (unsigned long *)LOADADDR;
+  int2hex(p[0]); puts("\n");
+  int2hex(p[1]); puts("\n");
+  int2hex(p[2]); puts("\n");
+  int2hex(p[3]); puts("\n");
+ }
+#endif
+
+  return 0;
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/rImage.lds idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/rImage.lds
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/rImage.lds	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/rImage.lds	2006-03-09 16:25:47.000000000 -0800
@@ -0,0 +1,31 @@
+OUTPUT_ARCH(mips)
+ENTRY(zstartup)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = 0x9FC00000;
+  .init          : { *(.init)		} =0
+  .text      :
+  {
+    _ftext = . ;
+    *(.text)
+    *(.rodata)
+    *(.rodata1)
+   . = ALIGN(4096);
+    input_data = .;
+    arch/mips/idt-boards/rc32300/EB365/boot/piggy.o
+    input_data_end = .;
+   . = ALIGN(4096);
+    *(.gnu.warning)
+  } =0
+
+  .reginfo : { *(.reginfo) }
+
+   . = 0x800A0000;
+  __bss_start = .;
+  .bss       :
+  {
+   *(.bss)
+  _end = . ;
+  }
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/s365led.h idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/s365led.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/s365led.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/s365led.h	2006-03-09 16:25:47.000000000 -0800
@@ -0,0 +1,62 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   IDT CPU LED address definitions. Though the registers are already defined
+ *   else where under linux tree, they are once again declared here for the
+ *    ease of syncing up with IDT bootloader code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef __S365LED__
+#define __S365LED__
+
+/*
+** following few lines define a macro DISPLAY
+** which is used to write a set of 4 characters
+** onto the EB365 LED.
+*/
+
+#define GPIO_BASE     PHYS_TO_K1(0x18048000)
+
+#define LED_BASE      PHYS_TO_K1(0x0C000000)
+#define LED_DIGIT0    0x3
+#define LED_DIGIT1    0x2
+#define LED_DIGIT2    0x1
+#define LED_DIGIT3    0x0
+
+#define DISPLAY(d0, d1, d2, d3)     \
+        li    t6, LED_BASE                    ;\
+        li    t7, (d0) & 0xff                 ;\
+        sb    t7, LED_DIGIT0(t6)              ;\
+        li    t7, (d1) & 0xff                 ;\
+        sb    t7, LED_DIGIT1(t6)              ;\
+        li    t7, (d2) & 0xff                 ;\
+        sb    t7, LED_DIGIT2(t6)              ;\
+        li    t7, (d3) & 0xff                 ;\
+        sb    t7, LED_DIGIT3(t6)
+
+#endif
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/s365ram.h idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/s365ram.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/s365ram.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/s365ram.h	2006-03-09 16:25:47.000000000 -0800
@@ -0,0 +1,144 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   IDT EB365 SDRAM setup values.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef __S365RAM__
+#define __S365RAM__
+/******************************** D E F I N E S *******************************/
+
+#define MB16	1
+#define MB32	2
+#define MB64	3
+#define MB128	4
+#define MB32SO	5
+
+#define DEV_CTL_BASE        PHYS_TO_K1(0x18010000)  /* device controller regs */
+#define SDRAM_BASE          PHYS_TO_K1(0x18018000)  /* SDRAM controller regs */
+#define GPIO_FUNC           0x0000609f		    /* SDRAM CLK; MEM[25:22]; UART */
+#define GPIO_CFG	    0x00000020		    /* GPIO5 ouput for SPI CS */
+#define GPIO_OUT	    0x00000020		    /* GPIO5 ouput 1 */
+#define ERR_CNTL_STATUS     PHYS_TO_K1(0x18028030)
+
+#define DEV1_BASE           0x08000000
+#define DEV_PROM_MASK       0xFFE00000
+#define DEV_PROM_CTRL       0x028A2205
+#define DEV_PROM_TC         0x00000A44
+#define DEV_FLASH_MASK      0xFF800000
+#define DEV_FLASH_CTRL      0x028A2206
+#define DEV_FLASH_TC        0x00000A44
+
+#define DEV2_BASE           0x0C000000
+#define DEV2_MASK           0xFF000000
+#define DEV2_CTRL           0x04108324              /* 8-bit devices */
+#define DEV2_TC             0x00000A44
+
+#define DEV3_BASE           0x00000000
+#define DEV3_MASK           0x00000000
+#define DEV3_CTRL           0x0FFFFFF4              /* ?-bit devices */
+#define DEV3_TC             0x00001FFF
+
+#define DEV4_BASE           0x00000000
+#define DEV4_MASK           0x00000000
+#define DEV4_CTRL           0x0FFFFFF4              /* ?-bit devices */
+#define DEV4_TC             0x00001FFF
+
+#define DEV5_BASE           0x00000000
+#define DEV5_MASK           0x00000000
+#define DEV5_CTRL           0x0FFFFFF4              /* ?-bit devices */
+#define DEV5_TC             0x00001FFF
+
+#define DATA_PATTERN        0xA5A5A5A5
+
+#if DRAMSZ == MB32SO
+
+/* Address space allocations */
+#define SDRAM_BNK0_BASE     0x00000000  /* 0 MB */
+#define SDRAM_BNK0_MASK     0xFE000000
+#define SDRAM_BNK1_BASE     0x02000000  /* 32 MB */
+#define SDRAM_BNK1_MASK     0x00000000
+#define SDRAM_BNK0_ABASE    0x00000000  /* 0 MB */
+#define SDRAM_BNK0_AMASK    0x00000000
+
+/* SDRAM Chip specific setup */
+#if MHZ == 90
+#define SDRAM_CR_BS 	    0x994330F0 /* SDRAM enable 	*/
+#define SDRAM_DS_BS 	    0x19433080 /* SDRAM disable */
+#define SDRAM_PC_VAL  	    0x194330c3 /* Precharge val */
+#define SDRAM_RFRSH_CMD     0x19433093 /* refresh cmd 	*/
+#define SDRAM_MODE_REG      0x19433083 /* mode register */
+#else
+#define SDRAM_CR_BS 	    0x984330F0 /* SDRAM enable 	*/
+#define SDRAM_DS_BS 	    0x18433080 /* SDRAM disable */
+#define SDRAM_PC_VAL  	    0x184330c3 /* Precharge val */
+#define SDRAM_RFRSH_CMD     0x18433093 /* refresh cmd 	*/
+#define SDRAM_MODE_REG      0x18433083 /* mode register */
+#endif
+
+#else
+
+/* Address space allocations */
+#define SDRAM_BNK0_BASE     0x00000000  /* 0 MB */
+#define SDRAM_BNK0_MASK     0xFF000000
+#define SDRAM_BNK1_BASE     0x01000000  /* 16 MB */
+#define SDRAM_BNK1_MASK     0x00000000
+#define SDRAM_BNK0_ABASE    0x00000000  /* 0 MB */
+#define SDRAM_BNK0_AMASK    0x00000000
+
+/* SDRAM Chip specific setup */
+#if MHZ == 90
+#define SDRAM_CR_BS 	    0x894370F0 /* SDRAM enable 	*/
+#define SDRAM_DS_BS 	    0x09437080 /* SDRAM disable */
+#define SDRAM_PC_VAL  	    0x094370c3 /* Precharge val */
+#define SDRAM_RFRSH_CMD     0x09437093 /* refresh cmd 	*/
+#define SDRAM_MODE_REG      0x09437083 /* mode register */
+#else
+#define SDRAM_CR_BS 	    0x884370F0 /* SDRAM enable 	*/
+#define SDRAM_DS_BS 	    0x08437080 /* SDRAM disable */
+#define SDRAM_PC_VAL  	    0x084370c3 /* Precharge val */
+#define SDRAM_RFRSH_CMD     0x08437093 /* refresh cmd 	*/
+#define SDRAM_MODE_REG      0x08437083 /* mode register */
+#endif
+
+#endif
+
+/* Refresh timer */
+#define SDRAM_RF_CNT_BS     0x00000000 /* refresh count reg */
+#define SDRAM_RF_CMPR_BS    0x00000040 /* refresh comp reg  */
+#if MHZ == 90
+#define SDRAM_RF_CMPR_SE_BS 0x000002EE /* slow expiration   */
+#else
+#define SDRAM_RF_CMPR_SE_BS 0x00000271 /* slow expiration   */
+#endif
+
+#define DELAY_200USEC       30000      /* not exactly */
+#define DISABLE_TIMER       0
+#define ENABLE_TIMER        1
+
+#endif
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/uart16550.c idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/uart16550.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/uart16550.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/uart16550.c	2006-03-09 16:25:47.000000000 -0800
@@ -0,0 +1,178 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   UART code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+
+#define RC32365_REG_BASE   0xb8000000
+#ifdef __MIPSEB__
+#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50003)
+#else
+#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50000)
+#endif
+
+#define BASE		   RC32300_UART0_BASE
+
+#define MAX_BAUD		(CONFIG_IDT_BOARD_FREQ / 16)
+#define REG_OFFSET		0x4
+
+/* === CONFIG === */
+
+/*
+ * #define BASE			0xb2001000
+ * #define MAX_BAUD		1152000
+ * #define REG_OFFSET		0x10
+ */
+#if (!defined(BASE) || !defined(MAX_BAUD) || !defined(REG_OFFSET))
+#error You must define BASE, MAX_BAUD and REG_OFFSET in the Makefile.
+#endif
+
+#ifndef INIT_SERIAL_PORT
+#define INIT_SERIAL_PORT	1
+#endif
+
+#ifndef DEFAULT_BAUD
+//#define DEFAULT_BAUD		UART16550_BAUD_115200
+#define DEFAULT_BAUD		UART16550_BAUD_9600
+#endif
+#ifndef DEFAULT_PARITY
+#define DEFAULT_PARITY		UART16550_PARITY_NONE
+#endif
+#ifndef DEFAULT_DATA
+#define DEFAULT_DATA		UART16550_DATA_8BIT
+#endif
+#ifndef DEFAULT_STOP
+#define DEFAULT_STOP		UART16550_STOP_1BIT
+#endif
+
+/* === END OF CONFIG === */
+
+typedef         unsigned char uint8;
+typedef         unsigned int  uint32;
+
+#define         UART16550_BAUD_2400             2400
+#define         UART16550_BAUD_4800             4800
+#define         UART16550_BAUD_9600             9600
+#define         UART16550_BAUD_19200            19200
+#define         UART16550_BAUD_38400            38400
+#define         UART16550_BAUD_57600            57600
+#define         UART16550_BAUD_115200           115200
+
+#define         UART16550_PARITY_NONE           0
+#define         UART16550_PARITY_ODD            0x08
+#define         UART16550_PARITY_EVEN           0x18
+#define         UART16550_PARITY_MARK           0x28
+#define         UART16550_PARITY_SPACE          0x38
+
+#define         UART16550_DATA_5BIT             0x0
+#define         UART16550_DATA_6BIT             0x1
+#define         UART16550_DATA_7BIT             0x2
+#define         UART16550_DATA_8BIT             0x3
+
+#define         UART16550_STOP_1BIT             0x0
+#define         UART16550_STOP_2BIT             0x4
+
+/* register offset */
+#define		OFS_RCV_BUFFER		(0*REG_OFFSET)
+#define		OFS_TRANS_HOLD		(0*REG_OFFSET)
+#define		OFS_SEND_BUFFER		(0*REG_OFFSET)
+#define		OFS_INTR_ENABLE		(1*REG_OFFSET)
+#define		OFS_INTR_ID		(2*REG_OFFSET)
+#define		OFS_DATA_FORMAT		(3*REG_OFFSET)
+#define		OFS_LINE_CONTROL	(3*REG_OFFSET)
+#define		OFS_MODEM_CONTROL	(4*REG_OFFSET)
+#define		OFS_RS232_OUTPUT	(4*REG_OFFSET)
+#define		OFS_LINE_STATUS		(5*REG_OFFSET)
+#define		OFS_MODEM_STATUS	(6*REG_OFFSET)
+#define		OFS_RS232_INPUT		(6*REG_OFFSET)
+#define		OFS_SCRATCH_PAD		(7*REG_OFFSET)
+
+#define		OFS_DIVISOR_LSB		(0*REG_OFFSET)
+#define		OFS_DIVISOR_MSB		(1*REG_OFFSET)
+
+#define		UART16550_READ(y)    (*((volatile uint8*)(BASE + y)))
+#define		UART16550_WRITE(y, z)  ((*((volatile uint8*)(BASE + y))) = z)
+
+static void Uart16550Init(uint32 baud, uint8 data, uint8 parity, uint8 stop)
+{
+	/* disable interrupts */
+	UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
+	UART16550_WRITE(OFS_INTR_ENABLE, 0);
+
+	/* set up baud rate */
+	{
+		uint32 divisor;
+
+		/* set DIAB bit */
+		UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
+
+		/* set divisor */
+		divisor = MAX_BAUD / baud;
+		UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
+		UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00)>>8);
+
+		/* clear DIAB bit */
+		UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
+	}
+
+	/* set data format */
+	UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
+}
+
+
+void
+putc_init(void)
+{
+#if INIT_SERIAL_PORT
+	Uart16550Init(DEFAULT_BAUD, DEFAULT_DATA, DEFAULT_PARITY, DEFAULT_STOP);
+#endif
+}
+
+void
+putc(unsigned char c)
+{
+	while ((UART16550_READ(OFS_LINE_STATUS) &0x20) == 0);
+	UART16550_WRITE(OFS_SEND_BUFFER, c);
+}
+
+#if 0
+unsigned char
+getc(void)
+{
+	while((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
+	return UART16550_READ(OFS_RCV_BUFFER);
+}
+
+int
+tstc(void)
+{
+	return((UART16550_READ(OFS_LINE_STATUS) & 0x01) != 0);
+}
+#endif
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/zImage.lds idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/zImage.lds
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/zImage.lds	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/zImage.lds	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,31 @@
+OUTPUT_ARCH(mips)
+ENTRY(zstartup)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = 0x88000000;
+  .init          : { *(.init)		} =0
+  .text      :
+  {
+    _ftext = . ;
+    *(.text)
+    *(.rodata)
+    *(.rodata1)
+   . = ALIGN(4096);
+    input_data = .;
+    arch/mips/idt-boards/rc32300/EB365/boot/piggy.o
+    input_data_end = .;
+   . = ALIGN(4096);
+    *(.gnu.warning)
+  } =0
+
+  .reginfo : { *(.reginfo) }
+
+   . = 0x800A0000;
+  __bss_start = .;
+  .bss       :
+  {
+   *(.bss)
+  _end = . ;
+  }
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/idtIRQ.S idtlinux/arch/mips/idt-boards/rc32300/EB365/idtIRQ.S
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/idtIRQ.S	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/idtIRQ.S	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,66 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Intterrupt dispatcher code for IDT boards
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+				
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
+
+	.text
+	.set	noreorder
+	.set	noat
+	.align	5
+	NESTED(rc32300_IRQ, PT_SIZE, sp)
+	SAVE_ALL
+	CLI
+
+	.set	at
+	.set	noreorder
+
+	mfc0    t0, CP0_CAUSE
+	move	a1, sp
+								  
+	/* check for r4k counter/timer IRQ. */
+	
+	andi    t1, t0, CAUSEF_IP7
+	beqz    t1, 1f
+	nop
+
+	jal     idt_timer_interrupt
+	li	a0, 7
+	j	ret_from_irq
+	nop
+1:
+	jal	rc32300_irqdispatch
+	move	a0, t0
+	j	ret_from_irq
+	nop
+
+	END(rc32300_IRQ)
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/irq.c idtlinux/arch/mips/idt-boards/rc32300/EB365/irq.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/irq.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/irq.c	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,284 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Interrupt routines for IDT EB365 boards
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/delay.h>
+
+#include <asm/bitops.h>
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+
+#include <asm/idt-boards/rc32300/rc32300.h>
+#include <asm/idt-boards/rc32300/rc32365_gpio.h>
+
+#undef DEBUG_IRQ
+#ifdef DEBUG_IRQ
+/* note: prints function name for you */
+#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
+#else
+#define DPRINTK(fmt, args...)
+#endif
+
+extern asmlinkage void rc32300_IRQ(void);
+
+static unsigned int startup_irq(unsigned int irq);
+static void end_irq(unsigned int irq_nr);
+static void mask_and_ack_irq(unsigned int irq_nr);
+static void rc32365_enable_irq(unsigned int irq_nr);
+static void rc32365_disable_irq(unsigned int irq_nr);
+
+extern void __init init_generic_irq(void);
+
+typedef struct {
+	u32 mask; 
+	volatile u32 *base_addr;
+} intr_group_t;
+
+static const intr_group_t intr_group[NUM_INTR_GROUPS] = {
+	{ 0x00000fff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET) },
+	{ 0x000001ff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET) },
+	{ 0x00000003, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET) },
+	{ 0x00000fff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET) },
+	{ 0x0000ffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET) }
+};
+
+#define READ_PEND(base) (*(base))
+#define READ_MASK(base) (*(base + 2))
+#define WRITE_MASK(base, val) (*(base + 2) = (val))
+
+static inline int irq_to_group(unsigned int irq_nr)
+{
+	return ((irq_nr - GROUP0_IRQ_BASE) >> 5);
+}
+
+static inline int group_to_ip(unsigned int group)
+{
+	return group + 2;
+}
+
+static inline void enable_local_irq(unsigned int ip)
+{
+	int ipnum = 0x100 << ip;
+	clear_c0_cause(ipnum);
+	set_c0_status(ipnum);
+}
+
+static inline void disable_local_irq(unsigned int ip)
+{
+	int ipnum = 0x100 << ip;
+	clear_c0_status(ipnum);
+}
+
+static inline void ack_local_irq(unsigned int ip)
+{
+	int ipnum = 0x100 << ip;
+	unsigned long flags;
+	
+	local_irq_save(flags);
+	
+	clear_c0_cause(ipnum);
+	
+	local_irq_restore(flags);
+}
+static void rc32365_enable_irq(unsigned int irq_nr)
+{
+	unsigned long flags;
+	int           ip = irq_nr - GROUP0_IRQ_BASE;
+	unsigned int  group, intr_bit;
+	volatile unsigned int  *addr;
+	
+	local_irq_save(flags);
+	
+	if (ip < 0)
+		enable_local_irq(irq_nr);
+	else {
+		group = ip >> 5;
+		
+		ip -= (group << 5);
+		intr_bit = 1 << ip;
+    
+		enable_local_irq(group_to_ip(group));
+    
+		addr = intr_group[group].base_addr;
+		WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
+	}
+
+	local_irq_restore(flags);
+}
+
+static void rc32365_disable_irq(unsigned int irq_nr)
+{
+	unsigned long flags;
+	int           ip = irq_nr - GROUP0_IRQ_BASE;
+	unsigned int  group, intr_bit, mask;
+	volatile unsigned int  *addr;
+
+	local_irq_save(flags);
+  
+	if (ip < 0)
+		disable_local_irq(irq_nr);
+	else {
+		group = ip >> 5;
+
+		ip -= group << 5;
+		intr_bit = 1 << ip;
+    
+		addr = intr_group[group].base_addr;
+		
+		mask = READ_MASK(addr);
+		mask |= intr_bit;
+		WRITE_MASK(addr, mask);
+    
+		if (mask == intr_group[group].mask)
+			disable_local_irq(group_to_ip(group));
+	}
+  
+	local_irq_restore(flags);
+}
+
+static unsigned int startup_irq(unsigned int irq_nr)
+{
+	rc32365_enable_irq(irq_nr);
+	return 0; 
+}
+
+static void shutdown_irq(unsigned int irq_nr)
+{
+	rc32365_disable_irq(irq_nr);
+	return;
+}
+
+static void mask_and_ack_irq(unsigned int irq_nr)
+{
+	rc32365_disable_irq(irq_nr);
+	ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
+}
+
+static void end_irq(unsigned int irq_nr)
+{
+	int ip = irq_nr - GROUP0_IRQ_BASE;
+	unsigned int intr_bit, group;
+	volatile unsigned int *addr;
+
+	unsigned long flags;
+
+	local_irq_save(flags);
+
+	if (!(irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
+		if (ip < 0)
+			enable_local_irq(irq_nr);
+		else {
+			if (irq_nr >= RC32365_PCI_INTA_IRQ && irq_nr <= RC32365_PCI_INTD_IRQ)
+				gpio->gpioistat = 0x0000f0ff;
+      
+			group = ip >> 5;
+
+			ip -= (group << 5);
+			intr_bit = 1 << ip;
+
+			
+			enable_local_irq(group_to_ip(group));
+  
+			addr = intr_group[group].base_addr;
+			WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
+		}
+	} 
+	else {
+		printk("warning: end_irq %d did not enable (%x)\n", 
+		       irq_nr, irq_desc[irq_nr].status);
+	}
+
+	local_irq_restore(flags);
+}
+
+static struct hw_interrupt_type rc32365_irq_type = {
+	"RC32365",
+	startup_irq,
+	shutdown_irq,
+	rc32365_enable_irq,
+	rc32365_disable_irq,
+	mask_and_ack_irq,
+	end_irq,
+	NULL
+};
+
+
+void __init arch_init_irq(void)
+{
+	int i;
+
+	printk("Initializing IRQ's: %d of %d\n", RC32365_NR_IRQS,NR_IRQS);  
+	memset(irq_desc, 0, sizeof(irq_desc));
+	set_except_vector(0, rc32300_IRQ);
+  
+	for (i = 0; i < RC32365_NR_IRQS; i++) {
+		irq_desc[i].status = IRQ_DISABLED;
+		irq_desc[i].action = NULL;
+		irq_desc[i].depth = 1;
+		irq_desc[i].handler = &rc32365_irq_type;
+		spin_lock_init(&irq_desc[i].lock);
+	}
+}
+
+/* Main Interrupt dispatcher */
+void rc32300_irqdispatch(unsigned long cp0_cause, struct pt_regs *regs)
+{
+	unsigned int ip, pend, group;
+	volatile unsigned int *addr;
+
+	if ((ip = (cp0_cause & 0x7c00))) {
+		group = 21 - rc32300_clz(ip);
+		
+		addr = intr_group[group].base_addr;
+
+		pend = READ_PEND(addr);
+		pend &= ~READ_MASK(addr); 
+		pend = 39 - rc32300_clz(pend);
+		do_IRQ((group << 5) + pend, regs);
+		return;
+	} 
+	else
+		return;
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/Makefile idtlinux/arch/mips/idt-boards/rc32300/EB365/Makefile
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/Makefile	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/Makefile	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,42 @@
+###############################################################################
+#
+#  BRIEF MODULE DESCRIPTION
+#     Makefile for IDT EB365 board BSP
+#
+#  Copyright 2006 IDT Inc. (rischelp@idt.com)
+#
+#  This program is free software; you can redistribute  it and/or modify it
+#  under  the terms of  the GNU General  Public License as published by the
+#  Free Software Foundation;  either version 2 of the  License, or (at your
+#  option) any later version.
+#
+#  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+#  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+#   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+#   NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+#   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+#   NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+#   USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+#   ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+#   THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#   You should have received a copy of the  GNU General Public License along
+#   with this program; if not, write  to the Free Software Foundation, Inc.,
+#   675 Mass Ave, Cambridge, MA 02139, USA.
+# 
+#  
+# 
+###############################################################################
+
+.S.s:
+	$(CPP) $(CFLAGS) $< -o $*.s
+.S.o:
+	$(CC) $(CFLAGS) -c $< -o $*.o
+
+obj-y	 := irq.o setup.o idtIRQ.o reset.o prom.o time.o
+obj-$(CONFIG_KGDB)			+= serial_gdb.o
+obj-$(CONFIG_SERIAL_8250)		+= serial.o
+subdir-$(CONFIG_IDT_BOOT_NVRAM)		+= nvram
+obj-$(CONFIG_IDT_BOOT_NVRAM)		+= nvram/built-in.o
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/nvram/Makefile idtlinux/arch/mips/idt-boards/rc32300/EB365/nvram/Makefile
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/nvram/Makefile	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/nvram/Makefile	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,44 @@
+###############################################################################
+#
+#  BRIEF MODULE DESCRIPTION
+#     Makefile for IDT EB365 nvram access routines
+#
+#  Copyright 2006 IDT Inc. (rischelp@idt.com)
+#
+#  This program is free software; you can redistribute  it and/or modify it
+#  under  the terms of  the GNU General  Public License as published by the
+#  Free Software Foundation;  either version 2 of the  License, or (at your
+#  option) any later version.
+#
+#  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+#  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+#   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+#   NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+#   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+#   NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+#   USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+#   ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+#   THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#   You should have received a copy of the  GNU General Public License along
+#   with this program; if not, write  to the Free Software Foundation, Inc.,
+#   675 Mass Ave, Cambridge, MA 02139, USA.
+# 
+#  
+# 
+###############################################################################
+
+.S.s:   
+	$(CPP) $(CFLAGS) $< -o $*.s
+.S.o:   
+	$(CC) $(CFLAGS) -c $< -o $*.o
+
+obj-y   := nvram365.o 
+
+
+
+
+
+
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/nvram/nvram365.c idtlinux/arch/mips/idt-boards/rc32300/EB365/nvram/nvram365.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/nvram/nvram365.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/nvram/nvram365.c	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,342 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     nvram interface routines.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include "nvram365.h"
+
+void setenv (char *e, char *v, int rewrite);
+char *getenv (char *e);
+void unsetenv (char *e);
+void purgeenv(void);
+char *getenv (char *s);
+void mapenv (int (*func)(char *, char *));
+
+static void nvram_initenv(void);
+
+static unsigned char
+nvram_getbyte(int offs)
+{
+  return(*((unsigned char*)(NVRAM_BASE + offs)));
+}
+
+static void
+nvram_setbyte(int offs, unsigned char val)
+{
+  unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
+
+  *nvramDataPointer = val;
+}
+
+static unsigned short
+nvram_getshort(int offs)
+{
+  return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
+}
+
+static void
+nvram_setshort(int offs, unsigned short val)
+{
+  nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
+  nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
+}
+/*
+ * calculate NVRAM checksum
+ */
+static unsigned short
+nvram_calcsum(void)
+{
+  unsigned short sum = NV_MAGIC;
+  int     i;
+
+  for (i = ENV_BASE; i < ENV_TOP; i += 2)
+    sum += nvram_getshort(i);
+  return(sum);
+}
+
+/*
+ * update the nvram checksum
+ */
+static void
+nvram_updatesum (void)
+{
+  nvram_setshort(NVOFF_CSUM, nvram_calcsum());
+}
+
+/*
+ * test validity of nvram by checksumming it
+ */
+static int
+nvram_isvalid(void)
+{
+  static  unsigned int is_valid;
+
+  if (is_valid)
+    return(1);
+
+  if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC)
+    nvram_initenv();
+  is_valid = 1;
+  return(1);
+}
+
+/* return nvram address of environment string */
+static int
+nvram_matchenv(char *s)
+{
+  int envsize, envp, n, i, varsize;
+  char *var;
+
+  envsize = nvram_getshort(NVOFF_ENVSIZE);
+  if (envsize > ENV_AVAIL)
+    return(0);     /* sanity */
+    
+  envp = ENV_BASE;
+
+  if ((n = strlen (s)) > 255)
+    return(0);
+    
+  while (envsize > 0) {
+    varsize = nvram_getbyte(envp);
+    if (varsize == 0 || (envp + varsize) > ENV_TOP)
+      return(0);   /* sanity */
+    for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
+      char c1 = nvram_getbyte(i);
+      char c2 = *var;
+      if (islower(c1))
+        c1 = toupper(c1);
+      if (islower(c2))
+        c2 = toupper(c2);
+      if (c1 != c2)
+        break;
+    }
+    if (i > envp + n) {       /* match so far */
+      if (n == varsize - 1)   /* match on boolean */
+        return(envp);
+      if (nvram_getbyte(i) == '=')  /* exact match on variable */
+        return(envp);
+    }
+    envsize -= varsize;
+    envp += varsize;
+  }
+  return(0);
+}
+
+static void nvram_initenv(void)
+{
+  nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
+  nvram_setshort(NVOFF_ENVSIZE, 0);
+
+  nvram_updatesum();
+}
+
+static void
+nvram_delenv(char *s)
+{
+  int nenvp, envp, envsize, nbytes;
+
+  envp = nvram_matchenv(s);
+  if (envp == 0)
+    return;
+
+  nenvp = envp + nvram_getbyte(envp);
+  envsize = nvram_getshort(NVOFF_ENVSIZE);
+  nbytes = envsize - (nenvp - ENV_BASE);
+  nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
+  while (nbytes--) {
+    nvram_setbyte(envp, nvram_getbyte(nenvp));
+    envp++;
+    nenvp++;
+  }
+  nvram_updatesum();
+}
+
+static int
+nvram_setenv(char *s, char *v)
+{
+  int ns, nv, total;
+  int envp;
+
+  if (!nvram_isvalid())
+    return(-1);
+
+  nvram_delenv(s);
+  ns = strlen(s);
+  if (ns == 0)
+    return(0);
+  if (v && *v) {
+    nv = strlen(v);
+    total = ns + nv + 2;
+  }
+  else {
+    nv = 0;
+    total = ns + 1;
+  }
+  if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
+    return(0);
+
+  envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
+
+  nvram_setbyte(envp, (unsigned char) total); 
+  envp++;
+
+  while (ns--) {
+    nvram_setbyte(envp, *s); 
+    envp++; 
+    s++;
+  }
+
+  if (nv) {
+    nvram_setbyte(envp, '='); 
+    envp++;
+    while (nv--) {
+      nvram_setbyte(envp, *v); 
+      envp++; 
+      v++;
+    }
+  }
+  nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
+  nvram_updatesum();
+  return(0);
+}
+
+static char *
+nvram_getenv(char *s)
+{
+  static char buf[256];   /* FIXME: this cannot be static */
+  int envp, ns, nbytes, i;
+
+  if (!nvram_isvalid())
+    return((char *)0);
+
+  envp = nvram_matchenv(s);
+  if (envp == 0)
+    return((char *)0);
+  ns = strlen(s);
+  if (nvram_getbyte(envp) == ns + 1)  /* boolean */
+    buf[0] = '\0';
+  else {
+    nbytes = nvram_getbyte(envp) - (ns + 2);
+    envp += ns + 2;
+    for (i = 0; i < nbytes; i++)
+      buf[i] = nvram_getbyte(envp++);
+    buf[i] = '\0';
+  }
+  return(buf);
+}
+
+static void
+nvram_unsetenv(char *s)
+{
+  if (!nvram_isvalid())
+    return;
+
+  nvram_delenv(s);
+}
+/*
+ * apply func to each string in environment
+ */
+static void
+nvram_mapenv(int (*func)(char *, char *))
+{
+  int envsize, envp, n, i, seeneql;
+  char name[256], value[256];
+  char c, *s;
+
+  if (!nvram_isvalid())
+    return;
+
+  envsize = nvram_getshort(NVOFF_ENVSIZE);
+  envp = ENV_BASE;
+
+  while (envsize > 0) {
+    value[0] = '\0';
+    seeneql = 0;
+    s = name;
+    n = nvram_getbyte(envp);
+    for (i = envp + 1; i < envp + n; i++) {
+      c = nvram_getbyte(i);
+      if ((c == '=') && !seeneql) {
+        *s = '\0';
+        s = value;
+        seeneql = 1;
+        continue;
+      }
+      *s++ = c;
+    }
+    *s = '\0';
+    (*func)(name, value);
+    envsize -= n;
+    envp += n;
+  }
+}
+/*
+ * Wrappers to allow 'special' environment variables to get processed
+ */
+void
+setenv(char *e, char *v, int rewrite)
+{
+  if (nvram_getenv(e) && !rewrite)
+    return;
+    
+  nvram_setenv(e, v);
+}
+
+char *
+getenv(char *e)
+{
+  return(nvram_getenv(e));
+}
+
+void
+unsetenv(char *e)
+{
+  nvram_unsetenv(e);
+}
+
+void
+purgeenv(void)
+{
+  int i;
+  unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
+  
+  for (i = ENV_BASE; i < ENV_TOP; i++)
+    *nvramDataPointer++ = 0;
+  
+  nvram_initenv();
+}
+
+void
+mapenv(int (*func)(char *, char *))
+{
+  nvram_mapenv(func);
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/nvram/nvram365.h idtlinux/arch/mips/idt-boards/rc32300/EB365/nvram/nvram365.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/nvram/nvram365.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/nvram/nvram365.h	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,60 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     nvram layout definitions
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#define NVRAM_BASE      0xAC800000
+#define TD_NVRAM_SIZE   0x2000
+
+/*
+ * defining ALGCOMPAT provides backward compatibility
+ * with Algorithmics derived PROM monitors
+ */
+#define NVOFFSET        0   /* use all of NVRAM */
+
+/* Offsets to reserved locations */
+              /* size description */
+#define NVOFF_MAGIC     (NVOFFSET + 0)  /* 2 magic value */
+#define NVOFF_CSUM      (NVOFFSET + 2)  /* 2 NVRAM environment checksum */
+#define NVOFF_ENVSIZE   (NVOFFSET + 4)  /* 2 size of 'environment' */
+#define NVOFF_TEST      (NVOFFSET + 5)  /* 1 cold start test byte */
+#define NVOFF_ETHADDR   (NVOFFSET + 6)  /* 6 decoded ethernet address */
+#define NVOFF_UNUSED    (NVOFFSET + 12) /* 0 current end of table */
+
+#define NV_MAGIC        0xdeaf          /* nvram magic number */
+#define NV_RESERVED     32               /* number of reserved bytes */
+
+#undef  NVOFF_ETHADDR
+#define NVOFF_ETHADDR   (NVOFFSET + NV_RESERVED - 6)
+
+/* number of bytes available for environment */
+#define ENV_BASE        (NVOFFSET + NV_RESERVED)
+#define ENV_TOP         TD_NVRAM_SIZE
+#define ENV_AVAIL       (ENV_TOP - ENV_BASE)
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/prom.c idtlinux/arch/mips/idt-boards/rc32300/EB365/prom.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/prom.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/prom.c	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,117 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     prom interface routines
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/console.h>
+#include <asm/bootinfo.h>
+#include <linux/bootmem.h>
+#include <linux/ioport.h>
+#include <linux/serial.h>
+#include <linux/serialP.h>
+#include <asm/serial.h>
+#include <linux/ioport.h>
+
+#include <asm/idt-boards/rc32300/rc32300.h>
+
+extern void setup_serial_port(void);
+unsigned int idt_cpu_freq = CONFIG_IDT_BOARD_FREQ;
+
+EXPORT_SYMBOL(idt_cpu_freq);
+
+#ifdef CONFIG_IDT_BOOT_NVRAM
+extern void mapenv(int (*func)(char *, char *));
+static int make_bootparm(char *name,char *val)
+{ 
+	if (strncmp(name, "bootparm", 8) == 0) {
+		strcat(arcs_cmdline," ");
+		strcat(arcs_cmdline,val);
+	}
+	else if(strncmp(name, "HZ", 2) == 0) {
+		idt_cpu_freq = simple_strtoul(val, 0, 10);
+		printk("CPU Clock at %d Hz (from HZ environment variable)\n",
+		       idt_cpu_freq);
+	}
+	return 0;
+}
+
+static void prom_init_cmdline(void)
+{ 
+	mapenv(&make_bootparm);
+}
+
+#else
+/* Kernel Boot parameters */
+//static unsigned char bootparm[]="ip=157.165.29.36:157.165.29.18::255.255.0.0::eth0";
+static unsigned char bootparm[]="console=ttyS0,9600";
+#endif
+
+extern unsigned long mips_machgroup;
+extern unsigned long mips_machtype;
+
+const char *get_system_type(void)
+{
+	return "IDT 79EB365";
+}
+
+struct resource rc32300_res_ram = {
+	"RAM",
+	0,
+	RAM_SIZE,
+	IORESOURCE_MEM
+};
+
+char * __init prom_getcmdline(void)
+{
+	return &(arcs_cmdline[0]);
+}
+
+void __init prom_init(void)
+{
+#ifdef CONFIG_IDT_BOOT_NVRAM
+	prom_init_cmdline();
+#endif
+
+	setup_serial_port();
+	mips_machgroup = MACH_GROUP_IDT;
+	mips_machtype = MACH_IDT_EB365;
+	add_memory_region(0,rc32300_res_ram.end - rc32300_res_ram.start,BOOT_MEM_RAM);
+  
+}
+
+unsigned long __init prom_free_prom_memory(void)
+{
+	return 0;
+}
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/reset.c idtlinux/arch/mips/idt-boards/rc32300/EB365/reset.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/reset.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/reset.c	2006-03-09 16:25:47.000000000 -0800
@@ -0,0 +1,67 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Reset EB365 board.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/processor.h>
+#include <asm/reboot.h>
+#include <asm/system.h>
+
+#include <asm/idt-boards/rc32300/rc32300.h>
+#include <asm/idt-boards/rc32300/rc32365.h>
+extern void (*flush_cache_all)(void);
+
+void rc32300_restart(char *command)
+{
+	set_c0_status((ST0_BEV | ST0_ERL));
+	set_c0_config(CONF_CM_UNCACHED);
+	flush_cache_all();
+	write_c0_wired(0);
+
+	rc32300_writel(0x80000001, RESET_CNTL);
+}
+
+void rc32300_halt(void)
+{
+	printk(KERN_NOTICE "\n** You can safely turn off the power\n");
+	while (1)
+		__asm__(".set\tmips3\n\t"
+	                "wait\n\t"
+			".set\tmips0");
+}
+
+void rc32300_power_off(void)
+{
+	rc32300_halt();
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/serial.c idtlinux/arch/mips/idt-boards/rc32300/EB365/serial.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/serial.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/serial.c	2006-03-09 16:25:47.000000000 -0800
@@ -0,0 +1,74 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Serial port initialisation.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+
+#include <asm/time.h>
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/serial.h>
+
+
+#include <asm/idt-boards/rc32300/rc32300.h>
+
+extern int __init early_serial_setup(struct uart_port *port);
+
+extern unsigned int idt_cpu_freq;
+
+extern int __init setup_serial_port(void)
+{ 
+	static struct uart_port serial_req[2];
+
+	memset(serial_req, 0, sizeof(serial_req));
+	serial_req[0].type       = PORT_16550A;
+	serial_req[0].line       = 0;
+	serial_req[0].irq        = RC32300_UART0_IRQ;
+	serial_req[0].flags      = STD_COM_FLAGS;
+	serial_req[0].uartclk    = idt_cpu_freq;
+	serial_req[0].iotype     = SERIAL_IO_MEM;
+	serial_req[0].membase    = (char *) KSEG1ADDR(RC32300_UART0_BASE);
+	serial_req[0].mapbase   = KSEG1ADDR(RC32300_UART0_BASE);
+	serial_req[0].regshift   = 2;
+	
+	early_serial_setup(&serial_req[0]);
+	
+	return 0;
+}
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/serial_gdb.c idtlinux/arch/mips/idt-boards/rc32300/EB365/serial_gdb.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/serial_gdb.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/serial_gdb.c	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,236 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *      EB365 specific polling driver for 16550 UART.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/serial_reg.h>
+
+/* set remote gdb baud rate at 115200 */
+
+#define GDB_BAUD 115200
+#define CONS_BAUD 9600
+
+extern unsigned int idt_cpu_freq;
+
+
+/* turn this on to watch the debug protocol echoed on the console port */
+#define DEBUG_REMOTE_DEBUG
+
+#ifdef __MIPSEB__
+#define CONS_PORT 0xb8050003u
+#define GDB_PORT  0xb8050003u
+#else
+#define CONS_PORT 0xb8050000u
+#define GDB_PORT  0xb8050000u
+#endif
+           
+volatile unsigned char *ports[2] = {
+	(volatile unsigned char *)CONS_PORT,
+	(volatile unsigned char *)GDB_PORT
+};
+
+
+void reset_gdb_port(void);
+void cons_putc(char c);
+int port_getc(int port);
+void port_putc(int port, char c);
+
+int cons_getc(void)
+{
+	return port_getc(0);
+}
+
+void cons_putc(char c)
+{
+	port_putc(0, c);
+}
+
+void cons_puts(char *s)
+{
+	while(*s) {
+		if(*s == '\n') cons_putc('\r');
+		cons_putc(*s);
+		s++;
+	}
+}
+
+void cons_do_putn(int n)
+{
+	if(n) {
+		cons_do_putn(n / 10);
+		cons_putc(n % 10 + '0');
+	}
+}
+
+void cons_putn(int n)
+{
+	if(n < 0) {
+		cons_putc('-');
+		n = -n;
+	}
+
+	if (n == 0) {
+		cons_putc('0');
+	} else {
+		cons_do_putn(n);
+	}
+}
+
+static int first = 1;
+
+int getDebugChar(void)
+{
+	int c;
+
+	if(first) reset_gdb_port();
+
+	c = port_getc(1);
+
+	return c;
+}
+
+int port_getc(int p)
+{
+	volatile unsigned char *port = ports[p];
+	int c;
+
+	while((*(port + UART_LSR * 4) & UART_LSR_DR) == 0) {
+		continue;
+	}       	
+
+	c = *(port + UART_RX * 4);
+
+	return c;
+}
+
+int port_getc_ready(int p)
+{
+	volatile unsigned char *port = ports[p];
+
+	return *(port + UART_LSR * 4) & UART_LSR_DR;
+}
+
+int isDebugReady(void)
+{
+	return port_getc_ready(1);
+}
+
+void putDebugChar(char c)
+{
+	if(first) reset_gdb_port();
+
+	port_putc(1, c);
+}
+
+#define OK_TO_XMT (UART_LSR_TEMT | UART_LSR_THRE)
+
+void port_putc(int p, char c)
+{
+	volatile unsigned char *port = ports[p];
+	volatile unsigned char *lsr = port + UART_LSR * 4;
+
+	while((*lsr & OK_TO_XMT) != OK_TO_XMT) {
+		continue;
+	}
+
+	*(port + UART_TX * 4) = c;
+}
+
+void reset_gdb_port(void)
+{
+	volatile unsigned char *port = ports[1];
+	unsigned int DIVISOR = (idt_cpu_freq / 16 / GDB_BAUD);
+
+	first = 0;
+
+#ifdef DEBUG_REMOTE_DEBUG
+	cons_puts("\n");
+	cons_puts("reset_gdb_port: initializing remote debug serial port (internal UART 0, baud=");
+	cons_putn(GDB_BAUD);
+	cons_puts(", MHz=");
+	cons_putn(idt_cpu_freq);
+	cons_puts(", divisor=");
+	cons_putn(DIVISOR);
+	cons_puts(")\n");
+#endif
+
+	/* wait for pending transfer to finish */
+	while((*(port + UART_LSR * 4) & OK_TO_XMT) != OK_TO_XMT);
+
+	/* reset the port */
+	*(port + UART_CSR * 4) = 0;
+
+	/* clear and enable the FIFOs */
+	*(port + UART_FCR * 4) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | 
+		UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;
+
+	/* set the baud rate */
+	*(port + UART_LCR * 4) = UART_LCR_DLAB;		/* enable DLL, DLM registers */
+	*(port + UART_DLL * 4) = DIVISOR;
+	*(port + UART_DLM * 4) = DIVISOR >> 8;
+
+	/* set the line control stuff and disable DLL, DLM regs */
+
+	*(port + UART_LCR * 4) = UART_LCR_STOP | 	/* 2 stop bits */
+		UART_LCR_WLEN8;				/* 8 bit word length */
+	
+	/* leave interrupts off */
+	*(port + UART_IER * 4) = 0;
+
+	/* the modem controls don't leave the chip on this port, so leave them alone */
+	*(port + UART_MCR * 4) = 0;
+}
+
+void reset_cons_port(void)
+{
+	volatile unsigned char *port = ports[0];
+	unsigned int DIVISOR = (idt_cpu_freq / 16 / CONS_BAUD);
+
+	/* reset the port */
+	*(port + UART_CSR * 4) = 0;
+
+	/* clear and enable the FIFOs */
+	*(port + UART_FCR * 4) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | 
+		UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;
+
+	/* set the baud rate */
+	*(port + UART_LCR * 4) = UART_LCR_DLAB;		/* enable DLL, DLM registers */
+
+	*(port + UART_DLL * 4) = DIVISOR;
+	*(port + UART_DLM * 4) = DIVISOR >> 8;
+	/* set the line control stuff and disable DLL, DLM regs */
+
+	*(port + UART_LCR * 4) = UART_LCR_STOP | 	/* 2 stop bits */
+		UART_LCR_WLEN8;				/* 8 bit word length */
+	
+	/* leave interrupts off */
+	*(port + UART_IER * 4) = 0;
+
+	/* the modem controls don't leave the chip on this port, so leave them alone */
+	*(port + UART_MCR * 4) = 0;
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/setup.c idtlinux/arch/mips/idt-boards/rc32300/EB365/setup.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/setup.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/setup.c	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,157 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     setup routines for IDT EB365 boards
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/pm.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+
+#include <linux/config.h>
+#include <linux/eisa.h>
+#include <linux/hdreg.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/mc146818rtc.h>
+#include <linux/console.h>
+#include <linux/fb.h>
+#include <linux/tty.h>
+
+#include <asm/reboot.h>
+
+#include <asm/idt-boards/rc32300/rc32300.h>
+
+extern void (*board_time_init)(void);
+extern void (*board_timer_setup)(struct irqaction *irq);
+extern void rc32300_time_init(void);
+extern void rc32300_timer_setup(struct irqaction *irq);
+extern char * __init prom_getcmdline(void);
+
+extern void rc32300_restart(char *);
+extern void rc32300_halt(void);
+extern void rc32300_power_off(void);
+
+unsigned int cedar_za;
+
+#define DIG0 ((volatile unsigned char *)0xAC000003)
+#define DIG1 ((volatile unsigned char *)0xAC000002)
+#define DIG2 ((volatile unsigned char *)0xAC000001)
+#define DIG3 ((volatile unsigned char *)0xAC000000)
+
+void idt_disp_char(int i, char c)
+{
+	switch (i) {
+	case 0: *DIG0 = c; break;
+	case 1: *DIG1 = c; break;
+	case 2: *DIG2 = c; break;
+	case 3: *DIG3 = c; break;
+	default: *DIG0 = '?'; break;
+	}
+}
+
+void idt_disp_str(char *s)
+{
+	int i;
+  
+	if (s == 0) {
+		idt_disp_char(0, 0x20);
+		idt_disp_char(1, 0x20);
+		idt_disp_char(2, 0x20);
+		idt_disp_char(3, 0x20);
+	} 
+	else {
+		for (i = 0; i < 4; i++) {
+			if (s[i]) 
+				idt_disp_char(i, s[i]);
+		}
+	}
+}
+
+static int __init idt_setup(void)
+{
+	char* argptr;
+	idt_disp_str("Unix");
+	
+	argptr = prom_getcmdline();
+
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+	if ((argptr = strstr(argptr, "console=")) == NULL) {
+	  argptr = prom_getcmdline();
+	  strcat(argptr, " console=ttyS0,9600");
+	}
+#endif
+
+	board_time_init = rc32300_time_init;
+	board_timer_setup = rc32300_timer_setup;
+
+	_machine_restart = rc32300_restart;
+	_machine_halt = rc32300_halt;
+	pm_power_off = rc32300_power_off;
+
+	set_io_port_base(KSEG1);
+
+	write_c0_wired(0);
+
+	/* Disable Watchdog timer */
+	rc32300_writel(0, 0xb802803c);
+
+	/* Revision ZA? */
+	cedar_za = (rc32300_readl(0xb8000018) & 0xff) ? 0 : 1;
+
+	if (cedar_za)
+		idt_disp_str("ZA  ");
+	else
+		idt_disp_str("  ZB");
+
+	
+	return 0;
+}
+
+//early_initcall(idt_setup);
+void __init plat_setup(void){
+  idt_setup();
+}
+
+int page_is_ram(unsigned long pagenr)
+{
+  return 1;
+}
+
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/time.c idtlinux/arch/mips/idt-boards/rc32300/EB365/time.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/time.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/EB365/time.c	2006-03-09 16:25:48.000000000 -0800
@@ -0,0 +1,140 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     timer routines for IDT EB365 boards
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ * 
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/mc146818rtc.h>
+#include <linux/irq.h>
+#include <linux/timex.h>
+
+#include <linux/param.h>
+#include <asm/mipsregs.h>
+#include <asm/ptrace.h>
+#include <asm/time.h>
+#include <asm/hardirq.h>
+
+#include <asm/mipsregs.h>
+#include <asm/ptrace.h>
+#include <asm/debug.h>
+#include <asm/time.h>
+
+#include <asm/idt-boards/rc32300/rc32300.h>
+
+static unsigned long r4k_offset; /* Amount to incr compare reg each time */
+static unsigned long r4k_cur;    /* What counter should be at next timer irq */
+
+extern unsigned int idt_cpu_freq;
+#if defined(CONFIG_MIPS_RTC)
+extern void rtc_ds1553_init(void);
+#endif
+
+/* 
+ * Figure out the r4k offset, the amount to increment the compare
+ * register for each time tick. There is no RTC available.
+ *
+ * The RC32300 counts at half the CPU *core* speed.
+ */
+static unsigned long __init cal_r4koff(void)
+{
+	mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
+	return (mips_hpt_frequency / HZ);
+}
+
+
+void __init rc32300_time_init(void)
+{
+	unsigned int est_freq, flags;
+	
+	local_irq_save(flags);
+	
+	printk("calculating r4koff... ");
+	r4k_offset = cal_r4koff();
+	printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
+  
+	est_freq = 2*r4k_offset*HZ;	
+	est_freq += 5000;    /* round */
+	est_freq -= est_freq%10000;
+	printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, 
+	       (est_freq%1000000)*100/1000000);
+	local_irq_restore(flags);
+  
+#if defined(CONFIG_MIPS_RTC)
+	rtc_ds1553_init();
+#endif
+
+}
+
+
+void __init rc32300_timer_setup(struct irqaction *irq)
+{
+	setup_irq(MIPS_CPU_TIMER_IRQ, irq);
+  
+  /* to generate the first timer interrupt */
+	r4k_cur = (read_c0_count() + r4k_offset);
+	write_c0_compare(r4k_cur);
+}
+
+static inline void ack_r4ktimer(unsigned long newval)
+{
+	write_c0_compare(newval);
+}
+
+extern void idt_disp_char(int i,char c);
+
+asmlinkage void idt_timer_interrupt(int irq,struct pt_regs *regs)
+{ 
+#ifdef CONFIG_KGDB
+	void kgdb_check(void);
+#endif
+
+	static unsigned int timerCount = 0;
+	static int toggle = 0;
+	
+	irq_enter();
+	kstat_this_cpu.irqs[irq]++;
+	
+	if( (timerCount++ % HZ) == 0)
+	{ 
+		toggle ^= 1;
+		idt_disp_char(0,toggle ? 'u' :'U');
+	}
+	
+	timer_interrupt(irq, NULL, regs);
+	irq_exit();
+
+#ifdef CONFIG_KGDB
+	kgdb_check();
+#endif
+}
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/csu_idt.S idtlinux/arch/mips/idt-boards/rc32300/S334/boot/csu_idt.S
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/csu_idt.S	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/csu_idt.S	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,412 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Board initialization code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/threads.h>
+
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/asm-offsets.h>
+#include <asm/cachectl.h>
+
+#include "iregdef.h"
+#include "idtcpu.h"
+#include "idthdr.h"
+
+#define MHZ CONFIG_IDT_BOARD_FREQ
+
+#include "s364.h"
+
+#if defined (S334A)
+#include "s334aram.h"
+#elif defined (S334)
+#include "s334ram.h"
+#endif	
+
+#define IndexInvalidate_I       0x00
+
+/*--------------------------------------------------------------
+** prom entry point table
+*-------------------------------------------------------------*/
+FRAME(start,sp,0,ra)
+	j idtstart
+
+idtstart:
+	.set	noreorder
+
+#if defined(CPU_R32364)
+	li	t0,PORT_WIDTH_CONTROL
+	li	t1,PORT_SETUP
+	sw	t1,0x0(t0)
+	li	t0,BTA_CONTROL
+	li	t1,BTA_SETUP
+	sw	t1,0x0(t0)
+	li	t0,SYS_BTA_CTRL
+	sw	t1,0x0(t0)
+#if MHZ > 50000000
+	li      t0,SYS_ALT_CTRL
+        li      t1,SYS_ALT_SETUP
+        sw      t1,0x0(t0)
+#endif
+        li      v0,0x00
+	or	v0,(SR_CU0|SR_BEV|SR_DE)
+#endif
+	mtc0	v0,C0_SR		# state unknown on reset
+	mtc0	zero,C0_CAUSE		# clear software interrupts
+
+#ifdef S334
+	/* initialize the PIO Direction for UART RC32334/2*/
+#define PIO_BASE_ADDR     0xb8000600
+#define PIO_DC_SET        0x00500050
+#define PIO_DC_MASK       0xff0fff0f
+
+	li      t0,PIO_BASE_ADDR
+	lw      t1,0x4(t0)
+	nop
+	li      t2,PIO_DC_MASK          #mask the UART bits
+	and     t1,t1,t2
+	nop
+	li      t2,PIO_DC_SET           #rx0=rx1=input, tx0=tx1=output
+	or      t1,t1,t2
+	nop
+	sw      t1,0x4(t0)
+
+	/*  disable the PCI bus error */
+        lui     t1,0xb800
+	ori     t1,t1,0x10
+	nop
+	lw      t0,0x0(t1)
+	nop
+	nop
+	ori     t0,t0,0x80
+	nop
+	sw      t0,0x0(t1)
+	nop
+	nop
+	nop
+#endif
+
+#if defined(CPU_R4000) || defined(CPU_R32364)
+	mfc0	v1,C0_CONFIG
+	/* Set cache mode: write-back */
+	li	v0, CFG_C_NCHRNT_WB  /* CFG_C_NCHRNT_WB CFG_C_NCHRNT_WT_NWA CFG_C_UNCACHED */
+	and	v1,~(0x7)
+	or	v1,v1,v0
+	mtc0	v1,C0_CONFIG
+	nop
+	nop
+	li	t0,MEM_BASE_BASE	/* load 2 base address registers' base */
+
+	li	t1,MBA_REG0		/* load into  memory base address register 0 */
+	sw	t1,0x0(t0)		/* set the memory base address register for Chip Select 0 - EPROM */
+
+	li	t1,MBM_REG0		/* load into  memory base mask register 0 */
+	sw	t1,0x4(t0)		/* set the memory base mask register for Chip Select 0 - EPROM */
+
+
+	li	t0,MEM_CTL_BASE		/* load all control registers' base address */
+
+	li      t1,MCR_CS0_BS           /* load  memory control register chip select 0 bit settings */
+	sw	t1,0x0(t0)		/* set the control register for Chip Select 0 - EPROM */
+
+	nop
+
+	li	t1,MCR_CS1_BS		/* load into upper half memory control register chip select 1 bit settings */
+	sw	t1,0x4(t0)		/* set the control register for Chip Select 1 - SRAM */
+	nop
+#ifdef S334
+	li      t1,MCR_CS2_BS           /* initialize CHIP-SELECT2 */
+        sw      t1,0x08(t0)
+	nop
+
+	li      t1,MCR_CS3_BS           /* initialize CHIP-SELECT3 */
+        sw      t1,0x0C(t0)
+	nop
+
+	li      t1,MCR_CS4_BS           /* initialize CHIP-SELECT4 for LED */
+	sw      t1,0x10(t0)
+	nop
+
+#endif
+	li	t1,MCR_CS5_BS		/* load into upper half memory control register chip select 5 bit settings */
+	sw	t1,0x14(t0)		/* set the control register for Chip Select 5 - External UART */
+	nop
+
+/*------------ load all R32 internal registers' base address ----------*/
+	li	t0,R32134_IREG_BASE	/* load t0 with all R32134 internal registers' base address */
+
+/* ------------------- Disable WatchDog Timer --------------------------------- */
+	li	t1,DISABLE_TIMER
+	sw	t1,0x730(t0)
+
+#if MEMCFG == SDRAM_ONLY || MEMCFG == SRAM_N_SDRAM || MEMCFG == SDRAM_N_SRAM
+/*--------------- disable EDO Controller ---------------------------*/
+	li	t1,0			/* EDO_CR_BS load EDO control register bit settings in t1 */
+	sw	t1,0x310(t0)		/* Disable  EDO control register */
+
+#elif MEMCFG == EDO_ONLY || MEMCFG == SRAM_N_EDO || MEMCFG == EDO_N_SRAM
+/*------------------------- disable SDRAM Controller --------------------------*/
+	li	t1,0
+	sw	t1,0x300(t0)
+#endif /* MEMCFG == EDO_ONLY || MEMCFG == SRAM_N_EDO || MEMCFG == EDO_N_SRAM */
+
+#if MEMCFG != SRAM_ONLY
+/*-------------- Initialize SDRAM or EDO Base and Mask Registers ----------*/
+
+	li	t1,DRAM_BNK0_BASE	/* load DRAM bank 0 physical address in t1 */
+	sw	t1,0xC0(t0)		/* set DRAM bank 0 base */
+	li	t1,DRAM_BNK1_BASE	/* load DRAM bank 1 physical address in t1 */
+	sw	t1,0xC8(t0)		/* set DRAM bank 1 base */
+	li	t1,DRAM_BNK2_BASE	/* load DRAM bank 2 physical address in t1 */
+	sw	t1,0xD0(t0)		/* set DRAM bank 2 base */
+	li	t1,DRAM_BNK3_BASE	/* load DRAM bank 3 physical address in t1 */
+	sw	t1,0xD8(t0)		/* set DRAM bank 3 base */
+
+	li	t1,DRAM_BNK0_MASK	/* load DRAM bank 0 size in t1 */
+	sw	t1,0xC4(t0)		/* set DRAM bank 0 mask */
+	li	t1,DRAM_BNK1_MASK	/* load DRAM bank 1 size in t1 */
+	sw	t1,0xCC(t0)		/* set DRAM bank 1 mask */
+	li	t1,DRAM_BNK2_MASK	/* load DRAM bank 2 size in t1 */
+	sw	t1,0xD4(t0)		/* set DRAM bank 2 mask */
+	li	t1,DRAM_BNK3_MASK	/* load DRAM bank 3 size in t1 */
+	sw	t1,0xDC(t0)		/* set DRAM bank 3 mask */
+
+#if  MEMCFG == SRAM_N_SDRAM || MEMCFG == SRAM_N_EDO || MEMCFG == SDRAM_N_SRAM || MEMCFG == EDO_N_SRAM
+/* ------------------------------- Setup SRAM if in place -----------------------------------------*/
+	li	t0,MEM_BASE_BASE	/* load 2 base address registers' base */
+	li	t1,MBA_REG1		/* load into memory base address register 1 */
+	sw	t1,0x8(t0)		/* set the memory base address register for Chip Select 1 - SRAM */
+
+	li	t1,MBM_REG1		/* load into memory base mask register 1 */
+	sw	t1,0xC(t0)		/* set the memory base mask register for Chip Select 1 - SRAM */
+#endif /*  MEMCFG == SRAM_N_SDRAM || MEMCFG == SRAM_N_EDO || MEMCFG == SDRAM_N_SRAM || MEMCFG == EDO_N_SRAM*/
+
+#if MEMCFG == EDO_ONLY || MEMCFG == SRAM_N_EDO || MEMCFG == EDO_N_SRAM
+/*-------------- Set EDO control register --------------------------*/
+	li	t1,EDO_CR_BS		/* load EDO control register bit settings in t1 */
+	sw	t1,0x310(t0)		/* set EDO control register */
+#endif /* MEMCFG == EDO_ONLY || MEMCFG == SRAM_N_EDO || MEMCFG == EDO_N_SRAM */
+
+/*-------------- Setup and Enable Refresh Timer --------------------*/
+	li	t0,TIMER_BASE		/* load timer register set base */
+
+	li	t1,DISABLE_TIMER	/* load diable timer bit settings into t1 */
+	sw	t1,0x60(t0)		/* disable timer */
+        nop
+
+#if MEMCFG == SDRAM_ONLY || MEMCFG == SRAM_N_SDRAM || MEMCFG == SDRAM_N_SRAM
+/*-------------- Enable SDRAM Controller ---------------------------*/
+	li	t0,R32134_IREG_BASE
+	li	t1,SDRAM_CR_BS
+	sw	t1,0x300(t0)
+        nop
+/*-------------- Delay Loop ----------------------------------------*/
+	li	v0,10000	/* 8x256us */
+1:	bne	v0,zero,1b
+	subu	v0,1		/* BDSLOT  */
+	nop
+	nop
+/*-------------- Setup Precharge Command ---------------------------*/
+	li	t2,2
+	li	t3,0
+1:	li	t1,SDRAM_PC_VAL
+	sw	t1,0x300(t0)
+	nop
+	nop
+	lw	t7,0x300(t0)
+	nop
+	li	t4,APATTERN
+#ifdef S334
+#if DRAMSZ != MB32SO
+	li	t5,0xA0000000 | DRAM_BNK0_BASE
+#else
+#ifdef S334A
+	li	t5,0xA0000000 | DRAM_BNK0_BASE
+#else
+	li	t5,0xA0000000 | DRAM_BNK3_BASE
+#endif
+#endif
+#else
+	li	t5,0xA0000000 | DRAM_BNK0_BASE
+#endif
+	sw	t4,0x0(t5)
+	addu	t3,1
+	bne	t3,t2,1b
+	nop
+#ifdef S334
+/*-------------- Setup Refresh Command -----------------------------*/
+	li	t2,8
+	li	t3,0
+1:	li	t1,SDRAM_RFRSH_CMD
+	sw	t1,0x300(t0)
+	sw	t4,0x0(t5)	/* note: t5 not disturbed */
+	addu	t3,1
+	bne	t3,t2,1b
+	nop
+#endif
+/*-------------- Setup up to write to Mode Register ----------------*/
+	li	t1,SDRAM_MODE_REG
+	sw	t1,0x300(t0)
+#ifdef S1254
+	addu	t5,0xC0		/* CAS Latency of 3 */
+#else
+	addu	t5,0x80
+#endif
+	sw	t4,0x0(t5)
+#ifdef S334
+	ori     t1,t1,0xff
+	sw      t1,0x300(t0)
+
+/* Set Secondary SDRAM Control register based on revision */
+	lw      t1,0x18(t0)     /* get SysID */
+  	andi    t1,0xf0		/* BD slot */
+  	beqz    t1,2f           /* skip if Z part */
+  	li      t3,0x10
+  	beq     t1,t3,1f      	/* Y part? */
+  	li      t2,0x2        	/* BD slot */
+  	ori     t2,0x200       	/* Add tWR for X part */
+1:
+  	sw      t2, 0x304(t0)   /* set secondary SDRAM control register */
+        nop
+2:
+#endif
+#endif /* MEMCFG == SDRAM_ONLY || MEMCFG == SRAM_N_SDRAM || MEMCFG == SDRAM_N_SRAM */
+
+/*-------------- Setup and Enable Refresh Timer --------------------*/
+
+	li	t0,TIMER_BASE		/* load timer register set base */
+
+	li	t1,0			/* load DRAM refresh timer count register bit settings in t1 */
+	sw	t1,0x64(t0)		/* set DRAM refresh timer count register bit settings */
+
+	li	t1,DRAM_RF_CMPR_BS	/* load DRAM refresh timer compare register bit settings in t1 */
+	sw	t1,0x68(t0)		/* set DRAM refresh timer compare register bit settings */
+
+	li	t1,CPU_BERR_BS
+	sw	t1,0x48(t0)
+	li	t1,IP_BERR_BS
+	sw	t1,0x58(t0)
+
+	li	t1,ENABLE_TIMER		/* load timer enable bit */
+	sw	t1,0x60(t0)		/* enable refresh timer */
+#ifdef S334
+	/* the memory system may need  some time to start up... */
+	li	v0,10000	/* 8x256us */
+1:	bne	v0,zero,1b
+	subu	v0,1		/* BDSLOT  */
+	nop
+	nop
+
+	li	t1,DRAM_RF_CMPR_SE_BS	/* load refresh timer compare value for slower expiration */
+	sw	t1,0x68(t0)		/* set compare register again */
+#else
+#if MEMCFG == EDO_ONLY || MEMCFG == EDO_N_SRAM || MEMCFG == SRAM_N_EDO
+	/* the memory system may need up to 120us to start up... */
+	li	v0,128		/* ~256us */
+1:	bne	v0,zero,1b
+	subu	v0,1		/* BDSLOT  */
+	nop
+	nop
+
+	li	t1,DRAM_RF_CMPR_SE_BS	/* load refresh timer compare value for slower expiration */
+	sw	t1,0x68(t0)		/* set compare register again */
+#endif /* MEMCFG == EDO_ONLY || MEMCFG == EDO_N_SRAM || MEMCFG == SRAM_N_EDO */
+#endif
+
+#endif /* MEMCFG != SRAM_ONLY */
+#if MEMCFG == SRAM_ONLY
+/* ------------------------------- Setup SRAM if in place -----------------------------------------*/
+
+/*
+** write some thing else in DRAM BANK 0 BASE address first since it has 0 by default.
+*/
+	li	t1,0x01000000	/* load DRAM bank 0 physical address in t1 */
+	sw	t1,0xC0(t0)		/* set DRAM bank 0 base */
+
+	li	t0,MEM_BASE_BASE	/* load 2 base address registers' base */
+	li	t1,MBA_REG1		/* load into memory base address register 1 */
+	sw	t1,0x8(t0)		/* set the memory base address register for Chip Select 1 - SRAM */
+
+	li	t1,MBM_REG1		/* load into memory base mask register 1 */
+	sw	t1,0xC(t0)		/* set the memory base mask register for Chip Select 1 - SRAM */
+#endif /* MEMCFG == SRAM_ONLY */
+
+
+#endif /* (CPU_R4000) || defined(CPU_R32364) */
+
+#if defined(S364)
+
+/*
+** before doing anything
+** initialize the section of memory used by cache initialization
+** whenever you boot out of ROM or reset-vector
+** This assumed to be 1MB.
+** --Sugan (11-22-96)
+*/
+	li	t0, 0xa0000000
+	li	t1, 0xa0100000
+1:
+        sw      zero,0x00(t0)
+        sw      zero,0x04(t0)
+        sw      zero,0x08(t0)
+        sw      zero,0x0c(t0)
+	addiu	t0,16		# DO NOT put this instruction in the
+                                # delay slot of "blt t0,t1,1b" since it
+                                # will run over the 1M boundary for 16 byte
+	                        # more which would cause problem if we have
+	                        # exactly 1M memory available on board.
+	nop
+	blt	t0,t1,1b
+        nop
+	nop
+	nop
+3:
+	mfc0	t0,C0_SR
+	nop
+	nop
+	and	t0,~SR_BEV
+	mtc0	t0,C0_SR
+	nop
+	nop
+4:
+#endif
+
+	li	v0,100000		/* large delay */
+1:	subu	v0,1			/* BDSLOT  */
+	bne	v0,zero,1b
+	nop
+	nop
+
+       la      k0, zstartup
+       j      k0
+       nop
+       nop
+
+ENDFRAME(start)
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/head.S idtlinux/arch/mips/idt-boards/rc32300/S334/boot/head.S
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/head.S	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/head.S	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,134 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Board initialisation code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/threads.h>
+
+#include <asm/asm.h>
+#include <asm/cacheops.h>
+#include <asm/mipsregs.h>
+#include <asm/asm-offsets.h>
+#include <asm/cachectl.h>
+#include <asm/regdef.h>
+
+#define IndexInvalidate_I       0x00
+
+	.set noreorder
+	.cprestore
+	LEAF(zstartup)
+zstartup:
+
+        la      sp, .stack
+	move	s0, a0
+	move	s1, a1
+	move	s2, a2
+	move	s3, a3
+
+	/* Clear BSS */
+	la	a0, .stack
+	la	a2, _end
+1:	sw	zero, 0(a0)
+	bne	a2, a0, 1b
+	addu	a0, 4
+#if 1
+	/* flush the I-Cache */
+	li	k0, 0x80000000  # start address
+	li	k1, 0x80002000  # end address (8KB I-Cache)
+	subu	k1, 128
+2:
+	.set mips3
+	cache	IndexInvalidate_I, 0(k0)
+	cache	IndexInvalidate_I, 16(k0)
+	cache	IndexInvalidate_I, 32(k0)
+	cache	IndexInvalidate_I, 48(k0)
+	cache	IndexInvalidate_I, 64(k0)
+	cache	IndexInvalidate_I, 80(k0)
+	cache	IndexInvalidate_I, 96(k0)
+	cache	IndexInvalidate_I, 112(k0)
+	.set mips0
+
+	bne	k0, k1, 2b
+	addu	k0, k0, 128
+	/* done */
+#endif
+#if 1
+	/* flush the D-Cache */
+	li	k0, 0x80000000  # start address
+	li	k1, 0x80000400  # end address (2KB I-Cache)
+	subu	k1, 128
+3:	
+	.set mips3
+	/* First way */
+	cache	Index_Writeback_Inv_D, 0(k0)
+	cache	Index_Writeback_Inv_D, 16(k0)
+	cache	Index_Writeback_Inv_D, 32(k0)
+	cache	Index_Writeback_Inv_D, 48(k0)
+	cache	Index_Writeback_Inv_D, 64(k0)
+	cache	Index_Writeback_Inv_D, 80(k0)
+	cache	Index_Writeback_Inv_D, 96(k0)
+	cache	Index_Writeback_Inv_D, 112(k0)
+	/* Second way */
+	cache	Index_Writeback_Inv_D, 1024(k0)
+	cache	Index_Writeback_Inv_D, 1040(k0)
+	cache	Index_Writeback_Inv_D, 1056(k0)
+	cache	Index_Writeback_Inv_D, 1072(k0)
+	cache	Index_Writeback_Inv_D, 1088(k0)
+	cache	Index_Writeback_Inv_D, 1104(k0)
+	cache	Index_Writeback_Inv_D, 1120(k0)
+	cache	Index_Writeback_Inv_D, 1136(k0)
+	.set mips0
+
+	bne	k0, k1, 3b
+	addu	k0, k0, 128
+	/* done */
+#endif
+	
+
+	la	ra, 4f
+	la	k0, decompress_kernel
+	jr	k0
+	nop
+4:
+
+	move	a0, s0
+	move	a1, s1
+	move	a2, s2
+	move	a3, s3
+	li	k0, KERNEL_ENTRY
+	jr	k0
+	nop
+5:
+	b 5b
+	END(zstartup)
+
+	.bss
+	.fill 0x2000
+	EXPORT(.stack)
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/idtcpu.h idtlinux/arch/mips/idt-boards/rc32300/S334/boot/idtcpu.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/idtcpu.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/idtcpu.h	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,614 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   IDT CPU register definitions. Though the registers are already defined
+ *   under asm directory, they are once again declared here for the ease of
+ *   syncing up with IDT bootloader code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#if defined(__IDTCPU_H__)
+#else
+#define __IDTCPU_H__
+
+
+/*
+** memory configuration and mapping
+*/
+#define K0BASE	0x80000000
+#define K0SIZE	0x20000000
+#define K1BASE	0xa0000000
+#define K1SIZE	0x20000000
+#define K2BASE	0xc0000000
+#if defined(S364)
+#define K2SIZE	0x3e000000
+#define ICEBASE	0xff000000
+#define ICESIZE	0x01000000
+#else
+#define K2SIZE	0x20000000
+#endif
+#if defined(CPU_R4000)
+#define KSBASE	0xe0000000
+#define KSSIZE	0x20000000
+#endif
+
+#define KUBASE	0
+#define KUSIZE	0x80000000
+
+/*
+** Exception Vectors
+*/
+#if defined(CPU_R3000)
+#define	UT_VEC	K0BASE			/* utlbmiss vector */
+#define E_VEC	(K0BASE+0x80)		/* exception vevtor */
+#endif
+#if defined(CPU_R4000) || defined S364  /*(CPU_R32364)      */
+#define	T_VEC	(K0BASE+0x000)		/* tlbmiss vector */
+#define X_VEC	(K0BASE+0x080)		/* xtlbmiss vector */
+#define C_VEC	(K1BASE+0x100)		/* cache error vector */
+#define E_VEC	(K0BASE+0x180)		/* exception vector */
+#define I_VEC	(K0BASE+0X200)		/* interrupt vector */
+#endif
+#define	R_VEC	(K1BASE+0x1fc00000)	/* reset vector */
+
+/*
+** Address conversion macros
+*/
+#ifdef CLANGUAGE
+#define	CAST(as) (as)
+#else
+#define	CAST(as)
+#endif
+#define	K0_TO_K1(x)	(CAST(unsigned)(x)|0xA0000000)	/* kseg0 to kseg1 */
+#define	K1_TO_K0(x)	(CAST(unsigned)(x)&0x9FFFFFFF)	/* kseg1 to kseg0 */
+#define	K0_TO_PHYS(x)	(CAST(unsigned)(x)&0x1FFFFFFF)	/* kseg0 to physical */
+#define	K1_TO_PHYS(x)	(CAST(unsigned)(x)&0x1FFFFFFF)	/* kseg1 to physical */
+#define	PHYS_TO_K0(x)	(CAST(unsigned)(x)|0x80000000)	/* physical to kseg0 */
+#define	PHYS_TO_K1(x)	(CAST(unsigned)(x)|0xA0000000)	/* physical to kseg1 */
+
+/*
+**	Cache size constants
+*/
+/* Sugan changed so that MINCACHE is 0x200 instead of 0x800 */
+#define	MINCACHE	0x200		/* 512 bytes  */
+#define	MAXCACHE	0x40000		/* 256*1024   256k */	
+
+#if defined CPU_R32364                  /* Includes RC32364, RC32332, RC32334 */
+#define	CFG_ICE		0x80000000	/* ICE detect */
+#define	CFG_ECMASK	0x70000000	/* System Clock Ratio */
+#define	CFG_ECBY2	0x00000000 	/* divide by 2 */
+#define	CFG_ECBY3	0x10000000 	/* divide by 3 */
+#define	CFG_ECBY4	0x20000000 	/* divide by 4 */
+#define	CFG_NBL		0x00800000	/* Non-Blocking load pending */
+#define	CFG_BE		0x00008000	/* Big Endian */
+#define	CFG_ICMASK	0x00000e00	/* Instruction cache size */
+#define	CFG_ICSHIFT	9
+#define	CFG_DCMASK	0x000001c0	/* Data cache size */
+#define	CFG_DCSHIFT	6
+#define	CFG_IB		0x00000020	/* Instruction cache line size */
+#define	CFG_DB		0x00000010	/* Data cache line size */
+#define	CFG_K0MASK	0x00000007	/* KSEG0 coherency algorithm */
+
+/*
+ * R32364 primary cache mode
+ */
+#define CFG_C_NCHRNT_WT_NWA	0
+#define CFG_C_NCHRNT_WT		1
+#define CFG_C_UNCACHED		2
+#define CFG_C_NCHRNT_WB		3
+
+/* Cache Operations */
+#define Index_Invalidate_I               0x0         /* 0       0 */
+#define Index_Writeback_Inv_D            0x1         /* 0       1 */
+#define Index_Invalidate_SI              0x2         /* 0       2 */
+#define Index_Writeback_Inv_SD           0x3         /* 0       3 */
+#define Index_Load_Tag_I                 0x4         /* 1       0 */
+#define Index_Load_Tag_D                 0x5         /* 1       1 */
+#define Index_Load_Tag_SI                0x6         /* 1       2 */
+#define Index_Load_Tag_SD                0x7         /* 1       3 */
+#define Index_Store_Tag_I                0x8         /* 2       0 */
+#define Index_Store_Tag_D                0x9         /* 2       1 */
+#define Index_Store_Tag_SI               0xA         /* 2       2 */
+#define Index_Store_Tag_SD               0xB         /* 2       3 */
+#define Create_Dirty_Exc_D               0xD         /* 3       1 */
+#define Create_Dirty_Exc_SD              0xF         /* 3       3 */
+#define Hit_Invalidate_I                 0x10        /* 4       0 */
+#define Hit_Invalidate_D                 0x11        /* 4       1 */
+#define Hit_Invalidate_SI                0x12        /* 4       2 */
+#define Hit_Invalidate_SD                0x13        /* 4       3 */
+#define Hit_Writeback_Inv_D              0x15        /* 5       1 */
+#define Hit_Writeback_Inv_SD             0x17        /* 5       3 */
+#define Fill_I                           0x14        /* 5       0 */
+#define Hit_Writeback_D                  0x19        /* 6       1 */
+#define Hit_Writeback_SD                 0x1B        /* 6       3 */
+#define Hit_Writeback_I                  0x18        /* 6       0 */
+#define Hit_Set_Virtual_SI               0x1E        /* 7       2 */
+#define Hit_Set_Virtual_SD               0x1F        /* 7       3 */
+#define CFG_EW32        0x00040000      /* 32 bit */
+#endif /* CPU_R32364 */
+
+#if defined(CPU_R4000)
+/* R4000 configuration register definitions */
+#define CFG_CM		0x80000000	/* Master-Checker mode */
+#define CFG_ECMASK	0x70000000	/* System Clock Ratio */
+#define CFG_ECBY2	0x00000000 	/* divide by 2 */
+#define CFG_ECBY3	0x10000000 	/* divide by 3 */
+#define CFG_ECBY4	0x20000000 	/* divide by 4 */
+#define CFG_EPMASK	0x0f000000	/* Transmit data pattern */
+#define CFG_EPD		0x00000000	/* D */
+#define CFG_EPDDX	0x01000000	/* DDX */
+#define CFG_EPDDXX	0x02000000	/* DDXX */
+#define CFG_EPDXDX	0x03000000	/* DXDX */
+#define CFG_EPDDXXX	0x04000000	/* DDXXX */
+#define CFG_EPDDXXXX	0x05000000	/* DDXXXX */
+#define CFG_EPDXXDXX	0x06000000	/* DXXDXX */
+#define CFG_EPDDXXXXX	0x07000000	/* DDXXXXX */
+#define CFG_EPDXXXDXXX	0x08000000	/* DXXXDXXX */
+#define CFG_SBMASK	0x00c00000	/* Secondary cache block size */
+#define CFG_SBSHIFT	22
+#define CFG_SB4		0x00000000	/* 4 words */
+#define CFG_SB8		0x00400000	/* 8 words */
+#define CFG_SB16	0x00800000	/* 16 words */
+#define CFG_SB32	0x00c00000	/* 32 words */
+#define CFG_SS		0x00200000	/* Split secondary cache */
+#define CFG_SW		0x00100000	/* Secondary cache port width */
+#define CFG_EWMASK	0x000c0000	/* System port width */
+#define CFG_EWSHIFT	18
+#define CFG_EW64	0x00000000	/* 64 bit */
+#define CFG_EW32	0x00040000	/* 32 bit */
+/* #if defined(CPU_R5000) */
+/* Sugan added for R5000 L2 cache 07-17-96 */
+#define L2_PAGESIZE	0x1000
+#define SIZE256K	0x00040000 /* 256KB in Hex */
+#define CFG_HARDL2	0x00020000 /* Hardware bit that enables/disables
+				      L2 cache */
+#define CFG_SE		0x1000
+#define CFG_SIZE512K	0x00000000 /* size of Scache is 512k */
+#define CFG_SIZE1MB 	0x00100000 /* size of Scache is 1MB */
+#define CFG_SIZE2MB 	0x00200000 /* size of Scache is 2MB */
+#define CFG_SIZEMASK	0x00300000 /* size mask */
+/* #endif */
+#define CFG_SC		0x00020000	/* Secondary cache absent */
+#define CFG_SM		0x00010000	/* Dirty Shared mode disabled */
+#define CFG_BE		0x00008000	/* Big Endian */
+#define CFG_EM		0x00004000	/* ECC mode enable */
+#define CFG_EB		0x00002000	/* Block ordering */
+#define CFG_ICMASK	0x00000e00	/* Instruction cache size */
+#define CFG_ICSHIFT	9
+#define CFG_DCMASK	0x000001c0	/* Data cache size */
+#define CFG_DCSHIFT	6
+#define CFG_IB		0x00000020	/* Instruction cache block size */
+#define CFG_DB		0x00000010	/* Data cache block size */
+#define CFG_CU		0x00000008	/* Update on Store Conditional */
+#define CFG_K0MASK	0x00000007	/* KSEG0 coherency algorithm */
+
+/*
+ * R4000 primary cache mode
+ */
+#define CFG_C_WRITETHROUGH_CACHE		0
+#define CFG_C_UNCACHED		2
+#define CFG_C_NONCOHERENT	3
+#define CFG_C_COHERENTXCL	4
+#define CFG_C_COHERENTXCLW	5
+#define CFG_C_COHERENTUPD	6
+
+/*
+ * R4000 cache operations (should be in assembler...?)
+ */
+#if defined(CPU_R5000)
+#define InvAllScache			 0x03	     /* 0	3 */
+#define IndexLoadTagScache		 0x07	     /* 1	3 */
+#define IndexStoreTagScache		 0x0b	     /* 2	3 */
+#define PageInvScache			 0x17	     /* 5	3 */
+#endif
+#define Index_Invalidate_I               0x0         /* 0       0 */
+#define Index_Writeback_Inv_D            0x1         /* 0       1 */
+#define Index_Invalidate_SI              0x2         /* 0       2 */
+#define Index_Writeback_Inv_SD           0x3         /* 0       3 */
+#define Index_Load_Tag_I                 0x4         /* 1       0 */
+#define Index_Load_Tag_D                 0x5         /* 1       1 */
+#define Index_Load_Tag_SI                0x6         /* 1       2 */
+#define Index_Load_Tag_SD                0x7         /* 1       3 */
+#define Index_Store_Tag_I                0x8         /* 2       0 */
+#define Index_Store_Tag_D                0x9         /* 2       1 */
+#define Index_Store_Tag_SI               0xA         /* 2       2 */
+#define Index_Store_Tag_SD               0xB         /* 2       3 */
+#define Create_Dirty_Exc_D               0xD         /* 3       1 */
+#define Create_Dirty_Exc_SD              0xF         /* 3       3 */
+#define Hit_Invalidate_I                 0x10        /* 4       0 */
+#define Hit_Invalidate_D                 0x11        /* 4       1 */
+#define Hit_Invalidate_SI                0x12        /* 4       2 */
+#define Hit_Invalidate_SD                0x13        /* 4       3 */
+#define Hit_Writeback_Inv_D              0x15        /* 5       1 */
+#define Hit_Writeback_Inv_SD             0x17        /* 5       3 */
+#define Fill_I                           0x14        /* 5       0 */
+#define Hit_Writeback_D                  0x19        /* 6       1 */
+#define Hit_Writeback_SD                 0x1B        /* 6       3 */
+#define Hit_Writeback_I                  0x18        /* 6       0 */
+#define Hit_Set_Virtual_SI               0x1E        /* 7       2 */
+#define Hit_Set_Virtual_SD               0x1F        /* 7       3 */
+
+#endif
+
+/*
+** TLB resource defines
+*/
+
+#if defined(CPU_R32364)  
+#define	N_TLB_ENTRIES	16
+#endif 
+
+#if defined(CPU_R4000)
+#define N_TLB_ENTRIES  48
+#endif
+
+#if defined (CPU_R32364)
+#define	TLBHI_VPN2MASK	0xffffe000
+#define	TLBHI_PIDMASK	0x000000ff
+#define	TLBHI_NPID	256
+
+#define	TLBLO_PFNMASK	0x03ffffc0
+#define	TLBLO_PFNSHIFT	6
+#define	TLBLO_D		0x00000004	/* writeable */
+#define	TLBLO_V		0x00000002	/* valid bit */
+#define	TLBLO_G		0x00000001	/* global access bit */
+#define	TLBLO_CMASK	0x00000038	/* cache algorithm mask */
+#define	TLBLO_CSHIFT	3
+
+#define	TLBLO_UNCACHED		(CFG_C_UNCACHED<<TLBLO_CSHIFT)
+#define	TLBLO_NCHRNT_WT_NWA	(CFG_C_NCHRNT_WT_NWA<<TLBLO_CSHIFT)
+#define	TLBLO_NCHRNT_WT		(CFG_C_NCHRNT_WT<<TLBLO_CSHIFT)
+#define	TLBLO_NCHRNT_WB		(CFG_C_NCHRNT_WB<<TLBLO_CSHIFT)
+
+#elif defined(CPU_R4000)
+#define	TLBHI_VPN2MASK	0xffffe000
+#define	TLBHI_PIDMASK	0x000000ff
+#define	TLBHI_NPID	256
+
+#define	TLBLO_PFNMASK	0x3fffffc0
+#define	TLBLO_PFNSHIFT	6
+#define	TLBLO_D		0x00000004	/* writeable */
+#define	TLBLO_V		0x00000002	/* valid bit */
+#define	TLBLO_G		0x00000001	/* global access bit */
+#define	TLBLO_CMASK	0x00000038	/* cache algorithm mask */
+#define	TLBLO_CSHIFT	3
+
+#define	TLBLO_UNCACHED		(CFG_C_UNCACHED<<TLBLO_CSHIFT)
+#define	TLBLO_NONCOHERENT	(CFG_C_NONCOHERENT<<TLBLO_CSHIFT)
+#define	TLBLO_COHERENTXCL	(CFG_C_COHERENTXCL<<TLBLO_CSHIFT)
+#define	TLBLO_COHERENTXCLW	(CFG_C_COHERENTXCLW<<TLBLO_CSHIFT)
+#define	TLBLO_COHERENTUPD	(CFG_C_COHERENTUPD<<TLBLO_CSHIFT)
+#endif
+#if defined(CPU_R4000)||defined(S364)
+#define	TLBINX_PROBE	0x80000000
+#define	TLBINX_INXMASK	0x0000003f
+
+#define	TLBRAND_RANDMASK	0x0000003f
+
+#define	TLBCTXT_BASEMASK	0xff800000
+#define	TLBCTXT_BASESHIFT	23
+
+#define	TLBCTXT_VPN2MASK	0x007ffff0
+#define	TLBCTXT_VPN2SHIFT	4
+
+#define	TLBPGMASK_MASK		0x01ffe000
+#endif
+
+#define	SR_PE		0x00100000	/* cache parity error */
+#if defined(CPU_R3000)
+#define	SR_CUMASK	0xf0000000	/* coproc usable bits */
+#define	SR_CU3		0x80000000	/* Coprocessor 3 usable */
+#define	SR_CU2		0x40000000	/* Coprocessor 2 usable */
+#define	SR_CU1		0x20000000	/* Coprocessor 1 usable */
+#define	SR_CU0		0x10000000	/* Coprocessor 0 usable */
+
+#define	SR_BEV		0x00400000	/* use boot exception vectors */
+
+/* Cache control bits */
+#define	SR_TS		0x00200000	/* TLB shutdown */
+#define	SR_CM		0x00080000	/* cache miss */
+#define	SR_PZ		0x00040000	/* cache parity zero */
+#define	SR_SWC		0x00020000	/* swap cache */
+#define	SR_ISC		0x00010000	/* Isolate data cache */
+
+/*
+**	status register interrupt masks and bits
+*/
+
+#define	SR_IMASK	0x0000ff00	/* Interrupt mask */
+#define	SR_IMASK8	0x00000000	/* mask level 8 */
+#define	SR_IMASK7	0x00008000	/* mask level 7 */
+#define	SR_IMASK6	0x0000c000	/* mask level 6 */
+#define	SR_IMASK5	0x0000e000	/* mask level 5 */
+#define	SR_IMASK4	0x0000f000	/* mask level 4 */
+#define	SR_IMASK3	0x0000f800	/* mask level 3 */
+#define	SR_IMASK2	0x0000fc00	/* mask level 2 */
+#define	SR_IMASK1	0x0000fe00	/* mask level 1 */
+#define	SR_IMASK0	0x0000ff00	/* mask level 0 */
+
+#define	SR_IMASKSHIFT	8
+
+#define	SR_IBIT8	0x00008000	/* bit level 8 */
+#define	SR_IBIT7	0x00004000	/* bit level 7 */
+#define	SR_IBIT6	0x00002000	/* bit level 6 */
+#define	SR_IBIT5	0x00001000	/* bit level 5 */
+#define	SR_IBIT4	0x00000800	/* bit level 4 */
+#define	SR_IBIT3	0x00000400	/* bit level 3 */
+#define	SR_IBIT2	0x00000200	/* bit level 2 */
+#define	SR_IBIT1	0x00000100	/* bit level 1 */
+
+#define	SR_KUO		0x00000020	/* old kernel/user, 0 => k, 1 => u */
+#define	SR_IEO		0x00000010	/* old interrupt enable, 1 => enable */
+#define	SR_KUP		0x00000008	/* prev kernel/user, 0 => k, 1 => u */
+#define	SR_IEP		0x00000004	/* prev interrupt enable, 1 => enable */
+#define	SR_KUC		0x00000002	/* cur kernel/user, 0 => k, 1 => u */
+#define	SR_IEC		0x00000001	/* cur interrupt enable, 1 => enable */
+#endif
+
+#if defined S364                        /* (CPU_R32364)        */
+#define	SR_CUMASK	0xf0000000	/* coproc usable bits */
+#define	SR_CU3		0x80000000	/* Coprocessor 3 usable */
+#define	SR_CU2		0x40000000	/* Coprocessor 2 usable */
+#define	SR_CU1		0x20000000	/* Coprocessor 1 usable */
+#define	SR_CU0		0x10000000	/* Coprocessor 0 usable */
+
+/* defines for R32364 processor */
+#define	SR_NBL		0x08000000	/* Non Blocking Load */
+#define	SR_RE		0X02000000	/* Reverse Endianness */
+#define	SR_DL		0x01000000	/* Data Cache Locking */
+#define	SR_IL		0x00800000	/* Instruction Cache Locking */
+
+#define	SR_BEV		0x00400000	/* Use boot exception vectors */
+#define	SR_SR		0x00100000	/* Soft reset */
+#define	SR_CH		0x00040000	/* Cache hit */
+#define	SR_CE		0x00020000	/* Use cache ECC  */
+#define	SR_DE		0x00010000	/* Disable cache exceptions */
+
+/*
+**	status register interrupt masks and bits
+*/
+
+#define	SR_IMASK	0x0000ff00	/* Interrupt mask */
+#define	SR_IMASK8	0x00000000	/* mask level 8 */
+#define	SR_IMASK7	0x00008000	/* mask level 7 */
+#define	SR_IMASK6	0x0000c000	/* mask level 6 */
+#define	SR_IMASK5	0x0000e000	/* mask level 5 */
+#define	SR_IMASK4	0x0000f000	/* mask level 4 */
+#define	SR_IMASK3	0x0000f800	/* mask level 3 */
+#define	SR_IMASK2	0x0000fc00	/* mask level 2 */
+#define	SR_IMASK1	0x0000fe00	/* mask level 1 */
+#define	SR_IMASK0	0x0000ff00	/* mask level 0 */
+
+#define	SR_IMASKSHIFT	8
+
+#define	SR_IBIT8	0x00008000	/* bit level 8 */
+#define	SR_IBIT7	0x00004000	/* bit level 7 */
+#define	SR_IBIT6	0x00002000	/* bit level 6 */
+#define	SR_IBIT5	0x00001000	/* bit level 5 */
+#define	SR_IBIT4	0x00000800	/* bit level 4 */
+#define	SR_IBIT3	0x00000400	/* bit level 3 */
+#define	SR_IBIT2	0x00000200	/* bit level 2 */
+#define	SR_IBIT1	0x00000100	/* bit level 1 */
+
+#define	SR_KSMASK	0x00000016	/* Kernel mode mask */
+#define	SR_KSUSER	0x00000000	/* User Mode */
+#define	SR_KSKERNEL	0x00000016	/* Kernel Mode */
+
+#define	SR_ERL		0x00000004	/* Error level */
+#define	SR_EXL		0x00000002	/* Exception level */
+#define	SR_IE		0x00000001	/* Interrupts enabled */
+#define	NOT_SR_IEC      0xfffffffe      /* assembler problem with li
+~SR_IEC */
+
+/* R32364 Cache locking bits */
+#define SR_ICACHELOCK 0x00800000
+#define SR_DCACHELOCK 0x01000000
+
+#endif /* CPU_R32364 */
+
+#if defined(CPU_R4000)
+#define	SR_CUMASK	0xf0000000	/* coproc usable bits */
+#define	SR_CU3		0x80000000	/* Coprocessor 3 usable */
+#define	SR_CU2		0x40000000	/* Coprocessor 2 usable */
+#define	SR_CU1		0x20000000	/* Coprocessor 1 usable */
+#define	SR_CU0		0x10000000	/* Coprocessor 0 usable */
+
+#define	SR_RP		0x08000000      /* Reduced power operation */
+#define	SR_FR		0x04000000	/* Additional floating pt registers */
+#define	SR_RE		0x02000000	/* Reverse endian in user mode */
+
+#define	SR_BEV		0x00400000	/* Use boot exception vectors */
+#define	SR_TS		0x00200000	/* TLB shutdown */
+#define	SR_SR		0x00100000	/* Soft reset */
+#define	SR_CH		0x00040000	/* Cache hit */
+#define	SR_CE		0x00020000	/* Use cache ECC  */
+#define	SR_DE		0x00010000	/* Disable cache exceptions */
+
+/*
+**	status register interrupt masks and bits
+*/
+
+#define	SR_IMASK	0x0000ff00	/* Interrupt mask */
+#define	SR_IMASK8	0x00000000	/* mask level 8 */
+#define	SR_IMASK7	0x00008000	/* mask level 7 */
+#define	SR_IMASK6	0x0000c000	/* mask level 6 */
+#define	SR_IMASK5	0x0000e000	/* mask level 5 */
+#define	SR_IMASK4	0x0000f000	/* mask level 4 */
+#define	SR_IMASK3	0x0000f800	/* mask level 3 */
+#define	SR_IMASK2	0x0000fc00	/* mask level 2 */
+#define	SR_IMASK1	0x0000fe00	/* mask level 1 */
+#define	SR_IMASK0	0x0000ff00	/* mask level 0 */
+
+#define	SR_IMASKSHIFT	8
+
+#define	SR_IBIT8	0x00008000	/* bit level 8 */
+#define	SR_IBIT7	0x00004000	/* bit level 7 */
+#define	SR_IBIT6	0x00002000	/* bit level 6 */
+#define	SR_IBIT5	0x00001000	/* bit level 5 */
+#define	SR_IBIT4	0x00000800	/* bit level 4 */
+#define	SR_IBIT3	0x00000400	/* bit level 3 */
+#define	SR_IBIT2	0x00000200	/* bit level 2 */
+#define	SR_IBIT1	0x00000100	/* bit level 1 */
+
+#define	SR_KSMASK	0x00000018	/* Kernel mode mask */
+#define	SR_KSUSER	0x00000010	/* User mode */
+#define	SR_KSSUPER	0x00000008	/* Supervisor mode */
+#define	SR_KSKERNEL	0x00000000	/* Kernel mode */
+#define	SR_ERL		0x00000004	/* Error level */
+#define	SR_EXL		0x00000002	/* Exception level */
+#define	SR_IE		0x00000001	/* Interrupts enabled */
+
+/* R4650 Cache locking bits */
+#define	SR_ICACHELOCK 0x00800000
+#define	SR_DCACHELOCK 0x01000000
+
+
+#endif
+#if defined(CPU_R3000)
+#define	SR_FR		0x04000000	/* Additional floating point registers */
+#endif
+
+
+
+/*
+ * Cause Register
+ */
+#define	CAUSE_BD	0x80000000	/* Branch delay slot */
+#define	CAUSE_CEMASK	0x30000000	/* coprocessor error */
+#define	CAUSE_CESHIFT	28
+#define	CAUSE_IW	0x01000000	/* Instruction watch */
+#define	CAUSE_DW	0x02000000	/* Data watch */
+#define	CAUSE_IPE	0x04000000	/* Imprecise exception */
+
+
+#define	CAUSE_IPMASK	0x0000FF00	/* Pending interrupt mask */
+#define	CAUSE_IPSHIFT	8
+
+/* Notice: Watch Exception if Exc. Code is 23 is not included in the mask
+ *	   for R32364.
+ */
+#define	CAUSE_EXCMASK	0x0000003C	/* Cause code bits */
+#define	CAUSE_EXCSHIFT	2
+
+#ifndef XDS
+/*
+**  Coprocessor 0 registers
+*/
+
+/* Evelyn, 12/12/94, for P3 	*/
+#define C0_IBASE        $0		/* I base */
+#define C0_IBOUND       $1		/* I bound */
+
+#define	C0_INX			$0		/* tlb index */
+#define	C0_RAND			$1		/* tlb random */
+#if defined(CPU_R3000)
+#define	C0_TLBLO	$2				/* tlb entry low */
+#define	C0_BUSCTRL		$2		/* bus control R3041 specific */
+#define	C0_CONFIG		$3		/* cache config */
+#define	C0_CTXT			$4		/* tlb context */
+#define	C0_BADVADDR		$8		/* bad virtual address */
+#define	C0_COUNT			$9		/* count R3041 specific */
+#define	C0_PORTSIZE		$10	/* port size R3041 specific */
+#define	C0_TLBHI			$10	/* tlb entry hi */
+#define	C0_COMPARE		$11	/* compare R3041 specific */
+#define	C0_SR				$12	/* status register */
+#define	C0_CAUSE			$13	/* exception cause */
+#define	C0_EPC			$14	/* exception pc */
+#define	C0_PRID			$15	/* revision identifier */
+#endif
+
+#if defined(S364)					/*(CPU_R32364)      */
+#define	C0_RANDOM		$1
+#define	C0_TLBLO0		$2		/* tlb entry low 0 */
+#define	C0_TLBLO1		$3		/* tlb entry low 1 */
+#define	C0_CTXT			$4		/* tlb context */
+#define	C0_PAGEMASK		$5		/* tlb page mask */
+#define	C0_WIRED			$6		/* number of wired tlb entries */
+
+#define	C0_INX			$0		/* tlb index */
+#define	C0_BADVADDR		$8		/* bad virtual address */
+#define	C0_COUNT			$9		/* timer count */
+#define	C0_TLBHI			$10	/* tlb entry hi */
+#define	C0_COMPARE		$11	/* timer comparator  */
+#define	C0_SR				$12	/* status register */
+#define	C0_CAUSE			$13	/* exception cause */
+#define	C0_EPC			$14	/* exception pc */
+#define	C0_PRID			$15	/* revision identifier */
+#define	C0_CONFIG		$16	/* configuration register */
+
+#define	C0_IWATCH		$18	/* Instr brk pt Virtual add. */
+#define	C0_DWATCH		$19	/* Data brk pt Virtual add. */
+
+#define	C0_IEPC			$22	/* Imprecise Exception pc */
+#define	C0_DEPC			$23	/* Debug Exception pc */
+#define	C0_DEBUG			$24	/* Debug control/status reg */
+
+#define	C0_ECC			$26	/* primary cache Parity control */
+#define	C0_CACHEERR		$27	/* cache error status */
+#define	C0_TAGLO			$28	/* cache tag lo */
+#define	C0_TAGHI			$29
+#define	C0_ERRPC			$30	/* cache error pc */
+#endif /* CPU_R32364 			*/
+
+#if defined(CPU_R4000)
+
+/* Evelyn, 12/12/94, for P3 	*/
+#define	C0_DBASE			$2		/* D base */
+#define	C0_DBOUND		$3		/* D bound */
+
+#define	C0_TLBLO0		$2		/* tlb entry low 0 */
+#define	C0_TLBLO1		$3		/* tlb entry low 1 */
+#define	C0_CTXT			$4		/* tlb context */
+#define	C0_PAGEMASK		$5		/* tlb page mask */
+#define	C0_WIRED			$6		/* number of wired tlb entries */
+
+#define	C0_BADVADDR		$8		/* bad virtual address */
+#define	C0_COUNT			$9		/* cycle count */
+#define	C0_TLBHI			$10	/* tlb entry hi */
+#define	C0_COMPARE		$11	/* cyccle count comparator  */
+#define	C0_SR				$12	/* status register */
+#define	C0_CAUSE			$13	/* exception cause */
+#define	C0_EPC			$14	/* exception pc */
+#define	C0_PRID			$15	/* revision identifier */
+#define	C0_CONFIG		$16	/* configuration register */
+
+/* Evelyn, 12/12/94, for P3   */
+#define	C0_CALG			$17	/* Calg rigister */
+#define	C0_IWATCH		$18	/* IWatch register */
+#define	C0_DWATCH		$19	/* DWatch register */
+
+#define	C0_LLADDR		$17	/* linked load address */
+#define	C0_WATCHLO		$18	/* watchpoint trap register */
+#define	C0_WATCHHI		$19	/* watchpoint trap register */
+#define	C0_XCTXT			$20 	/* extended tlb context */
+#define	C0_ECC			$26	/* secondary cache ECC control */
+#define	C0_CACHEERR		$27	/* cache error status */
+#define	C0_TAGLO			$28	/* cache tag lo */
+#define	C0_TAGHI			$29	/* cache tag hi */
+#define	C0_ERRPC			$30	/* cache error pc */
+#endif
+#endif 
+#endif /* defined(__IDTCPU_H__) */
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/idthdr.h idtlinux/arch/mips/idt-boards/rc32300/S334/boot/idthdr.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/idthdr.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/idthdr.h	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,54 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Some macros. Though they are already defined else where in the linux
+ *   tree, they are once again declared here for the ease of syncing up with
+ *    IDT bootloader code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef XDS
+
+#define	FRAME(name,frm_reg,offset,ret_reg)	\
+	.globl	name;				\
+	.ent	name;				\
+name:;						\
+	.frame	frm_reg,offset,ret_reg
+
+#define ENDFRAME(name) 	.end name
+
+#else
+
+#define FRAME(name,frm_reg,offset,ret_reg)      \
+name:
+
+#define ENDFRAME(name)
+
+#endif
+
+
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/image.lds.in idtlinux/arch/mips/idt-boards/rc32300/S334/boot/image.lds.in
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/image.lds.in	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/image.lds.in	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,31 @@
+OUTPUT_ARCH(mips)
+ENTRY(zstartup)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = IMSTART;
+  .init          : { *(.init)		} =0
+  .text      :
+  {
+    _ftext = . ;
+    *(.text)
+    *(.rodata)
+    *(.rodata1)
+   . = ALIGN(4096);
+    input_data = .;
+    arch/mips/idt-boards/rc32300/S334/boot/piggy.o
+    input_data_end = .;
+   . = ALIGN(4096);
+    *(.gnu.warning)
+  } =0
+
+  .reginfo : { *(.reginfo) }
+
+   . = BSS_START;
+  __bss_start = .;
+  .bss       :
+  {
+   *(.bss)
+  _end = . ;
+  }
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/iregdef.h idtlinux/arch/mips/idt-boards/rc32300/S334/boot/iregdef.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/iregdef.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/iregdef.h	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,284 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   IDT CPU register definitions. Though the registers are already defined
+ *   under asm directory, they are once again declared here for the ease of
+ *   syncing up with IDT bootloader code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#define r0	$0
+#define r1	$1 /*at assembler temp */
+#define r2	$2 /*v0 return value */
+#define r3	$3 /*v1 return value */
+#define r4	$4 /*a0 argument 0 */
+#define r5	$5 /*a1 argument 1 */
+#define r6	$6
+#define r7	$7
+#define r8	$8
+#define r9	$9
+#define r10	$10
+#define r11	$11
+#define r12	$12
+#define r13	$13
+
+#define r14	$14
+#define r15	$15
+#define r16	$16 /*s0 called saved */
+#define r17	$17
+#define r18	$18
+#define r19	$19
+#define r20	$20
+#define r21	$21
+#define r22	$22
+#define r23	$23 /*s7 called saved */
+#define r24	$24
+#define r25	$25
+#define r26	$26 /*k0 kernel temp. */
+#define r27	$27 /*k1   ""    ""   */
+#define r28	$28 /*gp global pointer */
+#define r29	$29 /*sp stack pointer */
+#define r30	$30 /*fp frame pointer */
+#define r31	$31 /*ra return address */
+
+#define fp0	$f0
+#define fp1	$f1
+#define fp2	$f2
+#define fp3	$f3
+#define fp4	$f4
+#define fp5	$f5
+#define fp6	$f6
+#define fp7	$f7
+#define fp8	$f8
+#define fp9	$f9
+#define fp10	$f10
+#define fp11	$f11
+#define fp12	$f12
+#define fp13	$f13
+#define fp14	$f14
+#define fp15	$f15
+#define fp16	$f16
+#define fp17	$f17
+#define fp18	$f18
+#define fp19	$f19
+#define fp20	$f20
+#define fp21	$f21
+#define fp22	$f22
+#define fp23	$f23
+#define fp24	$f24
+#define fp25	$f25
+#define fp26	$f26
+#define fp27	$f27
+#define fp28	$f28
+#define fp29	$f29
+#define fp30	$f30
+#define fp31	$f31
+
+#define fcr0	$0
+#define fcr30	$30
+#define fcr31	$31
+
+#define zero	$0	/* wired zero */
+#define AT	$at	/* assembler temp */
+#define v0	$2	/* return value */
+#define v1	$3
+#define a0	$4	/* argument registers */
+#define a1	$5
+#define a2	$6
+#define a3	$7
+#define t0	$8	/* caller saved */
+#define t1	$9
+#define t2	$10
+#define t3	$11
+#define t4	$12
+#define t5	$13
+#define t6	$14
+#define t7	$15
+#define s0	$16	/* callee saved */
+#define s1	$17
+#define s2	$18
+#define s3	$19
+#define s4	$20
+#define s5	$21
+#define s6	$22
+#define s7	$23
+#define t8	$24	/* code generator */
+#define t9	$25
+#define k0	$26	/* kernel temporary */
+#define k1	$27
+#define gp	$28	/* global pointer */
+#define sp	$29	/* stack pointer */
+#define s8	$30	/* yet another saved reg for the callee */
+#define fp	$30	/* frame pointer - this is being phased out by MIPS */
+#define ra	$31	/* return address */
+
+
+/*
+ * register names
+ */
+#define	R_R0		0
+#define	R_R1		1
+#define	R_R2		2
+#define	R_R3		3
+#define	R_R4		4
+#define	R_R5		5
+#define	R_R6		6
+#define	R_R7		7
+#define	R_R8		8
+#define	R_R9		9
+#define	R_R10		10
+#define	R_R11		11
+#define	R_R12		12
+#define	R_R13		13
+#define	R_R14		14
+#define	R_R15		15
+#define	R_R16		16
+#define	R_R17		17
+#define	R_R18		18
+#define	R_R19		19
+#define	R_R20		20
+#define	R_R21		21
+#define	R_R22		22
+#define	R_R23		23
+#define	R_R24		24
+#define	R_R25		25
+#define	R_R26		26
+#define	R_R27		27
+#define	R_R28		28
+#define	R_R29		29
+#define	R_R30		30
+#define	R_R31		31
+#define	R_F0		32
+#define	R_F1		33
+#define	R_F2		34
+#define	R_F3		35
+#define	R_F4		36
+#define	R_F5		37
+#define	R_F6		38
+#define	R_F7		39
+#define	R_F8		40
+#define	R_F9		41
+#define	R_F10		42
+#define	R_F11		43
+#define	R_F12		44
+#define	R_F13		45
+#define	R_F14		46
+#define	R_F15		47
+#define	R_F16		48
+#define	R_F17		49
+#define	R_F18		50
+#define	R_F19		51
+#define	R_F20		52
+#define	R_F21		53
+#define	R_F22		54
+#define	R_F23		55
+#define	R_F24		56
+#define	R_F25		57
+#define	R_F26		58
+#define	R_F27		59
+#define	R_F28		60
+#define	R_F29		61
+#define	R_F30		62
+#define	R_F31		63
+#define NCLIENTREGS	64
+#define	R_EPC		64
+#define	R_MDHI		65
+#define	R_MDLO		66
+#define	R_SR		67
+#define	R_CAUSE		68
+#define	R_TLBHI		69
+#ifdef CPU_R4000
+#define	R_TLBLO0	70
+#else
+#define	R_TLBLO		70
+#endif
+#define	R_BADVADDR	71
+#define	R_INX		72
+#define	R_RAND		73
+#define	R_CTXT		74
+#define	R_EXCTYPE	75
+#define R_MODE		76
+#define	R_PRID		77
+#define R_FCSR		78
+#define R_FEIR		79
+#ifdef CPU_R4000
+#define	R_TLBLO1	80
+#define R_PAGEMASK	81
+#define R_WIRED		82
+#define R_COUNT		83
+#define R_COMPARE	84
+#define R_CONFIG	85
+#define R_LLADDR	86
+#define R_WATCHLO	87
+#define R_WATCHHI	88
+#define R_ECC		89
+#define R_CACHEERR	90
+#define R_TAGLO		91
+#define R_TAGHI		92
+#define R_ERRPC		93
+#endif
+
+#ifdef CPU_R4000
+#define	NREGS		94
+#else
+#define NREGS		80
+#endif
+
+/*
+ * compiler defined bindings
+ */
+#define	R_ZERO		R_R0
+#define	R_AT		R_R1
+#define	R_V0		R_R2
+#define	R_V1		R_R3
+#define	R_A0		R_R4
+#define	R_A1		R_R5
+#define	R_A2		R_R6
+#define	R_A3		R_R7
+#define	R_T0		R_R8
+#define	R_T1		R_R9
+#define	R_T2		R_R10
+#define	R_T3		R_R11
+#define	R_T4		R_R12
+#define	R_T5		R_R13
+#define	R_T6		R_R14
+#define	R_T7		R_R15
+#define	R_S0		R_R16
+#define	R_S1		R_R17
+#define	R_S2		R_R18
+#define	R_S3		R_R19
+#define	R_S4		R_R20
+#define	R_S5		R_R21
+#define	R_S6		R_R22
+#define	R_S7		R_R23
+#define	R_T8		R_R24
+#define	R_T9		R_R25
+#define	R_K0		R_R26
+#define	R_K1		R_R27
+#define	R_GP		R_R28
+#define	R_SP		R_R29
+#define	R_FP		R_R30
+#define	R_RA		R_R31
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/Makefile idtlinux/arch/mips/idt-boards/rc32300/S334/boot/Makefile
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/Makefile	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/Makefile	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,151 @@
+###############################################################################
+#
+#  BRIEF MODULE DESCRIPTION
+#     Makefile create a compressed zImage or Rommable rImage
+#
+#  Copyright 2006 IDT Inc. (rischelp@idt.com)
+#
+#  This program is free software; you can redistribute  it and/or modify it
+#  under  the terms of  the GNU General  Public License as published by the
+#  Free Software Foundation;  either version 2 of the  License, or (at your
+#  option) any later version.
+#
+#  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+#  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+#   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+#   NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+#   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+#   NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+#   USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+#   ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+#   THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#   You should have received a copy of the  GNU General Public License along
+#   with this program; if not, write  to the Free Software Foundation, Inc.,
+#   675 Mass Ave, Cambridge, MA 02139, USA.
+# 
+# 
+###############################################################################
+
+###############################################################################
+# The following is taken from IDT/Sim Makefile
+###############################################################################
+TARGET=134
+TARGETDIR=S134_334
+# Even though this makefile is for S334A board, we continue to use files
+# from the S134 & S334 board based source.  A -DS334A in the sources
+# will distinguish code that is unique to S334A boards.
+
+#
+# following refers to memory type in use in eval board and if more than one
+# then the order is implied.  These are values for the switch MEMCFG.
+#
+SRAM_ONLY=1
+SDRAM_ONLY=2
+EDO_ONLY=3
+SRAM_N_SDRAM=4
+SRAM_N_EDO=5
+SDRAM_N_SRAM=6
+EDO_N_SRAM=7
+
+# following refers to size of the DRAM space.
+# These are values for the switch DRAMSZ.
+
+MB32=1
+MB64=2
+MB128=3
+MB32SO=4
+
+# following refers to the size of the boot EPROM space port width.
+# These values are for the switch EPRMPRTWD.
+
+EP8=1
+EP32=2
+
+MACH= -DS$(TARGET)  -DS334A -DS334 -DS364 -DCPU_R32364 -DMEMCFG=$(SDRAM_ONLY) -DDRAMSZ=$(MB32SO) -DEPRMPRTWD=$(EP32)
+COMMSWITCHES= $(INCDIRS) $(MACH)
+#***************** END IDT/Sim Makefile #####################################
+ZDEBUG=0
+export ZDEBUG
+
+# working space for gunzip:
+FREE_RAM      := 0x80C00000
+END_RAM       := 0x80E00000
+
+KERNELCONFIG  := $(TOPDIR)/.config
+include $(KERNELCONFIG)
+
+SIZE = $(CROSS_COMPILE)size
+
+O_FORMAT = $(shell $(OBJDUMP) -i | head -2 | grep elf32)
+
+SYSTEM	      := $(TOPDIR)/vmlinux
+ZBSS          := 0x800A0000
+
+ZIMSTART      := $(CONFIG_IDT_ZIMAGE_ADDR)
+RIMSTART      := 0x9FC00000
+
+LOADADDR      := 0x$(shell $(NM) $(SYSTEM) | grep "A _text" |cut -f1 -d' ')
+KERNEL_ENTRY  := $(shell $(OBJDUMP) -f $(SYSTEM) | sed -n -e 's/^start address //p')
+
+####################################################################################
+ZIMFLAGS        = s/IMSTART/$(ZIMSTART)/;s/BSS_START/$(ZBSS)/
+RIMFLAGS        = s/IMSTART/$(RIMSTART)/;s/BSS_START/$(ZBSS)/
+CFLAGS	:= -fno-pic -nostdinc -G 0 -mno-abicalls -fno-pic -pipe -I$(TOPDIR)/include
+AFLAGS	:= -D__ASSEMBLY__ $(CFLAGS)
+
+####################################################################################
+OBJECTS= $(obj)/piggy.o $(obj)/head.o $(obj)/misc.o
+ifneq ($(ZDEBUG),0)
+OBJECTS += $(obj)/uart16550.o
+endif
+
+$(obj)/zImage.lds: $(obj)/image.lds.in $(KERNELCONFIG)
+	@sed "$(ZIMFLAGS)" < $< > $@
+
+$(obj)/rImage.lds: $(obj)/image.lds.in $(KERNELCONFIG)
+	@sed "$(RIMFLAGS)" < $< > $@
+
+$(obj)/piggy.o: $(SYSTEM) $(obj)/Makefile
+	$(OBJCOPY) -S -O binary -R .note -R .comment $(SYSTEM) $(SYSTEM).bin
+	gzip -f -9 < $(SYSTEM).bin > $(SYSTEM).gz
+	echo "O_FORMAT:  " $(O_FORMAT); 
+	$(LD) -r -b binary --oformat $(O_FORMAT) -o $(obj)/piggy.o $(SYSTEM).gz
+	rm -f $(SYSTEM).bin $(SYSTEM).gz
+
+$(obj)/head.o: $(obj)/head.S $(SYSTEM) $(obj)/Makefile
+	$(CC) $(AFLAGS) -DKERNEL_ENTRY=$(KERNEL_ENTRY) -c $(obj)/head.S -o $(obj)/head.o
+
+$(obj)/misc.o: $(obj)/misc.c $(obj)/Makefile
+	$(CC) $(CFLAGS) -DLOADADDR=$(LOADADDR) -DFREE_RAM=$(FREE_RAM) -DEND_RAM=$(END_RAM) \
+		-c $< -DZDEBUG=$(ZDEBUG) -o $(obj)/misc.o
+
+$(obj)/uart16550.o: $(obj)/uart16550.c $(KERNELCONFIG)
+	$(CC) $(CFLAGS) -c $< -o $(obj)/uart16550.o
+
+$(obj)/csu_idt.o: $(obj)/csu_idt.S Makefile $(SYSTEM)
+	$(CC) $(AFLAGS) $(COMMSWITCHES) -c $< -o $(obj)/csu_idt.o
+
+zImage: $(obj)/zImage.lds $(SYSTEM) $(OBJECTS)
+	$(LD) -T$(obj)/zImage.lds -o $(TOPDIR)/zImage $(OBJECTS)
+	$(OBJCOPY) -S -O binary -R .note -R .comment $(TOPDIR)/zImage $(TOPDIR)/zImage.bin
+	$(OBJCOPY) -I binary -S -O srec --srec-forceS3 --srec-len=32 --change-start=0x00000000 \
+		 $(TOPDIR)/zImage.bin $(TOPDIR)/zImage.prm
+	$(SIZE) $(TOPDIR)/zImage |awk -F" " '{ print $$4 "\t" $$5 }' > $(TOPDIR)/zImage.size
+	rm -f *.o
+
+rImage: $(obj)/rImage.lds $(OBJECTS) $(obj)/csu_idt.o $(SYSTEM)
+	@rm -f $(TOPDIR)/*.prm
+	$(LD) -T$(obj)/rImage.lds -o $(TOPDIR)/rImage $(obj)/csu_idt.o $(OBJECTS) 
+	$(OBJCOPY) -S -O binary -R .note -R .comment $(TOPDIR)/rImage $(TOPDIR)/rImage.bin
+	$(OBJCOPY) -I binary -S -O srec -b 0 --srec-forceS3 --srec-len=32 --change-start=0x00000000 $(TOPDIR)/rImage.bin $(TOPDIR)/rImage0.prm
+	$(OBJCOPY) -I binary -S -O srec -b 1 --srec-forceS3 --srec-len=32 --change-start=0x00000000 $(TOPDIR)/rImage.bin $(TOPDIR)/rImage1.prm
+	$(OBJCOPY) -I binary -S -O srec -b 2 --srec-forceS3 --srec-len=32 --change-start=0x00000000 $(TOPDIR)/rImage.bin $(TOPDIR)/rImage2.prm
+	$(OBJCOPY) -I binary -S -O srec -b 3 --srec-forceS3 --srec-len=32 --change-start=0x00000000 $(TOPDIR)/rImage.bin $(TOPDIR)/rImage3.prm
+	$(SIZE) $(TOPDIR)/rImage |awk -F" " '{ print $$4 "\t" $$5 }' > $(TOPDIR)/rImage.size
+	rm -f *.o
+
+clean:
+	rm -f *.o $(TOPDIR)/zImage $(TOPDIR)/rImage $(TOPDIR)/*.prm $(TOPDIR)/rImage.size $(TOPDIR)/zImage.size
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/misc.c idtlinux/arch/mips/idt-boards/rc32300/S334/boot/misc.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/misc.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/misc.c	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,339 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Code to un-compress linux image
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/types.h>
+
+/*
+ * gzip declarations
+ */
+#define OF(args)  args
+#define STATIC static
+#define memzero(s, n)     memset ((s), 0, (n))
+typedef unsigned char uch;
+typedef unsigned short ush;
+typedef unsigned long ulg;
+#define WSIZE 0x8000		/* Window size must be at least 32k, */
+				/* and a power of two */
+static uch *inbuf;		/* input buffer */
+static uch window[WSIZE];	/* Sliding window buffer */
+
+/* gzip flag byte */
+#define ASCII_FLAG   0x01	/* bit 0 set: file probably ASCII text */
+#define CONTINUATION 0x02	/* bit 1 set: continuation of multi-part gzip file */
+#define EXTRA_FIELD  0x04	/* bit 2 set: extra field present */
+#define ORIG_NAME    0x08	/* bit 3 set: original file name present */
+#define COMMENT      0x10	/* bit 4 set: file comment present */
+#define ENCRYPTED    0x20	/* bit 5 set: file is encrypted */
+#define RESERVED     0xC0	/* bit 6,7:   reserved */
+
+
+static unsigned insize;	/* valid bytes in inbuf */
+static unsigned inptr;	/* index of next byte to be processed in inbuf */
+static unsigned outcnt;	/* bytes in output buffer */
+
+void variable_init(void);
+#if ZDEBUG > 0
+static void puts(const char *);
+extern void putc_init(void);
+extern void putc(unsigned char c);
+#endif
+static int fill_inbuf(void);
+static void flush_window(void);
+static void error(char *m);
+static void gzip_mark(void **);
+static void gzip_release(void **);
+
+extern char input_data[];
+
+extern char input_data_end[];
+
+#if ZDEBUG > 0
+void int2hex(unsigned long val)
+{
+        unsigned char buf[10];
+        int i;
+        for (i = 7;  i >= 0;  i--)
+        {
+                buf[i] = "0123456789ABCDEF"[val & 0x0F];
+                val >>= 4;
+        }
+        buf[8] = '\0';
+        puts(buf);
+}
+#endif
+
+static unsigned long byte_count;
+
+int get_byte(void)
+{
+#if ZDEBUG > 1
+	static int printCnt;
+#endif
+	unsigned char c = (inptr < insize ? inbuf[inptr++] : fill_inbuf());
+	byte_count++;
+
+#if ZDEBUG > 1
+	if (printCnt++ < 32)
+	{
+	  puts("byte count = ");
+	  int2hex(byte_count);
+	  puts(" byte val = ");
+	  int2hex(c);
+	  puts("\n");
+	}
+#endif
+	return c;
+}
+
+/* Diagnostic functions */
+#ifdef DEBUG
+#  define Assert(cond,msg) {if(!(cond)) error(msg);}
+#  define Trace(x) fprintf x
+#  define Tracev(x) {if (verbose) fprintf x ;}
+#  define Tracevv(x) {if (verbose>1) fprintf x ;}
+#  define Tracec(c,x) {if (verbose && (c)) fprintf x ;}
+#  define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}
+#else
+#  define Assert(cond,msg)
+#  define Trace(x)
+#  define Tracev(x)
+#  define Tracevv(x)
+#  define Tracec(c,x)
+#  define Tracecv(c,x)
+#endif
+
+/*
+ * This is set up by the setup-routine at boot-time
+ */
+
+static long bytes_out;
+static uch *output_data;
+static unsigned long output_ptr;
+
+
+static void *malloc(int size);
+static void free(void *where);
+static void error(char *m);
+static void gzip_mark(void **);
+static void gzip_release(void **);
+
+static unsigned long free_mem_ptr;
+static unsigned long free_mem_end_ptr;
+
+#include "../../../../../../lib/inflate.c"
+
+static void *malloc(int size)
+{
+	void *p;
+
+	if (size < 0)
+		error("Malloc error\n");
+	if (free_mem_ptr <= 0) error("Memory error\n");
+
+	free_mem_ptr = (free_mem_ptr + 3) & ~3;	/* Align */
+
+	p = (void *) free_mem_ptr;
+	free_mem_ptr += size;
+
+	if (free_mem_ptr >= free_mem_end_ptr)
+		error("\nOut of memory\n");
+
+	return p;
+}
+
+static void free(void *where)
+{				/* Don't care */
+}
+
+static void gzip_mark(void **ptr)
+{
+	*ptr = (void *) free_mem_ptr;
+}
+
+static void gzip_release(void **ptr)
+{
+	free_mem_ptr = (long) *ptr;
+}
+#if ZDEBUG > 0
+static void puts(const char *s)
+{
+	while (*s) {
+		if (*s == 10)
+			putc(13);
+		putc(*s++);
+	}
+}
+#endif
+void *memset(void *s, int c, size_t n)
+{
+	int i;
+	char *ss = (char *) s;
+
+	for (i = 0; i < n; i++)
+		ss[i] = c;
+	return s;
+}
+
+void *memcpy(void *__dest, __const void *__src, size_t __n)
+{
+	int i;
+	char *d = (char *) __dest, *s = (char *) __src;
+
+	for (i = 0; i < __n; i++)
+		d[i] = s[i];
+	return __dest;
+}
+
+/* ===========================================================================
+ * Fill the input buffer. This is called only when the buffer is empty
+ * and at least one byte is really needed.
+ */
+static int fill_inbuf(void)
+{
+	if (insize != 0) {
+		error("ran out of input data\n");
+	}
+
+	inbuf = input_data;
+	insize = &input_data_end[0] - &input_data[0];
+	inptr = 1;
+	return inbuf[0];
+}
+
+/* ===========================================================================
+ * Write the output window window[0..outcnt-1] and update crc and bytes_out.
+ * (Used for the decompressed data only.)
+ */
+static void flush_window(void)
+{
+	ulg c = crc;		/* temporary variable */
+	unsigned n;
+	uch *in, *out, ch;
+
+	in = window;
+	out = &output_data[output_ptr];
+	for (n = 0; n < outcnt; n++) {
+		ch = *out++ = *in++;
+		c = crc_32_tab[((int) c ^ ch) & 0xff] ^ (c >> 8);
+	}
+	crc = c;
+	bytes_out += (ulg) outcnt;
+	output_ptr += (ulg) outcnt;
+	outcnt = 0;
+}
+
+#if ZDEBUG > 0
+void check_mem(void)
+{
+	int i;
+
+	puts("\ncplens = ");
+	for (i = 0; i < 10; i++) {
+		int2hex(cplens[i]);
+		puts(" ");
+	}
+	puts("\ncplext = ");
+	for (i = 0; i < 10; i++) {
+		int2hex(cplext[i]);
+		puts(" ");
+	}
+	puts("\nborder = ");
+	for (i = 0; i < 10; i++) {
+		int2hex(border[i]);
+		puts(" ");
+	}
+	puts("\n");
+}
+#endif
+static void error(char *x)
+{
+#if ZDEBUG > 1
+	check_mem();
+	puts("\n\n");
+	puts(x);
+	puts("byte_count = ");
+	int2hex(byte_count);
+	puts("\n");
+	puts("\n\n -- Error. System halted");
+#endif
+	while (1);		/* Halt */
+}
+
+void variable_init(void)
+{
+	byte_count = 0;
+	output_data = (char *) LOADADDR;
+	free_mem_ptr = FREE_RAM;
+	free_mem_end_ptr = END_RAM;
+#if ZDEBUG > 1
+	puts("output_data      0x");
+	int2hex((unsigned long)output_data); puts("\n");
+	puts("free_mem_ptr     0x");
+	int2hex(free_mem_ptr); puts("\n");
+	puts("free_mem_end_ptr 0x");
+	int2hex(free_mem_end_ptr); puts("\n");
+	puts("input_data       0x");
+	int2hex((unsigned long)input_data); puts("\n");
+#endif
+}
+
+int decompress_kernel(void)
+{
+#if ZDEBUG > 0
+  putc_init();
+#if ZDEBUG > 2
+  check_mem();
+#endif
+#endif
+
+  variable_init();
+
+  makecrc();
+#if ZDEBUG > 0
+  puts("\n");
+  puts("Uncompressing Linux... \n");
+#endif
+  gunzip();		// ...see inflate.c
+#if ZDEBUG > 0
+  puts("Ok, booting the kernel.\n");
+#endif
+
+#if ZDEBUG > 1
+ {
+  unsigned long *p = (unsigned long *)LOADADDR;
+  int2hex(p[0]); puts("\n");
+  int2hex(p[1]); puts("\n");
+  int2hex(p[2]); puts("\n");
+  int2hex(p[3]); puts("\n");
+ }
+#endif
+
+  return 0;
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/rImage.lds idtlinux/arch/mips/idt-boards/rc32300/S334/boot/rImage.lds
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/rImage.lds	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/rImage.lds	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,31 @@
+OUTPUT_ARCH(mips)
+ENTRY(zstartup)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = 0x9FC00000;
+  .init          : { *(.init)		} =0
+  .text      :
+  {
+    _ftext = . ;
+    *(.text)
+    *(.rodata)
+    *(.rodata1)
+   . = ALIGN(4096);
+    input_data = .;
+    arch/mips/idt-boards/rc32300/S334/boot/piggy.o
+    input_data_end = .;
+   . = ALIGN(4096);
+    *(.gnu.warning)
+  } =0
+
+  .reginfo : { *(.reginfo) }
+
+   . = 0x800A0000;
+  __bss_start = .;
+  .bss       :
+  {
+   *(.bss)
+  _end = . ;
+  }
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/s334aram.h idtlinux/arch/mips/idt-boards/rc32300/S334/boot/s334aram.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/s334aram.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/s334aram.h	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,330 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   IDT S334 SDRAM setup values.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef __S334RAM__
+#define __S334RAM__
+/******************************** D E F I N E S *******************************/
+
+#define SRAM_ONLY	1
+#define SDRAM_ONLY	2
+/* #define EDO_ONLY	3 */
+#define SRAM_N_SDRAM	4
+/* #define SRAM_N_EDO	5 */
+#define SDRAM_N_SRAM	6
+/* #define EDO_N_SRAM	7 */
+
+#define APATTERN 0xa5a5a5a5
+
+#define MB32	1
+#define MB64	2
+#define MB128	3
+#define MB32SO  4
+
+#define EP8	1
+#define EP32	2
+
+#define EXTU	1
+#define INTU	2
+
+#ifndef LED_BASE
+
+#if defined(EB332)
+#define	LED_BASE	PHYS_TO_K1(0x10000000)
+#else
+#define	LED_BASE	PHYS_TO_K1(0x14000000)
+#endif /* EB332 */
+
+#define	LED_DIGIT0	0xf
+#define	LED_DIGIT1	0xb
+#define	LED_DIGIT2	0x7
+#define	LED_DIGIT3	0x3
+#define	LED_CLEAR	0x400
+
+#endif
+
+#define SYS_BTA_CTRL            PHYS_TO_K1(0x18000000)
+#define SYS_ALT_CTRL            PHYS_TO_K1(0x18000004)
+
+#if MHZ < 66000000
+#define SYS_ALT_SETUP           0x00000003 
+#define TRCD			0x00500000	/* used in SDRAM set-up (RCD value) */ 
+#else
+#define SYS_ALT_SETUP           0x00000007  
+#define TRCD			0x00600000	/* used in SDRAM set-up (RCD value) */  
+#endif
+
+#define	PORT_WIDTH_CONTROL	0xffffe200	/* port width control register address */
+#define	BTA_CONTROL		0xffffe204      /* was 0xffffe240 - hak 06-16-98 - BTA control register address */
+#define	BTA_SETUP		0x3FFFFFFF      /* 3 turnaround cycles for all regions */
+
+#if EPRMPRTWD == EP8
+
+#define	PORT_SETUP		0xaa822aaa       /* changed for 8-bit wide NVRAM at physical 1200_0000: Upen-000530*/
+
+#elif EPRMPRTWD == EP32
+#define PORT_SETUP		0xaa82aaaa	/* boot EPROM space port width = 32 bits */
+#else
+#error "illegal value for eprom port width"
+#endif
+
+#define MEM_CTL_BASE		PHYS_TO_K1(0x18000200)	/* base address of all (0-5) Memory Control Registers */
+#define MEM_BASE_BASE		PHYS_TO_K1(0x18000080)	/* base address of 2 (0-1) Base Address Registers */
+#define R32134_IREG_BASE	PHYS_TO_K1(0x18000000)	/* all R32134 internal registers' base address */
+
+/* 
+** b14:13=>01=PROM;b12=>1= do not assert CS during writes; b11:10=>00=8 bit port 
+** b09:05=>08=8 wait states; b04:00=>08= 8 wait states
+*/
+
+#define MCR_CS0_BS		0x31083108  
+
+
+/* 
+** b14:13=>00=SRAM;b12=>0= assert CS during writes; b11:10=>10=32 bit port 
+** b09:05=>FF=31 wait states; b04:00=>FF= 31 wait states.
+** NOTE: wait states should be tuned.
+*/
+
+#if defined(EB332)
+#define MCR_CS1_BS		0x60e760e7
+#else
+#define MCR_CS1_BS		0x28632863
+#endif /* EB332 */
+#define MCR_CS2_BS		0x60e760e7
+#define MCR_CS3_BS		0x60e760e7
+#define MCR_CS4_BS		0x60e760e7     /* S334 LED */
+
+/* 
+** b14:13=>01=I Type;b12=>0= assert CS during writes; b11:10=>00=8 bit port 
+** b09:05=>FF=31 wait states; b04:00=>FF= 31 wait states
+*/
+
+#define MCR_CS5_BS		0x60E760E7
+
+#define MBA_REG0		0x1FC00000  /* phys mem base addr reg val for CS 0 - EPROM */
+#define MBM_REG0		0xFFC00000  /* mem base mask reg for CS0 -EPROM-4MB */
+#define CPU_BERR_BS		0xFF
+#define IP_BERR_BS		0xFF
+
+
+
+/*********************************
+*    SRAM_ONLY section 				*
+*********************************/
+
+#if MEMCFG == SRAM_ONLY
+
+#define MBA_REG1		0x00000000   /* physical mem bas addr fir CS-1 */
+#define MBM_REG1		0xFFF00000   /* mem bas mask for CS1 */
+
+/****************************************
+*    SDRAM_ONLY or SDRAM_N_SRAM section *
+****************************************/
+
+#elif MEMCFG == SDRAM_ONLY || MEMCFG == SDRAM_N_SRAM
+
+/* =======  128 MB DIMM section ===============*/
+
+#if DRAMSZ == MB128
+
+#define DRAM_BNK0_BASE		0x00000000	/* 0 MB */
+#define DRAM_BNK1_BASE		0x02000000	/* 32 MB */
+#define DRAM_BNK2_BASE		0x04000000	/* 64 MB */
+#define DRAM_BNK3_BASE		0x06000000	/* 96 MB */
+
+#define DRAM_BNK0_MASK		0xFE000000	/* masks for other banks are defined at the end */
+
+#define SDRAM_CR_BS		0xB90500FF | TRCD	/* SDRAM enable */
+#define SDRAM_DS_BS		0x390500FF | TRCD	/* SDRAM disable */
+#define SDRAM_PC_VAL		0xB90501A0 | TRCD	/* precharge value */
+#define SDRAM_RFRSH_CMD		0xB9050090 | TRCD	/* refresh command */
+#define SDRAM_MODE_REG		0xB9050080 | TRCD	/* mode register */
+
+#if MEMCFG == SDRAM_N_SRAM
+/* leave a gap of one SDRAM bank's worth of space between end of SDRAM and start of SRAM */
+#define MBA_REG1 		0x0A000000  	/* physical mem bas add for CS1 - 128MB + 32MB*/
+#define MBM_REG1 		0xFFF00000  	/* mem bas mask for CS1 - SRAM */
+#endif 						/* #if MEMCFG == SDRAM_N_SRAM */
+
+/* ========  32MB DIMM section  ================*/
+
+#elif DRAMSZ == MB32
+
+#define DRAM_BNK0_BASE		0x00000000   	/* 0 MB */
+#define DRAM_BNK1_BASE		0x00800000	/* 8 MB */
+#define DRAM_BNK2_BASE		0x01000000	/* 16 MB */
+#define DRAM_BNK3_BASE		0x01800000	/* 24 MB */
+
+#define DRAM_BNK0_MASK		0xFF800000	/* masks for other banks are defined at the end */
+
+#define SDRAM_CR_BS		0xB90500FF | TRCD	/* SDRAM enable */
+#define SDRAM_DS_BS		0x390500FF | TRCD	/* SDRAM disable */
+#define SDRAM_PC_VAL		0xB90501A0 | TRCD	/* precharge value */
+#define SDRAM_RFRSH_CMD		0xB9050090 | TRCD	/* refresh command */
+#define SDRAM_MODE_REG		0xB9050080 | TRCD	/* mode register */
+
+#if MEMCFG == SDRAM_N_SRAM
+/* leave a gap of one SDRAM bank's worth of space between end of SDRAM and start of SRAM */
+#define MBA_REG1		0x04000000  	/* physical mem bas add for CS1 - 32MB*/
+#define MBM_REG1		0xFFF00000  	/* mem bas mask for CS1 - SRAM */
+#endif 						/* MEMCFG == SDRAM_N_SRAM */
+
+/* =======  32MB or 64 MB SODIMM section ======== */
+
+#elif DRAMSZ == MB32SO
+
+#define DRAM_BNK0_BASE		0x00000000	/* 0 MB */
+#define DRAM_BNK1_BASE		0x01000000	/* 8 MB */
+#define DRAM_BNK2_BASE		0x02000000	/* 16 MB */
+#define DRAM_BNK3_BASE		0x03000000	/* 24 MB */
+
+#define DRAM_BNK0_MASK		0xFF000000	/* masks for other banks are defined at the end */
+
+#define SDRAM_CR_BS		0x890580FF | TRCD	/* SDRAM enable */
+#define SDRAM_DS_BS		0x090580FF | TRCD	/* SDRAM disable */
+#define SDRAM_PC_VAL		0x890580A0 | TRCD	/* Precharge value */
+#define SDRAM_RFRSH_CMD		0x89058090 | TRCD	/* Refresh command */
+#define SDRAM_MODE_REG		0x89058080 | TRCD	/* Mode register */
+
+#if MEMCFG == SDRAM_N_SRAM
+/* leave a gap of one SDRAM bank's worth of space between end of SDRAM and start of SRAM */
+#define MBA_REG1		0x04000000	/* physical mem bas add for CS1 - 32MB*/
+#define MBM_REG1		0xFFF00000	/* mem bas mask for CS1 - SRAM */
+#endif 						/* MEMCFG == SDRAM_N_SRAM */
+
+#endif /* DRAMSZ == MB32SO */
+
+/***************************************************
+*    SRAM_N_SDRAM section (assumes 1 MB SRAM)     *
+***************************************************/
+
+#elif MEMCFG == SRAM_N_SDRAM
+
+/* ========= 128MB DIMM section ============ */
+
+#if DRAMSZ == MB128
+
+#define MBA_REG1		0x00000000	/* physical mem bas addr for CS1 */
+#define MBM_REG1		0xFFF00000	/* mem nase mask for CS1 */
+
+/* leave a gap of one SDRAM bank's worth of space between end of SRAM and start of SDRAM */
+#define DRAM_BNK0_BASE		0x02000000	/* bank 0 at 32 MB */
+#define DRAM_BNK1_BASE		0x04000000	/* 64 MB */
+#define DRAM_BNK2_BASE		0x06000000	/* 96 MB */
+#define DRAM_BNK3_BASE		0x08000000	/* 128 MB */
+
+#define DRAM_BNK0_MASK		0xFE000000	/* masks for other banks are defined at the end */
+
+#define SDRAM_CR_BS		0xB95500FF | TRCD	/* SDRAM enable */
+#define SDRAM_DS_BS		0x395500FF | TRCD	/* SDRAM disable */
+#define SDRAM_PC_VAL		0xB95501A0 | TRCD	/* precharge value */
+#define SDRAM_RFRSH_CMD		0xB9550090 | TRCD	/* refresh command */
+#define SDRAM_MODE_REG		0xB9550080 | TRCD	/* mode register */
+
+
+/* ========= 32MB DIMM section ============ */
+
+#elif DRAMSZ == MB32
+
+#define MBA_REG1		0x00000000	/* physical mem bas addr for CS1 */
+#define MBM_REG1		0xFFF00000	/* mem nase mask for CS1 */
+
+/* leave a gap of one SDRAM bank's worth of space between end of SRAM and start of SDRAM */
+#define DRAM_BNK0_BASE		0x00800000
+#define DRAM_BNK1_BASE		0x01000000
+#define DRAM_BNK2_BASE		0x01800000
+#define DRAM_BNK3_BASE		0x02000000
+
+#define DRAM_BNK0_MASK		0xFF800000	/* masks for other banks are defined at the end */
+
+#define SDRAM_CR_BS		0xB95500FF | TRCD	/* SDRAM enable */
+#define SDRAM_DS_BS		0x395500FF | TRCD	/* SDRAM disable */
+#define SDRAM_PC_VAL		0xB95501A0 | TRCD	/* precharge value */
+#define SDRAM_RFRSH_CMD		0xB9550090 | TRCD	/* refresh command */
+#define SDRAM_MODE_REG		0xB9550080 | TRCD	/* mode register */
+
+/* =======  32MB or 64 MB SODIMM section ======== */
+
+#elif DRAMSZ == MB32SO
+
+#define MBA_REG1		0x00000000	/* physical mem bas addr for CS1 */
+#define MBM_REG1		0xFFF00000	/* mem nase mask for CS1 */
+
+/* leave a gap of one SDRAM bank's worth of space between end of SRAM and start of SDRAM */
+#define DRAM_BNK0_BASE		0x01000000
+#define DRAM_BNK1_BASE		0x02000000
+#define DRAM_BNK2_BASE		0x03000000
+#define DRAM_BNK3_BASE		0x04000000
+
+#define DRAM_BNK0_MASK		0xFF000000	/* masks for other banks are defined at the end */
+
+#define SDRAM_CR_BS		0x8955C0FF | TRCD	/* SDRAM enable */
+#define SDRAM_DS_BS		0x0955C0FF | TRCD	/* SDRAM disable */
+#define SDRAM_PC_VAL		0x8955C0A0 | TRCD	/* precharge value */
+#define	SDRAM_RFRSH_CMD		0x8955C090 | TRCD	/* refresh command */
+#define SDRAM_MODE_REG     	0x8955C080 | TRCD	/* mode register */
+
+#else
+#error "unrecognized dram size"
+#endif /* DRAMSZ */
+
+#else
+#error "unrecogized memory configuration parameter"
+#endif /* error */
+
+/* These settings apply to all types of SDRAM modules */
+#if MEMCFG != SRAM_ONLY
+
+#define DRAM_BNK1_MASK		DRAM_BNK0_MASK
+#define DRAM_BNK2_MASK		DRAM_BNK0_MASK
+#define DRAM_BNK3_MASK		DRAM_BNK0_MASK
+
+#define DRAM_RF_CNT_BS		0x00000000   /* Refresh Count Reg setting*/
+#define DRAM_RF_CMPR_BS		0x00000040   /* Refresh Compare Reg: fast expiration */
+
+#if MHZ == 50000000
+#define DRAM_RF_CMPR_SE_BS	0x000002E8   /* Refresh Compare Reg: standard expiration */
+#elif MHZ == 66500000
+#define DRAM_RF_CMPR_SE_BS	0x000003E0   /* Refresh Compare Reg: standard expiration */
+#elif	MHZ == 75000000
+#define DRAM_RF_CMPR_SE_BS	0x00000460   /* Refresh Compare Reg: standard expiration */
+#else
+#error "MHZ setting in the Makefile must be equal to 50000000, 66500000 or 75000000 "
+#endif
+
+#endif
+/* parameters for initialising the S134 board EEPROM */
+#define DESTRUCTIVE 			1
+#define NONDESTRUCTIVE 		0
+
+#endif /* __S334RAM__ */
+
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/s334ram.h idtlinux/arch/mips/idt-boards/rc32300/S334/boot/s334ram.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/s334ram.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/s334ram.h	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,836 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   IDT S334 SDRAM setup values.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef __S334RAM__
+#define __S334RAM__
+/******************************** D E F I N E S *******************************/
+
+#define SRAM_ONLY	1
+#define SDRAM_ONLY	2
+#define EDO_ONLY	3
+#define SRAM_N_SDRAM	4
+#define SRAM_N_EDO	5
+#define SDRAM_N_SRAM	6
+#define EDO_N_SRAM	7
+
+#define MB32	1
+#define MB64	2
+#define MB128	3
+#define MB32SO  4
+
+#define EP8	1
+#define EP32	2
+
+#define EXTU	1
+#define INTU	2
+
+#ifndef LED_BASE
+
+#if defined(EB332)
+#define	LED_BASE	PHYS_TO_K1(0x10000000)
+#define	LED_DIGIT0	0xC
+#define	LED_DIGIT1	0x8
+#define	LED_DIGIT2	0x4
+#define	LED_DIGIT3	0x0
+#define	LED_CLEAR	0x400
+#else
+#define	LED_BASE	PHYS_TO_K1(0x14000000)
+#define	LED_DIGIT0	0xf
+#define	LED_DIGIT1	0xb
+#define	LED_DIGIT2	0x7
+#define	LED_DIGIT3	0x3
+#define	LED_CLEAR	0x400
+#endif
+
+#endif
+
+#define SYS_BTA_CTRL            PHYS_TO_K1(0x18000000)
+#define SYS_ALT_CTRL            PHYS_TO_K1(0x18000004)
+#if MHZ < 67000000
+#warning : compiling for less than 67 MHz
+#define SYS_ALT_SETUP           0x00000003  
+#else
+#warning : compiling for more than 67 MHz
+#define SYS_ALT_SETUP           0x00000007   
+#endif
+#define	PORT_WIDTH_CONTROL	0xffffe200	/* port width control register address */
+#define	BTA_CONTROL		0xffffe204      /* was 0xffffe240 - hak 06-16-98 - BTA control register address */
+#define	BTA_SETUP		0x3fffffff      /* 3 turnaround cycles for all regions */
+
+#if EPRMPRTWD == EP8
+/*#define	PORT_SETUP		0xaaa22aaa       was 0xaaa82aaa - hak 06-16-98, today 22 is for boot prom and external UART 1-4-99 */
+#if defined(EB332)
+#define PORT_SETUP              0xaaa22aaa
+#else
+#define	PORT_SETUP		0xaa822aaa       /* changed for 8-bit wide NVRAM at physical 1200_0000: Upen-000530*/
+#endif /* EB332 */
+#elif EPRMPRTWD == EP32
+#define PORT_SETUP		0xaaa2aaaa	/* boot EPROM space port width = 32 bits */
+#else
+#error "illegal value for eprom port width"
+#endif
+
+#define MEM_CTL_BASE		PHYS_TO_K1(0x18000200)	/* base address of all (0-5) Memory Control Registers */
+#define MEM_BASE_BASE		PHYS_TO_K1(0x18000080)	/* base address of 2 (0-1) Base Address Registers */
+#define R32134_IREG_BASE		PHYS_TO_K1(0x18000000)	/* all R32134 internal registers' base address */
+
+/* 
+** b14:13=>01=PROM;b12=>1= do not assert CS during writes; b11:10=>00=8 bit port 
+** b09:05=>0A=10 wait states; b04:00=>0A= 10 wait states
+*/
+
+
+/*#define MCR_CS0_BS		0x31ef31ef*/
+#define MCR_CS0_BS		0x30843084
+
+/* 
+** b14:13=>00=SRAM;b12=>0= assert CS during writes; b11:10=>10=32 bit port 
+** b09:05=>FF=31 wait states; b04:00=>FF= 31 wait states.
+** NOTE: wait states should be tuned.
+*/
+
+
+/*#define MCR_CS1_BS		0x28e728e7*/
+#define MCR_CS1_BS		0x28a528a5
+
+#define MCR_CS2_BS		0xa0e7a0e7
+
+#define MCR_CS3_BS		0xa0e7a0e7
+
+#define MCR_CS4_BS		0xa0e7a0e7     /* S334 LED */
+
+
+/* 
+** b14:13=>01=I Type;b12=>0= assert CS during writes; b11:10=>00=8 bit port 
+** b09:05=>FF=31 wait states; b04:00=>FF= 31 wait states
+*/
+
+#define MCR_CS5_BS		0xa0E7a0E7
+/*#define MCR_CS5_BS		0x21EF21EF*/
+
+/*
+** physical memory base address register value for Chip Select 0 - EPROM
+** NOTE: for starters see if you can just set the default value: 0x1FC00000
+*/
+#define MBA_REG0		0x1FC00000
+
+/*
+** memory base mask register value for Chip Select 0 - EPROM - 4MB
+*/
+#define MBM_REG0		0xFFC00000
+
+
+#define CPU_BERR_BS		0xFF
+#define IP_BERR_BS		0xFF
+
+
+
+#if MEMCFG == SRAM_ONLY
+/*
+** physical memory base address register value for Chip Select 1 - SRAM
+*/
+#define MBA_REG1		0x00000000
+
+/*
+** memory base mask register value for Chip Select 1 - SRAM - 1MB
+*/
+#define MBM_REG1		0xFFF00000
+
+#elif MEMCFG == SDRAM_ONLY || MEMCFG == SDRAM_N_SRAM
+/*
+*************************************
+** SDRAM_ONLY or SDRAM_N_SRAM section
+*************************************
+*/
+
+#define APATTERN 0xa5a5a5a5
+
+#if DRAMSZ == MB128
+/*
+===============================
+== 128MB section
+===============================
+*/
+/*
+** DRAM BANK0 BASE.  Starting Bank at 0MB:
+*/
+#define DRAM_BNK0_BASE		0x00000000
+/*
+** DRAM BANK1 BASE. 2nd bank at 32MB:
+*/
+#define DRAM_BNK1_BASE		0x02000000
+/*
+** DRAM BANK2 BASE. 3rd bank at 64MB:
+*/
+#define DRAM_BNK2_BASE		0x04000000
+/*
+** DRAM BANK3 BASE. 4th bank at 96MB:
+*/
+#define DRAM_BNK3_BASE		0x06000000
+/*
+** DRAM Bank 0 Mask
+*/
+#define DRAM_BNK0_MASK		0xFFF00000
+/*
+** DRAM Bank 1 Mask
+*/
+#define DRAM_BNK1_MASK		DRAM_BNK0_MASK
+/*
+** DRAM Bank 2 Mask
+*/
+#define DRAM_BNK2_MASK		DRAM_BNK0_MASK
+/*
+** DRAM Bank 3 Mask
+*/
+#define DRAM_BNK3_MASK		DRAM_BNK0_MASK
+/*
+** SDRAM ENABLE Settings
+*/
+#define SDRAM_CR_BS		0xb95500FF	/* old: 0x9EFBOOFF */
+/*
+** SDRAM DISABLE Settings
+*/
+#define SDRAM_DS_BS		0x2AF800FF
+/*
+** Precharge Value
+*/
+#define SDRAM_PC_VAL		0xb95501a0
+/*
+** Refresh Cmd
+*/
+#define	SDRAM_RFRSH_CMD		0xb9550090
+/*
+** Mode Register
+*/
+#define SDRAM_MODE_REG		0xAAF80080
+
+#if MEMCFG == SDRAM_N_SRAM
+/*
+** physical memory base address register value for Chip Select 1 - SRAM
+** at 128MB:
+*/
+#define MBA_REG1		0x08000000
+
+/*
+** memory base mask register value for Chip Select 1 - SRAM - 1MB
+*/
+#define MBM_REG1		0xFFF00000
+
+#endif /* #if MEMCFG == SDRAM_N_SRAM */
+
+#elif DRAMSZ == MB32
+/*
+===============================
+== 32MB section
+===============================
+*/
+/*
+** DRAM BANK0 BASE.  Starting Bank at 0MB:
+*/
+#define DRAM_BNK0_BASE		0x00000000
+/*
+** DRAM BANK1 BASE. 2nd bank at 8MB:
+*/
+#define DRAM_BNK1_BASE		0x00800000
+/*
+** DRAM BANK2 BASE. 3rd bank at 16MB:
+*/
+#define DRAM_BNK2_BASE		0x01000000
+/*
+** DRAM BANK3 BASE. 4th bank at 24MB:
+*/
+#define DRAM_BNK3_BASE		0x01800000
+/*
+** DRAM Bank 0 Mask
+*/
+#define DRAM_BNK0_MASK		0xFF800000
+/*
+** DRAM Bank 1 Mask
+*/
+#define DRAM_BNK1_MASK		DRAM_BNK0_MASK
+/*
+** DRAM Bank 2 Mask
+*/
+#define DRAM_BNK2_MASK		DRAM_BNK0_MASK
+/*
+** DRAM Bank 3 Mask
+*/
+#define DRAM_BNK3_MASK		DRAM_BNK0_MASK
+/*
+** SDRAM ENABLE Settings
+*/
+#define SDRAM_CR_BS		0xB95500FF	/* 11:18:99 0xBAF800FF */
+/*
+** SDRAM DISABLE Settings
+*/
+#define SDRAM_DS_BS		0x395500FF	/* 11:18:99 0x3AF800FF */
+/*
+** Precharge Value
+*/
+#define SDRAM_PC_VAL		0xB95501A0	/* 11:18:99 0xBAF801A0 */
+/*
+** Refresh Cmd
+*/
+#define	SDRAM_RFRSH_CMD		0xB9550090	/* 11:18:99 0xBAF80090 */
+/*
+** Mode Register
+*/
+#define SDRAM_MODE_REG		0xB9550080	/* 11:18:99 0xBAF80080 */
+/*
+** Refresh Count Register Bit Settings
+*/
+#define DRAM_RF_CNT_BS		0x00000000
+/*
+** Refresh Compare Register Bit Settings
+*/
+#define DRAM_RF_CMPR_BS		0x00000040
+/*
+** Refresh Compare Register Bit Settings for Slow Expiration
+*/
+#define DRAM_RF_CMPR_SE_BS	0x000002A0
+
+#if MEMCFG == SDRAM_N_SRAM
+/*
+** physical memory base address register value for Chip Select 1 - SRAM
+** at 32MB:
+*/
+#define MBA_REG1		0x04000000
+
+/*
+** memory base mask register value for Chip Select 1 - SRAM - 1MB
+*/
+#define MBM_REG1		0xFFF00000
+#endif /* MEMCFG == SDRAM_N_SRAM */
+
+#elif DRAMSZ == MB32SO
+/*
+===============================
+== 32MB SODIMM section
+===============================
+*/
+/*
+** DRAM BANK0 BASE.  Starting Bank at 0MB:
+*/
+#define DRAM_BNK0_BASE		0x03000000
+/*
+** DRAM BANK1 BASE. 2nd bank at 8MB:
+*/
+#define DRAM_BNK1_BASE		0x02000000
+/*
+** DRAM BANK2 BASE. 3rd bank at 16MB:
+*/
+#define DRAM_BNK2_BASE		0x01000000
+/*
+** DRAM BANK3 BASE. 4th bank at 24MB:
+*/
+#define DRAM_BNK3_BASE		0x00000000
+/*
+** DRAM Bank 0 Mask
+*/
+#define DRAM_BNK0_MASK		0xFF000000
+/*
+** DRAM Bank 1 Mask
+*/
+#define DRAM_BNK1_MASK		DRAM_BNK0_MASK
+/*
+** DRAM Bank 2 Mask
+*/
+#define DRAM_BNK2_MASK		DRAM_BNK0_MASK
+/*
+** DRAM Bank 3 Mask
+*/
+#define DRAM_BNK3_MASK		DRAM_BNK0_MASK
+/*
+** SDRAM ENABLE Settings
+*/
+/*#define SDRAM_CR_BS		0x8E78C0FF */   /* 11:18:99 0xBAF800FF */
+#define SDRAM_CR_BS		0x895580FF
+/*
+** SDRAM DISABLE Settings
+*/
+/* #define SDRAM_DS_BS		0x0E78C0FF*/	/* 11:18:99 0x3AF800FF */
+#define SDRAM_DS_BS		0x095580FF
+/*
+** Precharge Value
+*/
+/* #define SDRAM_PC_VAL		0x8E78C0A0*/	/* 11:18:99 0xBAF801A0 */
+#define SDRAM_PC_VAL		0x895580A0
+/*
+** Refresh Cmd
+*/
+/* #define	SDRAM_RFRSH_CMD	  0x8E78C090*/	/* 11:18:99 0xBAF80090 */
+#define	SDRAM_RFRSH_CMD	        0x89558090
+/*
+** Mode Register
+*/
+/*#define SDRAM_MODE_REG	0x8E78C080*/	/* 11:18:99 0xBAF80080 */
+#define SDRAM_MODE_REG	        0x89558080
+/*
+** Refresh Count Register Bit Settings
+*/
+#define DRAM_RF_CNT_BS		0x00000000
+/*
+** Refresh Compare Register Bit Settings
+*/
+#define DRAM_RF_CMPR_BS		0x00000040
+/*
+** Refresh Compare Register Bit Settings for Slow Expiration
+*/
+#define DRAM_RF_CMPR_SE_BS	0x000002A0
+
+#if MEMCFG == SDRAM_N_SRAM
+/*
+** physical memory base address register value for Chip Select 1 - SRAM
+** at 32MB:
+*/
+#define MBA_REG1		0x04000000
+
+/*
+** memory base mask register value for Chip Select 1 - SRAM - 1MB
+*/
+#define MBM_REG1		0xFFF00000
+#endif /* MEMCFG == SDRAM_N_SRAM */
+
+#endif /* DRAMSZ == MB32SO */
+
+#elif MEMCFG == EDO_ONLY || MEMCFG == EDO_N_SRAM
+/*
+*****************************************
+** EDO only section or EDO_N_SRAM section
+*****************************************
+*/
+/*
+** DRAM BANK0 BASE.  Starting Bank at 0MB
+*/
+#define DRAM_BNK0_BASE		0x00000000
+/*
+** DRAM BANK1 BASE. 2nd bank at 16MB
+*/
+#define DRAM_BNK1_BASE		0x01000000
+/*
+** DRAM BANK2 BASE. 3rd bank at 32MB:
+*/
+#define DRAM_BNK2_BASE		0x02000000
+/*
+** DRAM BANK3 BASE. 4th bank at 48MB:
+*/
+#define DRAM_BNK3_BASE		0x03000000
+/*
+** DRAM Bank 0 Mask
+*/
+#define DRAM_BNK0_MASK		0xFF000000
+/*
+** DRAM Bank 1 Mask
+*/
+#define DRAM_BNK1_MASK		DRAM_BNK0_MASK
+/*
+** DRAM Bank 2 Mask
+*/
+#define DRAM_BNK2_MASK		DRAM_BNK0_MASK
+/*
+** DRAM Bank 3 Mask
+*/
+#define DRAM_BNK3_MASK		DRAM_BNK0_MASK
+
+/*
+** EDO control register bit settings
+*/
+
+#define EDO_CR_BS		0x80000BA8	/* 0x80000E02 */
+
+/*
+** Refresh Count Register Bit Settings
+*/
+#define DRAM_RF_CNT_BS		0x00000000
+/*
+** Refresh Compare Register Bit Settings
+*/
+#define DRAM_RF_CMPR_BS		0x00000040
+/*
+** Refresh Compare Register Bit Settings for Slow Expiration
+*/
+#define DRAM_RF_CMPR_SE_BS	0x000000A0
+
+/*
+** EDO control register bit settings
+*/
+
+#define EDO_CR_BS		0x80000BA8	/* 0x80000E02 */
+
+#if MEMCFG == EDO_N_SRAM
+/*
+** physical memory base address register value for Chip Select 1 - SRAM
+** at 64MB:
+*/
+#define MBA_REG1		0x04000000
+
+/*
+** memory base mask register value for Chip Select 1 - SRAM - 1MB
+*/
+#define MBM_REG1		0xFFF00000
+#endif /* MEMCFG == EDO_N_SRAM */
+
+#elif MEMCFG == SRAM_N_SDRAM
+
+#define APATTERN 0xa5a5a5a5
+
+/*
+*******************************
+** SRAM and SDRAM section
+*******************************
+*/
+#if DRAMSZ == MB128
+/*
+===============================
+== 128MB section
+===============================
+*/
+/*
+** physical memory base address register value for Chip Select 1 - SRAM
+*/
+#define MBA_REG1		0x00000000
+
+/*
+** memory base mask register value for Chip Select 1 - SRAM - 1MB
+*/
+#define MBM_REG1		0xFFF00000
+
+/*
+** DRAM BANK0 BASE.  Starting Bank at 32MB:
+*/
+#define DRAM_BNK0_BASE		0x02000000
+/*
+** DRAM BANK1 BASE. 2nd bank at 64MB:
+*/
+#define DRAM_BNK1_BASE		0x04000000
+/*
+** DRAM BANK2 BASE. 3rd bank at 96MB:
+*/
+#define DRAM_BNK2_BASE		0x06000000
+/*
+** DRAM BANK3 BASE. 4th bank at 128MB:
+*/
+#define DRAM_BNK3_BASE		0x08000000
+/*
+** DRAM Bank 0 Mask
+*/
+#define DRAM_BNK0_MASK		0xFE000000
+/*
+** DRAM Bank 1 Mask
+*/
+#define DRAM_BNK1_MASK		DRAM_BNK0_MASK
+/*
+** DRAM Bank 2 Mask
+*/
+#define DRAM_BNK2_MASK		DRAM_BNK0_MASK
+/*
+** DRAM Bank 3 Mask
+*/
+#define DRAM_BNK3_MASK		DRAM_BNK0_MASK
+/*
+** SDRAM ENABLE Settings
+*/
+#define SDRAM_CR_BS		0xAAF800FF	/* old: 0x9EFBOOFF */
+/*
+** SDRAM DISABLE Settings
+*/
+#define SDRAM_DS_BS		0x2AF800FF
+/*
+** Precharge Value
+*/
+#define SDRAM_PC_VAL		0xAAF801A0
+/*
+** Refresh Cmd
+*/
+#define	SDRAM_RFRSH_CMD		0xAAF80090
+/*
+** Mode Register
+*/
+#define SDRAM_MODE_REG		0xAAF80080
+/*
+** Refresh Count Register Bit Settings
+*/
+#define DRAM_RF_CNT_BS		0x00000000
+/*
+** Refresh Compare Register Bit Settings
+*/
+#define DRAM_RF_CMPR_BS		0x00000040
+/*
+** Refresh Compare Register Bit Settings for Slow Expiration
+*/
+#define DRAM_RF_CMPR_SE_BS	0x000000A0
+
+#elif DRAMSZ == MB32
+/*
+===============================
+== 32MB section
+===============================
+*/
+
+/*
+** physical memory base address register value for Chip Select 1 - SRAM
+*/
+#define MBA_REG1		0x00000000
+
+/*
+** memory base mask register value for Chip Select 1 - SRAM - 1MB
+*/
+#define MBM_REG1		0xFFF00000
+
+/*
+** DRAM BANK0 BASE.  Starting Bank at 8MB:
+*/
+#define DRAM_BNK0_BASE		0x00800000
+/*
+** DRAM BANK1 BASE. 2nd bank at 16MB:
+*/
+#define DRAM_BNK1_BASE		0x01000000
+/*
+** DRAM BANK2 BASE. 3rd bank at 24MB:
+*/
+#define DRAM_BNK2_BASE		0x01800000
+/*
+** DRAM BANK3 BASE. 4th bank at 64MB:
+*/
+#define DRAM_BNK3_BASE		0x02000000
+/*
+** DRAM Bank 0 Mask
+*/
+#define DRAM_BNK0_MASK		0xFF800000
+/*
+** DRAM Bank 1 Mask
+*/
+#define DRAM_BNK1_MASK		DRAM_BNK0_MASK
+/*
+** DRAM Bank 2 Mask
+*/
+#define DRAM_BNK2_MASK		DRAM_BNK0_MASK
+/*
+** DRAM Bank 3 Mask
+*/
+#define DRAM_BNK3_MASK		DRAM_BNK0_MASK
+/*
+** SDRAM ENABLE Settings
+*/
+#define SDRAM_CR_BS		0xB95500FF	/* 11:18:99 0xBAF800FF */
+/*
+** SDRAM DISABLE Settings
+*/
+#define SDRAM_DS_BS		0x395500FF	/* 11:18:99 0x3AF800FF */
+/*
+** Precharge Value
+*/
+#define SDRAM_PC_VAL		0xB95501A0	/* 11:18:99 0xBAF801A0 */
+/*
+** Refresh Cmd
+*/
+#define	SDRAM_RFRSH_CMD		0xB9550090	/* 11:18:99 0xBAF80090 */
+/*
+** Mode Register
+*/
+#define SDRAM_MODE_REG		0xB9550080	/* 11:18:99 0xBAF80080 */
+/*
+** Refresh Count Register Bit Settings
+*/
+#define DRAM_RF_CNT_BS		0x00000000
+/*
+** Refresh Compare Register Bit Settings
+*/
+#define DRAM_RF_CMPR_BS		0x00000040
+/*
+** Refresh Compare Register Bit Settings for Slow Expiration
+*/
+#define DRAM_RF_CMPR_SE_BS	0x000001A0	/* 11:18:99 0x000000A0 */
+
+#elif DRAMSZ == MB32SO
+/*
+===============================
+== 32MB section
+===============================
+*/
+
+/*
+** physical memory base address register value for Chip Select 1 - SRAM
+*/
+#define MBA_REG1		0x00000000
+
+/*
+** memory base mask register value for Chip Select 1 - SRAM - 1MB
+*/
+#define MBM_REG1		0xFFF00000
+
+/*
+** DRAM BANK0 BASE.  Starting Bank at 8MB:
+*/
+#define DRAM_BNK0_BASE		0x04000000
+/*
+** DRAM BANK1 BASE. 2nd bank at 16MB:
+*/
+#define DRAM_BNK1_BASE		0x03000000
+/*
+** DRAM BANK2 BASE. 3rd bank at 24MB:
+*/
+#define DRAM_BNK2_BASE		0x02000000
+/*
+** DRAM BANK3 BASE. 4th bank at 64MB:
+*/
+#define DRAM_BNK3_BASE		0x01000000
+/*
+** DRAM Bank 0 Mask
+*/
+#define DRAM_BNK0_MASK		0xFF000000
+/*
+** DRAM Bank 1 Mask
+*/
+#define DRAM_BNK1_MASK		DRAM_BNK0_MASK
+/*
+** DRAM Bank 2 Mask
+*/
+#define DRAM_BNK2_MASK		DRAM_BNK0_MASK
+/*
+** DRAM Bank 3 Mask
+*/
+#define DRAM_BNK3_MASK		DRAM_BNK0_MASK
+/*
+** SDRAM ENABLE Settings
+*/
+/* #define SDRAM_CR_BS		0x8E78C0FF*/	/* 11:18:99 0xBAF800FF */
+#define SDRAM_CR_BS		0x8955C0FF
+/*
+** SDRAM DISABLE Settings
+*/
+/* #define SDRAM_DS_BS		0x0E78C0FF*/	/* 11:18:99 0x3AF800FF */
+#define SDRAM_DS_BS		0x0955C0FF
+/*
+** Precharge Value
+*/
+/* #define SDRAM_PC_VAL		0x8E78C0A0*/	/* 11:18:99 0xBAF801A0 */
+#define SDRAM_PC_VAL		0x8955C0A0
+/*
+** Refresh Cmd
+*/
+/*#define	SDRAM_RFRSH_CMD	  0x8E78C090*/	/* 11:18:99 0xBAF80090 */
+#define	SDRAM_RFRSH_CMD	        0x8955C090
+/*
+** Mode Register
+*/
+/*#define SDRAM_MODE_REG      0x8E78C080*/	/* 11:18:99 0xBAF80080 */
+#define SDRAM_MODE_REG          0x8955C080
+/*
+** Refresh Count Register Bit Settings
+*/
+#define DRAM_RF_CNT_BS		0x00000000
+/*
+** Refresh Compare Register Bit Settings
+*/
+#define DRAM_RF_CMPR_BS		0x00000040
+/*
+** Refresh Compare Register Bit Settings for Slow Expiration
+*/
+#define DRAM_RF_CMPR_SE_BS	0x000001A0	/* 11:18:99 0x000000A0 */
+
+#else
+#error "unrecognized dram size"
+#endif /* DRAMSZ */
+
+#elif MEMCFG == SRAM_N_EDO
+/*
+** physical memory base address register value for Chip Select 1 - SRAM
+*/
+#define MBA_REG1		0x00000000
+
+/*
+** memory base mask register value for Chip Select 1 - SRAM - 1MB
+*/
+#define MBM_REG1		0xFFF00000
+
+/*
+** DRAM BANK0 BASE.  Starting Bank at 16MB
+*/
+#define DRAM_BNK0_BASE		0x01000000
+/*
+** DRAM BANK1 BASE. 2nd bank at 32MB
+*/
+#define DRAM_BNK1_BASE		0x02000000
+/*
+** DRAM BANK2 BASE. 3rd bank at 48MB:
+*/
+#define DRAM_BNK2_BASE		0x03000000
+/*
+** DRAM BANK3 BASE. 4th bank at 64MB:
+*/
+#define DRAM_BNK3_BASE		0x04000000
+/*
+** DRAM Bank 0 Mask
+*/
+#define DRAM_BNK0_MASK		0xFF000000
+/*
+** DRAM Bank 1 Mask
+*/
+#define DRAM_BNK1_MASK		DRAM_BNK0_MASK
+/*
+** DRAM Bank 2 Mask
+*/
+#define DRAM_BNK2_MASK		DRAM_BNK0_MASK
+/*
+** DRAM Bank 3 Mask
+*/
+#define DRAM_BNK3_MASK		DRAM_BNK0_MASK
+
+/*
+** EDO control register bit settings
+*/
+#define EDO_CR_BS		0x80000BA8	/* 0x80000E02 */
+
+/*
+** Refresh Count Register Bit Settings
+*/
+#define DRAM_RF_CNT_BS		0x00000000
+/*
+** Refresh Compare Register Bit Settings
+*/
+#define DRAM_RF_CMPR_BS		0x00000040
+/*
+** Refresh Compare Register Bit Settings for Slow Expiration
+*/
+#define DRAM_RF_CMPR_SE_BS	0x000000A0
+
+#else
+#error "unrecogized memory configuration parameter"
+#endif /* error */
+
+/* parameters for initialising the S134 board EEPROM */
+#define DESTRUCTIVE 1
+#define NONDESTRUCTIVE 0
+
+#endif /* __S334RAM__ */
+
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/s364.h idtlinux/arch/mips/idt-boards/rc32300/S334/boot/s364.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/s364.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/s364.h	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,155 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   IDT S334 definitions
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#ifndef __S364134__
+#define __S364134__
+/******************************** D E F I N E S *******************************/
+#ifndef GPIO_BASE
+#ifdef S355
+#define GPIO_BASE PHYS_TO_K1(0x18040000)
+#else
+#define GPIO_BASE PHYS_TO_K1(0x18000600)
+#endif
+#endif
+/*
+** following defines simple and uniform to save and restore context
+** when enrtering and leaving as assemblu language program when memory
+** and registers are both premiunm.
+*/
+#define SAVE_CNTXT    \
+  subu  sp,64;    \
+  sw  t0,60(sp);  \
+  sw  t1,56(sp);  \
+  sw  t2,52(sp);  \
+  sw  t3,48(sp);  \
+  sw  t4,44(sp);  \
+  sw  t5,40(sp);  \
+  sw  t6,36(sp);  \
+  sw  t7,32(sp);  \
+  sw  t8,28(sp);  \
+  sw  t9,24(sp);  \
+  sw  a0,20(sp);  \
+  sw  a1,16(sp);  \
+  sw  a2,12(sp);  \
+  sw  a3,8(sp); \
+  sw  ra,4(sp)
+
+#define RSTR_CNTXT    \
+  lw  t0,60(sp);  \
+  lw  t1,56(sp);  \
+  lw  t2,52(sp);  \
+  lw  t3,48(sp);  \
+  lw  t4,44(sp);  \
+  lw  t5,40(sp);  \
+  lw  t6,36(sp);  \
+  lw  t7,32(sp);  \
+  lw  t8,28(sp);  \
+  lw  t9,24(sp);  \
+  lw  a0,20(sp);  \
+  lw  a1,16(sp);  \
+  lw  a2,12(sp);  \
+  lw  a3,8(sp); \
+  lw  ra,4(sp); \
+  add sp,64
+
+/*
+** Following define is to specify a maximum value for a software
+** busy wait counter.
+*/
+
+#define LP_CNT_100NS  1000      /* set this based on processor speed */
+#define LP_CNT_3S     1000000   /* set this based on processor speed */
+
+/*
+** Following are other common timer definitions.
+*/
+#ifdef S355
+#define TIMER_BASE    PHYS_TO_K1(0x18028000)  
+#define TIMEOUT_COUNT 0x00000FFF
+#else
+#define TIMER_BASE    PHYS_TO_K1(0x18000700)  
+#endif
+#define ENABLE_TIMER  0x1
+#define DISABLE_TIMER 0x0
+#define BIG_VALUE     0xFFFFFFFF
+
+#ifdef S355
+/* There is no DISPLAY on 355 boards*/
+#elif defined(S334)
+/*
+** following few lines define a macro DISPLAY
+** which is used to write a set of 4 characters
+** onto the S334 LED.
+*/
+
+#if defined(EB332)
+#define LED_BASE      PHYS_TO_K1(0x10000000)
+#define LED_DIGIT0    0xc
+#define LED_DIGIT1    0x8
+#define LED_DIGIT2    0x4
+#define LED_DIGIT3    0x0
+
+#define LED_CLEAR     0x400
+
+#else
+#define LED_BASE      PHYS_TO_K1(0x14000000)
+#define LED_DIGIT0    0xf
+#define LED_DIGIT1    0xb
+#define LED_DIGIT2    0x7
+#define LED_DIGIT3    0x3
+
+#define LED_CLEAR     0x400
+
+#endif
+
+#define DISPLAY(d0, d1, d2, d3)     \
+        li    t6, LED_BASE                    ;\
+        lb    t7, LED_CLEAR(t6)               ;\
+              nop                             ;\
+        li    t7, (d0) & 0xff                 ;\
+        sb    t7, LED_DIGIT0(t6)              ;\
+        li    t7, (d1) & 0xff                 ;\
+        sb    t7, LED_DIGIT1(t6)              ;\
+        li    t7, (d2) & 0xff                 ;\
+        sb    t7, LED_DIGIT2(t6)              ;\
+        li    t7, (d3) & 0xff                 ;\
+        sb    t7, LED_DIGIT3(t6)
+
+#define LEDCLEAR()              \
+        li    t6, LED_BASE                    ;\
+        lb    t7, LED_CLEAR(t6)               ;\
+              nop
+
+#endif
+
+#define DESTRUCTIVE     1
+#define NONDESTRUCTIVE  0
+
+#endif
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/uart16550.c idtlinux/arch/mips/idt-boards/rc32300/S334/boot/uart16550.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/uart16550.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/uart16550.c	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,178 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   UART code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+
+#define RC32334_REG_BASE   0xb8000000
+#ifdef __MIPSEB__
+#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
+#else
+#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
+#endif
+
+#define BASE		RC32300_UART0_BASE
+
+#define MAX_BAUD	(CONFIG_IDT_BOARD_FREQ / 16)
+#define REG_OFFSET	0x4
+
+/* === CONFIG === */
+
+/*
+ * #define BASE			0xb2001000
+ * #define MAX_BAUD		1152000
+ * #define REG_OFFSET		0x10
+ */
+#if (!defined(BASE) || !defined(MAX_BAUD) || !defined(REG_OFFSET))
+#error You must define BASE, MAX_BAUD and REG_OFFSET in the Makefile.
+#endif
+
+#ifndef INIT_SERIAL_PORT
+#define INIT_SERIAL_PORT	1
+#endif
+
+#ifndef DEFAULT_BAUD
+//#define DEFAULT_BAUD		UART16550_BAUD_115200
+#define DEFAULT_BAUD		UART16550_BAUD_9600
+#endif
+#ifndef DEFAULT_PARITY
+#define DEFAULT_PARITY		UART16550_PARITY_NONE
+#endif
+#ifndef DEFAULT_DATA
+#define DEFAULT_DATA		UART16550_DATA_8BIT
+#endif
+#ifndef DEFAULT_STOP
+#define DEFAULT_STOP		UART16550_STOP_1BIT
+#endif
+
+/* === END OF CONFIG === */
+
+typedef         unsigned char uint8;
+typedef         unsigned int  uint32;
+
+#define         UART16550_BAUD_2400             2400
+#define         UART16550_BAUD_4800             4800
+#define         UART16550_BAUD_9600             9600
+#define         UART16550_BAUD_19200            19200
+#define         UART16550_BAUD_38400            38400
+#define         UART16550_BAUD_57600            57600
+#define         UART16550_BAUD_115200           115200
+
+#define         UART16550_PARITY_NONE           0
+#define         UART16550_PARITY_ODD            0x08
+#define         UART16550_PARITY_EVEN           0x18
+#define         UART16550_PARITY_MARK           0x28
+#define         UART16550_PARITY_SPACE          0x38
+
+#define         UART16550_DATA_5BIT             0x0
+#define         UART16550_DATA_6BIT             0x1
+#define         UART16550_DATA_7BIT             0x2
+#define         UART16550_DATA_8BIT             0x3
+
+#define         UART16550_STOP_1BIT             0x0
+#define         UART16550_STOP_2BIT             0x4
+
+/* register offset */
+#define		OFS_RCV_BUFFER		(0*REG_OFFSET)
+#define		OFS_TRANS_HOLD		(0*REG_OFFSET)
+#define		OFS_SEND_BUFFER		(0*REG_OFFSET)
+#define		OFS_INTR_ENABLE		(1*REG_OFFSET)
+#define		OFS_INTR_ID		(2*REG_OFFSET)
+#define		OFS_DATA_FORMAT		(3*REG_OFFSET)
+#define		OFS_LINE_CONTROL	(3*REG_OFFSET)
+#define		OFS_MODEM_CONTROL	(4*REG_OFFSET)
+#define		OFS_RS232_OUTPUT	(4*REG_OFFSET)
+#define		OFS_LINE_STATUS		(5*REG_OFFSET)
+#define		OFS_MODEM_STATUS	(6*REG_OFFSET)
+#define		OFS_RS232_INPUT		(6*REG_OFFSET)
+#define		OFS_SCRATCH_PAD		(7*REG_OFFSET)
+
+#define		OFS_DIVISOR_LSB		(0*REG_OFFSET)
+#define		OFS_DIVISOR_MSB		(1*REG_OFFSET)
+
+#define		UART16550_READ(y)    (*((volatile uint8*)(BASE + y)))
+#define		UART16550_WRITE(y, z)  ((*((volatile uint8*)(BASE + y))) = z)
+
+static void Uart16550Init(uint32 baud, uint8 data, uint8 parity, uint8 stop)
+{
+	/* disable interrupts */
+	UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
+	UART16550_WRITE(OFS_INTR_ENABLE, 0);
+
+	/* set up baud rate */
+	{
+		uint32 divisor;
+
+		/* set DIAB bit */
+		UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
+
+		/* set divisor */
+		divisor = MAX_BAUD / baud;
+		UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
+		UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00)>>8);
+
+		/* clear DIAB bit */
+		UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
+	}
+
+	/* set data format */
+	UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
+}
+
+
+void
+putc_init(void)
+{
+#if INIT_SERIAL_PORT
+	Uart16550Init(DEFAULT_BAUD, DEFAULT_DATA, DEFAULT_PARITY, DEFAULT_STOP);
+#endif
+}
+
+void
+putc(unsigned char c)
+{
+	while ((UART16550_READ(OFS_LINE_STATUS) &0x20) == 0);
+	UART16550_WRITE(OFS_SEND_BUFFER, c);
+}
+
+#if 0
+unsigned char
+getc(void)
+{
+	while((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
+	return UART16550_READ(OFS_RCV_BUFFER);
+}
+
+int
+tstc(void)
+{
+	return((UART16550_READ(OFS_LINE_STATUS) & 0x01) != 0);
+}
+#endif
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/zImage.lds idtlinux/arch/mips/idt-boards/rc32300/S334/boot/zImage.lds
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/zImage.lds	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/zImage.lds	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,31 @@
+OUTPUT_ARCH(mips)
+ENTRY(zstartup)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = 0x80800000;
+  .init          : { *(.init)		} =0
+  .text      :
+  {
+    _ftext = . ;
+    *(.text)
+    *(.rodata)
+    *(.rodata1)
+   . = ALIGN(4096);
+    input_data = .;
+    arch/mips/idt-boards/rc32300/S334/boot/piggy.o
+    input_data_end = .;
+   . = ALIGN(4096);
+    *(.gnu.warning)
+  } =0
+
+  .reginfo : { *(.reginfo) }
+
+   . = 0x800A0000;
+  __bss_start = .;
+  .bss       :
+  {
+   *(.bss)
+  _end = . ;
+  }
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/idtIRQ.S idtlinux/arch/mips/idt-boards/rc32300/S334/idtIRQ.S
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/idtIRQ.S	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/idtIRQ.S	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,68 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Interrupt dispatcher code for IDT boards
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ *
+ **************************************************************************
+ */
+				
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
+
+	.text
+	.set	noreorder
+	.set	noat
+	.align	5
+	NESTED(rc32300_IRQ, PT_SIZE, sp)
+	SAVE_ALL
+	CLI
+
+	.set	at
+	.set	noreorder
+
+	mfc0    t0, CP0_CAUSE
+	move	a1, sp
+								  
+	/* check for r4k counter/timer IRQ. */
+	
+	andi    t1, t0, CAUSEF_IP7
+	beqz    t1, 1f
+	nop
+
+	jal     idt_timer_interrupt
+	li	a0, 7
+	j	ret_from_irq
+	nop
+1:
+	jal	rc32300_irqdispatch
+	move	a0, t0
+	j	ret_from_irq
+	nop
+
+	END(rc32300_IRQ)
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/irq.c idtlinux/arch/mips/idt-boards/rc32300/S334/irq.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/irq.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/irq.c	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,429 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *	RC32334 interrupt routines.
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *		stevel@mvista.com or source@mvista.com
+ *
+ *  This program is free software; you can redistribute	 it and/or modify it
+ *  under  the terms of	 the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the	License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED	  ``AS	IS'' AND   ANY	EXPRESS OR IMPLIED
+ *  WARRANTIES,	  INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO	EVENT  SHALL   THE AUTHOR  BE	 LIABLE FOR ANY	  DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED	  TO, PROCUREMENT OF  SUBSTITUTE GOODS	OR SERVICES; LOSS OF
+ *  USE, DATA,	OR PROFITS; OR	BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN	 CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/delay.h>
+
+#include <asm/bitops.h>
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+#include <asm/idt-boards/rc32300/rc32300.h>
+
+
+#undef DEBUG_IRQ
+//#define DEBUG_IRQ
+#ifdef DEBUG_IRQ
+/* note: prints function name for you */
+#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
+#else
+#define DPRINTK(fmt, args...)
+#endif
+
+extern asmlinkage void rc32300_IRQ(void);
+
+static unsigned int startup_irq(unsigned int irq);
+static void end_irq(unsigned int irq_nr);
+static void mask_and_ack_irq(unsigned int irq_nr);
+static void rc32300_enable_irq(unsigned int irq_nr);
+static void rc32300_disable_irq(unsigned int irq_nr);
+
+extern void __init init_generic_irq(void);
+
+#ifdef CONFIG_PM
+extern void counter0_irq(int irq, void *dev_id, struct pt_regs *regs);
+#endif
+
+
+typedef struct {
+  int irq_base;   /* Base IRQ # of this interrupt group */
+  int num_irqs;   /* Number of IRQs in this group */
+  u32 mask;       /* mask of valid bits in pending/mask/clear
+			   registers */
+} intr_group_t;
+
+static const intr_group_t intr_group[NUM_INTR_GROUPS] = {
+	{ -1, NUM_INTR_GROUPS, 0x00007ffe },  /* Group 0 indicates intrs in
+						 groups 1-14 */
+	{ GROUP1_IRQ_BASE,   1, 0x00000001 }, // bus error intr
+	{ GROUP2_IRQ_BASE,  12, 0x00000ffb }, // PIO active low intrs
+	{ GROUP3_IRQ_BASE,   8, 0x000000fb }, // PIO active high intrs
+	{ GROUP4_IRQ_BASE,   8, 0x000000ff }, // Timer Rollover intrs
+	{ GROUP5_IRQ_BASE,   3, 0x00000007 }, // UART0 intrs
+	{ GROUP6_IRQ_BASE,   3, 0x00000007 }, // UART1 intrs
+	{ GROUP7_IRQ_BASE,   5, 0x0000001f }, // DMA Ch0 intrs
+	{ GROUP8_IRQ_BASE,   5, 0x0000001f }, // DMA Ch1 intrs
+	{ GROUP9_IRQ_BASE,   5, 0x0000001f }, // DMA Ch2 intrs
+	{ GROUP10_IRQ_BASE,  5, 0x0000001f }, // DMA Ch3 intrs
+	{ GROUP11_IRQ_BASE,  4, 0x0000000f }, // PCI Ctlr error intrs
+	{ GROUP12_IRQ_BASE, 16, 0x0000ffff }, // PCI Satellite intrs
+	{ GROUP13_IRQ_BASE,  4, 0x0000000f }, // PCI to CPU mailbox intrs
+	{ GROUP14_IRQ_BASE,  1, 0x00000001 }  // SPI intr
+};
+
+#define READ_PEND(g) \
+       rc32300_readl(IC_GROUP0_PEND + (g)*IC_GROUP_OFFSET)
+#define WRITE_PEND(g,val) \
+       rc32300_writel((val), IC_GROUP0_PEND + (g)*IC_GROUP_OFFSET)
+#define READ_MASK(g) \
+       rc32300_readl(IC_GROUP0_MASK + (g)*IC_GROUP_OFFSET)
+#define WRITE_MASK(g,val) \
+       rc32300_writel((val), IC_GROUP0_MASK + (g)*IC_GROUP_OFFSET)
+#define READ_CLEAR(g) \
+       rc32300_readl(IC_GROUP0_CLEAR + (g)*IC_GROUP_OFFSET)
+#define WRITE_CLEAR(g,val) \
+       rc32300_writel((val), IC_GROUP0_CLEAR + (g)*IC_GROUP_OFFSET)
+
+static inline int irq_to_group(unsigned int irq_nr)
+{
+	int i;
+	for (i=NUM_INTR_GROUPS-1; i > 0; i--) {
+		if (irq_nr >= intr_group[i].irq_base)
+			break;
+	}
+
+	return i;
+}
+
+static inline int ip_to_irq(int ipnum)
+{
+	return ipnum;
+}
+
+static inline int irq_to_ip(int irq)
+{
+	return (irq < GROUP1_IRQ_BASE) ? irq : 5;
+}
+
+static inline void enable_local_irq(unsigned int irq_nr)
+{
+	int ipnum = irq_to_ip(irq_nr);
+	clear_c0_cause(1 << (ipnum + 8));
+	set_c0_status(1 << (ipnum + 8));
+}
+
+static inline void disable_local_irq(unsigned int irq_nr)
+{
+	int ipnum = irq_to_ip(irq_nr);
+	clear_c0_status(1 << (ipnum + 8));
+}
+
+static inline void ack_local_irq(unsigned int irq_nr)
+{
+	int ipnum = irq_to_ip(irq_nr);
+	clear_c0_cause(1 << (ipnum + 8));
+}
+
+static void enable_exp_irq(unsigned int irq_nr, int group)
+{
+	const intr_group_t* g = &intr_group[group];
+	u32 mask, intr_bit;
+	
+	// calc interrupt bit within group
+	intr_bit = (1 << (irq_nr - g->irq_base)) & g->mask;
+
+	if (!intr_bit)
+		return;
+	
+	DPRINTK("irq %d (group %d, mask %d)\n",
+		irq_nr, group, intr_bit);
+	
+	// first enable IP5 (IRQ3)
+	clear_c0_cause(1 << (5 + 8));
+	set_c0_status(1 << (5 + 8));
+	
+	// Clear the pending bit for the group
+	WRITE_CLEAR(0, (1 << group));
+	
+	// unmask appropriate group bit in group 0
+	mask = READ_MASK(0);
+
+	WRITE_MASK(0, mask | (1 << group));
+
+	// Clear the pending bit within the group
+	WRITE_CLEAR(group, intr_bit);
+
+	// unmask intr within group
+	mask = READ_MASK(group) & g->mask;
+
+	WRITE_MASK(group, mask | intr_bit);
+
+}
+
+static void disable_exp_irq(unsigned int irq_nr, int group)
+{
+	const intr_group_t* g = &intr_group[group];
+	u32 mask, intr_bit;
+	
+	// calc interrupt bit within group
+	intr_bit = (1 << (irq_nr - g->irq_base)) & g->mask;
+	if (!intr_bit)
+		return;
+	
+	DPRINTK("irq%d (group %d, mask %d)\n",
+		irq_nr, group, intr_bit);
+	
+	// mask intr within group
+	mask = READ_MASK(group) & g->mask;
+	mask &= ~intr_bit; // mask the intr bit
+	WRITE_MASK(group, mask);
+	
+	/*
+	  if there are no more interrupts enabled in this
+	  group, mask appropriate group bit in group 0
+	*/
+	if (!mask) {
+		mask = READ_MASK(0);
+		WRITE_MASK(0, mask & ~(1 << group));
+	}
+}
+
+static void ack_exp_irq(unsigned int irq_nr, int group)
+{
+	const intr_group_t* g = &intr_group[group];
+	u32 intr_bit;
+	
+	// calc interrupt bit within group
+	intr_bit = (1 << (irq_nr - g->irq_base)) & g->mask;
+	if (intr_bit) {
+		// clear intr within group
+		WRITE_CLEAR(group, intr_bit);
+	}
+	
+	/*
+	  if there are no more interrupts pending in this
+	  group, clear appropriate group pending bit in group 0
+	*/
+	if (!(READ_PEND(group) & g->mask)) {
+		WRITE_CLEAR(0, 1 << group);
+	}
+}
+
+
+static void rc32300_enable_irq(unsigned int irq_nr)
+{
+  unsigned long flags;
+  local_irq_save(flags);
+
+  if (irq_nr < GROUP1_IRQ_BASE)
+    enable_local_irq(irq_nr);
+  else {
+    int group = irq_to_group(irq_nr);
+    enable_exp_irq(irq_nr, group);
+  }
+
+  local_irq_restore(flags);
+}
+
+
+static void rc32300_disable_irq(unsigned int irq_nr)
+{
+  unsigned long flags;
+  local_irq_save(flags);
+
+	if (irq_nr < GROUP1_IRQ_BASE)
+		disable_local_irq(irq_nr);
+	else {
+		int group = irq_to_group(irq_nr);
+		disable_exp_irq(irq_nr, group);
+	}
+	
+	local_irq_restore(flags);
+}
+
+
+void rc32300_ack_irq(unsigned int irq_nr)
+{
+	if (irq_nr < GROUP1_IRQ_BASE) {
+		ack_local_irq(irq_nr);
+	} else {
+		int group = irq_to_group(irq_nr);
+		ack_exp_irq(irq_nr, group);
+	}
+}
+
+static unsigned int startup_irq(unsigned int irq_nr)
+{
+	rc32300_enable_irq(irq_nr);
+	return 0; 
+}
+
+
+static void shutdown_irq(unsigned int irq_nr)
+{
+	rc32300_disable_irq(irq_nr);
+	return;
+}
+
+
+static void mask_and_ack_irq(unsigned int irq_nr)
+{
+  unsigned long flags;
+  
+  local_irq_save(flags);
+  if (irq_nr < GROUP1_IRQ_BASE) {
+    disable_local_irq(irq_nr);
+    ack_local_irq(irq_nr);
+  } else {
+    int group = irq_to_group(irq_nr);
+    disable_exp_irq(irq_nr, group);
+    ack_exp_irq(irq_nr, group);
+  }
+  local_irq_restore(flags);
+	
+}
+
+static void end_irq(unsigned int irq_nr)
+{
+  unsigned long flags;
+
+  local_irq_save(flags);
+	if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
+		if (irq_nr < GROUP1_IRQ_BASE) {
+			ack_local_irq(irq_nr);
+			enable_local_irq(irq_nr);
+		} else {
+			int group = irq_to_group(irq_nr);
+			ack_exp_irq(irq_nr, group);
+			enable_exp_irq(irq_nr, group);
+		}
+	} else {
+		printk("warning: end_irq %d did not enable (%x)\n", 
+		       irq_nr, irq_desc[irq_nr].status);
+	}
+  local_irq_restore(flags);
+}
+
+static struct hw_interrupt_type rc32300_irq_type = {
+	"RC32334",
+	startup_irq,
+	shutdown_irq,
+	rc32300_enable_irq,
+	rc32300_disable_irq,
+	mask_and_ack_irq,
+	end_irq,
+	NULL
+};
+
+
+void __init arch_init_irq(void)
+{
+	int i;
+	unsigned long cp0_status;
+
+	printk("Initializing IRQ's: %d\n", RC32334_NR_IRQS);
+
+	cp0_status = read_c0_status();
+	memset(irq_desc, 0, sizeof(irq_desc));
+	set_except_vector(0, rc32300_IRQ);
+
+	for (i = 0; i < RC32334_NR_IRQS; i++) {
+                irq_desc[i].status = IRQ_DISABLED;
+                irq_desc[i].action = NULL;
+                irq_desc[i].depth = 1;
+		irq_desc[i].handler = &rc32300_irq_type;
+                spin_lock_init(&irq_desc[i].lock);
+	}
+}
+
+/*
+ * Interrupts are nested. Even if an interrupt handler is registered
+ * as "fast", we might get another interrupt before we return from
+ * *_dispatch().
+ */
+
+/* Dispatch to expanded interrupts */
+static void int3_dispatch(struct pt_regs *regs)
+{
+	int group, intr;
+	const intr_group_t* g;
+	u32 pend, group0_pend;
+
+	group0_pend = READ_PEND(0) & intr_group[0].mask;
+	group0_pend &= READ_MASK(0); // only unmasked groups
+	if (!group0_pend)
+		return; // no interrupts in any group!
+
+	group = 31 - rc32300_clz(group0_pend);
+	// group i has pending interrupts
+	g = &intr_group[group];
+	pend = READ_PEND(group) & g->mask;
+	pend &= READ_MASK(group); // only unmasked interrupts
+
+	if (!pend)
+		return; // no interrupts in this group ???
+		
+	intr = 31 - rc32300_clz(pend);
+#ifdef DEBUG_IRQ
+	idtprintf("%02d%02d", group, intr);
+#endif
+	do_IRQ(g->irq_base + intr, regs);
+}
+
+static void mips_spurious_interrupt(struct pt_regs *regs)
+{
+#if 0
+        return;
+#else
+        printk("got spurious interrupt\n");
+#endif
+}
+
+/* Main Interrupt dispatcher */
+void rc32300_irqdispatch(unsigned long cp0_cause, struct pt_regs *regs)
+{
+	unsigned long ip;
+	int ipnum;
+	
+	ip = (cp0_cause >> 8) & 0xff;
+	
+	if (!ip) {
+		mips_spurious_interrupt(regs);
+		return;
+	}
+	
+	ipnum = 31 - rc32300_clz(ip);
+	if (ipnum == 5) {
+		int3_dispatch(regs);
+	} else {
+		int irq = ip_to_irq(ipnum);
+		do_IRQ(irq, regs);
+	}
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/Makefile idtlinux/arch/mips/idt-boards/rc32300/S334/Makefile
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/Makefile	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/Makefile	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,42 @@
+###############################################################################
+#
+#  BRIEF MODULE DESCRIPTION
+#     Makefile for IDT S334A board BSP
+#
+#  Copyright 2006 IDT Inc. (rischelp@idt.com)
+#
+#  This program is free software; you can redistribute  it and/or modify it
+#  under  the terms of  the GNU General  Public License as published by the
+#  Free Software Foundation;  either version 2 of the  License, or (at your
+#  option) any later version.
+#
+#  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+#  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+#   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+#   NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+#   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+#   NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+#   USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+#   ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+#   THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#   You should have received a copy of the  GNU General Public License along
+#   with this program; if not, write  to the Free Software Foundation, Inc.,
+#   675 Mass Ave, Cambridge, MA 02139, USA.
+# 
+#  
+# 
+###############################################################################
+
+.S.s:
+	$(CPP) $(CFLAGS) $< -o $*.s
+.S.o:
+	$(CC) $(CFLAGS) -c $< -o $*.o
+
+obj-y	 := irq.o setup.o idtIRQ.o reset.o prom.o time.o 
+obj-$(CONFIG_KGDB)		+= serial_gdb.o
+obj-$(CONFIG_SERIAL_8250) 	+= serial.o
+subdir-$(CONFIG_IDT_BOOT_NVRAM) += nvram
+obj-$(CONFIG_IDT_BOOT_NVRAM) 	+= nvram/built-in.o
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/nvram/Makefile idtlinux/arch/mips/idt-boards/rc32300/S334/nvram/Makefile
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/nvram/Makefile	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/nvram/Makefile	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,37 @@
+###############################################################################
+#
+#  BRIEF MODULE DESCRIPTION
+#     Makefile for IDT S334 nvram access routines
+#
+#  Copyright 2006 IDT Inc. (rischelp@idt.com)
+#
+#  This program is free software; you can redistribute  it and/or modify it
+#  under  the terms of  the GNU General  Public License as published by the
+#  Free Software Foundation;  either version 2 of the  License, or (at your
+#  option) any later version.
+#
+#  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+#  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+#   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+#   NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+#   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+#   NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+#   USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+#   ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+#   THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#   You should have received a copy of the  GNU General Public License along
+#   with this program; if not, write  to the Free Software Foundation, Inc.,
+#   675 Mass Ave, Cambridge, MA 02139, USA.
+# 
+# 
+###############################################################################
+
+.S.s:   
+	$(CPP) $(CFLAGS) $< -o $*.s
+.S.o:   
+	$(CC) $(CFLAGS) -c $< -o $*.o
+
+
+obj-y   := nvram334.o spi.o
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/nvram/nvram334.c idtlinux/arch/mips/idt-boards/rc32300/S334/nvram/nvram334.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/nvram/nvram334.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/nvram/nvram334.c	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,534 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     nvram interface routines.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#define NVRAM_SPI
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include "nvram334.h"
+
+#if defined(NVRAM_SPI)
+#define WREN    0x0E
+#define WRDI    0x0C
+#define RDSR    0x0D
+#define WRSR    0x09
+#define READ    0x0B
+#define WRITE   0x0A
+
+extern void  enable_chipselect_spi(void);
+extern unsigned int send_to_spi(unsigned int);
+extern void  disable_chipselect_spi(void);
+
+extern void setenv(char *e, char *v, int rewrite);
+extern char * getenv(char *e);
+extern void unsetenv(char *e);
+extern void mapenv(int (*func)(char *, char *));
+extern void purgeenv(void);
+
+static void NVWR(unsigned int uiAddr, unsigned char ucData) 
+{
+  unsigned int uiStatus = 1;
+	
+  enable_chipselect_spi();
+  send_to_spi((unsigned int)(WREN));
+  disable_chipselect_spi();
+
+  /* send the Read Status command to AT25256 */
+  /* AT25256 EPROM is not ready if LSB=1 */
+  while (uiStatus & 0x1) {
+    enable_chipselect_spi();
+    send_to_spi((unsigned int)(RDSR));
+    uiStatus = send_to_spi(0);
+    disable_chipselect_spi();
+  }
+  /*.........................................................
+    send WRITE to SPI (followed by high_addr, low_addr, data)
+    .........................................................
+  */
+  enable_chipselect_spi();
+  send_to_spi((unsigned int)(WRITE));
+  send_to_spi(uiAddr >> 8);        /* offset into EPROM space - high byte */
+  send_to_spi(uiAddr);             /* offset into EPROM space - low byte */
+  send_to_spi((unsigned int)(ucData));  /* actual data to write into EPROM */
+  disable_chipselect_spi();
+
+  /* send the Read Status command to AT25256 */
+  /* AT25256 EPROM is not ready if LSB=1 */
+  uiStatus = 1;
+  while (uiStatus & 0x1) {
+    enable_chipselect_spi();
+    send_to_spi((unsigned int)(RDSR));
+    uiStatus = send_to_spi(0);
+    disable_chipselect_spi();
+  }
+}
+
+unsigned char
+NVRD(unsigned int uiAddr) 
+{
+	unsigned char ret;
+	unsigned int uiStatus = 1;
+	
+  /* send the Read Status command to AT25256 */
+  /* AT25256 EPROM is not ready if LSB=1 */
+  while (uiStatus & 0x1) {
+    enable_chipselect_spi();
+    send_to_spi((unsigned int)(RDSR));
+    uiStatus = send_to_spi(0);
+    disable_chipselect_spi();
+  }
+  /*.........................................................
+   send READ to SPI (followed by high_addr, low_addr)
+   .........................................................
+  */  
+  enable_chipselect_spi(); 
+  send_to_spi((unsigned int)(READ));
+  send_to_spi(uiAddr >> 8);  /* offset into EPROM space - high byte */
+  send_to_spi(uiAddr);       /* offset into EPROM space - low byte */
+  ret = send_to_spi(0);     /* dummy write returns data from EPROM, save it*/
+  disable_chipselect_spi();
+  return(ret);
+}
+#else
+unsigned char
+NVRD(unsigned int x)
+{
+  unsigned char nv_data;
+
+  nv_data = (unsigned char)(*(((unsigned char*)(NVRAM_BASE))+ x));
+  return(nv_data);
+}
+
+void 
+NVWR(unsigned int x , unsigned char v)
+{
+  int i = 0;
+  
+  *(((unsigned char*)(NVRAM_BASE)) + x) = v;
+
+  while (++i < 0x1000) ;
+}
+#endif
+
+/*
+ * The *env routines provide wrappers to the nvram_*env
+ * routines to allow any special processing of the environment
+ * to be carried out
+ * Yes this is a bit naff
+ */
+
+unsigned char
+nvram_getbyte(int offs)
+{
+  return(NVRD(offs));
+}
+
+void
+nvram_setbyte(int offs, unsigned char val)
+{
+  NVWR(offs, val);
+}
+
+/*
+ * BigEndian!
+ */
+unsigned short
+nvram_getshort(int offs)
+{
+  return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
+}
+
+void
+nvram_setshort(int offs, unsigned short val)
+{
+  nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
+  nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
+}
+
+unsigned int
+nvram_getint(int offs)
+{
+  unsigned int val;
+  val = nvram_getbyte(offs) << 24;
+  val |= nvram_getbyte(offs + 1) << 16;
+  val |= nvram_getbyte(offs + 2) << 8;
+  val |= nvram_getbyte(offs + 3);
+  return (val);
+}
+
+void
+nvram_setint(int offs, unsigned int val)
+{
+  nvram_setbyte(offs, val >> 24);
+  nvram_setbyte(offs + 1, val >> 16);
+  nvram_setbyte(offs + 2, val >> 8);
+  nvram_setbyte(offs + 3, val);
+}
+
+/*
+ * calculate NVRAM checksum
+ */
+static unsigned short
+nvram_calcsum (void)
+{
+  unsigned short sum = NV_MAGIC;
+  int     i;
+
+  for (i = ENV_BASE; i < ENV_TOP; i += 2)
+    sum += nvram_getshort(i);
+  return(sum);
+}
+
+/*
+ * update the nvram checksum
+ */
+static void
+nvram_updatesum (void)
+{
+  nvram_setshort(NVOFF_CSUM, nvram_calcsum());
+#if !defined(NVRAM_SPI)
+  eeprom_write_s334();
+#endif
+}
+
+/*
+ * test validity of nvram by checksumming it
+ */
+static int
+nvram_isvalid(void)
+{
+  static unsigned int is_valid;
+  unsigned short sum = NV_MAGIC;
+
+  if (is_valid)
+    return 1;
+
+#if !defined(NVRAM_SPI)
+  eeprom_read_s334();
+#endif
+  if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC)
+    return (0);
+  sum = nvram_calcsum ();
+  nvram_setshort(NVOFF_CSUM,sum);
+
+  is_valid = 1;
+  return(1);
+}
+
+/* return nvram address of environment string */
+static int
+nvram_matchenv(char *s)
+{
+  int envsize, envp, n, i, varsize;
+  char *var;
+
+  envsize = nvram_getshort(NVOFF_ENVSIZE);
+  if (envsize > ENV_AVAIL)
+    return (0);     /* sanity */
+  envp = ENV_BASE;
+
+  if ((n = strlen (s)) > 255)
+    return (0);
+  while (envsize > 0) {
+    varsize = NVRD(envp);
+    if (varsize == 0 || (envp + varsize) > ENV_TOP)
+      return (0);   /* sanity */
+    for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
+  char c1 = NVRD(i);
+  char c2 = *var;
+  if (islower (c1))
+      c1 = toupper (c1);
+  if (islower (c2))
+      c2 = toupper (c2);
+  if (c1 != c2)
+      break;
+    }
+    if (i > envp + n) {   /* match so far */
+      if (n == varsize - 1) /* match on boolean */
+        return(envp);
+      if (NVRD(i) == '=') /* exact match on variable */
+        return(envp);
+    }
+    envsize -= varsize;
+    envp += varsize;
+  }
+  return(0);
+}
+
+void
+nvram_initenv(void)
+{
+  nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
+  nvram_setshort(NVOFF_ENVSIZE, 0);
+  nvram_updatesum();
+}
+
+static void
+nvram_delenv(char *s)
+{
+  int nenvp, envp, envsize, nbytes;
+
+  envp = nvram_matchenv(s);
+  if (envp == 0)
+    return;
+  nenvp = envp + NVRD(envp);
+  envsize = nvram_getshort(NVOFF_ENVSIZE);
+  nbytes = envsize - (nenvp - ENV_BASE);
+  nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
+  while (nbytes--) {
+    NVWR (envp, NVRD(nenvp));
+    envp++;
+    nenvp++;
+  }
+
+  nvram_updatesum();
+}
+
+
+static int
+nvram_setenv(char *s, char *v)
+{
+  int ns, nv, total;
+  int envp;
+
+  if (!nvram_isvalid())
+    return (-1);
+
+  nvram_delenv(s);
+  ns = strlen(s);
+  if (ns == 0)
+    return(-1);
+  if (v && *v) {
+    nv = strlen(v);
+    total = ns + nv + 2;
+  }
+  else {
+    nv = 0;
+    total = ns + 1;
+  }
+  if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
+    return(-1);
+  envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
+  NVWR(envp, (unsigned char) total); envp++;
+  while (ns--) {
+    NVWR(envp, *s); envp++; s++;
+  }
+  if (nv) {
+    NVWR(envp, '='); envp++;
+    while (nv--) {
+      NVWR(envp, *v); envp++; v++;
+    }
+  }
+  nvram_setshort(NVOFF_ENVSIZE, envp - ENV_BASE);
+  nvram_updatesum();
+  return(0);
+}
+
+char *
+nvram_getenv(char *s)
+{
+  static char buf[256];   /* FIXME: this cannot be static */
+  int envp, ns, nbytes, i;
+
+  if (!nvram_isvalid())
+    return((char *)0);
+
+  envp = nvram_matchenv(s);
+  if (envp == 0)
+    return((char *)0);
+  ns = strlen(s);
+  if (NVRD(envp) == ns + 1) /* boolean */
+    buf[0] = '\0';
+  else {
+    nbytes = NVRD(envp) - (ns + 2);
+    envp += ns + 2;
+    for (i = 0; i < nbytes; i++)
+      buf[i] = NVRD(envp++);
+    buf[i] = '\0';
+  }
+  return (buf);
+}
+
+void
+nvram_unsetenv(char *s)
+{
+  if (!nvram_isvalid())
+    return;
+
+  nvram_delenv(s);
+}
+
+/*
+ * apply func to each string in environment
+ */
+void
+nvram_mapenv(int (*func)(char *, char *))
+{
+  int envsize, envp, n, i, seeneql;
+  char name[256], value[256];
+  char c, *s;
+
+  if (!nvram_isvalid())
+    return;
+
+  envsize = nvram_getshort(NVOFF_ENVSIZE);
+  envp = ENV_BASE;
+
+  while (envsize > 0) {
+    value[0] = '\0';
+    seeneql = 0;
+    s = name;
+    n = NVRD(envp);
+    for (i = envp + 1; i < envp + n; i++) {
+      c = NVRD(i);
+      if ((c == '=') && !seeneql){
+        *s = '\0';
+        s = value;
+        seeneql = 1;
+        continue;
+      }
+      *s++ = c;
+    }
+    *s = '\0';
+    (*func)(name, value);
+    envsize -= n;
+    envp += n;
+  }
+}
+
+#ifdef DEBUG
+void
+nvram_dumpenv(void)
+{
+  int envsize, envp, n, i;
+  char *var;
+
+  envsize = nvram_getshort(NVOFF_ENVSIZE);
+  envp = ENV_BASE;
+
+  printf ("NVRAM Environment:\n");
+  while (envsize) {
+    n = NVRD(envp);
+    for (i = envp + 1; i < envp + n; i++)
+      consputc (NVRD(i));
+    consputc('\n');
+    envsize -= n;
+    envp += n;
+  }
+  consputc('\n');
+}
+#endif
+
+#if 0
+static unsigned int
+digit(char c)
+{
+  if ('0' <= c && c <= '9')
+    return(c - '0');
+  if ('A' <= c && c <= 'Z')
+    return(10 + c - 'A');
+  if ('a' <= c && c <= 'z')
+    return(10 + c - 'a');
+  return(~0);
+}
+#endif
+/*
+ * Wrappers to allow 'special' environment variables to get processed
+ */
+void
+setenv(char *e, char *v, int rewrite)
+{
+  if (nvram_getenv(e) && !rewrite)
+    return;
+
+  nvram_setenv(e, v);
+}
+
+char *
+getenv(char *e)
+{
+  return(nvram_getenv (e));
+}
+
+void
+unsetenv(char *e)
+{
+  nvram_unsetenv(e);
+}
+
+void
+mapenv(int (*func)(char *, char *))
+{
+  nvram_mapenv(func);
+}
+
+#if !defined(NVRAM_SPI)
+#define WAIT(x) {int i = 0; while(++i < (x)) ; }
+void eeprom_read_s334()
+{
+  static IsVirgin;
+
+  if (IsVirgin)
+    return;
+
+  IsVirgin = 1;
+  NVRD(0x401);
+  WAIT(0x1000);
+  if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC)
+    nvram_initenv();
+}
+
+void eeprom_write_s334()
+{
+  NVWR(0x401, 0x20);
+  WAIT(0x8000);
+}
+
+extern void
+purgeenv(void)
+{
+  int i;
+
+  for (i = ENV_BASE; i < ENV_TOP; i++)
+    *(((unsigned char*)(NVRAM_BASE)) + i) = 0;
+  nvram_initenv();
+  eeprom_write_s334();
+}
+#else
+extern void
+purgeenv(void)
+{
+  int i;
+
+  for (i = ENV_BASE; i < ENV_TOP; i++)
+    NVWR(i, 0);
+  nvram_initenv();
+}
+#endif
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/nvram/nvram334.h idtlinux/arch/mips/idt-boards/rc32300/S334/nvram/nvram334.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/nvram/nvram334.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/nvram/nvram334.h	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,81 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     nvram layout definitions
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef _NVRAM_
+#define _NVRAM_
+
+#define TD_NVRAM_SIZE  512
+
+#if !defined(NVRAM_SPI)
+#define NVRAM_BASE     0xb2000000
+#define NVRAM_WRITE   (NVRAM_BASE + 0x00000400)
+#define NVRAM_READ     NVRAM_WRITE
+
+void eeprom_read_s334();
+void eeprom_write_s334();
+#endif
+
+/*
+ * defining ALGCOMPAT provides backward compatibility
+ * with Algorithmics derived PROM monitors
+ */
+#define ALGCOMPAT
+#ifdef ALGCOMPAT
+#define NVOFFSET  0   /* use all of NVRAM */
+#else
+#define NVOFFSET  1024    /* first 1Kb reserved for DECelx */
+#endif
+
+/* Offsets to reserved locations */
+              /* size description */
+#define NVOFF_MAGIC   (NVOFFSET + 0)  /* 2 magic value */
+#define NVOFF_CSUM    (NVOFFSET + 2)  /* 2 NVRAM environment checksum */
+#define NVOFF_ENVSIZE (NVOFFSET + 4)  /* 1 size of 'environment' */
+#define NVOFF_TEST    (NVOFFSET + 5)  /* 1 cold start test byte */
+#define NVOFF_ETHADDR (NVOFFSET + 6)  /* 6 decoded ethernet address */
+#define NVOFF_UNUSED  (NVOFFSET + c)  /* 0 current end of table */
+
+#define NV_MAGIC       0xdeaf         /* nvram magic number */
+#define NV_RESERVED    64             /* number of reserved bytes */
+
+#ifdef ALGCOMPAT
+/* ho hum... */
+#undef NVOFF_ETHADDR
+#define NVOFF_ETHADDR (NVOFFSET + NV_RESERVED - 6)
+#endif
+
+/* number of bytes available for environment */
+#define ENV_BASE      (NVOFFSET + NV_RESERVED)
+#define ENV_TOP        TD_NVRAM_SIZE
+#define ENV_AVAIL     (ENV_TOP - ENV_BASE)
+
+#endif /* _NVRAM_ */
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/nvram/spi.c idtlinux/arch/mips/idt-boards/rc32300/S334/nvram/spi.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/nvram/spi.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/nvram/spi.c	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,205 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     SPI interface routines.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+
+#define SPI_CNT       0xB8000900
+#define SPI_CNTL      0xB8000904
+#define SPI_STAT      0xB8000908
+#define SPI_DATA      0xB800090C
+
+#define SPI_CNT_DIV   0x00000008
+#define SPI_CNTL_VAL  0x0000007C
+#define SPI_STAT_SPIF 0x00000080
+
+#define GPIO_DAT      0xB8000600
+#define GPIO_DIR      0xB8000604
+#define GPIO_FUN      0xB8000608
+
+#define GPIO_SPI_CS   0x00000200
+
+#define CACHED_DLY    0x00003FFF
+#define UNCACHED_DLY  0x000000FF
+
+         /* AT25256 command definitions */
+#define WREN    0x0E
+#define WRDI    0x0C
+#define RDSR    0x0D
+#define WRSR    0x09
+#define READ    0x0B
+#define WRITE   0x0A
+
+extern unsigned int send_to_spi(unsigned int uiData);
+extern void enable_chipselect_spi(void);
+extern void disable_chipselect_spi(void);
+extern void initialize_hardware(void);
+
+static void delay(void);
+/* --------------------------------------------------*/
+static void delay(void)
+{
+	int i = CACHED_DLY;   /* we are running cached, longer count for delay */
+	while (i--);
+}
+
+/* --------------------------------------------------
+   Initialize the GPIO registers related to SPI functionality
+*/
+static void initialize_GPIO(void)
+{
+	unsigned int uiTempReg;
+	volatile unsigned int *uipGpioDir;
+	volatile unsigned int *uipGpioFun;
+	
+	uipGpioDir = (volatile unsigned int *)GPIO_DIR;
+	uipGpioFun = (volatile unsigned int *)GPIO_FUN;
+	/* .......... set up PIO Direction Register at GPIO_BASE+4.........
+	   PIO[10,9,8,7] are used for SPI.
+	   However, these correspond to bits 11,10,9,8 in PIO DIR REG
+	*/
+	uiTempReg  = *uipGpioDir;
+	*uipGpioDir = ((uiTempReg & 0x0F0FF) | 0x0E00);  /* bits 11,10,9 output(1), 8 input(0) - SPI */
+	
+	/* ........ set up PIO Effect/Function Select Register at GPIO_BASE+8
+	   PIO[10,9,8,7] are used for SPI.
+	   However, these correspond to bits 11,10,9,8 in PIO EFF/FUN REG
+	*/
+	
+	uiTempReg  = *uipGpioFun;
+	*uipGpioFun = ((uiTempReg & 0x0F0FF) | 0x0D00); /* spi_ss_n (bit9) is GPIO (0),rest are special/SPI (1)*/
+}
+
+/* --------------------------------------------------
+ */
+extern void disable_chipselect_spi(void)
+{
+	/* Write a 1 at chip select*/
+	*(volatile unsigned int *)GPIO_DAT |= GPIO_SPI_CS;
+}
+
+/*****************************************************************
+ * Sends data through SPI interface , returns data read from SPI.
+ * Input parameter: data to be sent
+ * Return value:    data read back from SPI
+ * SPI always transfers data in both directions simultaneously.
+ * To read back data which is in response to the previous command,
+ * do a dummy write to SPI which will read back the data you need.
+ * The word "data" is used here in a generic sense, it could actually
+ * be a SPI command written to SPI or status read back from SPI.
+ ****************************************************************/
+
+extern unsigned int send_to_spi(unsigned int uiData)
+{
+	/* write data */
+	delay();        /* let AT25256 do its write for awhile */
+	*(volatile unsigned int *)SPI_DATA = uiData;
+	
+	/* wait until transfer is finished */
+	delay();        /* let AT25256 do its write for awhile */
+	while (!(*(volatile unsigned int *)SPI_STAT & SPI_STAT_SPIF))
+		;
+	
+	/* wait until transfer is finished */
+	delay();        /* let AT25256 do its write for awhile */
+	
+	/* in SPI, reads and writes occur simultaneously */
+	return(*(volatile unsigned int *)SPI_DATA);       /* return SPI Data Register */
+}
+
+/* --------------------------------------------------
+ */
+
+extern void enable_chipselect_spi(void)
+{
+	/* Write a 0 at chip select*/
+	*(volatile unsigned int *)GPIO_DAT &= ~GPIO_SPI_CS;
+}
+
+/* --------------------------------------------------
+   Initialize the various SPI registers
+*/
+static void initialize_SPI(void)
+{
+	unsigned int uiTempReg;
+	
+	/* ........... Initialize SPI Clock Register
+	   ........... Depends on board's system frequency ........
+	*/
+	
+	*(volatile unsigned int *)SPI_CNT = SPI_CNT_DIV;       /* SPI prescalar counter */
+	/* this is further divided by 2 in the chip.
+	   AT25256 works at 3 MHz or under */
+	
+	disable_chipselect_spi();
+
+	/* Interrupts disabled, SPI on and Master, CPOL/CPHA=1,1, clock/2 */
+	*(volatile unsigned int *)SPI_CNTL = SPI_CNTL_VAL;
+	
+	/* .......... Clearing SPIF bit  ..............  */
+	uiTempReg = *(volatile unsigned int *)SPI_STAT;    /* dummy read */
+	uiTempReg = *(volatile unsigned int *)SPI_DATA;    /* dummy read */
+}
+
+/* --------------------------------------------------
+*/
+static void initialize_AT25256(void)
+{
+	unsigned int uiAtmelStatus;
+	
+	enable_chipselect_spi();
+	send_to_spi((unsigned int)(WRSR));
+	send_to_spi((unsigned int)(0x82));  /* AT25256 Status info to write */
+	/* 1000_0010: protect no blocks, WPEN,WEN=1 */
+	/* send the Read Status command to AT25256 */
+	send_to_spi((unsigned int)(RDSR));
+	
+	/* dummy write so we can read AT25256 status info */
+	uiAtmelStatus = send_to_spi(0);
+	disable_chipselect_spi();
+	
+	/* AT25256 EPROM is not ready if LSB=1 */
+	while (uiAtmelStatus & 0x1) {
+		enable_chipselect_spi();
+		send_to_spi((unsigned int)(RDSR));
+		uiAtmelStatus = send_to_spi(0);
+		disable_chipselect_spi();
+	}
+}
+/* --------------------------------------------------
+ */
+extern void initialize_hardware(void)
+{
+	initialize_GPIO();
+	initialize_SPI();
+	initialize_AT25256();
+}
+EXPORT_SYMBOL(initialize_hardware);
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/prom.c idtlinux/arch/mips/idt-boards/rc32300/S334/prom.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/prom.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/prom.c	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,117 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     prom interface routines
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/console.h>
+#include <asm/bootinfo.h>
+#include <linux/bootmem.h>
+#include <linux/ioport.h>
+#include <linux/serial.h>
+#include <linux/serialP.h>
+#include <asm/serial.h>
+#include <linux/ioport.h>
+
+#include <asm/idt-boards/rc32300/rc32300.h>
+
+unsigned int idt_cpu_freq = CONFIG_IDT_BOARD_FREQ;
+EXPORT_SYMBOL(idt_cpu_freq);
+
+extern void setup_serial_port(void);
+
+#ifdef CONFIG_IDT_BOOT_NVRAM
+extern void initialize_hardware(void);
+extern void mapenv(int (*func)(char *, char *));
+
+static int make_bootparm(char *name,char *val)
+{
+	if (strncmp(name, "bootparm", 8) == 0) {
+		strcat(arcs_cmdline,val);
+		strcat(arcs_cmdline," ");
+	}
+	else if(strncmp(name, "HZ", 2) == 0) {
+		idt_cpu_freq = simple_strtoul(val, 0, 10);
+		printk("CPU Clock at %d Hz (from HZ environment variable)\n",
+		       idt_cpu_freq);
+	}
+	return 0;
+}
+
+static void prom_init_cmdline(void)
+{
+	initialize_hardware();
+	memset(arcs_cmdline,0,sizeof(arcs_cmdline));
+	mapenv(&make_bootparm);
+}
+#endif
+extern unsigned long mips_machgroup;
+extern unsigned long mips_machtype;
+
+const char *get_system_type(void)
+{
+	return "IDT 79S334A";
+}
+
+struct resource rc32300_res_ram = {
+	"RAM",
+	0,
+	RAM_SIZE,
+	IORESOURCE_MEM
+};
+
+char * __init prom_getcmdline(void)
+{
+	return &(arcs_cmdline[0]);
+}
+
+void prom_init(void)
+{
+#ifdef CONFIG_IDT_BOOT_NVRAM
+	prom_init_cmdline();
+#endif
+
+	setup_serial_port();
+	/* set our arch type */
+	mips_machgroup = MACH_GROUP_IDT;
+	mips_machtype = MACH_IDT_S334;
+	add_memory_region(0,
+			  rc32300_res_ram.end - rc32300_res_ram.start,
+			  BOOT_MEM_RAM);
+	return;
+}
+
+void prom_free_prom_memory(void)
+{
+}
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/reset.c idtlinux/arch/mips/idt-boards/rc32300/S334/reset.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/reset.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/reset.c	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,71 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Reset EB365 board.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/processor.h>
+#include <asm/reboot.h>
+#include <asm/system.h>
+#include <asm/cacheflush.h>
+#include <asm/idt-boards/rc32300/rc32300.h>
+#include <asm/idt-boards/rc32300/rc32334.h>
+
+void rc32300_restart(char *command)
+{
+	set_c0_status((ST0_BEV | ST0_ERL));
+	set_c0_config(CONF_CM_UNCACHED);
+	flush_cache_all();
+	write_c0_wired(0);
+
+	// Trigger the WatchDog Timer (Timer 3) to warm reset
+	rc32300_writel(0, TIMER0_CNTL + 3*TIMER_REG_OFFSET);
+	rc32300_writel(0xd8, CPU_IP_BUSERR_CNTL);
+	rc32300_writel(0, TIMER0_COUNT + 3*TIMER_REG_OFFSET);
+	rc32300_writel(2, TIMER0_COMPARE + 3*TIMER_REG_OFFSET);
+	rc32300_writel(1, TIMER0_CNTL + 3*TIMER_REG_OFFSET);
+}
+
+void rc32300_halt(void)
+{
+	printk(KERN_NOTICE "\n** You can safely turn off the power\n");
+	while (1)
+		__asm__(".set\tmips3\n\t"
+	                "wait\n\t"
+			".set\tmips0");
+}
+
+void rc32300_power_off(void)
+{
+	rc32300_halt();
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/serial.c idtlinux/arch/mips/idt-boards/rc32300/S334/serial.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/serial.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/serial.c	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,72 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Serial port initialisation.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+
+#include <asm/time.h>
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/serial.h>
+
+#include <asm/idt-boards/rc32300/rc32300.h>
+
+
+extern int __init early_serial_setup(struct uart_port *port);
+
+extern unsigned int idt_cpu_freq;
+
+extern int __init setup_serial_port(void)
+{ 
+  static struct uart_port serial_req[2];
+
+  memset(serial_req, 0, sizeof(serial_req));
+  serial_req[0].type       = PORT_16550A;
+  serial_req[0].line       = 0;
+  serial_req[0].irq        = RC32300_UART0_IRQ;
+  serial_req[0].flags      = STD_COM_FLAGS;
+  serial_req[0].uartclk    = idt_cpu_freq;
+  serial_req[0].iotype     = SERIAL_IO_MEM;
+  serial_req[0].membase    = (char *) KSEG1ADDR(RC32300_UART0_BASE);
+  serial_req[0].mapbase    = KSEG1ADDR(RC32300_UART0_BASE);
+  serial_req[0].regshift   = 2;
+
+  early_serial_setup(&serial_req[0]);
+
+  return(0);
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/serial_gdb.c idtlinux/arch/mips/idt-boards/rc32300/S334/serial_gdb.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/serial_gdb.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/serial_gdb.c	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,272 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *      S334A specific polling driver for 16550 UART.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/serial_reg.h>
+
+/* set remote gdb baud rate at 115200 */
+
+#define GDB_BAUD 115200
+#define CONS_BAUD 9600
+
+extern unsigned int idt_cpu_freq;
+
+
+/* turn this on to watch the debug protocol echoed on the console port */
+#undef DEBUG_REMOTE_DEBUG
+
+#ifdef __MIPSEB__
+#define CONS_PORT 0xb8000803u
+#define GDB_PORT  0xb8000823u
+#else
+#define CONS_PORT 0xb8000800u
+#define GDB_PORT  0xb8000820u
+#endif
+           
+volatile unsigned char *ports[2] = {
+	(volatile unsigned char *)CONS_PORT,
+	(volatile unsigned char *)GDB_PORT
+};
+
+
+void reset_gdb_port(void);
+void cons_putc(char c);
+int port_getc(int port);
+void port_putc(int port, char c);
+
+int cons_getc(void)
+{
+	return port_getc(0);
+}
+
+void cons_putc(char c)
+{
+	port_putc(0, c);
+}
+
+void cons_puts(char *s)
+{
+	while(*s) {
+		if(*s == '\n') cons_putc('\r');
+		cons_putc(*s);
+		s++;
+	}
+}
+
+void cons_do_putn(int n)
+{
+	if(n) {
+		cons_do_putn(n / 10);
+		cons_putc(n % 10 + '0');
+	}
+}
+
+void cons_putn(int n)
+{
+	if(n < 0) {
+		cons_putc('-');
+		n = -n;
+	}
+
+	if (n == 0) {
+		cons_putc('0');
+	} else {
+		cons_do_putn(n);
+	}
+}
+
+#ifdef DEBUG_REMOTE_DEBUG
+static enum {HUH, SENDING, GETTING} state;
+
+static void sent(int c)
+{
+	switch(state) {
+	case HUH:
+	case GETTING:
+		cons_puts("\nSNT ");
+		state = SENDING;
+		/* fall through */
+	case SENDING:
+		cons_putc(c);
+		break;
+	}       
+}
+
+static void got(int c)
+{
+	switch(state) {
+	case HUH:
+	case SENDING:
+		cons_puts("\nGOT ");
+		state = GETTING;
+		/* fall through */
+	case GETTING:
+		cons_putc(c);
+		break;
+	}       
+}
+#endif /* DEBUG_REMOTE_DEBUG */
+
+static int first = 1;
+
+int getDebugChar(void)
+{
+	int c;
+
+	if(first) reset_gdb_port();
+
+	c = port_getc(1);
+
+#ifdef DEBUG_REMOTE_DEBUG
+	got(c);
+#endif
+
+	return c;
+}
+
+int port_getc(int p)
+{
+	volatile unsigned char *port = ports[p];
+	int c;
+
+	while((*(port + UART_LSR * 4) & UART_LSR_DR) == 0) {
+		continue;
+	}       	
+
+	c = *(port + UART_RX * 4);
+
+	return c;
+}
+
+int port_getc_ready(int p)
+{
+	volatile unsigned char *port = ports[p];
+
+	return *(port + UART_LSR * 4) & UART_LSR_DR;
+}
+
+int isDebugReady(void)
+{
+	return port_getc_ready(1);
+}
+
+void putDebugChar(char c)
+{
+	if(first) reset_gdb_port();
+
+#ifdef DEBUG_REMOTE_DEBUG
+	sent(c);
+#endif
+
+	port_putc(1, c);
+}
+
+#define OK_TO_XMT (UART_LSR_TEMT | UART_LSR_THRE)
+
+void port_putc(int p, char c)
+{
+	volatile unsigned char *port = ports[p];
+	volatile unsigned char *lsr = port + UART_LSR * 4;
+
+	while((*lsr & OK_TO_XMT) != OK_TO_XMT) {
+		continue;
+	}
+
+	*(port + UART_TX * 4) = c;
+}
+
+void reset_gdb_port(void)
+{
+	volatile unsigned char *port = ports[1];
+	unsigned int DIVISOR = (idt_cpu_freq / 16 / GDB_BAUD);
+
+	first = 0;
+
+#ifdef DEBUG_REMOTE_DEBUG
+	cons_puts("reset_gdb_port: initializing remote debug serial port (internal UART 1, ");
+	cons_putn(GDB_BAUD);
+	cons_puts("baud, MHz=");
+	cons_putn(idt_cpu_freq);
+	cons_puts(", divisor=");
+	cons_putn(DIVISOR);
+	cons_puts(")\n");
+#endif
+
+	/* reset the port */
+	*(port + UART_CSR * 4) = 0;
+
+	/* clear and enable the FIFOs */
+	*(port + UART_FCR * 4) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | 
+		UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;
+
+	/* set the baud rate */
+	*(port + UART_LCR * 4) = UART_LCR_DLAB;		/* enable DLL, DLM registers */
+	*(port + UART_DLL * 4) = DIVISOR;
+	*(port + UART_DLM * 4) = DIVISOR >> 8;
+
+	/* set the line control stuff and disable DLL, DLM regs */
+
+	*(port + UART_LCR * 4) = UART_LCR_STOP | 	/* 2 stop bits */
+		UART_LCR_WLEN8;				/* 8 bit word length */
+	
+	/* leave interrupts off */
+	*(port + UART_IER * 4) = 0;
+
+	/* the modem controls don't leave the chip on this port, so leave them alone */
+	*(port + UART_MCR * 4) = 0;
+}
+
+void reset_cons_port(void)
+{
+	volatile unsigned char *port = ports[0];
+	  unsigned int DIVISOR = (idt_cpu_freq / 16 / CONS_BAUD);
+
+	/* reset the port */
+	*(port + UART_CSR * 4) = 0;
+
+	/* clear and enable the FIFOs */
+	*(port + UART_FCR * 4) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | 
+		UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;
+
+	/* set the baud rate */
+	*(port + UART_LCR * 4) = UART_LCR_DLAB;		/* enable DLL, DLM registers */
+
+	*(port + UART_DLL * 4) = DIVISOR;
+	*(port + UART_DLM * 4) = DIVISOR >> 8;
+	/* set the line control stuff and disable DLL, DLM regs */
+
+	*(port + UART_LCR * 4) = UART_LCR_STOP | 	/* 2 stop bits */
+		UART_LCR_WLEN8;				/* 8 bit word length */
+	
+	/* leave interrupts off */
+	*(port + UART_IER * 4) = 0;
+
+	/* the modem controls don't leave the chip on this port, so leave them alone */
+	*(port + UART_MCR * 4) = 0;
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/setup.c idtlinux/arch/mips/idt-boards/rc32300/S334/setup.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/setup.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/setup.c	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,226 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     setup routines for IDT EB365 boards
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/pm.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+
+#include <linux/config.h>
+#include <linux/eisa.h>
+#include <linux/hdreg.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/mc146818rtc.h>
+#include <linux/console.h>
+#include <linux/fb.h>
+#include <linux/tty.h>
+
+#include <asm/reboot.h>
+
+#include <asm/idt-boards/rc32300/rc32300.h>
+
+extern void (*board_time_init)(void);
+extern void (*board_timer_setup)(struct irqaction *irq);
+extern void rc32300_time_init(void);
+extern void rc32300_timer_setup(struct irqaction *irq);
+extern char * __init prom_getcmdline(void);
+
+extern void rc32300_restart(char *);
+extern void rc32300_halt(void);
+extern void rc32300_power_off(void);
+extern void rc32300_ack_irq(unsigned int);
+#define DIG0 ((volatile unsigned char *)KSEG1ADDR(LCD_DIGIT0))
+#define DIG1 ((volatile unsigned char *)KSEG1ADDR(LCD_DIGIT1))
+#define DIG2 ((volatile unsigned char *)KSEG1ADDR(LCD_DIGIT2))
+#define DIG3 ((volatile unsigned char *)KSEG1ADDR(LCD_DIGIT3))
+
+
+
+void idt_disp_char(int i, char c)
+{ 
+	switch (i) {
+	case 0: *DIG0 = c; break;
+	case 1: *DIG1 = c; break;
+	case 2: *DIG2 = c; break;
+	case 3: *DIG3 = c; break;
+	default: *DIG0 = '?'; break;
+	}
+}
+
+
+int idtprintf(const char *fmt, ...)
+{
+	va_list args;
+	int i, len;
+	char str[256];
+	static int lcd_digit_reg[4] = {
+		KSEG1ADDR(LCD_DIGIT0),
+		KSEG1ADDR(LCD_DIGIT1),
+		KSEG1ADDR(LCD_DIGIT2),
+		KSEG1ADDR(LCD_DIGIT3)
+	};
+
+	va_start(args, fmt);
+	len = vsprintf(str, fmt, args);
+	va_end(args);
+
+	len = len > 4 ? 4 : len;
+	readb(KSEG1ADDR(LCD_CLEAR)); // clear the display
+	for (i = 0; i < len; i++) {
+		if (str[i])
+			writeb(str[i], lcd_digit_reg[i]);
+	}
+	
+	return len;
+}
+
+
+int  rc32334_be_handler(struct pt_regs *regs,int fixup)
+{
+        int data = regs->cp0_cause & 4;
+	u32 cntl;
+	extern void rc32300_ack_irq(unsigned int irq_nr);
+	
+	printk("RC32334 %s bus error:\n", data ? "Data" : "Instruction");
+	printk("  EPC == %08lx, RA == %08lx\n",
+	       regs->cp0_epc, regs->regs[31]);
+	printk("  CPU bus address == %08x\n",
+	       rc32300_readl(CPU_BUSERR_ADDR));
+	printk("  IP bus address == %08x\n",
+	       rc32300_readl(CPU_IP_BUSERR_ADDR));
+	cntl = rc32300_readl(CPU_IP_BUSERR_CNTL);
+	printk("  Bus error occured on a %s on %s bus\n",
+	       cntl & 1 ? "read" : "write",
+	       cntl & 4 ? "CPU" : "IP");
+
+	// ack the bus errors
+	rc32300_ack_irq(GROUP4_IRQ_BASE+4); // ack timer 4 rollover intr
+	rc32300_ack_irq(GROUP4_IRQ_BASE+5); // ack timer 5 rollover intr
+	rc32300_ack_irq(GROUP1_IRQ_BASE);   // ack bus error intr
+	rc32300_writel(cntl & ~0x07, CPU_IP_BUSERR_CNTL);
+
+        die_if_kernel("Oops", regs);
+        force_sig(SIGBUS, current);
+	return 0;
+}
+
+void __init bus_error_init(void)
+{
+	/*
+	 * The RC32334 uses two timers to count-out bus
+	 * timeouts. In addition to bus error exceptions,
+	 * the timer timeouts can trigger interrupts.
+	 *
+	 * On CPU reads, a bus error will cause an exception as well
+	 * as an interrupt. On CPU writes, a bus error only causes
+	 * an interrupt.
+	 */
+
+	/*
+	 * Disable CPU and IP Bus Error exceptions (PCI scan will
+	 * cause bus timeouts), and disable WatchDog.
+	 */
+	rc32300_writel(0x98, CPU_IP_BUSERR_CNTL);
+
+	rc32300_writel(0, TIMER0_CNTL + 4*TIMER_REG_OFFSET);
+	rc32300_writel(0, TIMER0_CNTL + 5*TIMER_REG_OFFSET);
+	rc32300_writel(0x3fff, TIMER0_COMPARE + 4*TIMER_REG_OFFSET);
+	rc32300_writel(0x3fff, TIMER0_COMPARE + 5*TIMER_REG_OFFSET);
+	rc32300_writel(1, TIMER0_CNTL + 4*TIMER_REG_OFFSET);
+	rc32300_writel(1, TIMER0_CNTL + 5*TIMER_REG_OFFSET);
+	
+}
+
+extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
+
+static int __init idt_setup(void)
+{
+	char* argptr;
+
+	argptr = prom_getcmdline();
+
+	board_time_init = rc32300_time_init;
+	board_timer_setup = rc32300_timer_setup;
+	board_be_handler = rc32334_be_handler;
+	_machine_restart = rc32300_restart;
+	_machine_halt = rc32300_halt;
+	pm_power_off = rc32300_power_off;
+
+	set_io_port_base(KSEG1);
+
+	// clear out any wired entries
+	write_c0_wired(0);
+
+	bus_error_init();
+
+	readb(KSEG1ADDR(LCD_CLEAR)); // clear the 4-digit LCD display
+
+	idtprintf("Unix");
+
+	return 0;
+}
+
+int page_is_ram(unsigned long pagenr)
+{
+	return 1;
+}
+
+static int __init buserror_enable(void)
+{
+  // ack any bus errors
+
+  rc32300_ack_irq(GROUP4_IRQ_BASE+4); // ack timer 4 rollover intr
+  rc32300_ack_irq(GROUP4_IRQ_BASE+5); // ack timer 5 rollover intr
+  rc32300_ack_irq(GROUP1_IRQ_BASE);   // ack bus error intr
+
+  /*
+   * Enable CPU and IP Bus Error exceptions, and disable WatchDog.
+   */
+  rc32300_writel(0x18, CPU_IP_BUSERR_CNTL);
+  return 0;
+}
+
+//early_initcall(idt_setup);
+void __init plat_setup(void){
+  idt_setup();
+}
+
+__initcall(buserror_enable);
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/time.c idtlinux/arch/mips/idt-boards/rc32300/S334/time.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/time.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32300/S334/time.c	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,149 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *    IDT S334 timer routines
+ *
+ *  Copyright 2006 IDT Inc.
+ *  Author: Integrated Device Technology Inc. rischelp@idt.com
+ *
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/mc146818rtc.h>
+#include <linux/irq.h>
+#include <linux/timex.h>
+
+#include <linux/param.h>
+#include <asm/mipsregs.h>
+#include <asm/ptrace.h>
+#include <asm/time.h>
+#include <asm/hardirq.h>
+
+#include <asm/mipsregs.h>
+#include <asm/ptrace.h>
+#include <asm/debug.h>
+#include <asm/time.h>
+
+#include <asm/idt-boards/rc32300/rc32300.h>
+
+static unsigned long r4k_offset; /* Amount to incr compare reg each time */
+static unsigned long r4k_cur;    /* What counter should be at next timer irq */
+
+extern unsigned int idt_cpu_freq;
+#if defined(CONFIG_IDT_79EB365) && defined(CONFIG_MIPS_RTC)
+extern void rtc_ds1553_init(void);
+#elif defined(CONFIG_IDT_79EB355) && defined(CONFIG_MIPS_RTC)
+extern void rtc_ds1501_init(void);
+#endif
+
+/* 
+ * Figure out the r4k offset, the amount to increment the compare
+ * register for each time tick. There is no RTC available.
+ *
+ * The RC32300 counts at half the CPU *core* speed.
+ */
+static unsigned long __init cal_r4koff(void)
+{
+  mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
+  return (mips_hpt_frequency / HZ);
+}
+
+
+void __init rc32300_time_init(void)
+{
+  unsigned int est_freq, flags;
+  
+  local_irq_save(flags);
+  
+  printk("calculating r4koff... ");
+  r4k_offset = cal_r4koff();
+  printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
+  
+  est_freq = 2*r4k_offset*HZ;	
+  est_freq += 5000;    /* round */
+  est_freq -= est_freq%10000;
+  printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, 
+	 (est_freq%1000000)*100/1000000);
+  local_irq_restore(flags);
+  
+#if defined(CONFIG_IDT_79EB365) && defined(CONFIG_MIPS_RTC)
+  rtc_ds1553_init();
+#elif defined(CONFIG_IDT_79EB355) && defined(CONFIG_MIPS_RTC)
+  rtc_ds1501_init();
+#endif
+
+}
+
+
+void __init rc32300_timer_setup(struct irqaction *irq)
+{
+  /* we are using the cpu counter for timer interrupts */
+  setup_irq(MIPS_CPU_TIMER_IRQ, irq);
+
+#if 0  
+  /* to generate the first timer interrupt */
+  r4k_cur = (read_c0_count() + r4k_offset);
+  write_c0_compare(r4k_cur);
+#endif
+}
+
+static inline void ack_r4ktimer(unsigned long newval)
+{
+  write_c0_compare(newval);
+}
+
+extern void idt_disp_char(int i,char c);
+
+asmlinkage void idt_timer_interrupt(int irq,struct pt_regs *regs)
+{ 
+#ifdef CONFIG_KGDB
+  void kgdb_check(void);
+#endif
+
+  static unsigned int timerCount = 0;
+  static int toggle = 0;
+
+  irq_enter();
+  kstat_this_cpu.irqs[irq]++;
+
+  if( (timerCount++ % HZ) == 0)
+    { 
+      toggle ^= 1;
+      idt_disp_char(0,toggle ? 'u' :'U');
+    }
+
+  timer_interrupt(irq, NULL, regs);
+  irq_exit();
+
+#ifdef CONFIG_KGDB
+  kgdb_check();
+#endif
+}
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/csu_idt.S idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/csu_idt.S
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/csu_idt.S	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/csu_idt.S	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,345 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Board initialization code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+	
+#include <linux/config.h>
+#include <linux/threads.h>
+
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/asm-offsets.h>
+#include <asm/cachectl.h>
+
+#define MHZ CONFIG_IDT_BOARD_FREQ
+		
+#include "idthdr.h"
+#include "iregdef.h"
+#include "idtcpu.h"
+#include "s434ram.h"
+#include "s434.h"
+
+#define IndexInvalidate_I       0x00
+
+/*--------------------------------------------------------------
+** prom entry point table
+*-------------------------------------------------------------*/
+
+FRAME(start,sp,0,ra)
+  j idtstart        /* begin monitor from start       |00| */
+
+idtstart:
+
+  .set  noreorder
+      mtc0  zero, C0_CAUSE
+            nop
+      li    v0, 0x0
+      or    v0, (SR_CU0 | SR_BEV)
+      mtc0  v0, C0_SR
+            nop
+      mfc0  v1, C0_CONFIG
+            nop
+      and   v1, ~(0x7)
+      ori   v1, 0x3
+      mtc0  v1, C0_CONFIG
+            nop
+            nop
+            
+/* ------------------- Disable WatchDog Timer ----------------------------- */
+      li    t0, WTC_BASE
+      sw    zero, 0x3C(t0) /* WTC */
+/* ------ Alternate functions for GPIO pins --------------------------------*/
+/* only UART0, UART1 and mem_addr */
+      li    t0, GPIO_BASE
+      li    t1, 0xf3
+      sw    t1, 0x0(t0)
+
+#if !defined(PCISAT)
+/* ------------------- Assert PCI reset ----------------------------------- */
+			li    t0, 0xb8080000
+      lw    t1, (t0)
+      andi  t2, t1, 0x1
+      beqz  t2, 2f
+            nop
+      andi  t2, t1, 0x3fe
+      sw    t2, (t0)
+      li    t2, 0x1000
+1:
+      addi  t2, -1
+      bnez  t2, 1b
+            nop
+2:
+      ori   t2, t1, 0x1
+      sw    t2, (t0)
+      lui   t2, 0x2
+rip:
+      lw    t1, 4(t0)
+      and   t1, t1, t2
+      bnez  t1, rip
+            nop
+#endif
+
+/* ------------------- Setup Device Controller ---------------------------- */
+      li    t0, DEV_CTL_BASE      /* load 2 base address registers' base    */
+      li    t1, DEV0_CTRL         /* device0 control parameter              */
+      sw    t1, 0x8(t0)           /* set the control register  CS0          */
+      li    t1, DEV0_TC           /* device0 timing config parameter        */
+      sw    t1, 0xC(t0)
+      li    t1, DEV1_BASE         /* set the device base register for CS1   */
+      sw    t1, 0x10(t0)
+      li    t1, DEV1_MASK         /* set the device mask register for CS1   */
+      sw    t1, 0x14(t0) 
+      li    t1, DEV1_CTRL         /* set the device control register for CS1*/
+      sw    t1, 0x18(t0)
+      li    t1, DEV1_TC           /* set the device timing register for CS1 */
+      sw    t1, 0x1C(t0) 
+
+      li    t1, DEV2_BASE         /* set the device base register for CS1   */
+      sw    t1, 0x20(t0)
+      li    t1, DEV2_MASK         /* set the device mask register for CS1   */
+      sw    t1, 0x24(t0) 
+      li    t1, DEV2_CTRL         /* set the device control register for CS1*/
+      sw    t1, 0x28(t0)
+      li    t1, DEV2_TC           /* set the device timing register for CS1 */
+      sw    t1, 0x2C(t0) 
+
+      li    t1, DEV3_BASE         /* set the device base register for CS1   */
+      sw    t1, 0x30(t0)
+      li    t1, DEV3_MASK         /* set the device mask register for CS1   */
+      sw    t1, 0x34(t0) 
+      li    t1, DEV3_CTRL         /* set the device control register for CS1*/
+      sw    t1, 0x38(t0)
+      li    t1, DEV3_TC           /* set the device timing register for CS1 */
+      sw    t1, 0x3C(t0) 
+
+      DISPLAY('I','D','D','R')
+#if MEMCFG != SRAM_ONLY
+
+/* ------------- INITIALIZE DDR SDRAM CONTROLLER ---------------------------*/
+
+      li    t1, 0x0               /* Add 200 microseconds of delay */
+      li    t2, DELAY_200USEC
+1:
+      add   t1, 1
+      bne   t1, t2, 1b
+            nop
+
+/*-------------- Initialize DDR Base and Mask Registers --------------------*/
+
+      li    t0, DDR_BASE
+
+  /* Load the DDRC, reset  Refresh Enable */
+      li    t1, DDRC_VAL_AT_INIT
+      sw    t1, 0x10(t0)
+      
+      sw    zero, 0x4(t0)
+      sw    zero, 0xc(t0)
+      sw    zero, 0x18(t0)
+
+  /* Store DDRBASE */
+      li    t1, DDR_BASE_VAL
+      sw    t1, 0x0(t0)
+
+  /* Store DDRMASK */
+      li    t1, DDR_MASK_VAL
+      sw    t1, 0x4(t0)
+
+  /* Store DDRABASE */
+      li    t1, DDR_ABASE_VAL
+      sw    t1, 0x14(t0)
+
+  /* Load DDRAMASK to disable alternate Mapping */
+      li    t1, DDR_AMASK_VAL
+      sw    t1, 0x18(t0)
+
+      li    t1, DDR_CUST_NOP      /* Write to DDR Custom transaction register */
+      sw    t1, 0x20(t0)
+
+      li    t2, DATA_PATTERN
+      li    t1, 0xA0000000 | DDR_BASE_VAL
+      sw    t2, 0x0(t1)
+
+  /* Add 200 microseconds of delay */
+      li    t1, 0x0
+      li    t2, DELAY_200USEC
+1:
+      add   t1, 1
+      bne   t1, t2, 1b
+            nop
+            
+  /* Register t0 carries pointer to the DDR_BASE: 0xB8018000 */
+      li    t1, DDR_CUST_PRECHARGE
+      sw    t1, 0x20(t0)    /* Write to DDR Custom transaction register */
+
+  /* Generate A10 high to pre-charge both the banks */
+      li    t2, DATA_PATTERN
+      li    t1, 0xA0000000 | DDR_PRECHARGE_OFFSET | DDR_BASE_VAL
+      sw    t2, 0x0(t1)
+
+  /* Register t0 carries pointer to the DDR_BASE: 0xB8018000 */
+      li    t1, DDR_LD_EMODE_REG
+      sw    t1, 0x20(t0)    /* Write to DDR Custom transaction register */
+
+  /* Generate EMODE register contents on A15-A2 */
+      li    t2, DATA_PATTERN
+      li    t1, 0xA0000000 | DDR_EMODE_VAL | DDR_BASE_VAL
+      sw    t2, 0x0(t1)
+
+  /* Register t0 carries pointer to the DDR_BASE: 0xB8018000 */
+      li    t1, DDR_LD_MODE_REG
+      sw    t1, 0x20(t0)    /* Write to DDR Custom transaction register */
+
+  /* Generate Mode register contents on the address bus A15-A2  */
+      li    t2, DATA_PATTERN
+      li    t1, 0xA0000000 | DDR_DLL_RES_MODE_VAL | DDR_BASE_VAL
+      sw    t2, 0x0(t1)
+
+  /* Delay of  1.6 microseconds ~ 300 delay iteration value */
+      li    t1, 0x0
+      li    t2, 500
+1:
+      add   t1, 1
+      bne   t1, t2, 1b
+            nop
+
+  /* Register t0 carries pointer to the DDR_BASE: 0xB8018000 */
+      li    t1, DDR_CUST_PRECHARGE
+      sw    t1, 0x20(t0)    /* Write to DDR Custom transaction register */
+
+  /* Generate A10 high to pre-charge both the banks */
+      li    t2, DATA_PATTERN
+      li    t1, 0xA0000000 | DDR_PRECHARGE_OFFSET | DDR_BASE_VAL
+      sw    t2, 0x0(t1)
+
+  /* Implements 9 cycles of Auto refresh allowing
+     sufficient margin for stability*/
+      li    t4, 9
+      li    t3, 0
+1:
+      li    t1, DDR_CUST_REFRESH
+      sw    t1, 0x20(t0)    /* Write to DDR Custom transaction register */
+
+  /* Read it back to flush CPU write buffers */
+      lw    t1, 0x20(t0)
+
+  /* Access DDR */
+      li    t2, DATA_PATTERN
+      li    t1, 0xA0000000 | DDR_BASE_VAL
+      sw    t2, 0x0(t1)
+
+      add   t3, 1
+      bne   t3, t4, 1b
+            nop
+
+  /* Register t0 carries pointer to the DDR_BASE: 0xB8018000 */
+      li    t1, DDR_LD_MODE_REG
+      sw    t1, 0x20(t0)    /* Write to DDR Custom transaction register */
+
+  /* Generate Mode Register contents on the address bus A12-A0 */
+      li    t2, DATA_PATTERN
+      li    t1, 0xA0000000 | DDR_DLL_MODE_VAL | DDR_BASE_VAL
+      sw    t2, 0x0(t1)
+
+  /* Initialize the refresh timer with fast refresh count */
+      li    t0, RCOUNT
+      li    t1, DDR_REF_CMP_FAST
+      
+  /* Set the RCOMPARE register */
+      sw    t1, 0x4(t0)
+
+  /* Enable the Refresh timer */
+      li    t1, 0x1           /* CE set to enabled the  Refresh counter */
+      sw    t1, 0x8(t0)
+
+  /* Enable RE-refresh enable in the DDRC register */
+      li    t0, DDR_BASE
+      li    t1, DDRC_VAL_NORMAL
+      sw    t1, 0x10(t0)
+
+  /* Add 200 microseconds of delay */
+      li    t1, 0x0
+      li    t2, DELAY_200USEC
+1:
+      add   t1, 1
+      bne   t1, t2, 1b
+            nop
+
+      li    t0, RCOUNT
+
+  /* Disable the refresh counter before changing the compare value */
+      sw    zero, 0x8(t0)
+
+  /* Set the RCOMPARE register with value gotten above */
+      li    t3, DDR_REF_CMP_VAL
+      sw    t3, 0x4(t0)
+
+  /* Enable the Refresh timer */
+      li    t1, 0x1           /* CE set to enabled the  Refresh counter */
+      sw    t1, 0x8(t0)
+
+  /* Add 200 microseconds of delay */
+      li    t1, 0x0
+      li    t2, DELAY_200USEC
+1:
+      add   t1, 1
+      bne   t1, t2, 1b
+            nop
+
+#endif
+	li    t0, 0xa0000000
+	li    t1, 0xa0100000
+1:
+	sw    zero, 0x00(t0)
+	sw    zero, 0x04(t0)
+	sw    zero, 0x08(t0)
+	sw    zero, 0x0c(t0)
+	addiu t0, 16
+	nop
+	blt   t0, t1, 1b
+	nop
+	nop
+	nop
+3:
+	mfc0  t0, C0_SR
+	nop
+	nop
+	and   t0, ~SR_BEV
+	mtc0  t0, C0_SR
+	nop
+	nop
+
+4:	
+	
+/* Jump to zImage startup */
+	        
+	la     k0, zstartup
+	j      k0
+	nop
+	nop
+
+ENDFRAME(start)
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/head.S idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/head.S
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/head.S	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/head.S	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,126 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Board initialisation code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+	
+#include <linux/config.h>
+#include <linux/threads.h>
+
+#include <asm/asm.h>
+#include <asm/cacheops.h>
+#include <asm/mipsregs.h>
+#include <asm/asm-offsets.h>
+#include <asm/cachectl.h>
+#include <asm/regdef.h>
+
+#define IndexInvalidate_I       0x00
+
+	.set noreorder
+	.cprestore
+	LEAF(zstartup)
+zstartup:
+
+        la      sp, .stack
+	move	s0, a0
+	move	s1, a1
+	move	s2, a2
+	move	s3, a3
+
+	/* Clear BSS */
+	/* Note: when zImage is in ROM, _edata and _bss point to
+	 * ROM space even when using -Tbss on the linker command line;
+	 * maybe ld.script needs to be corrected.
+	 */
+	la	a0, .stack
+	la	a2, _end
+1:	sw	zero, 0(a0)
+	bne	a2, a0, 1b
+	addu	a0, 4
+
+	/* flush the I-Cache */
+	li	k0, 0x80000000  # start address
+	li	k1, 0x80004000  # end address (16KB I-Cache)
+	subu	k1, 128
+
+2:
+	.set mips3
+	cache   IndexInvalidate_I, 0(k0)
+	cache   IndexInvalidate_I, 16(k0)
+	cache   IndexInvalidate_I, 32(k0)
+	cache   IndexInvalidate_I, 48(k0)
+	cache   IndexInvalidate_I, 64(k0)
+	cache   IndexInvalidate_I, 80(k0)
+	cache   IndexInvalidate_I, 96(k0)
+	cache   IndexInvalidate_I, 112(k0)
+	.set mips0
+
+	bne	k0, k1, 2b
+	addu	k0, k0, 128
+	/* done */
+
+	/* flush the D-Cache */
+	li	k0, 0x80000000  # start address
+	li	k1, 0x80004000  # end address (16KB I-Cache)
+	subu	k1, 128
+
+2:
+	.set mips3
+	cache   Index_Writeback_Inv_D, 0(k0)
+	cache   Index_Writeback_Inv_D, 16(k0)
+	cache   Index_Writeback_Inv_D, 32(k0)
+	cache   Index_Writeback_Inv_D, 48(k0)
+	cache   Index_Writeback_Inv_D, 64(k0)
+	cache   Index_Writeback_Inv_D, 80(k0)
+	cache   Index_Writeback_Inv_D, 96(k0)
+	cache   Index_Writeback_Inv_D, 112(k0)
+	.set mips0
+
+	bne	k0, k1, 2b
+	addu	k0, k0, 128
+	/* done */
+
+	la	ra, 3f
+	la	k0, decompress_kernel
+	jr	k0
+	nop
+3:
+
+	move	a0, s0
+	move	a1, s1
+	move	a2, s2
+	move	a3, s3
+	li	k0, KERNEL_ENTRY
+	jr	k0
+	nop
+4:
+	b 4b
+	END(zstartup)
+
+	.bss
+	.fill 0x2000
+	EXPORT(.stack)
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/idtcpu.h idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/idtcpu.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/idtcpu.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/idtcpu.h	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,336 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   IDT CPU register definitions. Though the registers are already defined
+ *   under asm directory, they are once again declared here for the ease of
+ *   syncing up with IDT bootloader code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+
+#if !defined(__IDTCPU_H__)
+#define __IDTCPU_H__
+/*
+** memory configuration and mapping
+*/
+#define K0BASE		0x80000000
+#define K0SIZE		0x20000000
+#define K1BASE		0xa0000000
+#define K1SIZE		0x20000000
+#define K2BASE		0xc0000000
+#if defined(CPU_R32364)
+#define K2SIZE		0x40000000
+#define ICEBASE		0xff000000
+#define ICESIZE		0x01000000
+#elif defined(CPU_R32438) || defined(CPU_R32434)
+#define K2SIZE		0x20000000
+#define K3BASE		0xe0000000
+#define K3SIZE          0x20000000
+#define ICEBASE		0xff200000
+#define ICESIZE		0x00200000
+#endif
+
+#define KUBASE		0
+#define KUSIZE		0x80000000
+
+/*
+** Exception Vectors
+*/
+
+#define	T_VEC	(K0BASE + 0x000)			/* tlbmiss vector */
+#define X_VEC	(K0BASE + 0x080)			/* xtlbmiss vector */
+#define C_VEC	(K1BASE + 0x100)			/* cache error vector */
+#define E_VEC	(K0BASE + 0x180)			/* exception vector */
+#define I_VEC	(K0BASE + 0X200)			/* interrupt vector */
+#define	R_VEC	(K1BASE + 0x1fc00000)	/* reset vector */
+
+/*
+** Address conversion macros
+*/
+#ifdef CLANGUAGE
+#define	CAST(as) (as)
+#else
+#define	CAST(as)
+#endif
+
+#define	K0_TO_K1(x)		(CAST(unsigned)(x) | 0xA0000000)	/* kseg0 to kseg1 */
+#define	K1_TO_K0(x)		(CAST(unsigned)(x) & 0x9FFFFFFF)	/* kseg1 to kseg0 */
+#define	K0_TO_PHYS(x)	(CAST(unsigned)(x) & 0x1FFFFFFF)	/* kseg0 to physical */
+#define	K1_TO_PHYS(x)	(CAST(unsigned)(x) & 0x1FFFFFFF)	/* kseg1 to physical */
+#define	PHYS_TO_K0(x)	(CAST(unsigned)(x) | 0x80000000)	/* physical to kseg0 */
+#define	PHYS_TO_K1(x)	(CAST(unsigned)(x) | 0xA0000000)	/* physical to kseg1 */
+
+#if defined(CPU_R32364)             /* Includes RC32332, RC32334 */
+#define	CFG_ICE					0x80000000	/* ICE detect */
+#define	CFG_ECMASK			0x70000000	/* System Clock Ratio */
+#define	CFG_ECBY2				0x00000000 	/* divide by 2 */
+#define	CFG_ECBY3				0x10000000 	/* divide by 3 */
+#define	CFG_ECBY4				0x20000000 	/* divide by 4 */
+#define	CFG_BE					0x00008000	/* Big Endian */
+#define	CFG_ICMASK			0x00000e00	/* Instruction cache size */
+#define	CFG_ICSHIFT			9
+#define	CFG_DCMASK			0x000001c0	/* Data cache size */
+#define	CFG_DCSHIFT			6
+#define	CFG_IB					0x00000020	/* Instruction cache line size */
+#define	CFG_DB					0x00000010	/* Data cache line size */
+#define	CFG_K0MASK			0x00000007	/* KSEG0 coherency algorithm */
+#elif defined(CPU_R32438) || defined(CPU_R32434)
+#define	CFG_MM					0x00060000  /* write buffer Merge Mode */
+#define CFG_BM					0x00010000  /* Burst Mode */
+#define	CFG_BE					0x00008000	/* Big Endian */
+#define	CFG_K0MASK			0x00000007	/* KSEG0 coherency algorithm */
+#endif
+
+/*
+ * Primary cache mode
+ */
+#if defined(CPU_R32364)
+#define CFG_C_NCHRNT_WT_NWA			0
+#define CFG_C_NCHRNT_WT					1
+#define CFG_C_UNCACHED					2
+#define CFG_C_NCHRNT_WB					3
+
+/* Cache Operations */
+#define Index_Invalidate_I      0x0         /* 0       0 */
+#define Index_Writeback_Inv_D   0x1         /* 0       1 */
+#define Index_Invalidate_SI     0x2         /* 0       2 */
+#define Index_Writeback_Inv_SD  0x3         /* 0       3 */
+#define Index_Load_Tag_I        0x4         /* 1       0 */
+#define Index_Load_Tag_D        0x5         /* 1       1 */
+#define Index_Load_Tag_SI       0x6         /* 1       2 */
+#define Index_Load_Tag_SD       0x7         /* 1       3 */
+#define Index_Store_Tag_I       0x8         /* 2       0 */
+#define Index_Store_Tag_D       0x9         /* 2       1 */
+#define Index_Store_Tag_SI      0xA         /* 2       2 */
+#define Index_Store_Tag_SD      0xB         /* 2       3 */
+#define Create_Dirty_Exc_D      0xD         /* 3       1 */
+#define Create_Dirty_Exc_SD     0xF         /* 3       3 */
+#define Hit_Invalidate_I        0x10        /* 4       0 */
+#define Hit_Invalidate_D        0x11        /* 4       1 */
+#define Hit_Invalidate_SI       0x12        /* 4       2 */
+#define Hit_Invalidate_SD       0x13        /* 4       3 */
+#define Hit_Writeback_Inv_D     0x15        /* 5       1 */
+#define Hit_Writeback_Inv_SD    0x17        /* 5       3 */
+#define Fill_I                  0x14        /* 5       0 */
+#define Hit_Writeback_D         0x19        /* 6       1 */
+#define Hit_Writeback_SD        0x1B        /* 6       3 */
+#define Hit_Writeback_I         0x18        /* 6       0 */
+#define Hit_Set_Virtual_SI      0x1E        /* 7       2 */
+#define Hit_Set_Virtual_SD      0x1F        /* 7       3 */
+#define CFG_EW32        				0x00040000      /* 32 bit */
+#elif defined(CPU_R32438) || defined(CPU_R32434)
+#define CFG_C_UNCACHED					2
+#define CFG_C_NCHRNT_WB					3
+
+/* Cache Operations */
+#define Index_Invalidate_I      0x0         /* 0       0 */
+#define Index_Invalidate_D      0x1         /* 0       0 */
+#define Index_Load_Tag_I        0x4         /* 1       0 */
+#define Index_Load_Tag_D        0x5         /* 1       1 */
+#define Index_Store_Tag_I       0x8         /* 2       0 */
+#define Index_Store_Tag_D       0x9         /* 2       1 */
+#define Hit_Invalidate_I        0x10        /* 4       0 */
+#define Hit_Invalidate_D        0x11        /* 4       1 */
+#define Fill_I                  0x14        /* 5       0 */
+#define Fetch_Lock_I						0x1C        /* 7       0 */
+#define Fetch_Lock_D						0x1D        /* 7       1 */
+#define CFG_EW32        				0x00040000      /* 32 bit */
+#endif
+
+/*
+** TLB resource defines
+*/
+
+#define	N_TLB_ENTRIES				16
+#define	TLBHI_VPN2MASK			0xffffe000
+#define	TLBHI_PIDMASK				0x000000ff
+#define	TLBHI_NPID					256
+
+#define	TLBLO_PFNMASK				0x03ffffc0
+#define	TLBLO_PFNSHIFT			6
+#define	TLBLO_D							0x00000004	/* writeable */
+#define	TLBLO_V							0x00000002	/* valid bit */
+#define	TLBLO_G							0x00000001	/* global access bit */
+#define	TLBLO_CMASK					0x00000038	/* cache algorithm mask */
+#define	TLBLO_CSHIFT				3
+
+#define	TLBLO_UNCACHED			(CFG_C_UNCACHED << TLBLO_CSHIFT)
+#define	TLBLO_NCHRNT_WT_NWA	(CFG_C_NCHRNT_WT_NWA << TLBLO_CSHIFT)
+#if defined(CPU_R32364)
+#define	TLBLO_NCHRNT_WT			(CFG_C_NCHRNT_WT << TLBLO_CSHIFT)
+#define	TLBLO_NCHRNT_WB			(CFG_C_NCHRNT_WB << TLBLO_CSHIFT)
+#endif
+
+#define	TLBINX_PROBE				0x80000000
+#define	TLBINX_INXMASK			0x0000003f
+
+#define	TLBRAND_RANDMASK		0x0000003f
+
+#define	TLBCTXT_BASEMASK		0xff800000
+#define	TLBCTXT_BASESHIFT		23
+
+#define	TLBCTXT_VPN2MASK		0x007ffff0
+#define	TLBCTXT_VPN2SHIFT		4
+
+#define	TLBPGMASK_MASK			0x01ffe000
+
+#define	SR_CUMASK				0xf0000000	/* coproc usable bits */
+#define	SR_CU3					0x80000000	/* Coprocessor 3 usable */
+#define	SR_CU2					0x40000000	/* Coprocessor 2 usable */
+#define	SR_CU1					0x20000000	/* Coprocessor 1 usable */
+#define	SR_CU0					0x10000000	/* Coprocessor 0 usable */
+
+/* #define	SR_PE						0x00100000*/  /* cache parity error */
+
+#if defined(CPU_R32364)
+#define	SR_RE						0X02000000	/* Reverse Endianness */
+#define	SR_DL						0x01000000	/* Data Cache Locking */
+#define	SR_IL						0x00800000	/* Instruction Cache Locking */
+
+#define	SR_BEV					0x00400000	/* Use boot exception vectors */
+#define	SR_SR						0x00100000	/* Soft reset */
+#define	SR_CH						0x00040000	/* Cache hit */
+#define	SR_CE						0x00020000	/* Use cache ECC  */
+#define	SR_DE						0x00010000	/* Disable cache exceptions */
+
+#elif defined(CPU_R32438) || defined(CPU_R32434)
+#define	SR_RP						0X08000000	/* Reduced Power mode */
+
+#define	SR_RE						0X02000000	/* Reverse Endianness */
+
+#define	SR_BEV					0x00400000	/* Use boot exception vectors */
+#define	SR_TS						0X00200000	/* TLB Shutdown */
+#define	SR_SR						0x00100000	/* Soft reset */
+#define	SR_NMI					0X00080000	/* NMI */
+#endif
+/*
+**	status register interrupt masks and bits
+*/
+
+#define	SR_IMASK				0x0000ff00	/* Interrupt mask */
+#define	SR_IMASK8				0x00000000	/* mask level 8 */
+#define	SR_IMASK7				0x00008000	/* mask level 7 */
+#define	SR_IMASK6				0x0000c000	/* mask level 6 */
+#define	SR_IMASK5				0x0000e000	/* mask level 5 */
+#define	SR_IMASK4				0x0000f000	/* mask level 4 */
+#define	SR_IMASK3				0x0000f800	/* mask level 3 */
+#define	SR_IMASK2				0x0000fc00	/* mask level 2 */
+#define	SR_IMASK1				0x0000fe00	/* mask level 1 */
+#define	SR_IMASK0				0x0000ff00	/* mask level 0 */
+
+#define	SR_IMASKSHIFT		8
+
+#define	SR_IBIT8				0x00008000	/* bit level 8 */
+#define	SR_IBIT7				0x00004000	/* bit level 7 */
+#define	SR_IBIT6				0x00002000	/* bit level 6 */
+#define	SR_IBIT5				0x00001000	/* bit level 5 */
+#define	SR_IBIT4				0x00000800	/* bit level 4 */
+#define	SR_IBIT3				0x00000400	/* bit level 3 */
+#define	SR_IBIT2				0x00000200	/* bit level 2 */
+#define	SR_IBIT1				0x00000100	/* bit level 1 */
+
+#define	SR_KSMASK				0x00000016	/* Kernel mode mask */
+#define	SR_KSUSER				0x00000000	/* User Mode */
+#define	SR_KSKERNEL			0x00000016	/* Kernel Mode */
+
+#define	SR_ERL					0x00000004	/* Error level */
+#define	SR_EXL					0x00000002	/* Exception level */
+#define	SR_IE						0x00000001	/* Interrupts enabled */
+#define	NOT_SR_IEC      0xfffffffe  /* assembler problem with li ~SR_IEC */
+
+/*
+ * Cause Register
+ */
+#define	CAUSE_BD				0x80000000	/* Branch delay slot */
+#define	CAUSE_CEMASK		0x30000000	/* coprocessor error */
+#define	CAUSE_CESHIFT		28
+#if defined(CPU_R32364)
+#define	CAUSE_IPE				0x04000000	/* Imprecise exception */
+#define	CAUSE_DW				0x02000000	/* Data watch */
+#define	CAUSE_IW				0x01000000	/* Instruction watch */
+#elif defined(CPU_R32438) || defined(CPU_R32434)
+#define CAUSE_IV			 	0x00800000	/* Interrupt Vector location */
+#define CAUSE_WP			 	0x00400000	/* Watch Exception deferred */
+#endif
+
+#define	CAUSE_IPMASK		0x0000FF00	/* Pending interrupt mask */
+#define	CAUSE_IPSHIFT		8
+
+/* Notice: Watch Exception if Exc. Code is 23 is not included in the mask
+ *	   for R32364.
+ */
+#define	CAUSE_EXCMASK		0x0000003C	/* Cause code bits */
+#define	CAUSE_EXCSHIFT	2
+
+#ifndef XDS
+/*
+**  Coprocessor 0 registers
+*/
+#define	C0_INX					$0		/* tlb index */
+#define	C0_RANDOM				$1
+#define	C0_TLBLO0				$2		/* tlb entry low 0 */
+#define	C0_TLBLO1				$3		/* tlb entry low 1 */
+#define	C0_CTXT					$4		/* tlb context */
+#define	C0_PAGEMASK			$5		/* tlb page mask */
+#define	C0_WIRED				$6		/* number of wired tlb entries */
+
+#define	C0_BADVADDR			$8		/* bad virtual address */
+#define	C0_COUNT				$9		/* timer count */
+#define	C0_TLBHI				$10		/* tlb entry hi */
+#define	C0_COMPARE			$11		/* timer comparator  */
+#define	C0_SR						$12		/* status register */
+#define	C0_CAUSE				$13		/* exception cause */
+#define	C0_EPC					$14		/* exception pc */
+#define	C0_PRID					$15		/* revision identifier */
+#define	C0_CONFIG				$16		/* configuration register */
+
+#if defined(CPU_R32364)
+#define	C0_IWATCH				$18		/* Instr brk pt Virtual add. */
+#define	C0_DWATCH				$19		/* Data brk pt Virtual add. */
+
+#define	C0_IEPC					$22		/* Imprecise Exception pc */
+#define	C0_DEPC					$23		/* Debug Exception pc */
+#define	C0_DEBUG				$24		/* Debug control/status reg */
+
+#define	C0_ECC					$26		/* primary cache Parity control */
+#define	C0_CACHEERR			$27		/* cache error status */
+#define	C0_TAGLO				$28		/* cache tag lo */
+#define	C0_ERRPC				$30		/* cache error pc */
+#elif defined(CPU_R32438) || defined(CPU_R32434)
+#define	C0_WATCHLO			$18		/* Watchpoint address (low) */
+#define	C0_WATCHHI			$19		/* Watchpoint address (high) */
+
+#define	C0_DEBUG				$23		/* Debug control/status reg */
+#define	C0_DEPC					$24		/* Debug Exception pc */
+
+#define	C0_ERRCTL				$26		/* Cache Error Control */
+#define	C0_TAGLO				$28		/* Cache Tag Lo */
+#define	C0_ERRPC				$30		/* Cache Error PC */
+#define C0_DESAVE				$31		/* Debug scratchpad reg. */
+#endif 
+
+#endif
+#endif /* defined(__IDTCPU_H__) */
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/idthdr.h idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/idthdr.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/idthdr.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/idthdr.h	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,53 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Some macros. Though they are already defined else where in the linux
+ *   tree, they are once again declared here for the ease of syncing up with
+ *    IDT bootloader code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#ifndef XDS
+
+#define	FRAME(name,frm_reg,offset,ret_reg)	\
+	.globl	name;				\
+	.ent	name;				\
+name:;						\
+	.frame	frm_reg,offset,ret_reg
+
+#define ENDFRAME(name) 	.end name
+
+#else
+
+#define FRAME(name,frm_reg,offset,ret_reg)      \
+name:
+
+#define ENDFRAME(name)
+
+#endif
+
+
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/image.lds.in idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/image.lds.in
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/image.lds.in	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/image.lds.in	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,31 @@
+OUTPUT_ARCH(mips)
+ENTRY(zstartup)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = IMSTART;
+  .init          : { *(.init)		} =0
+  .text      :
+  {
+    _ftext = . ;
+    *(.text)
+    *(.rodata)
+    *(.rodata1)
+   . = ALIGN(4096);
+    input_data = .;
+    arch/mips/idt-boards/rc32434/EB434/boot/piggy.o
+    input_data_end = .;
+   . = ALIGN(4096);
+    *(.gnu.warning)
+  } =0
+
+  .reginfo : { *(.reginfo) }
+
+   . = BSS_START;
+  __bss_start = .;
+  .bss       :
+  {
+   *(.bss)
+  _end = . ;
+  }
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/iregdef.h idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/iregdef.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/iregdef.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/iregdef.h	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,274 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   IDT CPU register definitions. Though the registers are already defined
+ *   under asm directory, they are once again declared here for the ease of
+ *   syncing up with IDT bootloader code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#ifdef CLANGUAGE
+struct ireg_desc {
+	char 	*ptr_field_name;	/* field name   */
+	short	num_digits;				/* number ofdigits to display */
+	short	num_spaces;				/* number of spaces to follow */
+	reg_t	fld_mask;					/* mask to extract value of field */
+	int	fld_shift;					/* shift amount to position field */
+  short    cpu;
+	char *CONST *ptr_enum_list;	/* ptr to an enumeration list */
+	  };
+
+/*
+** reg_name - structure that gives the reg. name, alt. reg name
+**		the reg index for fetching the value, the number
+**		of spaces req. so a tabular display will align
+**		a pointer to a structure defining the fields if
+**		required and a flag for the output type.
+*/
+struct reg_name {
+	char	*register_name;
+	char	*alt_reg_name;
+	short	reg_index;
+	short	space_pad;
+	CONST struct ireg_desc *ptr_reg_desc_flds;
+	unsigned char format_type;
+	unsigned char print_type;
+	short   reg_group;
+  short    cpu;
+	  };
+
+/* print format specifiers */
+#define PRT_HEX		0
+#define PRT_SGL 	1
+#define PRT_DBL 	2
+
+/* register group classifiers */
+#define GRP_CPU		0x0001
+#define GRP_FPR		0x0002
+#define GRP_FPS		0x0004
+#define GRP_FPD		0x0008
+#define GRP_CP0		0x0010
+#define GRP_CP0R	0x0020
+#endif
+
+/*
+** register names
+*/
+#define r0		$0
+#define r1		$1
+#define r2		$2
+#define r3		$3
+#define r4		$4
+#define r5		$5
+#define r6		$6
+#define r7		$7
+#define r8		$8
+#define r9		$9
+#define r10		$10
+#define r11		$11
+#define r12		$12
+#define r13		$13
+#define r14		$14
+#define r15		$15
+#define r16		$16
+#define r17		$17
+#define r18		$18
+#define r19		$19
+#define r20		$20
+#define r21		$21
+#define r22		$22
+#define r23		$23
+#define r24		$24
+#define r25		$25
+#define r26		$26
+#define r27		$27
+#define r28		$28
+#define r29		$29
+#define r30		$30
+#define r31		$31
+
+#define zero	$0		/* wired zero */
+#define AT		$at		/* assembler temp */
+#define v0		$2		/* return value */
+#define v1		$3
+#define a0		$4		/* argument registers a0-a3 */
+#define a1		$5
+#define a2		$6
+#define a3		$7
+#define t0		$8		/* caller saved  t0-t9 */
+#define t1		$9
+#define t2		$10
+#define t3		$11
+#define t4		$12
+#define t5		$13
+#define t6		$14
+#define t7		$15
+#define s0		$16		/* callee saved s0-s8 */
+#define s1		$17
+#define s2		$18
+#define s3		$19
+#define s4		$20
+#define s5		$21
+#define s6		$22
+#define s7		$23
+#define t8		$24
+#define t9		$25
+#define k0		$26		/* kernel usage */
+#define k1		$27		/* kernel usage */
+#define gp		$28		/* sdata pointer */
+#define sp		$29		/* stack pointer */
+#define s8		$30		/* yet another saved reg for the callee */
+#define fp		$30		/* frame pointer - this is being phased out by MIPS */
+#define ra		$31		/* return address */
+
+/*
+** relative position of registers in save reg area
+*/
+#define	R_R0		0
+#define	R_R1		1
+#define	R_R2		2
+#define	R_R3		3
+#define	R_R4		4
+#define	R_R5		5
+#define	R_R6		6
+#define	R_R7		7
+#define	R_R8		8
+#define	R_R9		9
+#define	R_R10		10
+#define	R_R11		11
+#define	R_R12		12
+#define	R_R13		13
+#define	R_R14		14
+#define	R_R15		15
+#define	R_R16		16
+#define	R_R17		17
+#define	R_R18		18
+#define	R_R19		19
+#define	R_R20		20
+#define	R_R21		21
+#define	R_R22		22
+#define	R_R23		23
+#define	R_R24		24
+#define	R_R25		25
+#define	R_R26		26
+#define	R_R27		27
+#define	R_R28		28
+#define	R_R29		29
+#define	R_R30		30
+#define	R_R31		31
+#define NCLIENTREGS	32
+#define	R_EPC				32
+#define	R_MDHI			33
+#define	R_MDLO		  34
+#define	R_SR				35
+#define	R_CAUSE			36
+#define	R_TLBHI			37
+#define	R_TLBLO0		38
+#define	R_BADVADDR	39
+#define	R_INX				40
+#define	R_RAND			41
+#define	R_CTXT			42
+#define	R_EXCTYPE		43
+#define R_MODE			44
+#define R_PRID			45
+#define R_TLBLO1		46
+#define R_PAGEMASK	47
+#define R_WIRED			48
+#define R_COUNT			49
+#define R_COMPARE		50
+#define R_CONFIG		51
+#if defined(CPU_R32434)
+#define R_WATCHLO   52
+#define R_WATCHHI   53
+#elif defined(CPU_R32364)
+#define R_IWATCH    52
+#define R_DWATCH    53
+#define R_ECC				54
+#define R_CACHEERR	55
+#endif
+#define R_TAGLO			56
+#define R_TAGHI			57
+#define R_ERRPC			58
+
+#define NREGS			  59
+
+#if __mips >= 3
+
+#define R_SZ		8
+#ifndef CLANGUAGE
+#define sreg		sd
+#define lreg		ld
+#define rmfc0		mfc0
+#define rmtc0		mtc0
+#endif
+
+#else
+
+#define R_SZ		4
+#ifndef CLANGUAGE
+#define sreg		sw
+#define lreg		lw
+#define rmfc0		mfc0
+#define rmtc0		mtc0
+#endif
+
+#endif
+
+/*
+** For those who like to think in terms of the compiler names for the regs
+*/
+#define	R_ZERO	R_R0
+#define	R_AT		R_R1
+#define	R_V0		R_R2
+#define	R_V1		R_R3
+#define	R_A0		R_R4
+#define	R_A1		R_R5
+#define	R_A2		R_R6
+#define	R_A3		R_R7
+#define	R_T0		R_R8
+#define	R_T1		R_R9
+#define	R_T2		R_R10
+#define	R_T3		R_R11
+#define	R_T4		R_R12
+#define	R_T5		R_R13
+#define	R_T6		R_R14
+#define	R_T7		R_R15
+#define	R_S0		R_R16
+#define	R_S1		R_R17
+#define	R_S2		R_R18
+#define	R_S3		R_R19
+#define	R_S4		R_R20
+#define	R_S5		R_R21
+#define	R_S6		R_R22
+#define	R_S7		R_R23
+#define	R_T8		R_R24
+#define	R_T9		R_R25
+#define	R_K0		R_R26
+#define	R_K1		R_R27
+#define	R_GP		R_R28
+#define	R_SP		R_R29
+#define	R_FP		R_R30
+#define	R_RA		R_R31
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/Makefile idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/Makefile
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/Makefile	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/Makefile	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,134 @@
+###############################################################################
+#
+#  BRIEF MODULE DESCRIPTION
+#     Makefile create a compressed zImage or Rommable rImage
+#
+#  Copyright 2006 IDT Inc. (rischelp@idt.com)
+#
+#  This program is free software; you can redistribute  it and/or modify it
+#  under  the terms of  the GNU General  Public License as published by the
+#  Free Software Foundation;  either version 2 of the  License, or (at your
+#  option) any later version.
+#
+#  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+#  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+#   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+#   NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+#   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+#   NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+#   USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+#   ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+#   THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#   You should have received a copy of the  GNU General Public License along
+#   with this program; if not, write  to the Free Software Foundation, Inc.,
+#   675 Mass Ave, Cambridge, MA 02139, USA.
+# 
+###############################################################################
+
+###############################################################################
+# The following is taken from IDT/Sim Makefile
+#############################################################################
+TARGET=434
+TARGETDIR=S434
+
+#
+# following refers to memory type in use in eval board and if more than one
+# then the order is implied.  These are values for the switch MEMCFG.
+#
+SRAM_ONLY=1
+SDRAM_ONLY=2
+SRAM_N_SDRAM=3
+SDRAM_N_SRAM=4
+
+# following refers to size of the DRAM space.
+# These are values for the switch DRAMSZ.
+
+MB32=1
+MB64=2
+MB128=3
+MB32SO=4
+
+MACH= -DEB434 -DS434 -DCPU_R32434 -DMIPSEL -DINET -DMEMCFG=$(SDRAM_ONLY) -DDRAMSZ=$(MB32) -DIDTSIM -DMHZ=$(MHZ) -DNVRAM_RTC -DUSE_SPI
+COMMSWITCHES = $(MACH)
+#***************** END IDT/Sim Makefile ##################################### 
+ZDEBUG=1
+export ZDEBUG
+
+# working space for gunzip:
+FREE_RAM      := 0x80C00000
+END_RAM       := 0x80E00000
+
+KERNELCONFIG  := $(TOPDIR)/.config
+include $(KERNELCONFIG)
+
+SIZE = $(CROSS_COMPILE)size
+
+O_FORMAT = $(shell $(OBJDUMP) -i | head -2 | grep elf32)
+
+SYSTEM	      := $(TOPDIR)/vmlinux
+ZBSS          := 0x800A0000
+
+ZIMSTART      := $(CONFIG_IDT_ZIMAGE_ADDR)
+RIMSTART      := 0x9FC00000
+
+LOADADDR      := 0x$(shell $(NM) $(SYSTEM) | grep "A _text" |cut -f1 -d' ')
+KERNEL_ENTRY  := $(shell $(OBJDUMP) -f $(SYSTEM) | sed -n -e 's/^start address //p')
+
+####################################################################################
+ZIMFLAGS        = s/IMSTART/$(ZIMSTART)/;s/BSS_START/$(ZBSS)/
+RIMFLAGS        = s/IMSTART/$(RIMSTART)/;s/BSS_START/$(ZBSS)/
+CFLAGS	:= -fno-pic -nostdinc -G 0 -mno-abicalls -fno-pic -pipe -I$(TOPDIR)/include
+AFLAGS	:= -D__ASSEMBLY__ $(CFLAGS)
+
+####################################################################################
+OBJECTS= $(obj)/piggy.o $(obj)/head.o $(obj)/misc.o
+ifneq ($(ZDEBUG),0)
+OBJECTS += $(obj)/uart16550.o
+endif
+
+$(obj)/zImage.lds: $(obj)/image.lds.in $(KERNELCONFIG)
+	@sed "$(ZIMFLAGS)" < $< > $@
+
+$(obj)/rImage.lds: $(obj)/image.lds.in $(KERNELCONFIG)
+	@sed "$(RIMFLAGS)" < $< > $@
+
+$(obj)/piggy.o: $(SYSTEM) $(obj)/Makefile
+	$(OBJCOPY) -S -O binary -R .note -R .comment $(SYSTEM) $(SYSTEM).bin
+	gzip -f -9 < $(SYSTEM).bin > $(SYSTEM).gz
+	echo "O_FORMAT:  " $(O_FORMAT); 
+	$(LD) -r -b binary --oformat $(O_FORMAT) -o $(obj)/piggy.o $(SYSTEM).gz
+	rm -f $(SYSTEM).bin $(SYSTEM).gz
+
+$(obj)/head.o: $(obj)/head.S $(SYSTEM) $(obj)/Makefile
+	$(CC) $(AFLAGS) -DKERNEL_ENTRY=$(KERNEL_ENTRY) -c $(obj)/head.S -o $(obj)/head.o
+
+$(obj)/misc.o: $(obj)/misc.c $(obj)/Makefile
+	$(CC) $(CFLAGS) -DLOADADDR=$(LOADADDR) -DFREE_RAM=$(FREE_RAM) -DEND_RAM=$(END_RAM) \
+		-c $< -DZDEBUG=$(ZDEBUG) -o $(obj)/misc.o
+
+$(obj)/uart16550.o: $(obj)/uart16550.c $(KERNELCONFIG)
+	$(CC) $(CFLAGS) -c $< -o $(obj)/uart16550.o
+
+$(obj)/csu_idt.o: $(obj)/csu_idt.S Makefile $(SYSTEM)
+	$(CC) $(AFLAGS) $(COMMSWITCHES) -c $< -o $(obj)/csu_idt.o
+
+zImage: $(obj)/zImage.lds $(SYSTEM) $(OBJECTS)
+	$(LD) -T$(obj)/zImage.lds -o $(TOPDIR)/zImage $(OBJECTS)
+	$(OBJCOPY) -S -O binary -R .note -R .comment $(TOPDIR)/zImage $(TOPDIR)/zImage.bin
+	$(OBJCOPY) -I binary -S -O srec --srec-forceS3 --srec-len=32 --change-start=0x00000000 \
+		 $(TOPDIR)/zImage.bin $(TOPDIR)/zImage.prm
+	$(SIZE) $(TOPDIR)/zImage |awk -F" " '{ print $$4 "\t" $$5 }' > $(TOPDIR)/zImage.size
+	rm -f *.o
+
+rImage: $(obj)/rImage.lds $(SYSTEM) $(OBJECTS) $(obj)/csu_idt.o
+	@rm -f $(TOPDIR)/*.prm
+	$(LD) -T$(obj)/rImage.lds -o $(TOPDIR)/rImage $(obj)/csu_idt.o $(OBJECTS) 
+	$(OBJCOPY) -S -O binary -R .note -R .comment $(TOPDIR)/rImage $(TOPDIR)/rImage.bin
+	$(OBJCOPY) -I binary -S -O srec --srec-forceS3 --srec-len=32 --change-start=0x00000000 \
+		 $(TOPDIR)/rImage.bin $(TOPDIR)/rImage.prm
+	$(SIZE) $(TOPDIR)/rImage |awk -F" " '{ print $$4 "\t" $$5 }' > $(TOPDIR)/rImage.size
+	rm -f *.o
+clean:
+	rm -f *.o $(TOPDIR)/zImage* $(TOPDIR)/rImage* $(TOPDIR)/*.prm $(TOPDIR)/rImage.size $(TOPDIR)/zImage.size
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/misc.c idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/misc.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/misc.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/misc.c	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,339 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Code to un-compress linux image
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/types.h>
+
+/*
+ * gzip declarations
+ */
+#define OF(args)  args
+#define STATIC static
+#define memzero(s, n)     memset ((s), 0, (n))
+typedef unsigned char uch;
+typedef unsigned short ush;
+typedef unsigned long ulg;
+#define WSIZE 0x8000		/* Window size must be at least 32k, */
+				/* and a power of two */
+static uch *inbuf;		/* input buffer */
+static uch window[WSIZE];	/* Sliding window buffer */
+
+/* gzip flag byte */
+#define ASCII_FLAG   0x01	/* bit 0 set: file probably ASCII text */
+#define CONTINUATION 0x02	/* bit 1 set: continuation of multi-part gzip file */
+#define EXTRA_FIELD  0x04	/* bit 2 set: extra field present */
+#define ORIG_NAME    0x08	/* bit 3 set: original file name present */
+#define COMMENT      0x10	/* bit 4 set: file comment present */
+#define ENCRYPTED    0x20	/* bit 5 set: file is encrypted */
+#define RESERVED     0xC0	/* bit 6,7:   reserved */
+
+
+static unsigned insize;	/* valid bytes in inbuf */
+static unsigned inptr;	/* index of next byte to be processed in inbuf */
+static unsigned outcnt;	/* bytes in output buffer */
+
+void variable_init(void);
+#if ZDEBUG > 0
+static void puts(const char *);
+extern void putc_init(void);
+extern void putc(unsigned char c);
+#endif
+static int fill_inbuf(void);
+static void flush_window(void);
+static void error(char *m);
+static void gzip_mark(void **);
+static void gzip_release(void **);
+
+extern char input_data[];
+
+extern char input_data_end[];
+
+#if ZDEBUG > 0
+void int2hex(unsigned long val)
+{
+        unsigned char buf[10];
+        int i;
+        for (i = 7;  i >= 0;  i--) {
+                buf[i] = "0123456789ABCDEF"[val & 0x0F];
+                val >>= 4;
+        }
+        buf[8] = '\0';
+        puts(buf);
+}
+#endif
+
+static unsigned long byte_count;
+
+int get_byte(void)
+{
+#if ZDEBUG > 1
+	static int printCnt;
+#endif
+	unsigned char c = (inptr < insize ? inbuf[inptr++] : fill_inbuf());
+	byte_count++;
+	
+#if ZDEBUG > 1
+	if (printCnt++ < 32) {
+		puts("byte count = ");
+		int2hex(byte_count);
+		puts(" byte val = ");
+		int2hex(c);
+		puts("\n");
+	}
+#endif
+	return c;
+}
+
+/* Diagnostic functions */
+#ifdef DEBUG
+#  define Assert(cond,msg) {if(!(cond)) error(msg);}
+#  define Trace(x) fprintf x
+#  define Tracev(x) {if (verbose) fprintf x ;}
+#  define Tracevv(x) {if (verbose>1) fprintf x ;}
+#  define Tracec(c,x) {if (verbose && (c)) fprintf x ;}
+#  define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}
+#else
+#  define Assert(cond,msg)
+#  define Trace(x)
+#  define Tracev(x)
+#  define Tracevv(x)
+#  define Tracec(c,x)
+#  define Tracecv(c,x)
+#endif
+
+/*
+ * This is set up by the setup-routine at boot-time
+ */
+
+static long bytes_out;
+static uch *output_data;
+static unsigned long output_ptr;
+
+
+static void *malloc(int size);
+static void free(void *where);
+static void error(char *m);
+static void gzip_mark(void **);
+static void gzip_release(void **);
+
+static unsigned long free_mem_ptr;
+static unsigned long free_mem_end_ptr;
+
+#include "../../../../../../lib/inflate.c"
+
+static void *malloc(int size)
+{
+	void *p;
+	
+	if (size < 0)
+		error("Malloc error\n");
+	if (free_mem_ptr <= 0) error("Memory error\n");
+	
+	free_mem_ptr = (free_mem_ptr + 3) & ~3;	/* Align */
+	
+	p = (void *) free_mem_ptr;
+	free_mem_ptr += size;
+	
+	if (free_mem_ptr >= free_mem_end_ptr)
+		error("\nOut of memory\n");
+	
+	return p;
+}
+
+static void free(void *where)
+{				/* Don't care */
+}
+
+static void gzip_mark(void **ptr)
+{
+	*ptr = (void *) free_mem_ptr;
+}
+
+static void gzip_release(void **ptr)
+{
+	free_mem_ptr = (long) *ptr;
+}
+#if ZDEBUG > 0
+static void puts(const char *s)
+{
+	while (*s) {
+		if (*s == 10)
+			putc(13);
+		putc(*s++);
+	}
+}
+#endif
+
+void *memset(void *s, int c, size_t n)
+{
+	int i;
+	char *ss = (char *) s;
+	
+	for (i = 0; i < n; i++)
+		ss[i] = c;
+	return s;
+}
+
+void *memcpy(void *__dest, __const void *__src, size_t __n)
+{
+	int i;
+	char *d = (char *) __dest, *s = (char *) __src;
+	
+	for (i = 0; i < __n; i++)
+		d[i] = s[i];
+	return __dest;
+}
+
+/* ===========================================================================
+ * Fill the input buffer. This is called only when the buffer is empty
+ * and at least one byte is really needed.
+ */
+static int fill_inbuf(void)
+{
+	if (insize != 0) {
+		error("ran out of input data\n");
+	}
+	
+	inbuf = input_data;
+	insize = &input_data_end[0] - &input_data[0];
+	inptr = 1;
+	return inbuf[0];
+}
+
+/* ===========================================================================
+ * Write the output window window[0..outcnt-1] and update crc and bytes_out.
+ * (Used for the decompressed data only.)
+ */
+static void flush_window(void)
+{
+	ulg c = crc;		/* temporary variable */
+	unsigned n;
+	uch *in, *out, ch;
+	
+	in = window;
+	out = &output_data[output_ptr];
+	for (n = 0; n < outcnt; n++) {
+		ch = *out++ = *in++;
+		c = crc_32_tab[((int) c ^ ch) & 0xff] ^ (c >> 8);
+	}
+	crc = c;
+	bytes_out += (ulg) outcnt;
+	output_ptr += (ulg) outcnt;
+	outcnt = 0;
+}
+
+#if ZDEBUG > 0
+void check_mem(void)
+{
+	int i;
+	
+	puts("\ncplens = ");
+	for (i = 0; i < 10; i++) {
+		int2hex(cplens[i]);
+		puts(" ");
+	}
+	puts("\ncplext = ");
+	for (i = 0; i < 10; i++) {
+		int2hex(cplext[i]);
+		puts(" ");
+	}
+	puts("\nborder = ");
+	for (i = 0; i < 10; i++) {
+		int2hex(border[i]);
+		puts(" ");
+	}
+	puts("\n");
+}
+#endif
+
+static void error(char *x)
+{
+#if ZDEBUG > 1
+	check_mem();
+	puts("\n\n");
+	puts(x);
+	puts("byte_count = ");
+	int2hex(byte_count);
+	puts("\n");
+	puts("\n\n -- Error. System halted");
+#endif
+	while (1);		/* Halt */
+}
+
+void variable_init(void)
+{
+	byte_count = 0;
+	output_data = (char *) LOADADDR;
+	free_mem_ptr = FREE_RAM;
+	free_mem_end_ptr = END_RAM;
+#if ZDEBUG > 1
+	puts("output_data      0x");
+	int2hex((unsigned long)output_data); puts("\n");
+	puts("free_mem_ptr     0x");
+	int2hex(free_mem_ptr); puts("\n");
+	puts("free_mem_end_ptr 0x");
+	int2hex(free_mem_end_ptr); puts("\n");
+	puts("input_data       0x");
+	int2hex((unsigned long)input_data); puts("\n");
+#endif
+}
+
+int decompress_kernel(void)
+{
+#if ZDEBUG > 0
+	putc_init();
+#if ZDEBUG > 2
+	check_mem();
+#endif
+#endif
+	
+	variable_init();
+	
+	makecrc();
+#if ZDEBUG > 0
+	puts("\n");
+	puts("Uncompressing Linux... \n");
+#endif
+	gunzip();		// ...see inflate.c
+#if ZDEBUG > 0
+	puts("Ok, booting the kernel.\n");
+#endif
+	
+#if ZDEBUG > 1
+	{
+		unsigned long *p = (unsigned long *)LOADADDR;
+		int2hex(p[0]); puts("\n");
+		int2hex(p[1]); puts("\n");
+		int2hex(p[2]); puts("\n");
+		int2hex(p[3]); puts("\n");
+	}
+#endif
+	
+	return 0;
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/rImage.lds idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/rImage.lds
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/rImage.lds	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/rImage.lds	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,31 @@
+OUTPUT_ARCH(mips)
+ENTRY(zstartup)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = 0x9FC00000;
+  .init          : { *(.init)		} =0
+  .text      :
+  {
+    _ftext = . ;
+    *(.text)
+    *(.rodata)
+    *(.rodata1)
+   . = ALIGN(4096);
+    input_data = .;
+    arch/mips/idt-boards/rc32434/EB434/boot/piggy.o
+    input_data_end = .;
+   . = ALIGN(4096);
+    *(.gnu.warning)
+  } =0
+
+  .reginfo : { *(.reginfo) }
+
+   . = 0x800A0000;
+  __bss_start = .;
+  .bss       :
+  {
+   *(.bss)
+  _end = . ;
+  }
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/s434.h idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/s434.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/s434.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/s434.h	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,137 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Some useful macros.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#ifndef __S434__
+#define __S434__
+/******************************** D E F I N E S *******************************/
+
+/*
+** following defines simple and uniform to save and restore context
+** when enrtering and leaving as assemblu language program when memory
+** and registers are both premiunm.
+*/
+#define SAVE_CNTXT  \
+  subu  sp, 64;     \
+  sw    t0, 60(sp); \
+  sw    t1, 56(sp); \
+  sw    t2, 52(sp); \
+  sw    t3, 48(sp); \
+  sw    t4, 44(sp); \
+  sw    t5, 40(sp); \
+  sw    t6, 36(sp); \
+  sw    t7, 32(sp); \
+  sw    t8, 28(sp); \
+  sw    t9, 24(sp); \
+  sw    a0, 20(sp); \
+  sw    a1, 16(sp); \
+  sw    a2, 12(sp); \
+  sw    a3,  8(sp); \
+  sw    ra,  4(sp)
+
+#define RSTR_CNTXT  \
+  lw    t0, 60(sp); \
+  lw    t1, 56(sp); \
+  lw    t2, 52(sp); \
+  lw    t3, 48(sp); \
+  lw    t4, 44(sp); \
+  lw    t5, 40(sp); \
+  lw    t6, 36(sp); \
+  lw    t7, 32(sp); \
+  lw    t8, 28(sp); \
+  lw    t9, 24(sp); \
+  lw    a0, 20(sp); \
+  lw    a1, 16(sp); \
+  lw    a2, 12(sp); \
+  lw    a3,  8(sp); \
+  lw    ra,  4(sp); \
+  add   sp, 64
+
+/*
+** Following define is to specify a maximum value for a software
+** busy wait counter.
+*/
+/*
+#define LP_CNT_100NS  1000      
+#define LP_CNT_3S     1000000   
+*/
+
+/*
+** Following are other common timer definitions.
+*/
+#define DDR_BASE           PHYS_TO_K1(0x18018000)
+#define TIMER_BASE        PHYS_TO_K1(0x18028000)  
+#define WTC_BASE          PHYS_TO_K1(0x18030000)
+#define INTERRUPT_BASE    PHYS_TO_K1(0x18038000)
+#define GPIO_BASE         PHYS_TO_K1(0x18050000)
+
+#define TIMEOUT_COUNT     0x00000FFF
+#define ENABLE_TIMER      0x1
+#define DISABLE_TIMER     0x0
+#define BIG_VALUE         0xFFFFFFFF
+
+/*
+** following few lines define a macro DISPLAY
+** which is used to write a set of 4 characters
+** onto the EB434/435 LED.
+*/
+
+#ifndef LED_BASE
+
+#define LED_BASE    PHYS_TO_K1(0x19000000)
+#define LED_DIGIT0  0x7
+#define LED_DIGIT1  0x6
+#define LED_DIGIT2  0x5
+#define LED_DIGIT3  0x4
+#define LED_CLEAR   0x0
+
+#endif
+
+#define DISPLAY(d0, d1, d2, d3)     \
+        li    t6, LED_BASE                    ;\
+        lb    t7, LED_CLEAR(t6)               ;\
+              nop                             ;\
+        li    t7, (d0) & 0xff                 ;\
+        sb    t7, LED_DIGIT0(t6)              ;\
+        li    t7, (d1) & 0xff                 ;\
+        sb    t7, LED_DIGIT1(t6)              ;\
+        li    t7, (d2) & 0xff                 ;\
+        sb    t7, LED_DIGIT2(t6)              ;\
+        li    t7, (d3) & 0xff                 ;\
+        sb    t7, LED_DIGIT3(t6)
+
+#define LEDCLEAR()              \
+        li    t6, LED_BASE                    ;\
+        lb    t7, LED_CLEAR(t6)               ;\
+              nop
+
+#define DESTRUCTIVE     1
+#define NONDESTRUCTIVE  0
+
+#endif
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/s434ram.h idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/s434ram.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/s434ram.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/s434ram.h	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,161 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   IDT EB434/435 DDR setup values.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+
+#ifndef __S434RAM__
+#define __S434RAM__
+/******************************** D E F I N E S *******************************/
+
+#define MB32      1
+#define MB64      2
+#define MB128     3
+
+#define DEV_CTL_BASE        PHYS_TO_K1(0x18010000)  /* device controller regs */
+#define DDR_CTL_BASE        PHYS_TO_K1(0x18018010)  /* DDR controller regs */
+
+#define DEV0_BASE           0x1FC00000
+#define DEV0_MASK           0xFFC00000
+#define DEV1_BASE           0x1A000000
+#define DEV1_MASK           0xFE000000
+#define DEV2_BASE           0x19000000
+#define DEV2_MASK           0xFF000000
+#define DEV3_BASE           0x00000000
+#define DEV3_MASK           0x00000000
+
+#if MHZ == 100000000
+#define DEV0_CTRL           0x04108324              /* 8-bit devices */
+#define DEV0_TC             0x00000000
+#define DEV1_CTRL           0x04108324              /* 8-bit devices */
+#define DEV1_TC             0x00000000
+#define DEV2_CTRL           0x04108324              /* 8-bit devices */
+#define DEV2_TC             0x00000000
+#define DEV3_CTRL           0x0FFFFFF4              /* 8-bit devices */
+#define DEV3_TC             0x00001FFF
+
+#elif MHZ == 133000000
+#define DEV0_CTRL           0x04108324              /* 8-bit devices */
+#define DEV0_TC             0x00000000
+#define DEV1_CTRL           0x05208324              /* 8-bit devices */
+#define DEV1_TC             0x00000000
+#define DEV2_CTRL           0x04108324              /* 8-bit devices */
+#define DEV2_TC             0x00000000
+#define DEV3_CTRL           0x0FFFFFF4              /* 8-bit devices */
+#define DEV3_TC             0x00001FFF
+
+#elif MHZ == 150000000
+#define DEV0_CTRL           0x04108324              /* 8-bit devices */
+#define DEV0_TC             0x00000000
+#define DEV1_CTRL           0x05208324              /* 8-bit devices */
+#define DEV1_TC             0x00000000
+#define DEV2_CTRL           0x04108324              /* 8-bit devices */
+#define DEV2_TC             0x00000000
+#define DEV3_CTRL           0x0FFFFFF4              /* 8-bit devices */
+#define DEV3_TC             0x00001FFF
+
+
+#elif MHZ == 175000000
+#define DEV0_CTRL           0x04108324              /* 8-bit devices */
+#define DEV0_TC             0x00000000
+#define DEV1_CTRL           0x05208324              /* 8-bit devices */
+#define DEV1_TC             0x00000000
+#define DEV2_CTRL           0x04108324              /* 8-bit devices */
+#define DEV2_TC             0x00000000
+#define DEV3_CTRL           0x0FFFFFF4              /* 8-bit devices */
+#define DEV3_TC             0x00001FFF
+
+#elif MHZ == 200000000
+#define DEV0_CTRL           0x05208324              /* 8-bit devices */
+#define DEV0_TC             0x00000000
+#define DEV1_CTRL           0x06308324              /* 8-bit devices */
+#define DEV1_TC             0x00000000
+#define DEV2_CTRL           0x05208324              /* 8-bit devices */
+#define DEV2_TC             0x00000000
+#define DEV3_CTRL           0x0FFFFFF4              /* 8-bit devices */
+#define DEV3_TC             0x00001FFF
+#endif
+
+#define DATA_PATTERN        0xA5A5A5A5
+#define RCOUNT              PHYS_TO_K1(0x18028030)
+
+#if DRAMSZ == MB32
+
+#define DDR_BASE_VAL          0x00000000
+#define DDR_MASK_VAL          0xFE000000
+#define DDR_ABASE_VAL         0x08000000
+#define DDR_AMASK_VAL         0x00000000
+
+#if MHZ == 100000000
+#define DDRC_VAL_NORMAL       0x82184800
+#define DDRC_VAL_AT_INIT      0x02184800
+#define DDR_REF_CMP_VAL       0x0000030c
+#elif MHZ == 133000000
+#define DDRC_VAL_NORMAL       0x82984800
+#define DDRC_VAL_AT_INIT      0x02984800
+#define DDR_REF_CMP_VAL       0x0000040e
+#elif MHZ == 150000000
+#define DDRC_VAL_NORMAL       0x82984800
+#define DDRC_VAL_AT_INIT      0x02984800
+#define DDR_REF_CMP_VAL       0x00000492
+#elif MHZ == 175000000
+#define DDRC_VAL_NORMAL       0x82994800
+#define DDRC_VAL_AT_INIT      0x02994800
+#define DDR_REF_CMP_VAL       0x00000516
+#elif MHZ == 200000000
+#define DDRC_VAL_NORMAL       0x82994800
+#define DDRC_VAL_AT_INIT      0x02994800
+#define DDR_REF_CMP_VAL       0x00000618
+#else
+#warning illegal value for MHZ
+#endif
+
+#define DDR_REF_CMP_FAST      0x00000080
+
+#define DDR_CUST_NOP          0x0000003F
+#define DDR_CUST_PRECHARGE    0x00000033
+#define DDR_CUST_REFRESH      0x00000027
+#define DDR_LD_MODE_REG       0x00000023
+#define DDR_LD_EMODE_REG      0x00000063
+
+/* 
+ * All generated addresses for DDR init during custom transactions are shifted
+ * by two address lines - see spec for used DDR chip
+ */
+#define DDR_PRECHARGE_OFFSET  0x00001000  /* 0x0400 - 9-bit page*/
+#define DDR_EMODE_VAL         0x00000000  /* 0x0000 */
+#define DDR_DLL_RES_MODE_VAL  0x00000584  /* 0x0161 - Reset DLL, CL2.5 */
+#define DDR_DLL_MODE_VAL      0x00000184  /* 0x0061 - CL2.5 */
+
+#define DELAY_200USEC         25000       /* not exactly */
+
+#else
+#error "unrecognized dram size"
+#endif
+
+#endif
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/uart16550.c idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/uart16550.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/uart16550.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/uart16550.c	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,154 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   UART code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#define RC32434_REG_BASE   0xb8000000
+#ifdef __MIPSEB__
+#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
+#else
+#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
+#endif
+
+#define BASE		        RC32434_UART0_BASE
+#define MAX_BAUD		(CONFIG_IDT_BOARD_FREQ / 16)
+#define REG_OFFSET		0x4
+
+
+#if (!defined(BASE) || !defined(MAX_BAUD) || !defined(REG_OFFSET))
+#error You must define BASE, MAX_BAUD and REG_OFFSET in the Makefile.
+#endif
+
+#ifndef INIT_SERIAL_PORT
+#define INIT_SERIAL_PORT	1
+#endif
+
+#ifndef DEFAULT_BAUD
+//#define DEFAULT_BAUD		UART16550_BAUD_115200
+#define DEFAULT_BAUD		UART16550_BAUD_9600
+#endif
+#ifndef DEFAULT_PARITY
+#define DEFAULT_PARITY		UART16550_PARITY_NONE
+#endif
+#ifndef DEFAULT_DATA
+#define DEFAULT_DATA		UART16550_DATA_8BIT
+#endif
+#ifndef DEFAULT_STOP
+#define DEFAULT_STOP		UART16550_STOP_1BIT
+#endif
+
+/* === END OF CONFIG === */
+
+typedef         unsigned char uint8;
+typedef         unsigned int  uint32;
+
+#define         UART16550_BAUD_2400             2400
+#define         UART16550_BAUD_4800             4800
+#define         UART16550_BAUD_9600             9600
+#define         UART16550_BAUD_19200            19200
+#define         UART16550_BAUD_38400            38400
+#define         UART16550_BAUD_57600            57600
+#define         UART16550_BAUD_115200           115200
+
+#define         UART16550_PARITY_NONE           0
+#define         UART16550_PARITY_ODD            0x08
+#define         UART16550_PARITY_EVEN           0x18
+#define         UART16550_PARITY_MARK           0x28
+#define         UART16550_PARITY_SPACE          0x38
+
+#define         UART16550_DATA_5BIT             0x0
+#define         UART16550_DATA_6BIT             0x1
+#define         UART16550_DATA_7BIT             0x2
+#define         UART16550_DATA_8BIT             0x3
+
+#define         UART16550_STOP_1BIT             0x0
+#define         UART16550_STOP_2BIT             0x4
+
+/* register offset */
+#define		OFS_RCV_BUFFER		(0*REG_OFFSET)
+#define		OFS_TRANS_HOLD		(0*REG_OFFSET)
+#define		OFS_SEND_BUFFER		(0*REG_OFFSET)
+#define		OFS_INTR_ENABLE		(1*REG_OFFSET)
+#define		OFS_INTR_ID		(2*REG_OFFSET)
+#define		OFS_DATA_FORMAT		(3*REG_OFFSET)
+#define		OFS_LINE_CONTROL	(3*REG_OFFSET)
+#define		OFS_MODEM_CONTROL	(4*REG_OFFSET)
+#define		OFS_RS232_OUTPUT	(4*REG_OFFSET)
+#define		OFS_LINE_STATUS		(5*REG_OFFSET)
+#define		OFS_MODEM_STATUS	(6*REG_OFFSET)
+#define		OFS_RS232_INPUT		(6*REG_OFFSET)
+#define		OFS_SCRATCH_PAD		(7*REG_OFFSET)
+
+#define		OFS_DIVISOR_LSB		(0*REG_OFFSET)
+#define		OFS_DIVISOR_MSB		(1*REG_OFFSET)
+
+#define		UART16550_READ(y)    (*((volatile uint8*)(BASE + y)))
+#define		UART16550_WRITE(y, z)  ((*((volatile uint8*)(BASE + y))) = z)
+
+static void Uart16550Init(uint32 baud, uint8 data, uint8 parity, uint8 stop)
+{
+	/* disable interrupts */
+	UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
+	UART16550_WRITE(OFS_INTR_ENABLE, 0);
+	
+	/* set up baud rate */
+	{
+		uint32 divisor;
+		
+		/* set DIAB bit */
+		UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
+		
+		/* set divisor */
+		divisor = MAX_BAUD / baud;
+		UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
+		UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00)>>8);
+		
+		/* clear DIAB bit */
+		UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
+	}
+	
+	/* set data format */
+	UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
+}
+
+
+void
+putc_init(void)
+{
+#if INIT_SERIAL_PORT
+	Uart16550Init(DEFAULT_BAUD, DEFAULT_DATA, DEFAULT_PARITY, DEFAULT_STOP);
+#endif
+}
+
+void
+putc(unsigned char c)
+{
+	while ((UART16550_READ(OFS_LINE_STATUS) &0x20) == 0);
+	UART16550_WRITE(OFS_SEND_BUFFER, c);
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/zImage.lds idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/zImage.lds
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/zImage.lds	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/zImage.lds	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,31 @@
+OUTPUT_ARCH(mips)
+ENTRY(zstartup)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = 0x9b000000;
+  .init          : { *(.init)		} =0
+  .text      :
+  {
+    _ftext = . ;
+    *(.text)
+    *(.rodata)
+    *(.rodata1)
+   . = ALIGN(4096);
+    input_data = .;
+    arch/mips/idt-boards/rc32434/EB434/boot/piggy.o
+    input_data_end = .;
+   . = ALIGN(4096);
+    *(.gnu.warning)
+  } =0
+
+  .reginfo : { *(.reginfo) }
+
+   . = 0x800A0000;
+  __bss_start = .;
+  .bss       :
+  {
+   *(.bss)
+  _end = . ;
+  }
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/idtIRQ.S idtlinux/arch/mips/idt-boards/rc32434/EB434/idtIRQ.S
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/idtIRQ.S	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/idtIRQ.S	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,79 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Intterrupt dispatcher code for IDT boards
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+		
+	
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
+
+	.text
+	.set	noreorder
+	.set	noat
+	.align	5
+	NESTED(idtIRQ, PT_SIZE, sp)
+	.set noat
+	SAVE_ALL
+	CLI
+
+	.set	at
+	.set	noreorder
+
+	/* Get the pending interrupts */
+	mfc0    t0, CP0_CAUSE
+	nop
+			 
+	/* Isolate the allowed ones by anding the irq mask */
+	mfc0    t2, CP0_STATUS
+	move	a1, sp		/* need a nop here, hence we anticipate */
+	andi    t0, CAUSEF_IP
+	and     t0, t2
+								  
+	/* check for r4k counter/timer IRQ. */
+	
+	andi    t1, t0, CAUSEF_IP7
+	beqz    t1, 1f
+	nop
+
+	jal     idt_timer_interrupt	
+
+	li	a0, 7
+
+	j	ret_from_irq
+	nop
+1:
+	jal	rc32434_irqdispatch
+	move	a0, t0
+	j	ret_from_irq
+	nop
+
+	END(idtIRQ)
+
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/irq.c idtlinux/arch/mips/idt-boards/rc32434/EB434/irq.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/irq.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/irq.c	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,263 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Interrupt routines for IDT EB434/435 boards
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/delay.h>
+
+#include <asm/bitops.h>
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+#include <asm/idt-boards/rc32434/rc32434.h>
+#include <asm/idt-boards/rc32434/rc32434_gpio.h>
+
+#include <asm/irq.h>
+
+#undef DEBUG_IRQ
+#ifdef DEBUG_IRQ
+/* note: prints function name for you */
+#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
+#else
+#define DPRINTK(fmt, args...)
+#endif
+
+extern asmlinkage void idtIRQ(void);
+static unsigned int startup_irq(unsigned int irq);
+static void end_irq(unsigned int irq_nr);
+static void mask_and_ack_irq(unsigned int irq_nr);
+static void rc32434_enable_irq(unsigned int irq_nr);
+static void rc32434_disable_irq(unsigned int irq_nr);
+
+extern void __init init_generic_irq(void);
+
+typedef struct {
+	u32 mask;
+	volatile u32 *base_addr;
+} intr_group_t;
+
+static const intr_group_t intr_group[NUM_INTR_GROUPS] = {
+	{ 0x0000efff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET) },
+	{ 0x00001fff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET) },
+	{ 0x00000007, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET) },
+	{ 0x0003ffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET) },
+	{ 0xffffffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET) }
+};
+
+#define READ_PEND(base) (*(base))
+#define READ_MASK(base) (*(base + 2))
+#define WRITE_MASK(base, val) (*(base + 2) = (val))
+
+static inline int irq_to_group(unsigned int irq_nr)
+{
+	return ((irq_nr - GROUP0_IRQ_BASE) >> 5);
+}
+
+static inline int group_to_ip(unsigned int group)
+{
+	return group + 2;
+}
+
+static inline void enable_local_irq(unsigned int ip)
+{
+	int ipnum = 0x100 << ip;
+	clear_c0_cause(ipnum);
+	set_c0_status(ipnum);
+}
+
+static inline void disable_local_irq(unsigned int ip)
+{
+	int ipnum = 0x100 << ip;
+	clear_c0_status(ipnum);
+}
+
+static inline void ack_local_irq(unsigned int ip)
+{
+	int ipnum = 0x100 << ip;
+	clear_c0_cause(ipnum);
+}
+
+static void rc32434_enable_irq(unsigned int irq_nr)
+{
+	int           ip = irq_nr - GROUP0_IRQ_BASE;
+	unsigned int  group, intr_bit;
+	volatile unsigned int  *addr;
+	if (ip < 0) {
+		enable_local_irq(irq_nr);
+	}
+	else {
+		// calculate group
+		group = ip >> 5;
+		
+		// calc interrupt bit within group
+		ip -= (group << 5);
+		intr_bit = 1 << ip;
+		
+		// first enable the IP mapped to this IRQ
+		enable_local_irq(group_to_ip(group));
+		
+		addr = intr_group[group].base_addr;
+		// unmask intr within group
+		WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
+	}
+}
+
+static void rc32434_disable_irq(unsigned int irq_nr)
+{
+	int           ip = irq_nr - GROUP0_IRQ_BASE;
+	unsigned int  group, intr_bit, mask;
+	volatile unsigned int  *addr;
+	
+	// calculate group
+	group = ip >> 5;
+	
+	// calc interrupt bit within group
+	ip -= group << 5;
+	intr_bit = 1 << ip;
+	
+	addr = intr_group[group].base_addr;
+	// mask intr within group
+	mask = READ_MASK(addr);
+	mask |= intr_bit;
+	WRITE_MASK(addr, mask);
+	
+	/*
+	  if there are no more interrupts enabled in this
+	  group, disable corresponding IP
+	*/
+	if (mask == intr_group[group].mask)
+		disable_local_irq(group_to_ip(group));
+}
+
+static unsigned int startup_irq(unsigned int irq_nr)
+{
+	rc32434_enable_irq(irq_nr);
+	return 0; 
+}
+
+static void shutdown_irq(unsigned int irq_nr)
+{
+	rc32434_disable_irq(irq_nr);
+	return;
+}
+
+static void mask_and_ack_irq(unsigned int irq_nr)
+{
+	rc32434_disable_irq(irq_nr);
+	ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
+}
+
+static void end_irq(unsigned int irq_nr)
+{
+	
+	int ip = irq_nr - GROUP0_IRQ_BASE;
+	unsigned int intr_bit, group;
+	volatile unsigned int *addr;
+	
+	if (!(irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
+		if (irq_nr == GROUP4_IRQ_BASE + 11)
+			gpio->gpioistat = 0xfffff7ff;
+		
+		group = ip >> 5;
+		
+		// calc interrupt bit within group
+		ip -= (group << 5);
+		intr_bit = 1 << ip;
+		
+		// first enable the IP mapped to this IRQ
+		enable_local_irq(group_to_ip(group));
+		
+		addr = intr_group[group].base_addr;
+		// unmask intr within group
+		WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
+	} 
+	else {
+		printk("warning: end_irq %d did not enable (%x)\n", 
+		       irq_nr, irq_desc[irq_nr].status);
+	}
+}
+
+static struct hw_interrupt_type rc32434_irq_type = {
+	.typename = "IDT434",
+	.startup  = startup_irq,
+	.shutdown = shutdown_irq,
+	.enable   = rc32434_enable_irq,
+	.disable  = rc32434_disable_irq,
+	.ack      = mask_and_ack_irq,
+	.end      = end_irq,
+};
+
+void __init arch_init_irq(void)
+{
+	int i;
+	printk("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);  
+	memset(irq_desc, 0, sizeof(irq_desc));
+	set_except_vector(0, idtIRQ);
+	
+	for (i = 0; i < RC32434_NR_IRQS; i++) {
+		irq_desc[i].status = IRQ_DISABLED;
+		irq_desc[i].action = NULL;
+		irq_desc[i].depth = 1;
+		irq_desc[i].handler = &rc32434_irq_type;
+		spin_lock_init(&irq_desc[i].lock);
+	}
+}
+
+/* Main Interrupt dispatcher */
+void rc32434_irqdispatch(unsigned long cp0_cause, struct pt_regs *regs)
+{
+	unsigned int ip, pend, group;
+	volatile unsigned int *addr;
+	
+	if ((ip = (cp0_cause & 0x7c00))) {
+		group = 21 - rc32434_clz(ip);
+		
+		addr = intr_group[group].base_addr;
+		
+		pend = READ_PEND(addr);
+		pend &= ~READ_MASK(addr); // only unmasked interrupts
+		pend = 39 - rc32434_clz(pend);
+		do_IRQ((group << 5) + pend, regs);
+		return;
+	} 
+	else
+		return;
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/Makefile idtlinux/arch/mips/idt-boards/rc32434/EB434/Makefile
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/Makefile	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/Makefile	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,41 @@
+###############################################################################
+#
+#  BRIEF MODULE DESCRIPTION
+#     Makefile for IDT EB434 BSP
+#
+#  Copyright 2006 IDT Inc. (rischelp@idt.com)
+#
+#  This program is free software; you can redistribute  it and/or modify it
+#  under  the terms of  the GNU General  Public License as published by the
+#  Free Software Foundation;  either version 2 of the  License, or (at your
+#  option) any later version.
+#
+#  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+#  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+#   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+#   NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+#   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+#   NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+#   USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+#   ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+#   THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#   You should have received a copy of the  GNU General Public License along
+#   with this program; if not, write  to the Free Software Foundation, Inc.,
+#   675 Mass Ave, Cambridge, MA 02139, USA.
+# 
+###############################################################################
+
+
+.S.s:
+	$(CPP) $(CFLAGS) $< -o $*.s
+.S.o:
+	$(CC) $(CFLAGS) -c $< -o $*.o
+
+obj-y	 := prom.o setup.o idtIRQ.o reset.o irq.o time.o
+obj-$(CONFIG_KGDB)			+= serial_gdb.o
+obj-$(CONFIG_SERIAL_8250) 		+= serial.o
+subdir-$(CONFIG_IDT_BOOT_NVRAM)		+= nvram
+obj-$(CONFIG_IDT_BOOT_NVRAM)    	+= nvram/built-in.o
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/nvram/Makefile idtlinux/arch/mips/idt-boards/rc32434/EB434/nvram/Makefile
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/nvram/Makefile	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/nvram/Makefile	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,39 @@
+###############################################################################
+#
+#  BRIEF MODULE DESCRIPTION
+#     Makefile for IDT EB434/435 nvram access routines
+#
+#  Copyright 2006 IDT Inc. (rischelp@idt.com)
+#
+#  This program is free software; you can redistribute  it and/or modify it
+#  under  the terms of  the GNU General  Public License as published by the
+#  Free Software Foundation;  either version 2 of the  License, or (at your
+#  option) any later version.
+#
+#  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+#  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+#   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+#   NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+#   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+#   NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+#   USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+#   ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+#   THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#   You should have received a copy of the  GNU General Public License along
+#   with this program; if not, write  to the Free Software Foundation, Inc.,
+#   675 Mass Ave, Cambridge, MA 02139, USA.
+#
+#
+###############################################################################
+
+obj-y   := nvram434.o
+obj-m   := $(O_TARGET)
+
+
+
+
+
+
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/nvram/nvram434.c idtlinux/arch/mips/idt-boards/rc32434/EB434/nvram/nvram434.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/nvram/nvram434.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/nvram/nvram434.c	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,382 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     nvram interface routines.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/ctype.h>
+#include <linux/string.h>
+
+//#include <asm/ds1553rtc.h>
+#include "nvram434.h"
+#include "rtc.h"
+#define  NVRAM_BASE RTCLOCK_BASE
+
+extern void setenv (char *e, char *v, int rewrite);
+extern void unsetenv (char *e);
+extern void mapenv (int (*func)(char *, char *));
+extern char *getenv (char *s);
+extern void purgeenv(void);
+
+static void nvram_initenv(void);
+
+static unsigned char
+nvram_getbyte(int offs)
+{
+  return(*((unsigned char*)(NVRAM_BASE + offs)));
+}
+
+static void
+nvram_setbyte(int offs, unsigned char val)
+{
+  unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
+
+  *nvramDataPointer = val;
+}
+
+/*
+ * BigEndian!
+ */
+static unsigned short
+nvram_getshort(int offs)
+{
+  return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
+}
+
+static void
+nvram_setshort(int offs, unsigned short val)
+{
+  nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
+  nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
+}
+#if 0
+static unsigned int
+nvram_getint(int offs)
+{
+  unsigned int val;
+  val = nvram_getbyte(offs) << 24;
+  val |= nvram_getbyte(offs + 1) << 16;
+  val |= nvram_getbyte(offs + 2) << 8;
+  val |= nvram_getbyte(offs + 3);
+  return(val);
+}
+
+static void
+nvram_setint(int offs, unsigned int val)
+{
+  nvram_setbyte(offs, val >> 24);
+  nvram_setbyte(offs + 1, val >> 16);
+  nvram_setbyte(offs + 2, val >> 8);
+  nvram_setbyte(offs + 3, val);
+}
+#endif
+/*
+ * calculate NVRAM checksum
+ */
+static unsigned short
+nvram_calcsum(void)
+{
+  unsigned short sum = NV_MAGIC;
+  int     i;
+
+  for (i = ENV_BASE; i < ENV_TOP; i += 2)
+    sum += nvram_getshort(i);
+  return(sum);
+}
+
+/*
+ * update the nvram checksum
+ */
+static void
+nvram_updatesum (void)
+{
+  nvram_setshort(NVOFF_CSUM, nvram_calcsum());
+}
+
+/*
+ * test validity of nvram by checksumming it
+ */
+static int
+nvram_isvalid(void)
+{
+  static int  is_valid;
+
+  if (is_valid)
+    return(1);
+
+  if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC)
+    nvram_initenv();
+  is_valid = 1;
+  return(1);
+}
+
+/* return nvram address of environment string */
+static int
+nvram_matchenv(char *s)
+{
+  int envsize, envp, n, i, varsize;
+  char *var;
+
+  envsize = nvram_getshort(NVOFF_ENVSIZE);
+  if (envsize > ENV_AVAIL)
+    return(0);     /* sanity */
+    
+  envp = ENV_BASE;
+
+  if ((n = strlen (s)) > 255)
+    return(0);
+    
+  while (envsize > 0) {
+    varsize = nvram_getbyte(envp);
+    if (varsize == 0 || (envp + varsize) > ENV_TOP)
+      return(0);   /* sanity */
+    for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
+      char c1 = nvram_getbyte(i);
+      char c2 = *var;
+      if (islower(c1))
+        c1 = toupper(c1);
+      if (islower(c2))
+        c2 = toupper(c2);
+      if (c1 != c2)
+        break;
+    }
+    if (i > envp + n) {       /* match so far */
+      if (n == varsize - 1)   /* match on boolean */
+        return(envp);
+      if (nvram_getbyte(i) == '=')  /* exact match on variable */
+        return(envp);
+    }
+    envsize -= varsize;
+    envp += varsize;
+  }
+  return(0);
+}
+
+static void nvram_initenv(void)
+{
+  nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
+  nvram_setshort(NVOFF_ENVSIZE, 0);
+
+  nvram_updatesum();
+}
+
+static void
+nvram_delenv(char *s)
+{
+  int nenvp, envp, envsize, nbytes;
+
+  envp = nvram_matchenv(s);
+  if (envp == 0)
+    return;
+
+  nenvp = envp + nvram_getbyte(envp);
+  envsize = nvram_getshort(NVOFF_ENVSIZE);
+  nbytes = envsize - (nenvp - ENV_BASE);
+  nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
+  while (nbytes--) {
+    nvram_setbyte(envp, nvram_getbyte(nenvp));
+    envp++;
+    nenvp++;
+  }
+  nvram_updatesum();
+}
+
+static int
+nvram_setenv(char *s, char *v)
+{
+  int ns, nv, total;
+  int envp;
+
+  if (!nvram_isvalid())
+    return(-1);
+
+  nvram_delenv(s);
+  ns = strlen(s);
+  if (ns == 0)
+    return (-1);
+  if (v && *v) {
+    nv = strlen(v);
+    total = ns + nv + 2;
+  }
+  else {
+    nv = 0;
+    total = ns + 1;
+  }
+  if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
+    return(-1);
+
+  envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
+
+  nvram_setbyte(envp, (unsigned char) total); 
+  envp++;
+
+  while (ns--) {
+    nvram_setbyte(envp, *s); 
+    envp++; 
+    s++;
+  }
+
+  if (nv) {
+    nvram_setbyte(envp, '='); 
+    envp++;
+    while (nv--) {
+      nvram_setbyte(envp, *v); 
+      envp++; 
+      v++;
+    }
+  }
+  nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
+  nvram_updatesum();
+  return 0;
+}
+
+static char *
+nvram_getenv(char *s)
+{
+  static char buf[256];   /* FIXME: this cannot be static */
+  int envp, ns, nbytes, i;
+
+  if (!nvram_isvalid())
+    return((char *)0);
+
+  envp = nvram_matchenv(s);
+  if (envp == 0)
+    return((char *)0);
+  ns = strlen(s);
+  if (nvram_getbyte(envp) == ns + 1)  /* boolean */
+    buf[0] = '\0';
+  else {
+    nbytes = nvram_getbyte(envp) - (ns + 2);
+    envp += ns + 2;
+    for (i = 0; i < nbytes; i++)
+      buf[i] = nvram_getbyte(envp++);
+    buf[i] = '\0';
+  }
+  return(buf);
+}
+
+static void
+nvram_unsetenv(char *s)
+{
+  if (!nvram_isvalid())
+    return;
+
+  nvram_delenv(s);
+}
+
+/*
+ * apply func to each string in environment
+ */
+static void
+nvram_mapenv(int (*func)(char *, char *))
+{
+  int envsize, envp, n, i, seeneql;
+  char name[256], value[256];
+  char c, *s;
+
+  if (!nvram_isvalid())
+    return;
+
+  envsize = nvram_getshort(NVOFF_ENVSIZE);
+  envp = ENV_BASE;
+
+  while (envsize > 0) {
+    value[0] = '\0';
+    seeneql = 0;
+    s = name;
+    n = nvram_getbyte(envp);
+    for (i = envp + 1; i < envp + n; i++) {
+      c = nvram_getbyte(i);
+      if ((c == '=') && !seeneql) {
+        *s = '\0';
+        s = value;
+        seeneql = 1;
+        continue;
+      }
+      *s++ = c;
+    }
+    *s = '\0';
+    (*func)(name, value);
+    envsize -= n;
+    envp += n;
+  }
+}
+#if 0
+static unsigned int
+digit(char c)
+{
+  if ('0' <= c && c <= '9')
+    return (c - '0');
+  if ('A' <= c && c <= 'Z')
+    return (10 + c - 'A');
+  if ('a' <= c && c <= 'z')
+    return (10 + c - 'a');
+  return (~0);
+}
+#endif
+/*
+ * Wrappers to allow 'special' environment variables to get processed
+ */
+void
+setenv(char *e, char *v, int rewrite)
+{
+  if (nvram_getenv(e) && !rewrite)
+    return;
+    
+  nvram_setenv(e, v);
+}
+
+char *
+getenv(char *e)
+{
+  return(nvram_getenv(e));
+}
+
+void
+unsetenv(char *e)
+{
+  nvram_unsetenv(e);
+}
+
+void
+purgeenv()
+{
+  int i;
+  unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
+  
+  for (i = ENV_BASE; i < ENV_TOP; i++)
+    *nvramDataPointer++ = 0;
+  nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
+  nvram_setshort(NVOFF_ENVSIZE, 0);
+  nvram_setshort(NVOFF_CSUM, NV_MAGIC);
+}
+
+void
+mapenv(int (*func)(char *, char *))
+{
+  nvram_mapenv(func);
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/nvram/nvram434.h idtlinux/arch/mips/idt-boards/rc32434/EB434/nvram/nvram434.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/nvram/nvram434.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/nvram/nvram434.h	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,58 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     nvram definitions.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+
+#ifndef _NVRAM_
+#define _NVRAM_
+#define NVOFFSET        0                 /* use all of NVRAM */
+
+/* Offsets to reserved locations */
+              /* size description */
+#define NVOFF_MAGIC     (NVOFFSET + 0)    /* 2 magic value */
+#define NVOFF_CSUM      (NVOFFSET + 2)    /* 2 NVRAM environment checksum */
+#define NVOFF_ENVSIZE   (NVOFFSET + 4)    /* 2 size of 'environment' */
+#define NVOFF_TEST      (NVOFFSET + 5)    /* 1 cold start test byte */
+#define NVOFF_ETHADDR   (NVOFFSET + 6)    /* 6 decoded ethernet address */
+#define NVOFF_UNUSED    (NVOFFSET + 12)   /* 0 current end of table */
+
+#define NV_MAGIC        0xdeaf            /* nvram magic number */
+#define NV_RESERVED     32                /* number of reserved bytes */
+
+#undef  NVOFF_ETHADDR
+#define NVOFF_ETHADDR   (NVOFFSET + NV_RESERVED - 6)
+
+/* number of bytes available for environment */
+#define ENV_BASE        (NVOFFSET + NV_RESERVED)
+#define ENV_TOP         TD_NVRAM_SIZE
+#define ENV_AVAIL       (ENV_TOP - ENV_BASE)
+
+#endif /* _NVRAM_ */
+
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/nvram/rtc.h idtlinux/arch/mips/idt-boards/rc32434/EB434/nvram/rtc.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/nvram/rtc.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/nvram/rtc.h	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,72 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     DS1553(Dallas Semiconductor) Real Time Clock and Non-Volatile RAM.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+
+#define RTCLOCK_BASE    0xBA000000
+
+/*
+ * To maintain endianess independence, make all accesses as 32-bit
+ * words with appropriate shifting.
+ */
+#define TD_NVRAM_SIZE 0x1FF0
+
+typedef struct td_clock {
+  unsigned char ram[TD_NVRAM_SIZE];
+  unsigned char flags;
+  unsigned char dummy;
+  unsigned char alarm_secs;
+  unsigned char alarm_mins;
+  unsigned char alarm_hours;
+  unsigned char alarm_date;
+  unsigned char interrupts;
+  unsigned char watchdog;
+  unsigned char century;
+  unsigned char secs;
+  unsigned char mins;
+  unsigned char hours;
+  unsigned char weekday;
+  unsigned char date;
+  unsigned char month;
+  unsigned char year;
+} RTC;
+
+#define rtc (*((volatile RTC *)RTCLOCK_BASE))
+
+/*
+ * Control register bit definitions
+ */
+#define TDC_ENA_READ      0x40
+#define TDC_DIS_READ      0xBF
+
+#define TDC_ENA_WRITE     0x80
+#define TDC_DIS_WRITE     0x7F
+
+#define TDC_RUN_OSC       0x80
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/prom.c idtlinux/arch/mips/idt-boards/rc32434/EB434/prom.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/prom.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/prom.c	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,142 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     prom interface routines
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/console.h>
+#include <asm/bootinfo.h>
+#include <linux/bootmem.h>
+#include <linux/ioport.h>
+#include <linux/serial.h>
+#include <linux/serialP.h>
+#include <asm/serial.h>
+#include <linux/ioport.h>
+
+
+unsigned int idt_cpu_freq = CONFIG_IDT_BOARD_FREQ;
+EXPORT_SYMBOL(idt_cpu_freq);
+
+extern void setup_serial_port(void);
+#ifdef CONFIG_IDT_BOOT_NVRAM
+extern void mapenv(int (*func)(char *, char *));
+static int make_bootparm(char *name,char *val)
+{ 
+/*
+ * The bootparameters are obtained from NVRAM and formatted here.
+ * For e.g.
+ *
+ *    netaddr=10.0.1.95
+ *    bootaddr=10.0.0.139
+ *    bootfile=vmlinus
+ *    bootparm1=root=/dev/nfs
+ *    bootparm2=ip=10.0.1.95
+ *
+ * is parsed to:
+ *
+ *      root=/dev/nfs ip=10.0.1.95
+ *
+ * in arcs_cmdline[].
+ */
+	if (strncmp(name, "bootparm", 8) == 0) {
+		strcat(arcs_cmdline,val);
+		strcat(arcs_cmdline," ");
+	}
+	else if(strncmp(name, "HZ", 2) == 0) {
+		idt_cpu_freq = simple_strtoul(val, 0, 10);
+		printk("CPU Clock at %d Hz (from HZ environment variable)\n",
+		       idt_cpu_freq);
+	}
+	return 0;
+}
+
+static void prom_init_cmdline(void)
+{ 
+	memset(arcs_cmdline,0,sizeof(arcs_cmdline));
+	mapenv(&make_bootparm);
+}
+#else
+/* Kernel Boot parameters */
+//static unsigned char bootparm[]="ip=157.165.29.36:157.165.29.18::255.255.0.0::eth0";
+static unsigned char bootparm[]="console=ttyS0,9600";
+#endif
+extern unsigned long mips_machgroup;
+extern unsigned long mips_machtype;
+
+/* IDT 79EB434/435 memory map -- we really should be auto sizing it */
+
+#define RAM_FIRST       0x80000400  /* Leave room for interrupt vectors */
+#define RAM_SIZE        32*1024*1024
+#define RAM_END         (0x80000000 + RAM_SIZE)     
+struct resource rc32434_res_ram = {
+	"RAM",
+	0,
+	RAM_SIZE,
+	IORESOURCE_MEM
+};
+
+char * __init prom_getcmdline(void)
+{ 
+	return &(arcs_cmdline[0]);
+}
+
+
+void __init prom_init(void)
+{
+#ifdef CONFIG_IDT_BOOT_NVRAM
+	/* set up command line */
+	prom_init_cmdline();
+#else
+	sprintf(arcs_cmdline,"%s",bootparm);
+#endif
+	
+	/* turn on the console */
+	
+	setup_serial_port();
+	/* set our arch type */
+	
+	mips_machgroup = MACH_GROUP_IDT;
+	mips_machtype = MACH_IDT_EB434;
+	
+	/*
+	 * give all RAM to boot allocator,
+	 * except where the kernel was loaded
+	 */
+	add_memory_region(0,
+			  rc32434_res_ram.end - rc32434_res_ram.start,
+			  BOOT_MEM_RAM);
+}
+
+void prom_free_prom_memory(void)
+{
+	printk("stubbed prom_free_prom_memory()\n");
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/reset.c idtlinux/arch/mips/idt-boards/rc32434/EB434/reset.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/reset.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/reset.c	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,47 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Reset EB434/435 board.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/irq.h>
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <linux/ioport.h>
+#include <asm/mipsregs.h>
+#include <asm/pgtable.h>
+#include <asm/reboot.h>
+#include <asm/addrspace.h>     /* for KSEG1ADDR() */
+
+void idt_reset(void)
+{
+	/* Reset*/
+	*(volatile u32 *)KSEG1ADDR(0x18008000) = 0x80000001;
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/serial.c idtlinux/arch/mips/idt-boards/rc32434/EB434/serial.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/serial.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/serial.c	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,85 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Serial port initialisation.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+
+#include <asm/time.h>
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/serial.h>
+
+#include <asm/idt-boards/rc32434/rc32434.h>
+extern int __init early_serial_setup(struct uart_port *port);
+
+#define BASE_BAUD (1843200 / 16)
+
+extern unsigned int idt_cpu_freq;
+extern int __init setup_serial_port(void)
+{
+	static struct uart_port serial_req[2];
+	
+	memset(serial_req, 0, sizeof(serial_req));
+	serial_req[0].type       = PORT_16550A;
+	serial_req[0].line       = 0;
+	serial_req[0].irq        = RC32434_UART0_IRQ;
+	serial_req[0].flags      = STD_COM_FLAGS;
+	serial_req[0].uartclk    = idt_cpu_freq;
+	serial_req[0].iotype     = SERIAL_IO_MEM;
+	serial_req[0].membase    = (char *) KSEG1ADDR(RC32434_UART0_BASE);
+	//  serial_req[0].fifosize   = 14;
+	serial_req[0].mapbase   = KSEG1ADDR(RC32434_UART0_BASE);
+	serial_req[0].regshift   = 2;
+	
+	serial_req[1].type       = PORT_16550A;
+	serial_req[1].line       = 1;
+	serial_req[1].irq        = EB434_UART1_IRQ;
+	serial_req[1].flags      = STD_COM_FLAGS;
+	serial_req[1].uartclk    = idt_cpu_freq;
+	serial_req[1].iotype     = SERIAL_IO_MEM;
+	serial_req[1].membase    = (char *)KSEG1ADDR(EB434_UART1_BASE);
+	//  serial_req[1].fifosize   = 14;
+	serial_req[1].regshift   = 2;
+	serial_req[1].mapbase   = KSEG1ADDR(EB434_UART1_BASE);
+	
+	early_serial_setup(&serial_req[0]);
+
+	early_serial_setup(&serial_req[1]);
+	
+	return(0);
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/serial_gdb.c idtlinux/arch/mips/idt-boards/rc32434/EB434/serial_gdb.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/serial_gdb.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/serial_gdb.c	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,305 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *      EB434/435 specific polling driver for 16550 UART.
+ *
+ *  Copyright 2005 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ ***************************************************************************
+ */
+
+#include <linux/serial_reg.h>
+
+/* turn this on to watch the debug protocol echoed on the console port */
+#undef DEBUG_REMOTE_DEBUG
+
+/* set remote gdb baud rate at 115200 */
+
+#define GDB_BAUD 115200
+#define CONS_BAUD 9600
+
+extern unsigned int idt_cpu_freq;
+
+#define EXT_FREQ    24000000
+#define INT_FREQ    idt_cpu_freq
+
+#define EXT_PORT    0xb9800000u
+#define EXT_SHIFT   0
+
+#ifdef __MIPSEB__
+#define INT_PORT    0xb8058003u
+#else
+#define INT_PORT    0xb8058000u
+#endif
+#define INT_SHIFT   2
+
+#define INT_FCR     UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14
+#define EXT_FCR     UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT
+
+typedef struct
+{
+  volatile unsigned char *base;
+  unsigned int shift;
+  unsigned int freq;
+  unsigned int fcr;
+} ser_port;
+
+ser_port ports[2] = 
+{
+  { (volatile unsigned char *)INT_PORT, INT_SHIFT, 0, INT_FCR},
+  { (volatile unsigned char *)EXT_PORT, EXT_SHIFT, EXT_FREQ, EXT_FCR}
+};
+
+/* To swap EXT and INT UART as console / gdb change this defines  */
+#define GDB_PORT    1
+#define CONS_PORT   0
+
+void reset_gdb_port(void);
+void cons_putc(char c);
+int port_getc(int port);
+void port_putc(int port, char c);
+
+int cons_getc(void)
+{
+	return port_getc(CONS_PORT);
+}
+
+void cons_putc(char c)
+{
+	port_putc(CONS_PORT, c);
+}
+
+void cons_puts(char *s)
+{
+	while(*s) {
+		if(*s == '\n') cons_putc('\r');
+		cons_putc(*s);
+		s++;
+	}
+}
+
+void cons_do_putn(int n)
+{
+	if(n) {
+		cons_do_putn(n / 10);
+		cons_putc(n % 10 + '0');
+	}
+}
+
+void cons_putn(int n)
+{
+	if(n < 0) {
+		cons_putc('-');
+		n = -n;
+	}
+
+	if (n == 0) {
+		cons_putc('0');
+	} else {
+		cons_do_putn(n);
+	}
+}
+
+#ifdef DEBUG_REMOTE_DEBUG
+static enum {HUH, SENDING, GETTING} state;
+
+static void sent(int c)
+{
+	switch(state) {
+	case HUH:
+	case GETTING:
+		cons_puts("\nSNT ");
+		state = SENDING;
+		/* fall through */
+	case SENDING:
+		cons_putc(c);
+		break;
+	}       
+}
+
+static void got(int c)
+{
+	switch(state) {
+	case HUH:
+	case SENDING:
+		cons_puts("\nGOT ");
+		state = GETTING;
+		/* fall through */
+	case GETTING:
+		cons_putc(c);
+		break;
+	}       
+}
+#endif /* DEBUG_REMOTE_DEBUG */
+
+static int first = 1;
+
+int getDebugChar(void)
+{
+	int c;
+
+	if(first) reset_gdb_port();
+
+	c = port_getc(GDB_PORT);
+
+#ifdef DEBUG_REMOTE_DEBUG
+	got(c);
+#endif
+
+	return c;
+}
+
+int port_getc(int p)
+{
+	volatile unsigned char *port = ports[p].base;
+	int s = ports[p].shift;
+	int c;
+
+	while((*(port + (UART_LSR << s)) & UART_LSR_DR) == 0) {
+		continue;
+	}       	
+
+	c = *(port + (UART_RX << s));
+
+	return c;
+}
+
+int port_getc_ready(int p)
+{
+	volatile unsigned char *port = ports[p].base;
+	int s = ports[p].shift;
+
+	return *(port + (UART_LSR << s)) & UART_LSR_DR;
+}
+
+int isDebugReady(void)
+{
+	return port_getc_ready(1);
+}
+
+void putDebugChar(char c)
+{
+	if(first) reset_gdb_port();
+
+#ifdef DEBUG_REMOTE_DEBUG
+	sent(c);
+#endif
+
+	port_putc(GDB_PORT, c);
+}
+
+#define OK_TO_XMT (UART_LSR_TEMT | UART_LSR_THRE)
+
+void port_putc(int p, char c)
+{
+	volatile unsigned char *port = ports[p].base;
+	int s = ports[p].shift;
+	volatile unsigned char *lsr = port + (UART_LSR << s);
+
+	while((*lsr & OK_TO_XMT) != OK_TO_XMT) {
+		continue;
+	}
+
+	*(port + (UART_TX << s)) = c;
+}
+
+void reset_gdb_port(void)
+{
+	volatile unsigned char *port = ports[GDB_PORT].base;
+	unsigned int s = ports[GDB_PORT].shift;
+	unsigned int DIVISOR;
+
+	if (ports[GDB_PORT].freq) 
+	  DIVISOR = (ports[GDB_PORT].freq / 16 / GDB_BAUD);
+	else
+	  DIVISOR = (idt_cpu_freq / 16 / GDB_BAUD);
+
+	first = 0;
+
+#ifdef DEBUG_REMOTE_DEBUG
+	cons_puts("reset_gdb_port: initializing remote debug serial port (internal UART, ");
+	cons_putn(GDB_BAUD);
+	cons_puts("baud, MHz=");
+	cons_putn(idt_cpu_freq);
+	cons_puts(", divisor=");
+	cons_putn(DIVISOR);
+	cons_puts(")\n");
+#endif
+
+	/* reset the port */
+	*(port + (UART_CSR << s)) = 0;
+
+	/* clear and enable the FIFOs */
+	*(port + (UART_FCR << s)) = ports[GDB_PORT].fcr;
+
+	/* set the baud rate */
+	*(port + (UART_LCR << s)) = UART_LCR_DLAB;		/* enable DLL, DLM registers */
+	*(port + (UART_DLL << s)) = DIVISOR;
+	*(port + (UART_DLM << s)) = DIVISOR >> 8;
+
+	/* set the line control stuff and disable DLL, DLM regs */
+
+	*(port + (UART_LCR << s)) = UART_LCR_STOP | 	/* 2 stop bits */
+		UART_LCR_WLEN8;				/* 8 bit word length */
+	
+	/* leave interrupts off */
+	*(port + (UART_IER << s)) = 0;
+
+	/* the modem controls don't leave the chip on this port, so leave them alone */
+	*(port + (UART_MCR << s)) = 0;
+}
+
+void reset_cons_port(void)
+{
+  volatile unsigned char *port = ports[CONS_PORT].base;
+  unsigned int s = ports[CONS_PORT].shift;
+  unsigned int DIVISOR;
+
+  if (ports[CONS_PORT].freq) 
+    DIVISOR = (ports[CONS_PORT].freq / 16 / CONS_BAUD);
+  else
+    DIVISOR = (idt_cpu_freq / 16 / CONS_BAUD);
+
+  /* reset the port */
+  *(port + (UART_CSR << s)) = 0;
+
+  /* clear and enable the FIFOs */
+  *(port + (UART_FCR << s)) = ports[CONS_PORT].fcr;
+
+  /* set the baud rate */
+  *(port + (UART_LCR << s)) = UART_LCR_DLAB;         /* enable DLL, DLM registers */
+
+  *(port + (UART_DLL << s)) = DIVISOR;
+  *(port + (UART_DLM << s)) = DIVISOR >> 8;
+  /* set the line control stuff and disable DLL, DLM regs */
+
+  *(port + (UART_LCR << s)) = UART_LCR_STOP |        /* 2 stop bits */
+    UART_LCR_WLEN8;                         /* 8 bit word length */
+        
+  /* leave interrupts off */
+  *(port + (UART_IER << s)) = 0;
+
+  /* the modem controls don't leave the chip on this port, so leave them alone */
+  *(port + (UART_MCR << s)) = 0;
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/setup.c idtlinux/arch/mips/idt-boards/rc32434/EB434/setup.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/setup.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/setup.c	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,166 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     setup routines for IDT EB434/435 boards
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/pm.h>
+#include <linux/sched.h>
+#include <linux/irq.h>
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <linux/ioport.h>
+#include <asm/mipsregs.h>
+#include <asm/pgtable.h>
+#include <asm/reboot.h>
+#include <asm/addrspace.h>     /* for KSEG1ADDR() */
+#include <asm/idt-boards/rc32434/rc32434.h>
+
+extern char * __init prom_getcmdline(void);
+
+extern void (*board_time_init)(void);
+extern void (*board_timer_setup)(struct irqaction *irq);
+extern void rc32434_time_init(void);
+extern void rc32434_timer_setup(struct irqaction *irq);
+extern void idt_reset(void);
+void idt_disp_str(char *s);
+
+#define epldMask ((volatile unsigned char *)0xB900000d)
+
+#define DIG_CLEAR ((volatile unsigned char *)0xB9000000)
+#define DIG0 ((volatile unsigned char *)0xB9000007)
+#define DIG1 ((volatile unsigned char *)0xB9000006)
+#define DIG2 ((volatile unsigned char *)0xB9000005)
+#define DIG3 ((volatile unsigned char *)0xB9000004)
+
+void idt_disp_char(int i, char c)
+{
+	switch(i) {
+	case 0: *DIG0 = c; break;
+	case 1: *DIG1 = c; break;
+	case 2: *DIG2 = c; break;
+	case 3: *DIG3 = c; break;
+	default: *DIG0 = '?'; break;
+	}
+}
+
+void idt_disp_str(char *s)
+{
+	if (s == 0) {
+		*DIG_CLEAR;
+	} else {
+		int i;
+		for(i = 0; i < 4; i++) {
+			if(s[i]) idt_disp_char(i, s[i]);
+		}
+	}
+}
+
+
+static void idt_machine_restart(char *command)
+{
+	printk("idt_machine_restart: command=%s\n", command);
+	idt_reset();
+}
+
+static void idt_machine_halt(void)
+{
+	printk("idt_machine_halt:  halted\n");
+	for(;;) continue;
+}
+
+static void idt_machine_power_off(void)
+{
+	printk("idt_machine_power_off:  It is now safe to turn off the power\n");
+	for(;;) continue;
+}
+
+
+static int __init idt_setup(void)
+{
+	char* argptr;
+	
+	idt_disp_str("Unix");
+	
+	argptr = prom_getcmdline();
+#ifdef CONFIG_SERIAL_CONSOLE
+	if ((argptr = strstr(argptr, "console=")) == NULL) {
+		argptr = prom_getcmdline();
+		strcat(argptr, " console=ttyS0,9600");
+	}
+#endif
+	
+	board_time_init = rc32434_time_init;
+	
+	board_timer_setup = rc32434_timer_setup;
+	
+	_machine_restart = idt_machine_restart;
+	_machine_halt = idt_machine_halt;
+	pm_power_off = idt_machine_power_off;
+	set_io_port_base(KSEG1);
+	/* Enable PCI interrupts in EPLD Mask register */
+	*epldMask = 0x0;
+	*(epldMask + 1) = 0x0;
+	
+	write_c0_wired(0);
+	
+	return 0;
+	
+}
+
+//early_initcall(idt_setup);
+
+void __init plat_setup(void){
+  idt_setup();
+}
+
+
+int page_is_ram(unsigned long pagenr)
+{
+	return 1;
+}
+
+const char *get_system_type(void)
+{
+	return "MIPS IDT32434";
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/time.c idtlinux/arch/mips/idt-boards/rc32434/EB434/time.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/time.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32434/EB434/time.c	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,130 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     timer routines for IDT EB434/435 boards
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/mc146818rtc.h>
+#include <linux/irq.h>
+#include <linux/timex.h>
+
+#include <linux/param.h>
+#include <asm/mipsregs.h>
+#include <asm/ptrace.h>
+#include <asm/time.h>
+#include <asm/hardirq.h>
+
+
+#include <asm/mipsregs.h>
+#include <asm/ptrace.h>
+#include <asm/debug.h>
+#include <asm/time.h>
+#include <asm/idt-boards/rc32434/rc32434.h>
+
+
+static unsigned long r4k_offset; /* Amount to incr compare reg each time */
+static unsigned long r4k_cur;    /* What counter should be at next timer irq */
+
+extern unsigned int idt_cpu_freq;
+
+#ifdef CONFIG_RTC_DS1553
+extern int rtc_1553_init(void);
+#endif
+
+/* 
+ * Figure out the r4k offset, the amount to increment the compare
+ * register for each time tick. There is no RTC available.
+ *
+ * The RC32434 counts at half the CPU *core* speed.
+ */
+static unsigned long __init cal_r4koff(void)
+{
+	mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
+	return (mips_hpt_frequency / HZ);
+}
+
+void __init rc32434_time_init(void)
+{
+        unsigned int est_freq, flags;
+	
+	local_irq_save(flags);
+	
+	printk("calculating r4koff... ");
+	r4k_offset = cal_r4koff();
+	printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
+	
+	est_freq = 2*r4k_offset*HZ;	
+	est_freq += 5000;    /* round */
+	est_freq -= est_freq%10000;
+	printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, 
+	       (est_freq%1000000)*100/1000000);
+	local_irq_restore(flags);
+	
+}
+
+void __init rc32434_timer_setup(struct irqaction *irq)
+{
+	/* we are using the cpu counter for timer interrupts */
+	setup_irq(MIPS_CPU_TIMER_IRQ, irq);
+	
+	/* to generate the first timer interrupt */
+	r4k_cur = (read_c0_count() + r4k_offset);
+	write_c0_compare(r4k_cur);
+	
+}
+
+extern void idt_disp_char(int i,char c);
+
+asmlinkage void idt_timer_interrupt(int irq,struct pt_regs *regs)
+{
+#ifdef CONFIG_KGDB
+	void kgdb_check(void);
+#endif
+
+	static unsigned int timerCount = 0;
+	static int toggle = 0;
+	
+	irq_enter();
+	kstat_this_cpu.irqs[irq]++;
+	
+	if( (timerCount++ % HZ) == 0)
+	{ 
+		toggle ^= 1;
+		idt_disp_char(0,toggle ? 'u' :'U');
+	}
+	timer_interrupt(irq, NULL, regs);
+	irq_exit();
+
+#ifdef CONFIG_KGDB
+	kgdb_check();
+#endif
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/.config idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/.config
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/.config	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/.config	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,1026 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.14
+# Tue Jan 31 16:33:33 2006
+#
+CONFIG_MIPS=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_HOTPLUG=y
+# CONFIG_KOBJECT_UEVENT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_INITRAMFS_SOURCE="../initrd/stage/"
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_ROOT_GID=0
+CONFIG_EMBEDDED=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SHMEM=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+# CONFIG_KMOD is not set
+
+#
+# Machine selection
+#
+CONFIG_IDT_BOARDS=y
+CONFIG_IDT_EB438=y
+# CONFIG_IDT_EB434 is not set
+CONFIG_IDT_BOARD_FREQ=150000000
+CONFIG_IDT_ZIMAGE_ADDR=0x88000000
+CONFIG_IDT_BOOT_NVRAM=y
+# CONFIG_MIPS_MTX1 is not set
+# CONFIG_MIPS_BOSPORUS is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1100 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_MIPS_PB1550 is not set
+# CONFIG_MIPS_PB1200 is not set
+# CONFIG_MIPS_DB1000 is not set
+# CONFIG_MIPS_DB1100 is not set
+# CONFIG_MIPS_DB1500 is not set
+# CONFIG_MIPS_DB1550 is not set
+# CONFIG_MIPS_DB1200 is not set
+# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_IVR is not set
+# CONFIG_MIPS_ITE8172 is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SEAD is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_MOMENCO_JAGUAR_ATX is not set
+# CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_MOMENCO_OCELOT_3 is not set
+# CONFIG_MOMENCO_OCELOT_C is not set
+# CONFIG_MOMENCO_OCELOT_G is not set
+# CONFIG_MIPS_XXS1500 is not set
+# CONFIG_PNX8550_V2PCI is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_DDB5074 is not set
+# CONFIG_DDB5476 is not set
+# CONFIG_DDB5477 is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_QEMU is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_PTSWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SNI_RM200_PCI is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_TOSHIBA_RBTX4927 is not set
+# CONFIG_TOSHIBA_RBTX4938 is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_BOOT_ELF32=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+
+#
+# CPU selection
+#
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_R4X00=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPSR1=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+
+#
+# Kernel type
+#
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_MIPS_MT=y
+# CONFIG_MIPS_MT_SMP is not set
+CONFIG_MIPS_VPE_LOADER=y
+# CONFIG_MIPS_VPE_LOADER_TOM is not set
+# CONFIG_MIPS_VPE_APSP_API is not set
+# CONFIG_64BIT_PHYS_ADDR is not set
+# CONFIG_CPU_ADVANCED is not set
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_LEGACY_PROC=y
+CONFIG_MMU=y
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PCI Hotplug Support
+#
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_TRAD_SIGNALS=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_FWMARK=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+
+#
+# IP: Virtual Server Configuration
+#
+CONFIG_IP_VS=m
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_SH=m
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=m
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_IP_NF_CONNTRACK=m
+CONFIG_IP_NF_CT_ACCT=y
+CONFIG_IP_NF_CONNTRACK_MARK=y
+CONFIG_IP_NF_CONNTRACK_EVENTS=y
+CONFIG_IP_NF_CONNTRACK_NETLINK=m
+CONFIG_IP_NF_CT_PROTO_SCTP=m
+CONFIG_IP_NF_FTP=m
+CONFIG_IP_NF_IRC=m
+# CONFIG_IP_NF_NETBIOS_NS is not set
+CONFIG_IP_NF_TFTP=m
+CONFIG_IP_NF_AMANDA=m
+CONFIG_IP_NF_PPTP=m
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_LIMIT=m
+CONFIG_IP_NF_MATCH_IPRANGE=m
+CONFIG_IP_NF_MATCH_MAC=m
+CONFIG_IP_NF_MATCH_PKTTYPE=m
+CONFIG_IP_NF_MATCH_MARK=m
+CONFIG_IP_NF_MATCH_MULTIPORT=m
+CONFIG_IP_NF_MATCH_TOS=m
+CONFIG_IP_NF_MATCH_RECENT=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_DSCP=m
+CONFIG_IP_NF_MATCH_AH_ESP=m
+CONFIG_IP_NF_MATCH_LENGTH=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_MATCH_TCPMSS=m
+CONFIG_IP_NF_MATCH_HELPER=m
+CONFIG_IP_NF_MATCH_STATE=m
+CONFIG_IP_NF_MATCH_CONNTRACK=m
+CONFIG_IP_NF_MATCH_OWNER=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_REALM=m
+CONFIG_IP_NF_MATCH_SCTP=m
+CONFIG_IP_NF_MATCH_DCCP=m
+CONFIG_IP_NF_MATCH_COMMENT=m
+CONFIG_IP_NF_MATCH_CONNMARK=m
+CONFIG_IP_NF_MATCH_CONNBYTES=m
+CONFIG_IP_NF_MATCH_HASHLIMIT=m
+CONFIG_IP_NF_MATCH_STRING=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_IP_NF_TARGET_TCPMSS=m
+CONFIG_IP_NF_TARGET_NFQUEUE=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_SAME=m
+CONFIG_IP_NF_NAT_SNMP_BASIC=m
+CONFIG_IP_NF_NAT_IRC=m
+CONFIG_IP_NF_NAT_FTP=m
+CONFIG_IP_NF_NAT_TFTP=m
+CONFIG_IP_NF_NAT_AMANDA=m
+CONFIG_IP_NF_NAT_PPTP=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_TOS=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_DSCP=m
+CONFIG_IP_NF_TARGET_MARK=m
+CONFIG_IP_NF_TARGET_CLASSIFY=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_TARGET_CONNMARK=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_TARGET_NOTRACK=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# DCCP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+CONFIG_ATALK=m
+CONFIG_DEV_APPLETALK=y
+CONFIG_IPDDP=m
+CONFIG_IPDDP_ENCAP=y
+CONFIG_IPDDP_DECAP=y
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+CONFIG_NET_DIVERT=y
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_CLK_JIFFIES=y
+# CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set
+# CONFIG_NET_SCH_CLK_CPU is not set
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_INGRESS=m
+CONFIG_NET_QOS=y
+CONFIG_NET_ESTIMATOR=y
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+# CONFIG_CLS_U32_PERF is not set
+CONFIG_NET_CLS_IND=y
+# CONFIG_CLS_U32_MARK is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_CLS_POLICE=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_IEEE80211 is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_LBD is not set
+# CONFIG_CDROM_PKTCDVD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# PHY device support
+#
+CONFIG_PHYLIB=y
+CONFIG_PHYCONTROL=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=y
+CONFIG_CICADA_PHY=m
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_IDT_RC32438_ETH=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_DGRS is not set
+# CONFIG_EEPRO100 is not set
+CONFIG_E100=y
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_LAN_SAA9730 is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Hardware Monitoring support
+#
+# CONFIG_HWMON is not set
+# CONFIG_HWMON_VID is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia Capabilities Port drivers
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB is not set
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
+# SN Devices
+#
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_ZISOFS_FS=m
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+CONFIG_RELAYFS_FS=m
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=m
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=m
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=m
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_DES=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_AES=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_DEFLATE=m
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_CRC32C=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Hardware crypto devices
+#
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+CONFIG_CRC32=y
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=m
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/csu_idt.S idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/csu_idt.S
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/csu_idt.S	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/csu_idt.S	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,414 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Board initialization code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/threads.h>
+
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/asm-offsets.h>
+#include <asm/cachectl.h>
+
+#include "idthdr.h"
+#include "iregdef.h"
+#include "idtcpu.h"
+#include "s438ram.h"
+#include "s438.h"
+
+/*--------------------------------------------------------------
+** prom entry point table
+*-------------------------------------------------------------*/
+
+FRAME(start,sp,0,ra)
+	j idtstart        /* begin monitor from start       |00| */
+
+idtstart:
+
+  .set  noreorder
+/* ------ Alternate functions for GPIO pins --------------------------------*/
+/* Neb: only UART0, UART1 and mem_addr */
+	li    t0, GPIO_BASE
+	li    t1, 0x00f00303
+	sw    t1, 0x0(t0)
+      
+	mtc0  zero, C0_CAUSE
+        nop
+	li    v0, 0x0
+	or    v0, (SR_CU0 | SR_BEV)
+	mtc0  v0, C0_SR
+        nop
+	mfc0  v1, C0_CONFIG
+	nop
+	and   v1, ~(0x7)
+	ori   v1, 0x3
+	mtc0  v1, C0_CONFIG
+        nop
+        nop
+            
+/* ------------------- Disable WatchDog Timer ----------------------------- */
+      li    t0, WTC_BASE
+      li    t1, 0x0
+      sw    t1, 0x3C(t0) /* WTC */
+
+/* ------------- Clear PCI Local Base Control registers ------------------- */
+      li    t0, 0xb8080000
+      sw    zero, 0x18(t0)
+      sw    zero, 0x24(t0)
+      sw    zero, 0x30(t0)
+      sw    zero, 0x3c(t0)
+
+/* ------------------- Assert PCI reset ----------------------------------- */
+      lw    t1, (t0)
+      andi  t2, t1, 0x1
+      beqz  t2, 2f
+            nop
+      andi  t2, t1, 0x3fe
+      sw    t2, (t0)
+      li    t2, 0x1000
+1:
+      addi  t2, -1
+      bnez  t2, 1b
+            nop
+2:
+      ori   t2, t1, 0x1
+      sw    t2, (t0)
+      lui   t2, 0x2
+rip:
+      lw    t1, 4(t0)
+      and   t1, t1, t2
+      bnez  t1, rip
+            nop
+
+/* ----------- Set Disable Write Transaction Merging on IPBus ------------- */
+      lui   t0, 0xb804
+      li    t1, 0x8
+      sw    t1, 0x4054(t0)
+
+/* ------------------- Setup Device Controller ---------------------------- */
+      li    t0, DEV_CTL_BASE      /* load 2 base address registers' base    */
+      lui   t2, 0xB800
+      lw    t1, 0x8004(t2)        /* get BCV                                */
+      li    t2, 0x80              /* check width of boot device 8/16 bit    */
+      and   t1, t1, t2
+      bnez  t1, 1f                
+            nop
+    /* 8 bit device - boot from PROM - CS1 is FLASH                         */
+      li    t1, DEV_PROM_CTRL     /* device0 control parameter              */
+      sw    t1, 0x8(t0)           /* set the control register  CS0          */
+      li    t1, DEV_PROM_TC       /* device0 timing config parameter        */
+      sw    t1, 0xC(t0)
+      li    t1, DEV1_BASE         /* set the device base register for CS1   */
+      sw    t1, 0x10(t0)
+      li    t1, DEV_FLASH_MASK    /* set the device mask register for CS1   */
+      sw    t1, 0x14(t0) 
+      li    t1, DEV_FLASH_CTRL    /* set the device control register for CS1*/
+      sw    t1, 0x18(t0)
+      li    t1, DEV_FLASH_TC      /* set the device timing register for CS1 */
+      sw    t1, 0x1C(t0) 
+      b     2f                    
+            nop
+1:
+    /* 16 bit device - boot from FLASH - CS1 is PROM                        */
+      li    t1, DEV_FLASH_CTRL    /* device0 control parameter              */
+      sw    t1, 0x8(t0)           /* set the control register  CS0          */
+      li    t1, DEV_FLASH_TC      /* device0 timing config parameter        */
+      sw    t1, 0xC(t0)
+      li    t1, DEV1_BASE         /* set the device base register for CS1   */
+      sw    t1, 0x10(t0)
+      li    t1, DEV_PROM_MASK     /* set the device mask register for CS1   */
+      sw    t1, 0x14(t0) 
+      li    t1, DEV_PROM_CTRL     /* set the device control register for CS1*/
+      sw    t1, 0x18(t0)
+      li    t1, DEV_PROM_TC       /* set the device timing register for CS1 */
+      sw    t1, 0x1C(t0) 
+2:
+      li    t1, DEV2_BASE         /* set the device base register for CS1   */
+      sw    t1, 0x20(t0)
+      li    t1, DEV2_MASK         /* set the device mask register for CS1   */
+      sw    t1, 0x24(t0) 
+      li    t1, DEV2_CTRL         /* set the device control register for CS1*/
+      sw    t1, 0x28(t0)
+      li    t1, DEV2_TC           /* set the device timing register for CS1 */
+      sw    t1, 0x2C(t0) 
+
+      li    t1, DEV3_BASE         /* set the device base register for CS1   */
+      sw    t1, 0x30(t0)
+      li    t1, DEV3_MASK         /* set the device mask register for CS1   */
+      sw    t1, 0x34(t0) 
+      li    t1, DEV3_CTRL         /* set the device control register for CS1*/
+      sw    t1, 0x38(t0)
+      li    t1, DEV3_TC           /* set the device timing register for CS1 */
+      sw    t1, 0x3C(t0) 
+
+      li    t1, DEV4_BASE         /* set the device base register for CS1   */
+      sw    t1, 0x40(t0)
+      li    t1, DEV4_MASK         /* set the device mask register for CS1   */
+      sw    t1, 0x44(t0) 
+      li    t1, DEV4_CTRL         /* set the device control register for CS1*/
+      sw    t1, 0x48(t0)
+      li    t1, DEV4_TC           /* set the device timing register for CS1 */
+      sw    t1, 0x4C(t0) 
+
+      li    t1, DEV5_BASE         /* set the device base register for CS1   */
+      sw    t1, 0x50(t0)
+      li    t1, DEV5_MASK         /* set the device mask register for CS1   */
+      sw    t1, 0x54(t0) 
+      li    t1, DEV5_CTRL         /* set the device control register for CS1*/
+      sw    t1, 0x58(t0)
+      li    t1, DEV5_TC           /* set the device timing register for CS1 */
+      sw    t1, 0x5C(t0) 
+
+#if MEMCFG != SRAM_ONLY
+
+/* ------------- INITIALIZE DDR SDRAM CONTROLLER ---------------------------*/
+
+      li    t1, 0x0               /* Add 200 microseconds of delay */
+      li    t2, DELAY_200USEC
+1:
+      add   t1, 1
+      bne   t1, t2, 1b
+            nop
+
+/*-------------- Initialize DDR Base and Mask Registers --------------------*/
+
+      li    t0, DDRBASE
+
+  /* Load the DDRC, reset  Refresh Enable */
+      li    t1, DDRC_VAL_AT_INIT
+      sw    t1, 0x10(t0)
+      
+      sw    zero, 0x4(t0)
+      sw    zero, 0xc(t0)
+      sw    zero, 0x18(t0)
+
+  /* Store DDR0BASE */
+      li    t1, DDR0_BASE_VAL
+      sw    t1, 0x0(t0)
+
+  /* Store DDR0MASK */
+      li    t1, DDR0_MASK_VAL
+      sw    t1, 0x4(t0)
+
+  /* Store DDR1BASE */
+      li    t1, DDR1_BASE_VAL
+      sw    t1, 0x8(t0)
+
+  /* Load DDR1MASK to disable DDR CS1 */
+      li    t1, DDR1_MASK_VAL
+      sw    t1, 0x0C(t0)
+
+  /* Store DDR0ABASE */
+      li    t1, DDR0_BASE_VAL
+      sw    t1, 0x14(t0)
+
+  /* Load DDR0AMASK to disable alternate Mapping */
+      li    t1, DDR0_AMASK_VAL
+      sw    t1, 0x18(t0)
+
+      li    t1, DDR_CUST_NOP      /* Write to DDR Custom transaction register */
+      sw    t1, 0x20(t0)
+
+      li    t2, DATA_PATTERN
+      li    t1, 0xA0000000 | DDR0_BASE_VAL
+      sw    t2, 0x0(t1)
+
+  /* Add 200 microseconds of delay */
+      li    t1, 0x0
+      li    t2, DELAY_200USEC
+1:
+      add   t1, 1
+      bne   t1, t2, 1b
+            nop
+            
+  /* Register t0 carries pointer to the DDR_BASE: 0xB8018000 */
+      li    t1, DDR_CUST_PRECHARGE
+      sw    t1, 0x20(t0)    /* Write to DDR Custom transaction register */
+
+  /* Generate A10 high to pre-charge both the banks */
+      li    t2, DATA_PATTERN
+      li    t1, 0xA0000000 | DDR_PRECHARGE_OFFSET | DDR0_BASE_VAL
+      sw    t2, 0x0(t1)
+
+  /* Register t0 carries pointer to the DDR_BASE: 0xB8018000 */
+      li    t1, DDR_LD_EMODE_REG
+      sw    t1, 0x20(t0)    /* Write to DDR Custom transaction register */
+
+  /* Generate EMODE register contents on A15-A2 */
+      li    t2, DATA_PATTERN
+      li    t1, 0xA0000000 | DDR_EMODE_VAL | DDR0_BASE_VAL
+      sw    t2, 0x0(t1)
+
+  /* Register t0 carries pointer to the DDR_BASE: 0xB8018000 */
+      li    t1, DDR_LD_MODE_REG
+      sw    t1, 0x20(t0)    /* Write to DDR Custom transaction register */
+
+  /* Generate Mode register contents on the address bus A15-A2  */
+      li    t2, DATA_PATTERN
+      li    t1, 0xA0000000 | DDR_DLL_RES_MODE_VAL | DDR0_BASE_VAL
+      sw    t2, 0x0(t1)
+
+  /* Delay of  1.6 microseconds ~ 300 delay iteration value */
+      li    t1, 0x0
+      li    t2, 500
+1:
+      add   t1, 1
+      bne   t1, t2, 1b
+            nop
+
+  /* Register t0 carries pointer to the DDR_BASE: 0xB8018000 */
+      li    t1, DDR_CUST_PRECHARGE
+      sw    t1, 0x20(t0)    /* Write to DDR Custom transaction register */
+
+  /* Generate A10 high to pre-charge both the banks */
+      li    t2, DATA_PATTERN
+      li    t1, 0xA0000000 | DDR_PRECHARGE_OFFSET | DDR0_BASE_VAL
+      sw    t2, 0x0(t1)
+
+  /* Implements 9 cycles of Auto refresh allowing 
+     sufficient margin for stability*/
+      li    t4, 9
+      li    t3, 0
+1:
+      li    t1, DDR_CUST_REFRESH
+      sw    t1, 0x20(t0)    /* Write to DDR Custom transaction register */
+
+  /* Read it back to flush CPU write buffers */
+      lw    t1, 0x20(t0)
+
+  /* Access DDR */
+      li    t2, DATA_PATTERN
+      li    t1, 0xA0000000 | DDR0_BASE_VAL
+      sw    t2, 0x0(t1)
+
+      add   t3, 1
+      bne   t3, t4, 1b
+            nop
+
+  /* Register t0 carries pointer to the DDR_BASE: 0xB8018000 */
+      li    t1, DDR_LD_MODE_REG
+      sw    t1, 0x20(t0)    /* Write to DDR Custom transaction register */
+
+  /* Generate Mode Register contents on the address bus A12-A0 */
+      li    t2, DATA_PATTERN
+      li    t1, 0xA0000000 | DDR_DLL_MODE_VAL | DDR0_BASE_VAL
+      sw    t2, 0x0(t1)
+
+  /* Initialize the refresh timer with fast refresh count */
+      li    t0, RCOUNT
+      li    t1, DDR_REF_CMP_FAST
+      
+  /* Set the RCOMPARE register */
+      sw    t1, 0x4(t0)
+
+  /* Enable the Refresh timer */
+      li    t1, 0x1           /* CE set to enabled the  Refresh counter */
+      sw    t1, 0x8(t0)
+
+  /* Enable RE-refresh enable in the DDRC register */
+      li    t0, DDRBASE
+      li    t1, DDRC_VAL_NORMAL
+      sw    t1, 0x10(t0)
+
+  /* Add 200 microseconds of delay */
+      li    t1, 0x0
+      li    t2, DELAY_200USEC
+1:
+      add   t1, 1
+      bne   t1, t2, 1b
+            nop
+
+      li    t0, RCOUNT
+
+  /* Find Refresh Timer Compare value value based on revision - Check for IP7 */
+      li    t2, 0x1
+      mtc0  t2, C0_COMPARE
+      mtc0  zero, C0_COUNT
+            nop
+            nop
+      mfc0  t1, C0_CAUSE
+            nop
+      li    t3, DDR_REF_CMP_VAL_ZB
+      andi  t1, 0x8000
+      bnez  t1, acacia_zb
+            nop
+      li    t3, DDR_REF_CMP_VAL
+acacia_zb:
+
+  /* Disable the refresh counter before changing the compare value */
+      li    t1, 0x0
+      sw    t1, 0x8(t0)
+
+  /* Set the RCOMPARE register */
+      sw    t3, 0x4(t0)
+
+  /* Enable the Refresh timer */
+      li    t1, 0x1           /* CE set to enabled the  Refresh counter */
+      sw    t1, 0x8(t0)
+
+  /* Add 200 microseconds of delay */
+      li    t1, 0x0
+      li    t2, DELAY_200USEC
+1:
+      add   t1, 1
+      bne   t1, t2, 1b
+            nop
+
+#endif
+	li    t0, 0xa0000000
+	li    t1, 0xa0100000
+1:
+	sw    zero, 0x00(t0)
+	sw    zero, 0x04(t0)
+	sw    zero, 0x08(t0)
+	sw    zero, 0x0c(t0)
+	addiu t0, 16
+	nop
+	blt   t0, t1, 1b
+	nop
+	nop
+	nop
+3:
+	mfc0  t0, C0_SR
+	nop
+	nop
+	and   t0, ~SR_BEV
+	mtc0  t0, C0_SR
+	nop
+	nop
+4:
+
+/* Jump to zImage startup */
+	
+	la     k0, zstartup
+	j      k0
+	nop
+	nop
+
+ENDFRAME(start)
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/head.S idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/head.S
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/head.S	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/head.S	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,126 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Board initialisation code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/threads.h>
+
+#include <asm/asm.h>
+#include <asm/cacheops.h>
+#include <asm/mipsregs.h>
+#include <asm/asm-offsets.h>
+#include <asm/cachectl.h>
+#include <asm/regdef.h>
+
+#define IndexInvalidate_I       0x00
+
+	.set noreorder
+	.cprestore
+	LEAF(zstartup)
+zstartup:
+
+        la      sp, .stack
+	move	s0, a0
+	move	s1, a1
+	move	s2, a2
+	move	s3, a3
+
+	/* Clear BSS */
+	/* Note: when zImage is in ROM, _edata and _bss point to
+	 * ROM space even when using -Tbss on the linker command line;
+	 * maybe ld.script needs to be corrected.
+	 */
+	la	a0, .stack
+	la	a2, _end
+1:	sw	zero, 0(a0)
+	bne	a2, a0, 1b
+	addu	a0, 4
+
+	/* flush the I-Cache */
+	li	k0, 0x80000000  # start address
+	li	k1, 0x80004000  # end address (16KB I-Cache)
+	subu	k1, 128
+
+2:
+	.set mips3
+	cache   IndexInvalidate_I, 0(k0)
+	cache   IndexInvalidate_I, 16(k0)
+	cache   IndexInvalidate_I, 32(k0)
+	cache   IndexInvalidate_I, 48(k0)
+	cache   IndexInvalidate_I, 64(k0)
+	cache   IndexInvalidate_I, 80(k0)
+	cache   IndexInvalidate_I, 96(k0)
+	cache   IndexInvalidate_I, 112(k0)
+	.set mips0
+
+	bne	k0, k1, 2b
+	addu	k0, k0, 128
+	/* done */
+
+	/* flush the D-Cache */
+	li	k0, 0x80000000  # start address
+	li	k1, 0x80004000  # end address (16KB I-Cache)
+	subu	k1, 128
+
+2:
+	.set mips3
+	cache   Index_Writeback_Inv_D, 0(k0)
+	cache   Index_Writeback_Inv_D, 16(k0)
+	cache   Index_Writeback_Inv_D, 32(k0)
+	cache   Index_Writeback_Inv_D, 48(k0)
+	cache   Index_Writeback_Inv_D, 64(k0)
+	cache   Index_Writeback_Inv_D, 80(k0)
+	cache   Index_Writeback_Inv_D, 96(k0)
+	cache   Index_Writeback_Inv_D, 112(k0)
+	.set mips0
+
+	bne	k0, k1, 2b
+	addu	k0, k0, 128
+	/* done */
+
+	la	ra, 3f
+	la	k0, decompress_kernel
+	jr	k0
+	nop
+3:
+
+	move	a0, s0
+	move	a1, s1
+	move	a2, s2
+	move	a3, s3
+	li	k0, KERNEL_ENTRY
+	jr	k0
+	nop
+4:
+	b 4b
+	END(zstartup)
+
+	.bss
+	.fill 0x2000
+	EXPORT(.stack)
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/idtcpu.h idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/idtcpu.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/idtcpu.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/idtcpu.h	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,335 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   IDT CPU register definitions. Though the registers are already defined
+ *   under asm directory, they are once again declared here for the ease of
+ *   syncing up with IDT bootloader code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#if !defined(__IDTCPU_H__)
+#define __IDTCPU_H__
+/*
+** memory configuration and mapping
+*/
+#define K0BASE		0x80000000
+#define K0SIZE		0x20000000
+#define K1BASE		0xa0000000
+#define K1SIZE		0x20000000
+#define K2BASE		0xc0000000
+#if defined(CPU_R32364)
+#define K2SIZE		0x40000000
+#define ICEBASE		0xff000000
+#define ICESIZE		0x01000000
+#elif defined(CPU_R32438)
+#define K2SIZE		0x20000000
+#define K3BASE		0xe0000000
+#define K3SIZE    0x20000000
+#define ICEBASE		0xff200000
+#define ICESIZE		0x00200000
+#endif
+
+#define KUBASE		0
+#define KUSIZE		0x80000000
+
+/*
+** Exception Vectors
+*/
+
+#define	T_VEC	(K0BASE + 0x000)			/* tlbmiss vector */
+#define X_VEC	(K0BASE + 0x080)			/* xtlbmiss vector */
+#define C_VEC	(K1BASE + 0x100)			/* cache error vector */
+#define E_VEC	(K0BASE + 0x180)			/* exception vector */
+#define I_VEC	(K0BASE + 0X200)			/* interrupt vector */
+#define	R_VEC	(K1BASE + 0x1fc00000)	/* reset vector */
+
+/*
+** Address conversion macros
+*/
+#ifdef CLANGUAGE
+#define	CAST(as) (as)
+#else
+#define	CAST(as)
+#endif
+
+#define	K0_TO_K1(x)		(CAST(unsigned)(x) | 0xA0000000)	/* kseg0 to kseg1 */
+#define	K1_TO_K0(x)		(CAST(unsigned)(x) & 0x9FFFFFFF)	/* kseg1 to kseg0 */
+#define	K0_TO_PHYS(x)	(CAST(unsigned)(x) & 0x1FFFFFFF)	/* kseg0 to physical */
+#define	K1_TO_PHYS(x)	(CAST(unsigned)(x) & 0x1FFFFFFF)	/* kseg1 to physical */
+#define	PHYS_TO_K0(x)	(CAST(unsigned)(x) | 0x80000000)	/* physical to kseg0 */
+#define	PHYS_TO_K1(x)	(CAST(unsigned)(x) | 0xA0000000)	/* physical to kseg1 */
+
+#if defined(CPU_R32364)             /* Includes RC32332, RC32334 */
+#define	CFG_ICE					0x80000000	/* ICE detect */
+#define	CFG_ECMASK			0x70000000	/* System Clock Ratio */
+#define	CFG_ECBY2				0x00000000 	/* divide by 2 */
+#define	CFG_ECBY3				0x10000000 	/* divide by 3 */
+#define	CFG_ECBY4				0x20000000 	/* divide by 4 */
+#define	CFG_BE					0x00008000	/* Big Endian */
+#define	CFG_ICMASK			0x00000e00	/* Instruction cache size */
+#define	CFG_ICSHIFT			9
+#define	CFG_DCMASK			0x000001c0	/* Data cache size */
+#define	CFG_DCSHIFT			6
+#define	CFG_IB					0x00000020	/* Instruction cache line size */
+#define	CFG_DB					0x00000010	/* Data cache line size */
+#define	CFG_K0MASK			0x00000007	/* KSEG0 coherency algorithm */
+#elif defined(CPU_R32438)
+#define	CFG_MM					0x00060000  /* write buffer Merge Mode */
+#define CFG_BM					0x00010000  /* Burst Mode */
+#define	CFG_BE					0x00008000	/* Big Endian */
+#define	CFG_K0MASK			0x00000007	/* KSEG0 coherency algorithm */
+#endif
+
+/*
+ * Primary cache mode
+ */
+#if defined(CPU_R32364)
+#define CFG_C_NCHRNT_WT_NWA			0
+#define CFG_C_NCHRNT_WT					1
+#define CFG_C_UNCACHED					2
+#define CFG_C_NCHRNT_WB					3
+
+/* Cache Operations */
+#define Index_Invalidate_I      0x0         /* 0       0 */
+#define Index_Writeback_Inv_D   0x1         /* 0       1 */
+#define Index_Invalidate_SI     0x2         /* 0       2 */
+#define Index_Writeback_Inv_SD  0x3         /* 0       3 */
+#define Index_Load_Tag_I        0x4         /* 1       0 */
+#define Index_Load_Tag_D        0x5         /* 1       1 */
+#define Index_Load_Tag_SI       0x6         /* 1       2 */
+#define Index_Load_Tag_SD       0x7         /* 1       3 */
+#define Index_Store_Tag_I       0x8         /* 2       0 */
+#define Index_Store_Tag_D       0x9         /* 2       1 */
+#define Index_Store_Tag_SI      0xA         /* 2       2 */
+#define Index_Store_Tag_SD      0xB         /* 2       3 */
+#define Create_Dirty_Exc_D      0xD         /* 3       1 */
+#define Create_Dirty_Exc_SD     0xF         /* 3       3 */
+#define Hit_Invalidate_I        0x10        /* 4       0 */
+#define Hit_Invalidate_D        0x11        /* 4       1 */
+#define Hit_Invalidate_SI       0x12        /* 4       2 */
+#define Hit_Invalidate_SD       0x13        /* 4       3 */
+#define Hit_Writeback_Inv_D     0x15        /* 5       1 */
+#define Hit_Writeback_Inv_SD    0x17        /* 5       3 */
+#define Fill_I                  0x14        /* 5       0 */
+#define Hit_Writeback_D         0x19        /* 6       1 */
+#define Hit_Writeback_SD        0x1B        /* 6       3 */
+#define Hit_Writeback_I         0x18        /* 6       0 */
+#define Hit_Set_Virtual_SI      0x1E        /* 7       2 */
+#define Hit_Set_Virtual_SD      0x1F        /* 7       3 */
+#define CFG_EW32        				0x00040000      /* 32 bit */
+#elif defined(CPU_R32438)
+#define CFG_C_UNCACHED					2
+#define CFG_C_NCHRNT_WB					3
+
+/* Cache Operations */
+#define Index_Invalidate_I      0x0         /* 0       0 */
+#define Index_Invalidate_D      0x1         /* 0       0 */
+#define Index_Load_Tag_I        0x4         /* 1       0 */
+#define Index_Load_Tag_D        0x5         /* 1       1 */
+#define Index_Store_Tag_I       0x8         /* 2       0 */
+#define Index_Store_Tag_D       0x9         /* 2       1 */
+#define Hit_Invalidate_I        0x10        /* 4       0 */
+#define Hit_Invalidate_D        0x11        /* 4       1 */
+#define Fill_I                  0x14        /* 5       0 */
+#define Fetch_Lock_I						0x1C        /* 7       0 */
+#define Fetch_Lock_D						0x1D        /* 7       1 */
+#define CFG_EW32        				0x00040000      /* 32 bit */
+#endif
+
+/*
+** TLB resource defines
+*/
+
+#define	N_TLB_ENTRIES				16
+#define	TLBHI_VPN2MASK			0xffffe000
+#define	TLBHI_PIDMASK				0x000000ff
+#define	TLBHI_NPID					256
+
+#define	TLBLO_PFNMASK				0x03ffffc0
+#define	TLBLO_PFNSHIFT			6
+#define	TLBLO_D							0x00000004	/* writeable */
+#define	TLBLO_V							0x00000002	/* valid bit */
+#define	TLBLO_G							0x00000001	/* global access bit */
+#define	TLBLO_CMASK					0x00000038	/* cache algorithm mask */
+#define	TLBLO_CSHIFT				3
+
+#define	TLBLO_UNCACHED			(CFG_C_UNCACHED << TLBLO_CSHIFT)
+#define	TLBLO_NCHRNT_WT_NWA	(CFG_C_NCHRNT_WT_NWA << TLBLO_CSHIFT)
+#if defined(CPU_R32364)
+#define	TLBLO_NCHRNT_WT			(CFG_C_NCHRNT_WT << TLBLO_CSHIFT)
+#define	TLBLO_NCHRNT_WB			(CFG_C_NCHRNT_WB << TLBLO_CSHIFT)
+#endif
+
+#define	TLBINX_PROBE				0x80000000
+#define	TLBINX_INXMASK			0x0000003f
+
+#define	TLBRAND_RANDMASK		0x0000003f
+
+#define	TLBCTXT_BASEMASK		0xff800000
+#define	TLBCTXT_BASESHIFT		23
+
+#define	TLBCTXT_VPN2MASK		0x007ffff0
+#define	TLBCTXT_VPN2SHIFT		4
+
+#define	TLBPGMASK_MASK			0x01ffe000
+
+#define	SR_CUMASK				0xf0000000	/* coproc usable bits */
+#define	SR_CU3					0x80000000	/* Coprocessor 3 usable */
+#define	SR_CU2					0x40000000	/* Coprocessor 2 usable */
+#define	SR_CU1					0x20000000	/* Coprocessor 1 usable */
+#define	SR_CU0					0x10000000	/* Coprocessor 0 usable */
+
+/* #define	SR_PE						0x00100000*/  /* cache parity error */
+
+#if defined(CPU_R32364)
+#define	SR_RE						0X02000000	/* Reverse Endianness */
+#define	SR_DL						0x01000000	/* Data Cache Locking */
+#define	SR_IL						0x00800000	/* Instruction Cache Locking */
+
+#define	SR_BEV					0x00400000	/* Use boot exception vectors */
+#define	SR_SR						0x00100000	/* Soft reset */
+#define	SR_CH						0x00040000	/* Cache hit */
+#define	SR_CE						0x00020000	/* Use cache ECC  */
+#define	SR_DE						0x00010000	/* Disable cache exceptions */
+
+#elif defined(CPU_R32438)
+#define	SR_RP						0X08000000	/* Reduced Power mode */
+
+#define	SR_RE						0X02000000	/* Reverse Endianness */
+
+#define	SR_BEV					0x00400000	/* Use boot exception vectors */
+#define	SR_TS						0X00200000	/* TLB Shutdown */
+#define	SR_SR						0x00100000	/* Soft reset */
+#define	SR_NMI					0X00080000	/* NMI */
+#endif
+/*
+**	status register interrupt masks and bits
+*/
+
+#define	SR_IMASK				0x0000ff00	/* Interrupt mask */
+#define	SR_IMASK8				0x00000000	/* mask level 8 */
+#define	SR_IMASK7				0x00008000	/* mask level 7 */
+#define	SR_IMASK6				0x0000c000	/* mask level 6 */
+#define	SR_IMASK5				0x0000e000	/* mask level 5 */
+#define	SR_IMASK4				0x0000f000	/* mask level 4 */
+#define	SR_IMASK3				0x0000f800	/* mask level 3 */
+#define	SR_IMASK2				0x0000fc00	/* mask level 2 */
+#define	SR_IMASK1				0x0000fe00	/* mask level 1 */
+#define	SR_IMASK0				0x0000ff00	/* mask level 0 */
+
+#define	SR_IMASKSHIFT		8
+
+#define	SR_IBIT8				0x00008000	/* bit level 8 */
+#define	SR_IBIT7				0x00004000	/* bit level 7 */
+#define	SR_IBIT6				0x00002000	/* bit level 6 */
+#define	SR_IBIT5				0x00001000	/* bit level 5 */
+#define	SR_IBIT4				0x00000800	/* bit level 4 */
+#define	SR_IBIT3				0x00000400	/* bit level 3 */
+#define	SR_IBIT2				0x00000200	/* bit level 2 */
+#define	SR_IBIT1				0x00000100	/* bit level 1 */
+
+#define	SR_KSMASK				0x00000016	/* Kernel mode mask */
+#define	SR_KSUSER				0x00000000	/* User Mode */
+#define	SR_KSKERNEL			0x00000016	/* Kernel Mode */
+
+#define	SR_ERL					0x00000004	/* Error level */
+#define	SR_EXL					0x00000002	/* Exception level */
+#define	SR_IE						0x00000001	/* Interrupts enabled */
+#define	NOT_SR_IEC      0xfffffffe  /* assembler problem with li ~SR_IEC */
+
+/*
+ * Cause Register
+ */
+#define	CAUSE_BD				0x80000000	/* Branch delay slot */
+#define	CAUSE_CEMASK		0x30000000	/* coprocessor error */
+#define	CAUSE_CESHIFT		28
+#if defined(CPU_R32364)
+#define	CAUSE_IPE				0x04000000	/* Imprecise exception */
+#define	CAUSE_DW				0x02000000	/* Data watch */
+#define	CAUSE_IW				0x01000000	/* Instruction watch */
+#elif defined(CPU_R32438)
+#define CAUSE_IV			 	0x00800000	/* Interrupt Vector location */
+#define CAUSE_WP			 	0x00400000	/* Watch Exception deferred */
+#endif
+
+#define	CAUSE_IPMASK		0x0000FF00	/* Pending interrupt mask */
+#define	CAUSE_IPSHIFT		8
+
+/* Notice: Watch Exception if Exc. Code is 23 is not included in the mask
+ *	   for R32364.
+ */
+#define	CAUSE_EXCMASK		0x0000003C	/* Cause code bits */
+#define	CAUSE_EXCSHIFT	2
+
+#ifndef XDS
+/*
+**  Coprocessor 0 registers
+*/
+#define	C0_INX					$0		/* tlb index */
+#define	C0_RANDOM				$1
+#define	C0_TLBLO0				$2		/* tlb entry low 0 */
+#define	C0_TLBLO1				$3		/* tlb entry low 1 */
+#define	C0_CTXT					$4		/* tlb context */
+#define	C0_PAGEMASK			$5		/* tlb page mask */
+#define	C0_WIRED				$6		/* number of wired tlb entries */
+
+#define	C0_BADVADDR			$8		/* bad virtual address */
+#define	C0_COUNT				$9		/* timer count */
+#define	C0_TLBHI				$10		/* tlb entry hi */
+#define	C0_COMPARE			$11		/* timer comparator  */
+#define	C0_SR						$12		/* status register */
+#define	C0_CAUSE				$13		/* exception cause */
+#define	C0_EPC					$14		/* exception pc */
+#define	C0_PRID					$15		/* revision identifier */
+#define	C0_CONFIG				$16		/* configuration register */
+
+#if defined(CPU_R32364)
+#define	C0_IWATCH				$18		/* Instr brk pt Virtual add. */
+#define	C0_DWATCH				$19		/* Data brk pt Virtual add. */
+
+#define	C0_IEPC					$22		/* Imprecise Exception pc */
+#define	C0_DEPC					$23		/* Debug Exception pc */
+#define	C0_DEBUG				$24		/* Debug control/status reg */
+
+#define	C0_ECC					$26		/* primary cache Parity control */
+#define	C0_CACHEERR			$27		/* cache error status */
+#define	C0_TAGLO				$28		/* cache tag lo */
+#define	C0_ERRPC				$30		/* cache error pc */
+#elif defined(CPU_R32438)
+#define	C0_WATCHLO			$18		/* Watchpoint address (low) */
+#define	C0_WATCHHI			$19		/* Watchpoint address (high) */
+
+#define	C0_DEBUG				$23		/* Debug control/status reg */
+#define	C0_DEPC					$24		/* Debug Exception pc */
+
+#define	C0_ERRCTL				$26		/* Cache Error Control */
+#define	C0_TAGLO				$28		/* Cache Tag Lo */
+#define	C0_ERRPC				$30		/* Cache Error PC */
+#define C0_DESAVE				$31		/* Debug scratchpad reg. */
+#endif 
+
+#endif
+#endif /* defined(__IDTCPU_H__) */
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/idthdr.h idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/idthdr.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/idthdr.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/idthdr.h	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,53 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Some macros. Though they are already defined else where in the linux
+ *   tree, they are once again declared here for the ease of syncing up with
+ *    IDT bootloader code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#ifndef XDS
+
+#define	FRAME(name,frm_reg,offset,ret_reg)	\
+	.globl	name;				\
+	.ent	name;				\
+name:;						\
+	.frame	frm_reg,offset,ret_reg
+
+#define ENDFRAME(name) 	.end name
+
+#else
+
+#define FRAME(name,frm_reg,offset,ret_reg)      \
+name:
+
+#define ENDFRAME(name)
+
+#endif
+
+
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/image.lds.in idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/image.lds.in
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/image.lds.in	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/image.lds.in	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,31 @@
+OUTPUT_ARCH(mips)
+ENTRY(zstartup)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = IMSTART;
+  .init          : { *(.init)		} =0
+  .text      :
+  {
+    _ftext = . ;
+    *(.text)
+    *(.rodata)
+    *(.rodata1)
+   . = ALIGN(4096);
+    input_data = .;
+    arch/mips/idt-boards/rc32438/EB438/boot/piggy.o
+    input_data_end = .;
+   . = ALIGN(4096);
+    *(.gnu.warning)
+  } =0
+
+  .reginfo : { *(.reginfo) }
+
+   . = BSS_START;
+  __bss_start = .;
+  .bss       :
+  {
+   *(.bss)
+  _end = . ;
+  }
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/iregdef.h idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/iregdef.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/iregdef.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/iregdef.h	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,274 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   IDT CPU register definitions. Though the registers are already defined
+ *   under asm directory, they are once again declared here for the ease of
+ *   syncing up with IDT bootloader code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#ifdef CLANGUAGE
+struct ireg_desc {
+	char 	*ptr_field_name;	/* field name   */
+	short	num_digits;				/* number ofdigits to display */
+	short	num_spaces;				/* number of spaces to follow */
+	reg_t	fld_mask;					/* mask to extract value of field */
+	int	fld_shift;					/* shift amount to position field */
+  short    cpu;
+	char *CONST *ptr_enum_list;	/* ptr to an enumeration list */
+	  };
+
+/*
+** reg_name - structure that gives the reg. name, alt. reg name
+**		the reg index for fetching the value, the number
+**		of spaces req. so a tabular display will align
+**		a pointer to a structure defining the fields if
+**		required and a flag for the output type.
+*/
+struct reg_name {
+	char	*register_name;
+	char	*alt_reg_name;
+	short	reg_index;
+	short	space_pad;
+	CONST struct ireg_desc *ptr_reg_desc_flds;
+	unsigned char format_type;
+	unsigned char print_type;
+	short   reg_group;
+  short    cpu;
+	  };
+
+/* print format specifiers */
+#define PRT_HEX		0
+#define PRT_SGL 	1
+#define PRT_DBL 	2
+
+/* register group classifiers */
+#define GRP_CPU		0x0001
+#define GRP_FPR		0x0002
+#define GRP_FPS		0x0004
+#define GRP_FPD		0x0008
+#define GRP_CP0		0x0010
+#define GRP_CP0R	0x0020
+#endif
+
+/*
+** register names
+*/
+#define r0		$0
+#define r1		$1
+#define r2		$2
+#define r3		$3
+#define r4		$4
+#define r5		$5
+#define r6		$6
+#define r7		$7
+#define r8		$8
+#define r9		$9
+#define r10		$10
+#define r11		$11
+#define r12		$12
+#define r13		$13
+#define r14		$14
+#define r15		$15
+#define r16		$16
+#define r17		$17
+#define r18		$18
+#define r19		$19
+#define r20		$20
+#define r21		$21
+#define r22		$22
+#define r23		$23
+#define r24		$24
+#define r25		$25
+#define r26		$26
+#define r27		$27
+#define r28		$28
+#define r29		$29
+#define r30		$30
+#define r31		$31
+
+#define zero	$0		/* wired zero */
+#define AT		$at		/* assembler temp */
+#define v0		$2		/* return value */
+#define v1		$3
+#define a0		$4		/* argument registers a0-a3 */
+#define a1		$5
+#define a2		$6
+#define a3		$7
+#define t0		$8		/* caller saved  t0-t9 */
+#define t1		$9
+#define t2		$10
+#define t3		$11
+#define t4		$12
+#define t5		$13
+#define t6		$14
+#define t7		$15
+#define s0		$16		/* callee saved s0-s8 */
+#define s1		$17
+#define s2		$18
+#define s3		$19
+#define s4		$20
+#define s5		$21
+#define s6		$22
+#define s7		$23
+#define t8		$24
+#define t9		$25
+#define k0		$26		/* kernel usage */
+#define k1		$27		/* kernel usage */
+#define gp		$28		/* sdata pointer */
+#define sp		$29		/* stack pointer */
+#define s8		$30		/* yet another saved reg for the callee */
+#define fp		$30		/* frame pointer - this is being phased out by MIPS */
+#define ra		$31		/* return address */
+
+/*
+** relative position of registers in save reg area
+*/
+#define	R_R0		0
+#define	R_R1		1
+#define	R_R2		2
+#define	R_R3		3
+#define	R_R4		4
+#define	R_R5		5
+#define	R_R6		6
+#define	R_R7		7
+#define	R_R8		8
+#define	R_R9		9
+#define	R_R10		10
+#define	R_R11		11
+#define	R_R12		12
+#define	R_R13		13
+#define	R_R14		14
+#define	R_R15		15
+#define	R_R16		16
+#define	R_R17		17
+#define	R_R18		18
+#define	R_R19		19
+#define	R_R20		20
+#define	R_R21		21
+#define	R_R22		22
+#define	R_R23		23
+#define	R_R24		24
+#define	R_R25		25
+#define	R_R26		26
+#define	R_R27		27
+#define	R_R28		28
+#define	R_R29		29
+#define	R_R30		30
+#define	R_R31		31
+#define NCLIENTREGS	32
+#define	R_EPC				32
+#define	R_MDHI			33
+#define	R_MDLO		  34
+#define	R_SR				35
+#define	R_CAUSE			36
+#define	R_TLBHI			37
+#define	R_TLBLO0		38
+#define	R_BADVADDR	39
+#define	R_INX				40
+#define	R_RAND			41
+#define	R_CTXT			42
+#define	R_EXCTYPE		43
+#define R_MODE			44
+#define R_PRID			45
+#define R_TLBLO1		46
+#define R_PAGEMASK	47
+#define R_WIRED			48
+#define R_COUNT			49
+#define R_COMPARE		50
+#define R_CONFIG		51
+#if defined(CPU_R32438)
+#define R_WATCHLO   52
+#define R_WATCHHI   53
+#elif defined(CPU_R32364)
+#define R_IWATCH    52
+#define R_DWATCH    53
+#define R_ECC				54
+#define R_CACHEERR	55
+#endif
+#define R_TAGLO			56
+#define R_TAGHI			57
+#define R_ERRPC			58
+
+#define NREGS			  59
+
+#if __mips >= 3
+
+#define R_SZ		8
+#ifndef CLANGUAGE
+#define sreg		sd
+#define lreg		ld
+#define rmfc0		mfc0
+#define rmtc0		mtc0
+#endif
+
+#else
+
+#define R_SZ		4
+#ifndef CLANGUAGE
+#define sreg		sw
+#define lreg		lw
+#define rmfc0		mfc0
+#define rmtc0		mtc0
+#endif
+
+#endif
+
+/*
+** For those who like to think in terms of the compiler names for the regs
+*/
+#define	R_ZERO	R_R0
+#define	R_AT		R_R1
+#define	R_V0		R_R2
+#define	R_V1		R_R3
+#define	R_A0		R_R4
+#define	R_A1		R_R5
+#define	R_A2		R_R6
+#define	R_A3		R_R7
+#define	R_T0		R_R8
+#define	R_T1		R_R9
+#define	R_T2		R_R10
+#define	R_T3		R_R11
+#define	R_T4		R_R12
+#define	R_T5		R_R13
+#define	R_T6		R_R14
+#define	R_T7		R_R15
+#define	R_S0		R_R16
+#define	R_S1		R_R17
+#define	R_S2		R_R18
+#define	R_S3		R_R19
+#define	R_S4		R_R20
+#define	R_S5		R_R21
+#define	R_S6		R_R22
+#define	R_S7		R_R23
+#define	R_T8		R_R24
+#define	R_T9		R_R25
+#define	R_K0		R_R26
+#define	R_K1		R_R27
+#define	R_GP		R_R28
+#define	R_SP		R_R29
+#define	R_FP		R_R30
+#define	R_RA		R_R31
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/Makefile idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/Makefile
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/Makefile	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/Makefile	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,136 @@
+###############################################################################
+#
+#  BRIEF MODULE DESCRIPTION
+#     Makefile create a compressed zImage or Rommable rImage
+#
+#  Copyright 2006 IDT Inc. (rischelp@idt.com)
+#
+#  This program is free software; you can redistribute  it and/or modify it
+#  under  the terms of  the GNU General  Public License as published by the
+#  Free Software Foundation;  either version 2 of the  License, or (at your
+#  option) any later version.
+#
+#  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+#  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+#   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+#   NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+#   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+#   NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+#   USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+#   ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+#   THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#   You should have received a copy of the  GNU General Public License along
+#   with this program; if not, write  to the Free Software Foundation, Inc.,
+#   675 Mass Ave, Cambridge, MA 02139, USA.
+# 
+###############################################################################
+
+###############################################################################
+# The following is taken from IDT/Sim Makefile
+#############################################################################
+TARGET=438
+TARGETDIR=S438
+MHZ=100000000
+
+#
+# following refers to memory type in use in eval board and if more than one
+# then the order is implied.  These are values for the switch MEMCFG.
+#
+SRAM_ONLY=1
+SDRAM_ONLY=2
+SRAM_N_SDRAM=3
+SDRAM_N_SRAM=4
+
+# following refers to size of the DRAM space.
+# These are values for the switch DRAMSZ.
+
+MB32=1
+MB64=2
+MB128=3
+MB32SO=4
+
+MACH= -DEB438 -DS438 -DCPU_R32438 -DMIPSEL -DINET -DMEMCFG=$(SDRAM_ONLY) -DDRAMSZ=$(MB64) -DIDTSIM -DMHZ=$(MHZ) -DNVRAM_RTC -DUSE_SPI
+COMMSWITCHES = $(MACH)
+#***************** END IDT/Sim Makefile ##################################### 
+ZDEBUG=1
+export ZDEBUG
+
+# working space for gunzip:
+FREE_RAM      := 0x80C00000
+END_RAM       := 0x80E00000
+
+KERNELCONFIG  := $(TOPDIR)/.config
+include $(KERNELCONFIG)
+
+SIZE = $(CROSS_COMPILE)size
+
+O_FORMAT = $(shell $(OBJDUMP) -i | head -2 | grep elf32)
+
+SYSTEM	      := $(TOPDIR)/vmlinux
+ZBSS          := 0x800A0000
+
+ZIMSTART      := $(CONFIG_IDT_ZIMAGE_ADDR)
+RIMSTART      := 0x9FC00000
+
+LOADADDR      := 0x$(shell $(NM) $(SYSTEM) | grep "A _text" |cut -f1 -d' ')
+KERNEL_ENTRY  := $(shell $(OBJDUMP) -f $(SYSTEM) | sed -n -e 's/^start address //p')
+
+####################################################################################
+ZIMFLAGS        = s/IMSTART/$(ZIMSTART)/;s/BSS_START/$(ZBSS)/
+RIMFLAGS        = s/IMSTART/$(RIMSTART)/;s/BSS_START/$(ZBSS)/
+CFLAGS	:= -fno-pic -nostdinc -G 0 -mno-abicalls -fno-pic -pipe -I$(TOPDIR)/include
+AFLAGS	:= -D__ASSEMBLY__ $(CFLAGS)
+
+####################################################################################
+OBJECTS= $(obj)/piggy.o $(obj)/head.o $(obj)/misc.o
+ifneq ($(ZDEBUG),0)
+OBJECTS += $(obj)/uart16550.o
+endif
+
+$(obj)/zImage.lds: $(obj)/image.lds.in $(KERNELCONFIG)
+	@sed "$(ZIMFLAGS)" < $< > $@
+
+$(obj)/rImage.lds: $(obj)/image.lds.in $(KERNELCONFIG)
+	@sed "$(RIMFLAGS)" < $< > $@
+
+$(obj)/piggy.o: $(SYSTEM) $(obj)/Makefile
+	$(OBJCOPY) -S -O binary -R .note -R .comment $(SYSTEM) $(SYSTEM).bin
+	gzip -f -9 < $(SYSTEM).bin > $(SYSTEM).gz
+	echo "O_FORMAT:  " $(O_FORMAT); 
+	$(LD) -r -b binary --oformat $(O_FORMAT) -o $(obj)/piggy.o $(SYSTEM).gz
+	rm -f $(SYSTEM).bin $(SYSTEM).gz
+
+$(obj)/head.o: $(obj)/head.S $(SYSTEM) $(obj)/Makefile
+	$(CC) $(AFLAGS) -DKERNEL_ENTRY=$(KERNEL_ENTRY) -c $(obj)/head.S -o $(obj)/head.o
+
+$(obj)/misc.o: $(obj)/misc.c $(obj)/Makefile
+	$(CC) $(CFLAGS) -DLOADADDR=$(LOADADDR) -DFREE_RAM=$(FREE_RAM) -DEND_RAM=$(END_RAM) \
+		-c $< -DZDEBUG=$(ZDEBUG) -o $(obj)/misc.o
+
+$(obj)/uart16550.o: $(obj)/uart16550.c $(KERNELCONFIG)
+	$(CC) $(CFLAGS) -c $< -o $(obj)/uart16550.o
+
+$(obj)/csu_idt.o: $(obj)/csu_idt.S Makefile $(SYSTEM)
+	$(CC) $(AFLAGS) $(COMMSWITCHES) -c $< -o $(obj)/csu_idt.o
+
+zImage: $(obj)/zImage.lds $(SYSTEM) $(OBJECTS)
+	$(LD) -T$(obj)/zImage.lds -o $(TOPDIR)/zImage $(OBJECTS)
+	$(OBJCOPY) -S -O binary -R .note -R .comment $(TOPDIR)/zImage $(TOPDIR)/zImage.bin
+	$(OBJCOPY) -I binary -S -O srec --srec-forceS3 --srec-len=32 --change-start=0x00000000 \
+		 $(TOPDIR)/zImage.bin $(TOPDIR)/zImage.prm
+	$(SIZE) $(TOPDIR)/zImage |awk -F" " '{ print $$4 "\t" $$5 }' > $(TOPDIR)/zImage.size
+	rm -f *.o
+
+rImage: $(obj)/rImage.lds $(SYSTEM) $(OBJECTS) $(obj)/csu_idt.o
+	echo $(TOPDRIR)
+	@rm -f $(TOPDIR)/*.prm
+	$(LD) -T$(obj)/rImage.lds -o $(TOPDIR)/rImage $(obj)/csu_idt.o $(OBJECTS) 
+	$(OBJCOPY) -S -O binary -R .note -R .comment $(TOPDIR)/rImage $(TOPDIR)/rImage.bin
+	$(OBJCOPY) -I binary -S -O srec --srec-forceS3 --srec-len=32 --change-start=0x00000000 \
+		 $(TOPDIR)/rImage.bin $(TOPDIR)/rImage.prm
+	$(SIZE) $(TOPDIR)/rImage |awk -F" " '{ print $$4 "\t" $$5 }' > $(TOPDIR)/rImage.size
+	rm -f *.o
+clean:
+	rm -f *.o $(TOPDIR)/zImage* $(TOPDIR)/rImage* $(TOPDIR)/*.prm $(TOPDIR)/rImage.size $(TOPDIR)/zImage.size
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/misc.c idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/misc.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/misc.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/misc.c	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,339 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Code to un-compress linux image
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/types.h>
+
+/*
+ * gzip declarations
+ */
+#define OF(args)  args
+#define STATIC static
+#define memzero(s, n)     memset ((s), 0, (n))
+typedef unsigned char uch;
+typedef unsigned short ush;
+typedef unsigned long ulg;
+#define WSIZE 0x8000		/* Window size must be at least 32k, */
+				/* and a power of two */
+static uch *inbuf;		/* input buffer */
+static uch window[WSIZE];	/* Sliding window buffer */
+
+/* gzip flag byte */
+#define ASCII_FLAG   0x01	/* bit 0 set: file probably ASCII text */
+#define CONTINUATION 0x02	/* bit 1 set: continuation of multi-part gzip file */
+#define EXTRA_FIELD  0x04	/* bit 2 set: extra field present */
+#define ORIG_NAME    0x08	/* bit 3 set: original file name present */
+#define COMMENT      0x10	/* bit 4 set: file comment present */
+#define ENCRYPTED    0x20	/* bit 5 set: file is encrypted */
+#define RESERVED     0xC0	/* bit 6,7:   reserved */
+
+
+static unsigned insize;	/* valid bytes in inbuf */
+static unsigned inptr;	/* index of next byte to be processed in inbuf */
+static unsigned outcnt;	/* bytes in output buffer */
+
+void variable_init(void);
+#if ZDEBUG > 0
+static void puts(const char *);
+extern void putc_init(void);
+extern void putc(unsigned char c);
+#endif
+static int fill_inbuf(void);
+static void flush_window(void);
+static void error(char *m);
+static void gzip_mark(void **);
+static void gzip_release(void **);
+
+extern char input_data[];
+
+extern char input_data_end[];
+
+#if ZDEBUG > 0
+void int2hex(unsigned long val)
+{
+        unsigned char buf[10];
+        int i;
+        for (i = 7;  i >= 0;  i--)
+        {
+                buf[i] = "0123456789ABCDEF"[val & 0x0F];
+                val >>= 4;
+        }
+        buf[8] = '\0';
+        puts(buf);
+}
+#endif
+
+static unsigned long byte_count;
+
+int get_byte(void)
+{
+#if ZDEBUG > 1
+	static int printCnt;
+#endif
+	unsigned char c = (inptr < insize ? inbuf[inptr++] : fill_inbuf());
+	byte_count++;
+
+#if ZDEBUG > 1
+	if (printCnt++ < 32)
+	{
+	  puts("byte count = ");
+	  int2hex(byte_count);
+	  puts(" byte val = ");
+	  int2hex(c);
+	  puts("\n");
+	}
+#endif
+	return c;
+}
+
+/* Diagnostic functions */
+#ifdef DEBUG
+#  define Assert(cond,msg) {if(!(cond)) error(msg);}
+#  define Trace(x) fprintf x
+#  define Tracev(x) {if (verbose) fprintf x ;}
+#  define Tracevv(x) {if (verbose>1) fprintf x ;}
+#  define Tracec(c,x) {if (verbose && (c)) fprintf x ;}
+#  define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}
+#else
+#  define Assert(cond,msg)
+#  define Trace(x)
+#  define Tracev(x)
+#  define Tracevv(x)
+#  define Tracec(c,x)
+#  define Tracecv(c,x)
+#endif
+
+/*
+ * This is set up by the setup-routine at boot-time
+ */
+
+static long bytes_out;
+static uch *output_data;
+static unsigned long output_ptr;
+
+
+static void *malloc(int size);
+static void free(void *where);
+static void error(char *m);
+static void gzip_mark(void **);
+static void gzip_release(void **);
+
+static unsigned long free_mem_ptr;
+static unsigned long free_mem_end_ptr;
+
+#include "../../../../../../lib/inflate.c"
+
+static void *malloc(int size)
+{
+	void *p;
+
+	if (size < 0)
+		error("Malloc error\n");
+	if (free_mem_ptr <= 0) error("Memory error\n");
+
+	free_mem_ptr = (free_mem_ptr + 3) & ~3;	/* Align */
+
+	p = (void *) free_mem_ptr;
+	free_mem_ptr += size;
+
+	if (free_mem_ptr >= free_mem_end_ptr)
+		error("\nOut of memory\n");
+
+	return p;
+}
+
+static void free(void *where)
+{				/* Don't care */
+}
+
+static void gzip_mark(void **ptr)
+{
+	*ptr = (void *) free_mem_ptr;
+}
+
+static void gzip_release(void **ptr)
+{
+	free_mem_ptr = (long) *ptr;
+}
+#if ZDEBUG > 0
+static void puts(const char *s)
+{
+	while (*s) {
+		if (*s == 10)
+			putc(13);
+		putc(*s++);
+	}
+}
+#endif
+void *memset(void *s, int c, size_t n)
+{
+	int i;
+	char *ss = (char *) s;
+
+	for (i = 0; i < n; i++)
+		ss[i] = c;
+	return s;
+}
+
+void *memcpy(void *__dest, __const void *__src, size_t __n)
+{
+	int i;
+	char *d = (char *) __dest, *s = (char *) __src;
+
+	for (i = 0; i < __n; i++)
+		d[i] = s[i];
+	return __dest;
+}
+
+/* ===========================================================================
+ * Fill the input buffer. This is called only when the buffer is empty
+ * and at least one byte is really needed.
+ */
+static int fill_inbuf(void)
+{
+	if (insize != 0) {
+		error("ran out of input data\n");
+	}
+
+	inbuf = input_data;
+	insize = &input_data_end[0] - &input_data[0];
+	inptr = 1;
+	return inbuf[0];
+}
+
+/* ===========================================================================
+ * Write the output window window[0..outcnt-1] and update crc and bytes_out.
+ * (Used for the decompressed data only.)
+ */
+static void flush_window(void)
+{
+	ulg c = crc;		/* temporary variable */
+	unsigned n;
+	uch *in, *out, ch;
+
+	in = window;
+	out = &output_data[output_ptr];
+	for (n = 0; n < outcnt; n++) {
+		ch = *out++ = *in++;
+		c = crc_32_tab[((int) c ^ ch) & 0xff] ^ (c >> 8);
+	}
+	crc = c;
+	bytes_out += (ulg) outcnt;
+	output_ptr += (ulg) outcnt;
+	outcnt = 0;
+}
+
+#if ZDEBUG > 0
+void check_mem(void)
+{
+	int i;
+
+	puts("\ncplens = ");
+	for (i = 0; i < 10; i++) {
+		int2hex(cplens[i]);
+		puts(" ");
+	}
+	puts("\ncplext = ");
+	for (i = 0; i < 10; i++) {
+		int2hex(cplext[i]);
+		puts(" ");
+	}
+	puts("\nborder = ");
+	for (i = 0; i < 10; i++) {
+		int2hex(border[i]);
+		puts(" ");
+	}
+	puts("\n");
+}
+#endif
+static void error(char *x)
+{
+#if ZDEBUG > 1
+	check_mem();
+	puts("\n\n");
+	puts(x);
+	puts("byte_count = ");
+	int2hex(byte_count);
+	puts("\n");
+	puts("\n\n -- Error. System halted");
+#endif
+	while (1);		/* Halt */
+}
+
+void variable_init(void)
+{
+	byte_count = 0;
+	output_data = (char *) LOADADDR;
+	free_mem_ptr = FREE_RAM;
+	free_mem_end_ptr = END_RAM;
+#if ZDEBUG > 1
+	puts("output_data      0x");
+	int2hex((unsigned long)output_data); puts("\n");
+	puts("free_mem_ptr     0x");
+	int2hex(free_mem_ptr); puts("\n");
+	puts("free_mem_end_ptr 0x");
+	int2hex(free_mem_end_ptr); puts("\n");
+	puts("input_data       0x");
+	int2hex((unsigned long)input_data); puts("\n");
+#endif
+}
+
+int decompress_kernel(void)
+{
+#if ZDEBUG > 0
+  putc_init();
+#if ZDEBUG > 2
+  check_mem();
+#endif
+#endif
+
+  variable_init();
+
+  makecrc();
+#if ZDEBUG > 0
+  puts("\n");
+  puts("Uncompressing Linux... \n");
+#endif
+  gunzip();		// ...see inflate.c
+#if ZDEBUG > 0
+  puts("Ok, booting the kernel.\n");
+#endif
+
+#if ZDEBUG > 1
+ {
+  unsigned long *p = (unsigned long *)LOADADDR;
+  int2hex(p[0]); puts("\n");
+  int2hex(p[1]); puts("\n");
+  int2hex(p[2]); puts("\n");
+  int2hex(p[3]); puts("\n");
+ }
+#endif
+
+  return 0;
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/rImage.lds idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/rImage.lds
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/rImage.lds	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/rImage.lds	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,31 @@
+OUTPUT_ARCH(mips)
+ENTRY(zstartup)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = 0x9FC00000;
+  .init          : { *(.init)		} =0
+  .text      :
+  {
+    _ftext = . ;
+    *(.text)
+    *(.rodata)
+    *(.rodata1)
+   . = ALIGN(4096);
+    input_data = .;
+    arch/mips/idt-boards/rc32438/EB438/boot/piggy.o
+    input_data_end = .;
+   . = ALIGN(4096);
+    *(.gnu.warning)
+  } =0
+
+  .reginfo : { *(.reginfo) }
+
+   . = 0x800A0000;
+  __bss_start = .;
+  .bss       :
+  {
+   *(.bss)
+  _end = . ;
+  }
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/s438.h idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/s438.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/s438.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/s438.h	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,137 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Some useful macros.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#ifndef __S438__
+#define __S438__
+/******************************** D E F I N E S *******************************/
+
+/*
+** following defines simple and uniform to save and restore context
+** when enrtering and leaving as assemblu language program when memory
+** and registers are both premiunm.
+*/
+#define SAVE_CNTXT  \
+  subu  sp, 64;     \
+  sw    t0, 60(sp); \
+  sw    t1, 56(sp); \
+  sw    t2, 52(sp); \
+  sw    t3, 48(sp); \
+  sw    t4, 44(sp); \
+  sw    t5, 40(sp); \
+  sw    t6, 36(sp); \
+  sw    t7, 32(sp); \
+  sw    t8, 28(sp); \
+  sw    t9, 24(sp); \
+  sw    a0, 20(sp); \
+  sw    a1, 16(sp); \
+  sw    a2, 12(sp); \
+  sw    a3,  8(sp); \
+  sw    ra,  4(sp)
+
+#define RSTR_CNTXT  \
+  lw    t0, 60(sp); \
+  lw    t1, 56(sp); \
+  lw    t2, 52(sp); \
+  lw    t3, 48(sp); \
+  lw    t4, 44(sp); \
+  lw    t5, 40(sp); \
+  lw    t6, 36(sp); \
+  lw    t7, 32(sp); \
+  lw    t8, 28(sp); \
+  lw    t9, 24(sp); \
+  lw    a0, 20(sp); \
+  lw    a1, 16(sp); \
+  lw    a2, 12(sp); \
+  lw    a3,  8(sp); \
+  lw    ra,  4(sp); \
+  add   sp, 64
+
+/*
+** Following define is to specify a maximum value for a software
+** busy wait counter.
+*/
+/*
+#define LP_CNT_100NS  1000      
+#define LP_CNT_3S     1000000   
+*/
+
+/*
+** Following are other common timer definitions.
+*/
+#define DDRBASE           PHYS_TO_K1(0x18018000)
+#define TIMER_BASE        PHYS_TO_K1(0x18028000)  
+#define WTC_BASE          PHYS_TO_K1(0x18030000)  
+#define INTERRUPT_BASE    PHYS_TO_K1(0x18038000)
+#define GPIO_BASE         PHYS_TO_K1(0x18048000)
+
+#define TIMEOUT_COUNT     0x00000FFF
+#define ENABLE_TIMER      0x1
+#define DISABLE_TIMER     0x0
+#define BIG_VALUE         0xFFFFFFFF
+
+/*
+** following few lines define a macro DISPLAY
+** which is used to write a set of 4 characters
+** onto the EB438 LED.
+*/
+
+#ifndef LED_BASE
+
+#define LED_BASE    PHYS_TO_K1(0x0C040000)
+#define LED_DIGIT0  0x3
+#define LED_DIGIT1  0x2
+#define LED_DIGIT2  0x1
+#define LED_DIGIT3  0x0
+#define LED_CLEAR   -0x40000
+
+#endif
+
+#define DISPLAY(d0, d1, d2, d3)     \
+        li    t6, LED_BASE                    ;\
+        lb    t7, LED_CLEAR(t6)               ;\
+              nop                             ;\
+        li    t7, (d0) & 0xff                 ;\
+        sb    t7, LED_DIGIT0(t6)              ;\
+        li    t7, (d1) & 0xff                 ;\
+        sb    t7, LED_DIGIT1(t6)              ;\
+        li    t7, (d2) & 0xff                 ;\
+        sb    t7, LED_DIGIT2(t6)              ;\
+        li    t7, (d3) & 0xff                 ;\
+        sb    t7, LED_DIGIT3(t6)
+
+#define LEDCLEAR()              \
+        li    t6, LED_BASE                    ;\
+        lb    t7, LED_CLEAR(t6)               ;\
+              nop
+
+#define DESTRUCTIVE     1
+#define NONDESTRUCTIVE  0
+
+#endif
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/s438ram.h idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/s438ram.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/s438ram.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/s438ram.h	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,140 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   IDT EB438 DDR setup values.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#ifndef __S438RAM__
+#define __S438RAM__
+/******************************** D E F I N E S *******************************/
+
+#define SRAM_ONLY     1
+#define SDRAM_ONLY    2
+#define SRAM_N_SDRAM  3
+#define SDRAM_N_SRAM  4
+
+#define MB32      1
+#define MB64      2
+#define MB128     3
+
+#define DEV_CTL_BASE        PHYS_TO_K1(0x18010000)  /* device controller regs */
+#define DDR_CTL_BASE        PHYS_TO_K1(0x18018010)  /* DDR controller regs */
+
+#define DEV1_BASE           0x08000000
+#define DEV_PROM_MASK       0xFFF00000
+#define DEV_PROM_CTRL       0x04108324
+#define DEV_PROM_TC         0x00000000
+#define DEV_FLASH_MASK      0xFFE00000
+#define DEV_FLASH_CTRL      0x04108325
+#define DEV_FLASH_TC        0x00000000
+
+#define DEV2_BASE           0x0C000000
+#define DEV2_MASK           0xFC000000
+#define DEV2_CTRL           0x04108324              /* 8-bit devices */
+#define DEV2_TC             0x00000000
+
+#if MEMCFG == SRAM_ONLY || MEMCFG == SRAM_N_SDRAM
+#define DEV3_BASE           0x00000000
+#define DEV3_MASK           0xFC000000
+#define DEV3_CTRL           0x04108325              /* 16-bit devices */
+#define DEV3_TC             0x00000000
+#else
+#define DEV3_BASE           0x10000000
+#define DEV3_MASK           0xFC000000
+#define DEV3_CTRL           0x04108325              /* 16-bit devices */
+#define DEV3_TC             0x00000000
+#endif
+
+#define DEV4_BASE           0x00000000
+#define DEV4_MASK           0x00000000
+#define DEV4_CTRL           0x0FFFFFF4              /* ?-bit devices */
+#define DEV4_TC             0x00001FFF
+
+#define DEV5_BASE           0x00000000
+#define DEV5_MASK           0x00000000
+#define DEV5_CTRL           0x0FFFFFF4              /* ?-bit devices */
+#define DEV5_TC             0x00001FFF
+
+#define DATA_PATTERN        0xA5A5A5A5
+#define RCOUNT              PHYS_TO_K1(0x18028024)
+
+#if DRAMSZ == MB64
+
+#if MEMCFG == SDRAM_ONLY || MEMCFG == SDRAM_N_SRAM
+#define DDR0_BASE_VAL       0x00000000
+#define DDR0_MASK_VAL       0xFC000000
+#define DDR1_BASE_VAL       0x04000000
+#define DDR1_MASK_VAL       0x00000000
+#define DDR0_ABASE_VAL      0x08000000
+#define DDR0_AMASK_VAL      0x00000000
+#elif MEMCFG == SRAM_N_SDRAM
+#define DDR0_BASE_VAL       0x04000000
+#define DDR0_MASK_VAL       0xFC000000
+#define DDR1_BASE_VAL       0x08000000
+#define DDR1_MASK_VAL       0x00000000
+#define DDR0_ABASE_VAL      0x00000000
+#define DDR0_AMASK_VAL      0x00000000
+#elif MEMCFG == SRAM_ONLY
+#define DDR0_BASE_VAL       0x00000000
+#define DDR0_MASK_VAL       0x00000000
+#define DDR1_BASE_VAL       0x00000000
+#define DDR1_MASK_VAL       0x00000000
+#define DDR0_ABASE_VAL      0x00000000
+#define DDR0_AMASK_VAL      0x00000000
+#else
+illegal value for MEMCFG
+#endif
+
+#define DDRC_VAL_NORMAL       0x82984940 /* 0xA32A4980 */
+#define DDRC_VAL_AT_INIT      0x02984940 /* 0x232A4980 */
+
+#define DDR_REF_CMP_FAST      0x00000080 /* was 0x00000100 */
+#define DDR_REF_CMP_VAL       0x00000080 /* was 0x0000040e */
+#define DDR_REF_CMP_VAL_ZB    0x0000040E
+
+#define DDR_CUST_NOP          0x0000003F
+#define DDR_CUST_PRECHARGE    0x00000033
+#define DDR_CUST_REFRESH      0x00000027
+#define DDR_LD_MODE_REG       0x00000023
+#define DDR_LD_EMODE_REG      0x00000063
+
+/* 
+ * All generated addresses for DDR init during custom transactions are shifted
+ * by two address lines - see spec for used DDR chip
+ */
+#define DDR_PRECHARGE_OFFSET  0x00001000  /* 0x0400 - 9-bit page*/
+#define DDR_EMODE_VAL         0x00000000  /* 0x0000 */
+#define DDR_DLL_RES_MODE_VAL  0x00000584  /* 0x0161 - Reset DLL, CL2.5 */
+#define DDR_DLL_MODE_VAL      0x00000184  /* 0x0061 - CL2.5 */
+
+#define DELAY_200USEC         25000       /* not exactly */
+
+#else
+#error "unrecognized dram size"
+#endif
+
+#endif
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/uart16550.c idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/uart16550.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/uart16550.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/uart16550.c	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,177 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   UART code.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+
+#define RC32438_REG_BASE   0xb8000000
+#ifdef __MIPSEB__
+#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50003)
+#else
+#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50000)
+#endif
+
+#define BASE		   RC32438_UART0_BASE
+
+#define MAX_BAUD		(CONFIG_IDT_BOARD_FREQ / 16)
+#define REG_OFFSET		0x4
+
+/* === CONFIG === */
+
+/*
+ * #define BASE			0xb2001000
+ * #define MAX_BAUD		1152000
+ * #define REG_OFFSET		0x10
+ */
+#if (!defined(BASE) || !defined(MAX_BAUD) || !defined(REG_OFFSET))
+#error You must define BASE, MAX_BAUD and REG_OFFSET in the Makefile.
+#endif
+
+#ifndef INIT_SERIAL_PORT
+#define INIT_SERIAL_PORT	1
+#endif
+
+#ifndef DEFAULT_BAUD
+//#define DEFAULT_BAUD		UART16550_BAUD_115200
+#define DEFAULT_BAUD		UART16550_BAUD_9600
+#endif
+#ifndef DEFAULT_PARITY
+#define DEFAULT_PARITY		UART16550_PARITY_NONE
+#endif
+#ifndef DEFAULT_DATA
+#define DEFAULT_DATA		UART16550_DATA_8BIT
+#endif
+#ifndef DEFAULT_STOP
+#define DEFAULT_STOP		UART16550_STOP_1BIT
+#endif
+
+/* === END OF CONFIG === */
+
+typedef         unsigned char uint8;
+typedef         unsigned int  uint32;
+
+#define         UART16550_BAUD_2400             2400
+#define         UART16550_BAUD_4800             4800
+#define         UART16550_BAUD_9600             9600
+#define         UART16550_BAUD_19200            19200
+#define         UART16550_BAUD_38400            38400
+#define         UART16550_BAUD_57600            57600
+#define         UART16550_BAUD_115200           115200
+
+#define         UART16550_PARITY_NONE           0
+#define         UART16550_PARITY_ODD            0x08
+#define         UART16550_PARITY_EVEN           0x18
+#define         UART16550_PARITY_MARK           0x28
+#define         UART16550_PARITY_SPACE          0x38
+
+#define         UART16550_DATA_5BIT             0x0
+#define         UART16550_DATA_6BIT             0x1
+#define         UART16550_DATA_7BIT             0x2
+#define         UART16550_DATA_8BIT             0x3
+
+#define         UART16550_STOP_1BIT             0x0
+#define         UART16550_STOP_2BIT             0x4
+
+/* register offset */
+#define		OFS_RCV_BUFFER		(0*REG_OFFSET)
+#define		OFS_TRANS_HOLD		(0*REG_OFFSET)
+#define		OFS_SEND_BUFFER		(0*REG_OFFSET)
+#define		OFS_INTR_ENABLE		(1*REG_OFFSET)
+#define		OFS_INTR_ID		(2*REG_OFFSET)
+#define		OFS_DATA_FORMAT		(3*REG_OFFSET)
+#define		OFS_LINE_CONTROL	(3*REG_OFFSET)
+#define		OFS_MODEM_CONTROL	(4*REG_OFFSET)
+#define		OFS_RS232_OUTPUT	(4*REG_OFFSET)
+#define		OFS_LINE_STATUS		(5*REG_OFFSET)
+#define		OFS_MODEM_STATUS	(6*REG_OFFSET)
+#define		OFS_RS232_INPUT		(6*REG_OFFSET)
+#define		OFS_SCRATCH_PAD		(7*REG_OFFSET)
+
+#define		OFS_DIVISOR_LSB		(0*REG_OFFSET)
+#define		OFS_DIVISOR_MSB		(1*REG_OFFSET)
+
+#define		UART16550_READ(y)    (*((volatile uint8*)(BASE + y)))
+#define		UART16550_WRITE(y, z)  ((*((volatile uint8*)(BASE + y))) = z)
+
+static void Uart16550Init(uint32 baud, uint8 data, uint8 parity, uint8 stop)
+{
+	/* disable interrupts */
+	UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
+	UART16550_WRITE(OFS_INTR_ENABLE, 0);
+
+	/* set up baud rate */
+	{
+		uint32 divisor;
+
+		/* set DIAB bit */
+		UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
+
+		/* set divisor */
+		divisor = MAX_BAUD / baud;
+		UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
+		UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00)>>8);
+
+		/* clear DIAB bit */
+		UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
+	}
+
+	/* set data format */
+	UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
+}
+
+
+void
+putc_init(void)
+{
+#if INIT_SERIAL_PORT
+	Uart16550Init(DEFAULT_BAUD, DEFAULT_DATA, DEFAULT_PARITY, DEFAULT_STOP);
+#endif
+}
+
+void
+putc(unsigned char c)
+{
+	while ((UART16550_READ(OFS_LINE_STATUS) &0x20) == 0);
+	UART16550_WRITE(OFS_SEND_BUFFER, c);
+}
+
+#if 0
+unsigned char
+getc(void)
+{
+	while((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
+	return UART16550_READ(OFS_RCV_BUFFER);
+}
+
+int
+tstc(void)
+{
+	return((UART16550_READ(OFS_LINE_STATUS) & 0x01) != 0);
+}
+#endif
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/zImage.lds idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/zImage.lds
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/boot/zImage.lds	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/boot/zImage.lds	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,31 @@
+OUTPUT_ARCH(mips)
+ENTRY(zstartup)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = 0x88000000;
+  .init          : { *(.init)		} =0
+  .text      :
+  {
+    _ftext = . ;
+    *(.text)
+    *(.rodata)
+    *(.rodata1)
+   . = ALIGN(4096);
+    input_data = .;
+    arch/mips/idt-boards/rc32438/EB438/boot/piggy.o
+    input_data_end = .;
+   . = ALIGN(4096);
+    *(.gnu.warning)
+  } =0
+
+  .reginfo : { *(.reginfo) }
+
+   . = 0x800A0000;
+  __bss_start = .;
+  .bss       :
+  {
+   *(.bss)
+  _end = . ;
+  }
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/idtIRQ.S idtlinux/arch/mips/idt-boards/rc32438/EB438/idtIRQ.S
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/idtIRQ.S	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/idtIRQ.S	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,72 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Intterrupt dispatcher code for IDT boards
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>				
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
+
+	.text
+	.set	noreorder
+	.set	noat
+	.align	5
+	NESTED(idtIRQ, PT_SIZE, sp)
+	SAVE_ALL
+	CLI
+
+	.set	at
+	.set	noreorder
+
+	mfc0    t0, CP0_CAUSE
+	move	a1, sp
+								  
+	/* check for r4k counter/timer IRQ. */
+
+#ifdef CONFIG_RC32438_REVISION_ZA
+	andi    t1, t0, CAUSEF_IP2
+#else	
+	andi    t1, t0, CAUSEF_IP7
+#endif	
+	beqz    t1, 1f
+	nop
+
+	jal     idt_timer_interrupt
+	li	a0, 7
+	j	ret_from_irq
+	nop
+1:
+	jal	rc32438_irqdispatch
+	move	a0, t0
+	j	ret_from_irq
+	nop
+
+	END(idtIRQ)
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/irq.c idtlinux/arch/mips/idt-boards/rc32438/EB438/irq.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/irq.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/irq.c	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,264 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Interrupt routines for IDT EB438 boards
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/delay.h>
+
+#include <asm/bitops.h>
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+#include <asm/idt-boards/rc32438/rc32438.h>
+#include <asm/idt-boards/rc32438/rc32438_gpio.h>
+
+#include <asm/irq.h>
+
+#undef DEBUG_IRQ
+#ifdef DEBUG_IRQ
+/* note: prints function name for you */
+#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
+#else
+#define DPRINTK(fmt, args...)
+#endif
+
+extern asmlinkage void idtIRQ(void);
+static unsigned int startup_irq(unsigned int irq);
+static void end_irq(unsigned int irq_nr);
+static void mask_and_ack_irq(unsigned int irq_nr);
+static void rc32438_enable_irq(unsigned int irq_nr);
+static void rc32438_disable_irq(unsigned int irq_nr);
+
+extern void __init init_generic_irq(void);
+
+typedef struct {
+  u32 mask;
+  volatile u32 *base_addr;
+} intr_group_t;
+
+static const intr_group_t intr_group[NUM_INTR_GROUPS] = {
+  { 0x0000efff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET) },
+  { 0x00001fff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET) },
+  { 0x00000007, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET) },
+  { 0x0003ffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET) },
+  { 0xffffffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET) }
+};
+
+#define READ_PEND(base) (*(base))
+#define READ_MASK(base) (*(base + 2))
+#define WRITE_MASK(base, val) (*(base + 2) = (val))
+
+static inline int irq_to_group(unsigned int irq_nr)
+{
+  return ((irq_nr - GROUP0_IRQ_BASE) >> 5);
+}
+
+static inline int group_to_ip(unsigned int group)
+{
+  return group + 2;
+}
+
+static inline void enable_local_irq(unsigned int ip)
+{
+  int ipnum = 0x100 << ip;
+  clear_c0_cause(ipnum);
+  set_c0_status(ipnum);
+}
+
+static inline void disable_local_irq(unsigned int ip)
+{
+  int ipnum = 0x100 << ip;
+  clear_c0_status(ipnum);
+}
+
+static inline void ack_local_irq(unsigned int ip)
+{
+  int ipnum = 0x100 << ip;
+  clear_c0_cause(ipnum);
+}
+static void rc32438_enable_irq(unsigned int irq_nr)
+{
+  int           ip = irq_nr - GROUP0_IRQ_BASE;
+  unsigned int  group, intr_bit;
+  volatile unsigned int  *addr;
+  if (ip < 0)
+    {
+      enable_local_irq(irq_nr);
+    }
+  else
+    {
+  // calculate group
+  group = ip >> 5;
+    
+  // calc interrupt bit within group
+  ip -= (group << 5);
+  intr_bit = 1 << ip;
+    
+  // first enable the IP mapped to this IRQ
+  enable_local_irq(group_to_ip(group));
+    
+  addr = intr_group[group].base_addr;
+  // unmask intr within group
+  WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
+    }
+}
+
+static void rc32438_disable_irq(unsigned int irq_nr)
+{
+  int           ip = irq_nr - GROUP0_IRQ_BASE;
+  unsigned int  group, intr_bit, mask;
+  volatile unsigned int  *addr;
+
+  // calculate group
+  group = ip >> 5;
+
+  // calc interrupt bit within group
+  ip -= group << 5;
+  intr_bit = 1 << ip;
+    
+  addr = intr_group[group].base_addr;
+  // mask intr within group
+  mask = READ_MASK(addr);
+  mask |= intr_bit;
+  WRITE_MASK(addr, mask);
+    
+  /*
+    if there are no more interrupts enabled in this
+    group, disable corresponding IP
+  */
+  if (mask == intr_group[group].mask)
+    disable_local_irq(group_to_ip(group));
+}
+static unsigned int startup_irq(unsigned int irq_nr)
+{
+  rc32438_enable_irq(irq_nr);
+  return 0; 
+}
+
+static void shutdown_irq(unsigned int irq_nr)
+{
+  rc32438_disable_irq(irq_nr);
+  return;
+}
+
+static void mask_and_ack_irq(unsigned int irq_nr)
+{
+  rc32438_disable_irq(irq_nr);
+  ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
+}
+
+static void end_irq(unsigned int irq_nr)
+{
+
+  int ip = irq_nr - GROUP0_IRQ_BASE;
+  unsigned int intr_bit, group;
+  volatile unsigned int *addr;
+
+  if (!(irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
+    if (irq_nr == GROUP4_IRQ_BASE + 27)
+      gpio->gpioistat = 0xf7ffffff;
+      
+    group = ip >> 5;
+
+    // calc interrupt bit within group
+    ip -= (group << 5);
+    intr_bit = 1 << ip;
+    
+    // first enable the IP mapped to this IRQ
+    enable_local_irq(group_to_ip(group));
+  
+    addr = intr_group[group].base_addr;
+    // unmask intr within group
+    WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
+  } 
+  else {
+    printk("warning: end_irq %d did not enable (%x)\n", 
+	   irq_nr, irq_desc[irq_nr].status);
+  }
+}
+
+static struct hw_interrupt_type rc32438_irq_type = {
+  .typename = "IDT438",
+  .startup  = startup_irq,
+  .shutdown = shutdown_irq,
+  .enable   = rc32438_enable_irq,
+  .disable  = rc32438_disable_irq,
+  .ack      = mask_and_ack_irq,
+  .end      = end_irq,
+};
+
+void __init arch_init_irq(void)
+{
+  int i;
+  printk("Initializing IRQ's: %d out of %d\n", RC32438_NR_IRQS, NR_IRQS);  
+  memset(irq_desc, 0, sizeof(irq_desc));
+  set_except_vector(0, idtIRQ);
+  
+  for (i = 0; i < RC32438_NR_IRQS; i++) {
+    irq_desc[i].status = IRQ_DISABLED;
+    irq_desc[i].action = NULL;
+    irq_desc[i].depth = 1;
+    irq_desc[i].handler = &rc32438_irq_type;
+    spin_lock_init(&irq_desc[i].lock);
+  }
+}
+
+/* Main Interrupt dispatcher */
+void rc32438_irqdispatch(unsigned long cp0_cause, struct pt_regs *regs)
+{
+  unsigned int ip, pend, group;
+  volatile unsigned int *addr;
+
+  if ((ip = (cp0_cause & 0x7c00))) {
+    group = 21 - rc32438_clz(ip);
+
+    addr = intr_group[group].base_addr;
+
+    pend = READ_PEND(addr);
+    pend &= ~READ_MASK(addr); // only unmasked interrupts
+    pend = 39 - rc32438_clz(pend);
+    do_IRQ((group << 5) + pend, regs);
+    return;
+  } 
+  else
+    return;
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/Makefile idtlinux/arch/mips/idt-boards/rc32438/EB438/Makefile
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/Makefile	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/Makefile	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,42 @@
+###############################################################################
+#
+#  BRIEF MODULE DESCRIPTION
+#     Makefile for IDT EB438 board BSP
+#
+#  Copyright 2006 IDT Inc. (rischelp@idt.com)
+#
+#  This program is free software; you can redistribute  it and/or modify it
+#  under  the terms of  the GNU General  Public License as published by the
+#  Free Software Foundation;  either version 2 of the  License, or (at your
+#  option) any later version.
+#
+#  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+#  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+#   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+#   NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+#   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+#   NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+#   USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+#   ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+#   THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#   You should have received a copy of the  GNU General Public License along
+#   with this program; if not, write  to the Free Software Foundation, Inc.,
+#   675 Mass Ave, Cambridge, MA 02139, USA.
+# 
+# 
+###############################################################################
+
+
+.S.s:
+	$(CPP) $(CFLAGS) $< -o $*.s
+.S.o:
+	$(CC) $(CFLAGS) -c $< -o $*.o
+
+obj-y	 := irq.o prom.o time.o setup.o idtIRQ.o reset.o
+obj-$(CONFIG_KGDB)			+= serial_gdb.o
+obj-$(CONFIG_SERIAL_8250) 		+= serial.o
+subdir-$(CONFIG_IDT_BOOT_NVRAM)		+= nvram
+obj-$(CONFIG_IDT_BOOT_NVRAM)    	+= nvram/built-in.o
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/nvram/Makefile idtlinux/arch/mips/idt-boards/rc32438/EB438/nvram/Makefile
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/nvram/Makefile	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/nvram/Makefile	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,42 @@
+###############################################################################
+#
+#  BRIEF MODULE DESCRIPTION
+#     Makefile for IDT EB438 nvram access routines
+#
+#  Copyright 2006 IDT Inc. (rischelp@idt.com)
+#
+#  This program is free software; you can redistribute  it and/or modify it
+#  under  the terms of  the GNU General  Public License as published by the
+#  Free Software Foundation;  either version 2 of the  License, or (at your
+#  option) any later version.
+#
+#  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+#  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+#   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+#   NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+#   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+#   NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+#   USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+#   ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+#   THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#   You should have received a copy of the  GNU General Public License along
+#   with this program; if not, write  to the Free Software Foundation, Inc.,
+#   675 Mass Ave, Cambridge, MA 02139, USA.
+#
+###############################################################################
+
+.S.s:   
+	$(CPP) $(CFLAGS) $< -o $*.s
+.S.o:   
+	$(CC) $(CFLAGS) -c $< -o $*.o
+
+obj-y   := nvram438.o
+
+
+
+
+
+
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/nvram/nvram438.c idtlinux/arch/mips/idt-boards/rc32438/EB438/nvram/nvram438.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/nvram/nvram438.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/nvram/nvram438.c	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,356 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     nvram interface routines.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+  **************************************************************************
+ */
+
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include "nvram438.h"
+#include "rtc.h"
+#define  NVRAM_BASE RTCLOCK_BASE
+
+extern void setenv (char *e, char *v, int rewrite);
+extern void unsetenv (char *e);
+extern void mapenv (int (*func)(char *, char *));
+extern char *getenv (char *s);
+extern void purgeenv(void);
+
+static void nvram_initenv(void);
+
+static unsigned char
+nvram_getbyte(int offs)
+{
+  return(*((unsigned char*)(NVRAM_BASE + offs)));
+}
+
+static void
+nvram_setbyte(int offs, unsigned char val)
+{
+  unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
+
+  *nvramDataPointer = val;
+}
+
+static unsigned short
+nvram_getshort(int offs)
+{
+  return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
+}
+
+static void
+nvram_setshort(int offs, unsigned short val)
+{
+  nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
+  nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
+}
+/*
+ * calculate NVRAM checksum
+ */
+static unsigned short
+nvram_calcsum(void)
+{
+  unsigned short sum = NV_MAGIC;
+  int     i;
+
+  for (i = ENV_BASE; i < ENV_TOP; i += 2)
+    sum += nvram_getshort(i);
+  return(sum);
+}
+
+/*
+ * update the nvram checksum
+ */
+static void
+nvram_updatesum (void)
+{
+  nvram_setshort(NVOFF_CSUM, nvram_calcsum());
+}
+
+/*
+ * test validity of nvram by checksumming it
+ */
+static int
+nvram_isvalid(void)
+{
+  static int  is_valid;
+
+  if (is_valid)
+    return(1);
+
+  if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC)
+    nvram_initenv();
+  is_valid = 1;
+  return(1);
+}
+
+/* return nvram address of environment string */
+static int
+nvram_matchenv(char *s)
+{
+  int envsize, envp, n, i, varsize;
+  char *var;
+
+  envsize = nvram_getshort(NVOFF_ENVSIZE);
+  if (envsize > ENV_AVAIL)
+    return(0);     /* sanity */
+    
+  envp = ENV_BASE;
+
+  if ((n = strlen (s)) > 255)
+    return(0);
+    
+  while (envsize > 0) {
+    varsize = nvram_getbyte(envp);
+    if (varsize == 0 || (envp + varsize) > ENV_TOP)
+      return(0);   /* sanity */
+    for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
+      char c1 = nvram_getbyte(i);
+      char c2 = *var;
+      if (islower(c1))
+        c1 = toupper(c1);
+      if (islower(c2))
+        c2 = toupper(c2);
+      if (c1 != c2)
+        break;
+    }
+    if (i > envp + n) {       /* match so far */
+      if (n == varsize - 1)   /* match on boolean */
+        return(envp);
+      if (nvram_getbyte(i) == '=')  /* exact match on variable */
+        return(envp);
+    }
+    envsize -= varsize;
+    envp += varsize;
+  }
+  return(0);
+}
+
+static void nvram_initenv(void)
+{
+  nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
+  nvram_setshort(NVOFF_ENVSIZE, 0);
+
+  nvram_updatesum();
+}
+
+static void
+nvram_delenv(char *s)
+{
+  int nenvp, envp, envsize, nbytes;
+
+  envp = nvram_matchenv(s);
+  if (envp == 0)
+    return;
+
+  nenvp = envp + nvram_getbyte(envp);
+  envsize = nvram_getshort(NVOFF_ENVSIZE);
+  nbytes = envsize - (nenvp - ENV_BASE);
+  nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
+  while (nbytes--) {
+    nvram_setbyte(envp, nvram_getbyte(nenvp));
+    envp++;
+    nenvp++;
+  }
+  nvram_updatesum();
+}
+
+static int
+nvram_setenv(char *s, char *v)
+{
+  int ns, nv, total;
+  int envp;
+
+  if (!nvram_isvalid())
+    return(-1);
+
+  nvram_delenv(s);
+  ns = strlen(s);
+  if (ns == 0)
+    return (-1);
+  if (v && *v) {
+    nv = strlen(v);
+    total = ns + nv + 2;
+  }
+  else {
+    nv = 0;
+    total = ns + 1;
+  }
+  if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
+    return(-1);
+
+  envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
+
+  nvram_setbyte(envp, (unsigned char) total); 
+  envp++;
+
+  while (ns--) {
+    nvram_setbyte(envp, *s); 
+    envp++; 
+    s++;
+  }
+
+  if (nv) {
+    nvram_setbyte(envp, '='); 
+    envp++;
+    while (nv--) {
+      nvram_setbyte(envp, *v); 
+      envp++; 
+      v++;
+    }
+  }
+  nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
+  nvram_updatesum();
+  return 0;
+}
+
+static char *
+nvram_getenv(char *s)
+{
+  static char buf[256];   /* FIXME: this cannot be static */
+  int envp, ns, nbytes, i;
+
+  if (!nvram_isvalid())
+    return((char *)0);
+
+  envp = nvram_matchenv(s);
+  if (envp == 0)
+    return((char *)0);
+  ns = strlen(s);
+  if (nvram_getbyte(envp) == ns + 1)  /* boolean */
+    buf[0] = '\0';
+  else {
+    nbytes = nvram_getbyte(envp) - (ns + 2);
+    envp += ns + 2;
+    for (i = 0; i < nbytes; i++)
+      buf[i] = nvram_getbyte(envp++);
+    buf[i] = '\0';
+  }
+  return(buf);
+}
+
+static void
+nvram_unsetenv(char *s)
+{
+  if (!nvram_isvalid())
+    return;
+
+  nvram_delenv(s);
+}
+
+/*
+ * apply func to each string in environment
+ */
+static void
+nvram_mapenv(int (*func)(char *, char *))
+{
+  int envsize, envp, n, i, seeneql;
+  char name[256], value[256];
+  char c, *s;
+
+  if (!nvram_isvalid())
+    return;
+
+  envsize = nvram_getshort(NVOFF_ENVSIZE);
+  envp = ENV_BASE;
+
+  while (envsize > 0) {
+    value[0] = '\0';
+    seeneql = 0;
+    s = name;
+    n = nvram_getbyte(envp);
+    for (i = envp + 1; i < envp + n; i++) {
+      c = nvram_getbyte(i);
+      if ((c == '=') && !seeneql) {
+        *s = '\0';
+        s = value;
+        seeneql = 1;
+        continue;
+      }
+      *s++ = c;
+    }
+    *s = '\0';
+    (*func)(name, value);
+    envsize -= n;
+    envp += n;
+  }
+}
+#if 0
+static unsigned int
+digit(char c)
+{
+  if ('0' <= c && c <= '9')
+    return (c - '0');
+  if ('A' <= c && c <= 'Z')
+    return (10 + c - 'A');
+  if ('a' <= c && c <= 'z')
+    return (10 + c - 'a');
+  return (~0);
+}
+#endif
+/*
+ * Wrappers to allow 'special' environment variables to get processed
+ */
+void
+setenv(char *e, char *v, int rewrite)
+{
+  if (nvram_getenv(e) && !rewrite)
+    return;
+    
+  nvram_setenv(e, v);
+}
+
+char *
+getenv(char *e)
+{
+  return(nvram_getenv(e));
+}
+
+void
+unsetenv(char *e)
+{
+  nvram_unsetenv(e);
+}
+
+void
+purgeenv()
+{
+  int i;
+  unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
+  
+  for (i = ENV_BASE; i < ENV_TOP; i++)
+    *nvramDataPointer++ = 0;
+  nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
+  nvram_setshort(NVOFF_ENVSIZE, 0);
+  nvram_setshort(NVOFF_CSUM, NV_MAGIC);
+}
+
+void
+mapenv(int (*func)(char *, char *))
+{
+  nvram_mapenv(func);
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/nvram/nvram438.h idtlinux/arch/mips/idt-boards/rc32438/EB438/nvram/nvram438.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/nvram/nvram438.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/nvram/nvram438.h	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,57 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     nvram definitions.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_EB438_NVRAM_H__
+#define __IDT_EB438_NVRAM_H__
+#define NVOFFSET        0                 /* use all of NVRAM */
+
+/* Offsets to reserved locations */
+              /* size description */
+#define NVOFF_MAGIC     (NVOFFSET + 0)    /* 2 magic value */
+#define NVOFF_CSUM      (NVOFFSET + 2)    /* 2 NVRAM environment checksum */
+#define NVOFF_ENVSIZE   (NVOFFSET + 4)    /* 2 size of 'environment' */
+#define NVOFF_TEST      (NVOFFSET + 5)    /* 1 cold start test byte */
+#define NVOFF_ETHADDR   (NVOFFSET + 6)    /* 6 decoded ethernet address */
+#define NVOFF_UNUSED    (NVOFFSET + 12)   /* 0 current end of table */
+
+#define NV_MAGIC        0xdeaf            /* nvram magic number */
+#define NV_RESERVED     32                /* number of reserved bytes */
+
+#undef  NVOFF_ETHADDR
+#define NVOFF_ETHADDR   (NVOFFSET + NV_RESERVED - 6)
+
+/* number of bytes available for environment */
+#define ENV_BASE        (NVOFFSET + NV_RESERVED)
+#define ENV_TOP         TD_NVRAM_SIZE
+#define ENV_AVAIL       (ENV_TOP - ENV_BASE)
+
+#endif //__IDT_EB438_NVRAM_H__
+
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/nvram/rtc.h idtlinux/arch/mips/idt-boards/rc32438/EB438/nvram/rtc.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/nvram/rtc.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/nvram/rtc.h	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,74 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     DS1553(Dallas Semiconductor) Real Time Clock and Non-Volatile RAM.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_EB438_RTC_H__
+#define __IDT_EB438_RTC_H__
+#define RTCLOCK_BASE    0xAC080000
+
+/*
+ * To maintain endianess independence, make all accesses as 32-bit
+ * words with appropriate shifting.
+ */
+#define TD_NVRAM_SIZE 0x2000
+
+typedef struct td_clock {
+  unsigned char ram[0x1FF0];
+  unsigned char flags;
+  unsigned char dummy;
+  unsigned char alarm_secs;
+  unsigned char alarm_mins;
+  unsigned char alarm_hours;
+  unsigned char alarm_date;
+  unsigned char interrupts;
+  unsigned char watchdog;
+  unsigned char century;
+  unsigned char secs;
+  unsigned char mins;
+  unsigned char hours;
+  unsigned char weekday;
+  unsigned char date;
+  unsigned char month;
+  unsigned char year;
+} RTC;
+
+#define rtc (*((volatile RTC *)RTCLOCK_BASE))
+
+/*
+ * Control register bit definitions
+ */
+#define TDC_ENA_READ      0x40
+#define TDC_DIS_READ      0xbf
+
+#define TDC_ENA_WRITE     0x80
+#define TDC_DIS_WRITE     0x7f
+
+#define TDC_RUN_OSC       0x80
+
+#endif //__IDT_EB438_RTC_H__
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/nvram438.c idtlinux/arch/mips/idt-boards/rc32438/EB438/nvram438.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/nvram438.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/nvram438.c	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,348 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Routines to access the NVRAM on IDT EB438 board
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/string.h>
+#include <linux/ctype.h>
+
+#include "nvram438.h"
+#include "rtc.h"
+#define  NVRAM_BASE RTCLOCK_BASE
+
+extern void setenv (char *e, char *v, int rewrite);
+extern void unsetenv (char *e);
+extern void mapenv (int (*func)(char *, char *));
+extern char *getenv (char *s);
+extern void purgeenv(void);
+
+static void nvram_initenv(void);
+
+static unsigned char
+nvram_getbyte(int offs)
+{
+  return(*((unsigned char*)(NVRAM_BASE + offs)));
+}
+
+static void
+nvram_setbyte(int offs, unsigned char val)
+{
+  unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
+
+  *nvramDataPointer = val;
+}
+
+/*
+ * BigEndian!
+ */
+static unsigned short
+nvram_getshort(int offs)
+{
+  return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
+}
+
+static void
+nvram_setshort(int offs, unsigned short val)
+{
+  nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
+  nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
+}
+/*
+ * calculate NVRAM checksum
+ */
+static unsigned short
+nvram_calcsum(void)
+{
+  unsigned short sum = NV_MAGIC;
+  int     i;
+
+  for (i = ENV_BASE; i < ENV_TOP; i += 2)
+    sum += nvram_getshort(i);
+  return(sum);
+}
+
+/*
+ * update the nvram checksum
+ */
+static void
+nvram_updatesum (void)
+{
+  nvram_setshort(NVOFF_CSUM, nvram_calcsum());
+}
+
+/*
+ * test validity of nvram by checksumming it
+ */
+static int
+nvram_isvalid(void)
+{
+  static int  is_valid;
+
+  if (is_valid)
+    return(1);
+
+  if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC)
+    nvram_initenv();
+  is_valid = 1;
+  return(1);
+}
+
+/* return nvram address of environment string */
+static int
+nvram_matchenv(char *s)
+{
+  int envsize, envp, n, i, varsize;
+  char *var;
+
+  envsize = nvram_getshort(NVOFF_ENVSIZE);
+  if (envsize > ENV_AVAIL)
+    return(0);     /* sanity */
+    
+  envp = ENV_BASE;
+
+  if ((n = strlen (s)) > 255)
+    return(0);
+    
+  while (envsize > 0) {
+    varsize = nvram_getbyte(envp);
+    if (varsize == 0 || (envp + varsize) > ENV_TOP)
+      return(0);   /* sanity */
+    for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
+      char c1 = nvram_getbyte(i);
+      char c2 = *var;
+      if (islower(c1))
+        c1 = toupper(c1);
+      if (islower(c2))
+        c2 = toupper(c2);
+      if (c1 != c2)
+        break;
+    }
+    if (i > envp + n) {       /* match so far */
+      if (n == varsize - 1)   /* match on boolean */
+        return(envp);
+      if (nvram_getbyte(i) == '=')  /* exact match on variable */
+        return(envp);
+    }
+    envsize -= varsize;
+    envp += varsize;
+  }
+  return(0);
+}
+
+static void nvram_initenv(void)
+{
+  nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
+  nvram_setshort(NVOFF_ENVSIZE, 0);
+
+  nvram_updatesum();
+}
+
+static void
+nvram_delenv(char *s)
+{
+  int nenvp, envp, envsize, nbytes;
+
+  envp = nvram_matchenv(s);
+  if (envp == 0)
+    return;
+
+  nenvp = envp + nvram_getbyte(envp);
+  envsize = nvram_getshort(NVOFF_ENVSIZE);
+  nbytes = envsize - (nenvp - ENV_BASE);
+  nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
+  while (nbytes--) {
+    nvram_setbyte(envp, nvram_getbyte(nenvp));
+    envp++;
+    nenvp++;
+  }
+  nvram_updatesum();
+}
+
+static int
+nvram_setenv(char *s, char *v)
+{
+  int ns, nv, total;
+  int envp;
+
+  if (!nvram_isvalid())
+    return(-1);
+
+  nvram_delenv(s);
+  ns = strlen(s);
+  if (ns == 0)
+    return (-1);
+  if (v && *v) {
+    nv = strlen(v);
+    total = ns + nv + 2;
+  }
+  else {
+    nv = 0;
+    total = ns + 1;
+  }
+  if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
+    return(-1);
+
+  envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
+
+  nvram_setbyte(envp, (unsigned char) total); 
+  envp++;
+
+  while (ns--) {
+    nvram_setbyte(envp, *s); 
+    envp++; 
+    s++;
+  }
+
+  if (nv) {
+    nvram_setbyte(envp, '='); 
+    envp++;
+    while (nv--) {
+      nvram_setbyte(envp, *v); 
+      envp++; 
+      v++;
+    }
+  }
+  nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
+  nvram_updatesum();
+  return 0;
+}
+
+static char *
+nvram_getenv(char *s)
+{
+  static char buf[256];   /* FIXME: this cannot be static */
+  int envp, ns, nbytes, i;
+
+  if (!nvram_isvalid())
+    return((char *)0);
+
+  envp = nvram_matchenv(s);
+  if (envp == 0)
+    return((char *)0);
+  ns = strlen(s);
+  if (nvram_getbyte(envp) == ns + 1)  /* boolean */
+    buf[0] = '\0';
+  else {
+    nbytes = nvram_getbyte(envp) - (ns + 2);
+    envp += ns + 2;
+    for (i = 0; i < nbytes; i++)
+      buf[i] = nvram_getbyte(envp++);
+    buf[i] = '\0';
+  }
+  return(buf);
+}
+
+static void
+nvram_unsetenv(char *s)
+{
+  if (!nvram_isvalid())
+    return;
+
+  nvram_delenv(s);
+}
+
+/*
+ * apply func to each string in environment
+ */
+static void
+nvram_mapenv(int (*func)(char *, char *))
+{
+  int envsize, envp, n, i, seeneql;
+  char name[256], value[256];
+  char c, *s;
+
+  if (!nvram_isvalid())
+    return;
+
+  envsize = nvram_getshort(NVOFF_ENVSIZE);
+  envp = ENV_BASE;
+
+  while (envsize > 0) {
+    value[0] = '\0';
+    seeneql = 0;
+    s = name;
+    n = nvram_getbyte(envp);
+    for (i = envp + 1; i < envp + n; i++) {
+      c = nvram_getbyte(i);
+      if ((c == '=') && !seeneql) {
+        *s = '\0';
+        s = value;
+        seeneql = 1;
+        continue;
+      }
+      *s++ = c;
+    }
+    *s = '\0';
+    (*func)(name, value);
+    envsize -= n;
+    envp += n;
+  }
+}
+/*
+ * Wrappers to allow 'special' environment variables to get processed
+ */
+void
+setenv(char *e, char *v, int rewrite)
+{
+  if (nvram_getenv(e) && !rewrite)
+    return;
+    
+  nvram_setenv(e, v);
+}
+
+char *
+getenv(char *e)
+{
+  return(nvram_getenv(e));
+}
+
+void
+unsetenv(char *e)
+{
+  nvram_unsetenv(e);
+}
+
+void
+purgeenv()
+{
+  int i;
+  unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
+  
+  for (i = ENV_BASE; i < ENV_TOP; i++)
+    *nvramDataPointer++ = 0;
+  nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
+  nvram_setshort(NVOFF_ENVSIZE, 0);
+  nvram_setshort(NVOFF_CSUM, NV_MAGIC);
+}
+
+void
+mapenv(int (*func)(char *, char *))
+{
+  nvram_mapenv(func);
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/nvram438.h idtlinux/arch/mips/idt-boards/rc32438/EB438/nvram438.h
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/nvram438.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/nvram438.h	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,54 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Definitions for NVRAM on IDT EB438 board
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+
+#define NVOFFSET        0                 /* use all of NVRAM */
+
+/* Offsets to reserved locations */
+              /* size description */
+#define NVOFF_MAGIC     (NVOFFSET + 0)    /* 2 magic value */
+#define NVOFF_CSUM      (NVOFFSET + 2)    /* 2 NVRAM environment checksum */
+#define NVOFF_ENVSIZE   (NVOFFSET + 4)    /* 2 size of 'environment' */
+#define NVOFF_TEST      (NVOFFSET + 5)    /* 1 cold start test byte */
+#define NVOFF_ETHADDR   (NVOFFSET + 6)    /* 6 decoded ethernet address */
+#define NVOFF_UNUSED    (NVOFFSET + 12)   /* 0 current end of table */
+
+#define NV_MAGIC        0xdeaf            /* nvram magic number */
+#define NV_RESERVED     32                /* number of reserved bytes */
+
+#undef  NVOFF_ETHADDR
+#define NVOFF_ETHADDR   (NVOFFSET + NV_RESERVED - 6)
+
+/* number of bytes available for environment */
+#define ENV_BASE        (NVOFFSET + NV_RESERVED)
+#define ENV_TOP         TD_NVRAM_SIZE
+#define ENV_AVAIL       (ENV_TOP - ENV_BASE)
+
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/prom.c idtlinux/arch/mips/idt-boards/rc32438/EB438/prom.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/prom.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/prom.c	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,138 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     prom interface routines
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/console.h>
+#include <asm/bootinfo.h>
+#include <linux/bootmem.h>
+#include <linux/ioport.h>
+#include <linux/serial.h>
+#include <linux/serialP.h>
+#include <asm/serial.h>
+#include <linux/ioport.h>
+
+unsigned int idt_cpu_freq = CONFIG_IDT_BOARD_FREQ;
+EXPORT_SYMBOL(idt_cpu_freq);
+
+extern void setup_serial_port(void);
+#ifdef CONFIG_IDT_BOOT_NVRAM
+extern void mapenv(int (*func)(char *, char *));
+static int make_bootparm(char *name,char *val)
+{ 
+/*
+ * The bootparameters are obtained from NVRAM and formatted here.
+ * For e.g.
+ *
+ *    netaddr=10.0.1.95
+ *    bootaddr=10.0.0.139
+ *    bootfile=vmlinus
+ *    bootparm1=root=/dev/nfs
+ *    bootparm2=ip=10.0.1.95
+ *
+ * is parsed to:
+ *
+ *      root=/dev/nfs ip=10.0.1.95
+ *
+ * in arcs_cmdline[].
+ */
+  if (strncmp(name, "bootparm", 8) == 0) {
+    strcat(arcs_cmdline,val);
+    strcat(arcs_cmdline," ");
+  }
+  else if(strncmp(name, "HZ", 2) == 0) {
+    idt_cpu_freq = simple_strtoul(val, 0, 10);
+    printk("CPU Clock at %d Hz (from HZ environment variable)\n",
+           idt_cpu_freq);
+  }
+  return 0;
+}
+static void prom_init_cmdline(void)
+{ 
+  memset(arcs_cmdline,0,sizeof(arcs_cmdline));
+  mapenv(&make_bootparm);
+}
+#else
+/* Kernel Boot parameters */
+//static unsigned char bootparm[]="ip=157.165.29.36:157.165.29.18::255.255.0.0::eth0";
+static unsigned char bootparm[]="console=ttyS0,9600";
+#endif
+extern unsigned long mips_machgroup;
+extern unsigned long mips_machtype;
+
+/* IDT 79EB438 memory map -- we really should be auto sizing it */
+
+#define RAM_FIRST       0x80000400  /* Leave room for interrupt vectors */
+#define RAM_SIZE        60*1024*1024
+#define RAM_END         (0x80000000 + RAM_SIZE)     
+struct resource rc32438_res_ram = {
+	"RAM",
+	0,
+	RAM_SIZE,
+	IORESOURCE_MEM
+};
+
+char * __init prom_getcmdline(void)
+{ 
+  return &(arcs_cmdline[0]);
+}
+
+
+void __init prom_init(void)
+{
+#ifdef CONFIG_IDT_BOOT_NVRAM
+	/* set up command line */
+	prom_init_cmdline();
+#else
+	sprintf(arcs_cmdline,"%s",bootparm);
+#endif
+
+	/* set our arch type */
+
+	setup_serial_port();
+
+	mips_machgroup = MACH_GROUP_IDT;
+	mips_machtype = MACH_IDT_EB438;
+
+	/*
+	 * give all RAM to boot allocator,
+	 * except where the kernel was loaded
+	 */
+	add_memory_region(0,
+			  rc32438_res_ram.end - rc32438_res_ram.start,
+			  BOOT_MEM_RAM);
+}
+
+void prom_free_prom_memory(void)
+{
+	printk("stubbed prom_free_prom_memory()\n");
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/reset.c idtlinux/arch/mips/idt-boards/rc32438/EB438/reset.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/reset.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/reset.c	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,64 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Reset EB438 board.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/irq.h>
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <linux/ioport.h>
+#include <asm/mipsregs.h>
+#include <asm/pgtable.h>
+#include <linux/mc146818rtc.h>
+#include <asm/reboot.h>
+#include <asm/addrspace.h>    
+
+extern void (*flush_cache_all)(void);
+
+void idt_reset(void)
+{
+
+  set_c0_status((ST0_BEV | ST0_ERL));
+  set_c0_config(CONF_CM_UNCACHED);
+  flush_cache_all();
+  write_c0_wired(0);
+
+  /* Errata item #13 */
+
+  *((volatile u32 *)KSEG1ADDR(0x18080000)) = 0x0;
+  *((volatile u32 *)KSEG1ADDR(0x18080018)) = 0x0;
+  *((volatile u32 *)KSEG1ADDR(0x18080024)) = 0x0;
+  *((volatile u32 *)KSEG1ADDR(0x18080030)) = 0x0;
+  *((volatile u32 *)KSEG1ADDR(0x1808003c)) = 0x0;
+
+  /* Reset*/
+  *((volatile u32 *)KSEG1ADDR(0x18008000)) = 0x80000001;
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/serial.c idtlinux/arch/mips/idt-boards/rc32438/EB438/serial.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/serial.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/serial.c	2006-03-09 16:25:49.000000000 -0800
@@ -0,0 +1,84 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Serial port initialisation.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+
+#include <asm/time.h>
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/serial.h>
+
+#include <asm/idt-boards/rc32438/rc32438.h>
+extern int __init early_serial_setup(struct uart_port *port);
+
+#define BASE_BAUD (1843200 / 16)
+
+extern unsigned int idt_cpu_freq;
+extern int __init setup_serial_port(void)
+{
+  static struct uart_port serial_req[2];
+
+  memset(serial_req, 0, sizeof(serial_req));
+  serial_req[0].type       = PORT_16550A;
+  serial_req[0].line       = 0;
+  serial_req[0].irq        = RC32438_UART0_IRQ;
+  serial_req[0].flags      = STD_COM_FLAGS;
+  serial_req[0].uartclk    = idt_cpu_freq;
+  serial_req[0].iotype     = SERIAL_IO_MEM;
+  serial_req[0].membase    = (char *) KSEG1ADDR(RC32438_UART0_BASE);
+
+  serial_req[0].mapbase   = KSEG1ADDR(RC32438_UART0_BASE);
+  serial_req[0].regshift   = 2;
+
+  serial_req[1].type       = PORT_16550A;
+  serial_req[1].line       = 1;
+  serial_req[1].irq        = RC32438_UART1_IRQ;
+  serial_req[1].flags      = STD_COM_FLAGS;
+  serial_req[1].uartclk    = idt_cpu_freq;
+  serial_req[1].iotype     = SERIAL_IO_MEM;
+  serial_req[1].membase    = (char *) KSEG1ADDR(RC32438_UART1_BASE);
+
+  serial_req[1].regshift   = 2;
+  serial_req[1].mapbase   = KSEG1ADDR(RC32438_UART1_BASE);
+
+  early_serial_setup(&serial_req[0]);
+  early_serial_setup(&serial_req[1]);
+
+  return(0);
+}
+//early_initcall(setup_serial_port);
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/serial_gdb.c idtlinux/arch/mips/idt-boards/rc32438/EB438/serial_gdb.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/serial_gdb.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/serial_gdb.c	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,272 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *      EB438 specific polling driver for 16550 UART.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ ***************************************************************************
+ */
+
+#include <linux/serial_reg.h>
+
+/* set remote gdb baud rate at 115200 */
+
+#define GDB_BAUD 115200
+#define CONS_BAUD 9600
+
+extern unsigned int idt_cpu_freq;
+
+
+/* turn this on to watch the debug protocol echoed on the console port */
+#undef DEBUG_REMOTE_DEBUG
+
+#ifdef __MIPSEB__
+#define CONS_PORT 0xb8050003u
+#define GDB_PORT  0xb8050023u
+#else
+#define CONS_PORT 0xb8050000u
+#define GDB_PORT  0xb8050020u
+#endif
+           
+volatile unsigned char *ports[2] = {
+	(volatile unsigned char *)CONS_PORT,
+	(volatile unsigned char *)GDB_PORT
+};
+
+
+void reset_gdb_port(void);
+void cons_putc(char c);
+int port_getc(int port);
+void port_putc(int port, char c);
+
+int cons_getc(void)
+{
+	return port_getc(0);
+}
+
+void cons_putc(char c)
+{
+	port_putc(0, c);
+}
+
+void cons_puts(char *s)
+{
+	while(*s) {
+		if(*s == '\n') cons_putc('\r');
+		cons_putc(*s);
+		s++;
+	}
+}
+
+void cons_do_putn(int n)
+{
+	if(n) {
+		cons_do_putn(n / 10);
+		cons_putc(n % 10 + '0');
+	}
+}
+
+void cons_putn(int n)
+{
+	if(n < 0) {
+		cons_putc('-');
+		n = -n;
+	}
+
+	if (n == 0) {
+		cons_putc('0');
+	} else {
+		cons_do_putn(n);
+	}
+}
+
+#ifdef DEBUG_REMOTE_DEBUG
+static enum {HUH, SENDING, GETTING} state;
+
+static void sent(int c)
+{
+	switch(state) {
+	case HUH:
+	case GETTING:
+		cons_puts("\nSNT ");
+		state = SENDING;
+		/* fall through */
+	case SENDING:
+		cons_putc(c);
+		break;
+	}       
+}
+
+static void got(int c)
+{
+	switch(state) {
+	case HUH:
+	case SENDING:
+		cons_puts("\nGOT ");
+		state = GETTING;
+		/* fall through */
+	case GETTING:
+		cons_putc(c);
+		break;
+	}       
+}
+#endif /* DEBUG_REMOTE_DEBUG */
+
+static int first = 1;
+
+int getDebugChar(void)
+{
+	int c;
+
+	if(first) reset_gdb_port();
+
+	c = port_getc(1);
+
+#ifdef DEBUG_REMOTE_DEBUG
+	got(c);
+#endif
+
+	return c;
+}
+
+int port_getc(int p)
+{
+	volatile unsigned char *port = ports[p];
+	int c;
+
+	while((*(port + UART_LSR * 4) & UART_LSR_DR) == 0) {
+		continue;
+	}       	
+
+	c = *(port + UART_RX * 4);
+
+	return c;
+}
+
+int port_getc_ready(int p)
+{
+	volatile unsigned char *port = ports[p];
+
+	return *(port + UART_LSR * 4) & UART_LSR_DR;
+}
+
+int isDebugReady(void)
+{
+	return port_getc_ready(1);
+}
+
+void putDebugChar(char c)
+{
+	if(first) reset_gdb_port();
+
+#ifdef DEBUG_REMOTE_DEBUG
+	sent(c);
+#endif
+
+	port_putc(1, c);
+}
+
+#define OK_TO_XMT (UART_LSR_TEMT | UART_LSR_THRE)
+
+void port_putc(int p, char c)
+{
+	volatile unsigned char *port = ports[p];
+	volatile unsigned char *lsr = port + UART_LSR * 4;
+
+	while((*lsr & OK_TO_XMT) != OK_TO_XMT) {
+		continue;
+	}
+
+	*(port + UART_TX * 4) = c;
+}
+
+void reset_gdb_port(void)
+{
+	volatile unsigned char *port = ports[1];
+	unsigned int DIVISOR = (idt_cpu_freq / 16 / GDB_BAUD);
+
+	first = 0;
+
+#ifdef DEBUG_REMOTE_DEBUG
+	cons_puts("reset_gdb_port: initializing remote debug serial port (internal UART 1, ");
+	cons_putn(GDB_BAUD);
+	cons_puts("baud, MHz=");
+	cons_putn(idt_cpu_freq);
+	cons_puts(", divisor=");
+	cons_putn(DIVISOR);
+	cons_puts(")\n");
+#endif
+
+	/* reset the port */
+	*(port + UART_CSR * 4) = 0;
+
+	/* clear and enable the FIFOs */
+	*(port + UART_FCR * 4) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | 
+		UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;
+
+	/* set the baud rate */
+	*(port + UART_LCR * 4) = UART_LCR_DLAB;		/* enable DLL, DLM registers */
+	*(port + UART_DLL * 4) = DIVISOR;
+	*(port + UART_DLM * 4) = DIVISOR >> 8;
+
+	/* set the line control stuff and disable DLL, DLM regs */
+
+	*(port + UART_LCR * 4) = UART_LCR_STOP | 	/* 2 stop bits */
+		UART_LCR_WLEN8;				/* 8 bit word length */
+	
+	/* leave interrupts off */
+	*(port + UART_IER * 4) = 0;
+
+	/* the modem controls don't leave the chip on this port, so leave them alone */
+	*(port + UART_MCR * 4) = 0;
+}
+
+void reset_cons_port(void)
+{
+	volatile unsigned char *port = ports[0];
+	  unsigned int DIVISOR = (idt_cpu_freq / 16 / CONS_BAUD);
+
+	/* reset the port */
+	*(port + UART_CSR * 4) = 0;
+
+	/* clear and enable the FIFOs */
+	*(port + UART_FCR * 4) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | 
+		UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;
+
+	/* set the baud rate */
+	*(port + UART_LCR * 4) = UART_LCR_DLAB;		/* enable DLL, DLM registers */
+
+	*(port + UART_DLL * 4) = DIVISOR;
+	*(port + UART_DLM * 4) = DIVISOR >> 8;
+	/* set the line control stuff and disable DLL, DLM regs */
+
+	*(port + UART_LCR * 4) = UART_LCR_STOP | 	/* 2 stop bits */
+		UART_LCR_WLEN8;				/* 8 bit word length */
+	
+	/* leave interrupts off */
+	*(port + UART_IER * 4) = 0;
+
+	/* the modem controls don't leave the chip on this port, so leave them alone */
+	*(port + UART_MCR * 4) = 0;
+}
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/setup.c idtlinux/arch/mips/idt-boards/rc32438/EB438/setup.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/setup.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/setup.c	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,172 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     setup routines for IDT EB438 boards
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/pm.h>
+#include <linux/sched.h>
+#include <linux/irq.h>
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <linux/ioport.h>
+#include <asm/mipsregs.h>
+#include <asm/pgtable.h>
+#include <linux/mc146818rtc.h>
+#include <asm/reboot.h>
+#include <asm/addrspace.h>    
+#include <asm/idt-boards/rc32438/rc32438.h>
+
+extern char * __init prom_getcmdline(void);
+
+extern void (*board_time_init)(void);
+extern void (*board_timer_setup)(struct irqaction *irq);
+extern void rc32438_time_init(void);
+extern void rc32438_timer_setup(struct irqaction *irq);
+#ifdef CONFIG_RTC_DS1553
+extern unsigned long (*rtc_get_time)(void);
+extern int (*rtc_set_time)(unsigned long);
+extern unsigned long rtc_ds1553_get_time(void);
+extern int rtc_ds1553_set_time(unsigned long t);
+#endif  
+extern void idt_reset(void);
+void idt_disp_str(char *s);
+
+#define DIG_CLEAR ((volatile unsigned char *)0xAC000000)
+#define DIG0 ((volatile unsigned char *)0xAC040003)
+#define DIG1 ((volatile unsigned char *)0xAC040002)
+#define DIG2 ((volatile unsigned char *)0xAC040001)
+#define DIG3 ((volatile unsigned char *)0xAC040000)
+
+void idt_disp_char(int i, char c)
+{
+  switch(i) {
+  case 0: *DIG0 = c; break;
+  case 1: *DIG1 = c; break;
+  case 2: *DIG2 = c; break;
+  case 3: *DIG3 = c; break;
+  default: *DIG0 = '?'; break;
+  }
+}
+
+void idt_disp_str(char *s)
+{
+  if(s == 0) {
+    char c;
+    c = *DIG_CLEAR;
+  } else {
+    int i;
+    for(i = 0; i < 4; i++) {
+      if(s[i]) idt_disp_char(i, s[i]);
+    }
+  }
+}
+
+
+static void idt_machine_restart(char *command)
+{
+  printk("idt_machine_restart: command=%s\n", command);
+  
+  idt_reset();
+}
+
+static void idt_machine_halt(void)
+{
+  printk("idt_machine_halt:  halted\n");
+  for(;;) continue;
+}
+
+static void idt_machine_power_off(void)
+{
+  printk("idt_machine_power_off:  It is now safe to turn off the power\n");
+  for(;;) continue;
+}
+static int __init idt_setup(void)
+{
+  char* argptr;
+  
+  idt_disp_str("unix");
+  
+  argptr = prom_getcmdline();
+
+#ifdef CONFIG_SERIAL_CONSOLE
+  if ((argptr = strstr(argptr, "console=")) == NULL) {
+    argptr = prom_getcmdline();
+    strcat(argptr, " console=ttyS0,9600");
+  }
+#endif
+
+
+  board_time_init = rc32438_time_init;
+  board_timer_setup = rc32438_timer_setup;
+
+  
+#ifdef CONFIG_RTC_DS1553
+  rtc_get_time = rtc_ds1553_get_time;
+  rtc_set_time = rtc_ds1553_set_time;
+
+#endif  
+  _machine_restart = idt_machine_restart;
+  _machine_halt = idt_machine_halt;
+  pm_power_off = idt_machine_power_off;
+  set_io_port_base(KSEG1);
+  write_c0_wired(0);
+  return 0;
+  
+}
+
+//early_initcall(idt_setup);
+
+void __init plat_setup(void){
+  idt_setup();
+}
+
+int page_is_ram(unsigned long pagenr)
+{
+  return 1;
+}
+
+const char *get_system_type(void)
+{
+  return "MIPS IDT32438";
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/time.c idtlinux/arch/mips/idt-boards/rc32438/EB438/time.c
--- linux-2.6.16-rc5/arch/mips/idt-boards/rc32438/EB438/time.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/idt-boards/rc32438/EB438/time.c	2006-03-09 16:25:50.000000000 -0800
@@ -0,0 +1,174 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     timer routines for IDT EB438 boards
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/mc146818rtc.h>
+#include <linux/irq.h>
+#include <linux/timex.h>
+
+#include <linux/param.h>
+#include <asm/mipsregs.h>
+#include <asm/ptrace.h>
+#include <asm/time.h>
+#include <asm/hardirq.h>
+
+
+#include <asm/mipsregs.h>
+#include <asm/ptrace.h>
+#include <asm/debug.h>
+#include <asm/time.h>
+#include <asm/idt-boards/rc32438/rc32438.h>
+#include  <asm/idt-boards/rc32438/rc32438_timer.h>
+
+static unsigned long r4k_offset;
+extern unsigned int idt_cpu_freq;
+
+#if defined(CONFIG_IDT_79EB438) && defined(CONFIG_MIPS_RTC)
+extern void rtc_ds1553_init(void);
+#endif
+
+#ifdef CONFIG_RC32438_REVISION_ZA  
+/* how many counter cycles in a jiffy */
+static unsigned long cycles_per_jiffy;
+/* expirelo is the count value for next CPU timer interrupt */
+static unsigned int expirelo;
+
+
+static void idt_timer_ack(void)
+{
+	unsigned int count ;
+        count = idttimer->tim[0].count;
+        idttimer->tim[0].compare = (count + cycles_per_jiffy);
+        idttimer->tim[0].ctc =  0x1;
+}
+
+static unsigned int idt_hpt_read(void)
+{
+	return idttimer->tim[0].count;
+}
+
+
+static void idt_hpt_timer_init(unsigned int count)
+{
+        count = idttimer->tim[0].count - count;
+        expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
+        idttimer->tim[0].count = (expirelo - cycles_per_jiffy);
+        idttimer->tim[0].compare = expirelo;
+        idttimer->tim[0].count = count;
+}
+#endif
+
+static unsigned long __init cal_r4koff(void)
+{
+	mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
+	return (mips_hpt_frequency / HZ);
+}
+
+void __init rc32438_time_init(void)
+{
+        unsigned int est_freq, flags;
+
+	local_irq_save(flags);
+
+	printk("calculating r4koff... ");
+	r4k_offset = cal_r4koff();
+	printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
+
+	est_freq = 2*r4k_offset*HZ;	
+	est_freq += 5000;    /* round */
+	est_freq -= est_freq%10000;
+	printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, 
+	       (est_freq%1000000)*100/1000000);
+
+#ifdef CONFIG_RC32438_REVISION_ZA
+	printk("Enabling workaround for ZA part.\n");
+	cycles_per_jiffy = (mips_hpt_frequency + HZ / 2) / HZ;
+	mips_hpt_read = idt_hpt_read;
+	mips_hpt_init = idt_hpt_timer_init;
+	mips_timer_ack = idt_timer_ack;
+#endif	
+#if defined(CONFIG_IDT_79EB438) && defined(CONFIG_MIPS_RTC)
+	rtc_ds1553_init();
+#endif
+	local_irq_restore(flags);
+
+}
+
+void __init rc32438_timer_setup(struct irqaction *irq)
+{
+#ifdef CONFIG_RC32438_REVISION_ZA
+        setup_irq(8, irq);
+        idttimer->tim[0].count = 0;
+        idttimer->tim[0].compare = cycles_per_jiffy;
+        idttimer->tim[0].ctc = 0x1;
+#else
+	static unsigned long r4k_cur; 
+	setup_irq(MIPS_CPU_TIMER_IRQ, irq);
+  
+	/* to generate the first timer interrupt */
+	r4k_cur = (read_c0_count() + r4k_offset);
+	write_c0_compare(r4k_cur);
+#endif
+  
+}
+
+extern void idt_disp_char(int i,char c);
+
+asmlinkage void idt_timer_interrupt(int irq,struct pt_regs *regs)
+{
+#ifdef CONFIG_KGDB
+	void kgdb_check(void);
+#endif
+
+	static unsigned int timerCount = 0;
+	static int toggle = 0;
+
+	irq_enter();
+	kstat_this_cpu.irqs[irq]++;
+
+	if( (timerCount++ % HZ) == 0)
+	{ 
+		toggle ^= 1;
+		idt_disp_char(0,toggle ? 'u' :'U');
+	}
+	timer_interrupt(irq, NULL, regs);
+
+	irq_exit();
+
+#ifdef CONFIG_KGDB
+	kgdb_check();
+#endif
+}
+
+
diff -uNr linux-2.6.16-rc5/arch/mips/Kconfig idtlinux/arch/mips/Kconfig
--- linux-2.6.16-rc5/arch/mips/Kconfig	2006-02-27 02:56:56.000000000 -0800
+++ idtlinux/arch/mips/Kconfig	2006-03-09 16:25:51.000000000 -0800
@@ -210,6 +210,15 @@
 	  located at <http://www.globespan.net/>. Say Y here if you wish to
 	  build a kernel for this platform.
 
+config IDT_BOARDS
+        bool "Support for IDT evaluation boards"
+        help
+         IDT evaluation boards for the Interprise family of Integrated Processors
+         based on the 4KC and RC32300 MIPS Core.
+	 
+	 More information can be found at <http://www.idt.com/?catID=58532>
+
+
 config MIPS_ITE8172
 	bool "Support for ITE 8172G board"
 	select DMA_NONCOHERENT
@@ -787,6 +796,8 @@
 source "arch/mips/tx4938/Kconfig"
 source "arch/mips/vr41xx/Kconfig"
 source "arch/mips/philips/pnx8550/common/Kconfig"
+source "arch/mips/idt-boards/Kconfig"
+
 
 endmenu
 
@@ -1119,6 +1130,13 @@
 	  might be a safe bet.  If the resulting kernel does not work,
 	  try to recompile with R3000.
 
+config CPU_RC32300
+        bool "RC32300"
+	select CPU_HAS_PREFETCH
+	select CPU_SUPPORTS_32BIT_KERNEL
+        help
+          IDT Chronus core
+
 config CPU_TX39XX
 	bool "R39XX"
 	depends on SYS_HAS_CPU_TX39XX
diff -uNr linux-2.6.16-rc5/arch/mips/kernel/cpu-probe.c idtlinux/arch/mips/kernel/cpu-probe.c
--- linux-2.6.16-rc5/arch/mips/kernel/cpu-probe.c	2006-02-27 02:56:56.000000000 -0800
+++ idtlinux/arch/mips/kernel/cpu-probe.c	2006-03-09 16:25:44.000000000 -0800
@@ -113,6 +113,7 @@
 	case CPU_RM7000:
 	case CPU_RM9000:
 	case CPU_TX49XX:
+	case CPU_RC32300:
 	case CPU_4KC:
 	case CPU_4KEC:
 	case CPU_4KSC:
@@ -221,6 +222,18 @@
 			c->options |= MIPS_CPU_FPU;
 		c->tlbsize = 64;
 		break;
+
+	case PRID_IMP_RC32334:
+	case PRID_IMP_RC32355:  
+                c->cputype = CPU_RC32300;
+		c->isa_level = MIPS_CPU_ISA_II;
+		c->options = R4K_OPTS | MIPS_CPU_DIVEC | MIPS_CPU_WATCH | MIPS_CPU_LLSC;
+		c->tlbsize = 16;
+		c->icache.ways = 2;
+		c->dcache.ways = 2;
+		c->scache.flags = MIPS_CACHE_NOT_PRESENT;
+		break;
+
 	case PRID_IMP_R4000:
 		if (read_c0_config() & CONF_SC) {
 			if ((c->processor_id & 0xff) >= PRID_REV_R4400)
diff -uNr linux-2.6.16-rc5/arch/mips/kernel/Makefile idtlinux/arch/mips/kernel/Makefile
--- linux-2.6.16-rc5/arch/mips/kernel/Makefile	2006-02-27 02:56:56.000000000 -0800
+++ idtlinux/arch/mips/kernel/Makefile	2006-03-09 16:25:44.000000000 -0800
@@ -16,6 +16,7 @@
 obj-$(CONFIG_CPU_R3000)		+= r2300_fpu.o r2300_switch.o
 obj-$(CONFIG_CPU_TX39XX)	+= r2300_fpu.o r2300_switch.o
 obj-$(CONFIG_CPU_TX49XX)	+= r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_RC32300)       += r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_R4000)		+= r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_VR41XX)	+= r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_R4300)		+= r4k_fpu.o r4k_switch.o
diff -uNr linux-2.6.16-rc5/arch/mips/lib-32/Makefile idtlinux/arch/mips/lib-32/Makefile
--- linux-2.6.16-rc5/arch/mips/lib-32/Makefile	2006-02-27 02:56:56.000000000 -0800
+++ idtlinux/arch/mips/lib-32/Makefile	2006-03-09 16:25:44.000000000 -0800
@@ -9,6 +9,7 @@
 obj-$(CONFIG_CPU_NEVADA)	+= dump_tlb.o
 obj-$(CONFIG_CPU_R10000)	+= dump_tlb.o
 obj-$(CONFIG_CPU_R3000)		+= r3k_dump_tlb.o
+obj-$(CONFIG_CPU_RC32300)       += dump_tlb.o
 obj-$(CONFIG_CPU_R4300)		+= dump_tlb.o
 obj-$(CONFIG_CPU_R4X00)		+= dump_tlb.o
 obj-$(CONFIG_CPU_R5000)		+= dump_tlb.o
diff -uNr linux-2.6.16-rc5/arch/mips/Makefile idtlinux/arch/mips/Makefile
--- linux-2.6.16-rc5/arch/mips/Makefile	2006-02-27 02:56:56.000000000 -0800
+++ idtlinux/arch/mips/Makefile	2006-03-09 16:25:53.000000000 -0800
@@ -200,6 +200,11 @@
 			-Wa,--trap
 CHECKFLAGS-$(CONFIG_CPU_TX49XX)	+= -D_MIPS_ISA=_MIPS_ISA_MIPS3
 
+cflags-$(CONFIG_CPU_RC32300)	+= \
+			$(call set_gccflags,mips2,mips2,mips2) \
+			-Wa,--trap
+CHECKFLAGS-$(CONFIG_CPU_RC32300)	+= -D_MIPS_ISA=_MIPS_ISA_MIPS2
+
 cflags-$(CONFIG_CPU_MIPS32_R1)	+= \
 			$(call set_gccflags,mips32,mips32,r4600,mips3,mips2) \
 			-Wa,--trap
@@ -739,6 +744,51 @@
 core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/common/
 load-$(CONFIG_TOSHIBA_RBTX4938) += 0xffffffff80100000
 
+
+
+
+#
+# IDT EB438 board
+#
+core-$(CONFIG_IDT_EB438)	+= arch/mips/idt-boards/rc32438/EB438/
+cflags-$(CONFIG_IDT_EB438)	+= -Iinclude/asm-mips/mach-idt
+load-$(CONFIG_IDT_EB438)	+= 0x80100000
+
+#
+# IDT EB434/435 board
+#
+core-$(CONFIG_IDT_EB434)	+= arch/mips/idt-boards/rc32434/EB434/
+cflags-$(CONFIG_IDT_EB434)	+= -Iinclude/asm-mips/mach-idt
+load-$(CONFIG_IDT_EB434)	+= 0x80100000
+
+#
+# IDT EB365/336 board
+#
+core-$(CONFIG_IDT_EB365)        += arch/mips/idt-boards/rc32300/EB365/
+cflags-$(CONFIG_IDT_EB365)      += -Iinclude/asm-mips/mach-idt
+load-$(CONFIG_IDT_EB365)        += 0x80100000
+
+#
+# IDT EB355 board
+#
+core-$(CONFIG_IDT_EB355)	+= arch/mips/idt-boards/rc32300/EB355/
+cflags-$(CONFIG_IDT_EB355)	+= -Iinclude/asm-mips/mach-idt
+load-$(CONFIG_IDT_EB355)	+= 0x80100000
+
+#
+# IDT S334 board
+#
+core-$(CONFIG_IDT_S334)		+= arch/mips/idt-boards/rc32300/S334/
+cflags-$(CONFIG_IDT_S334)	+= -Iinclude/asm-mips/mach-idt
+load-$(CONFIG_IDT_S334)		+= 0x80100000
+
+
+
+
+
+
+
+
 cflags-y			+= -Iinclude/asm-mips/mach-generic
 drivers-$(CONFIG_PCI)		+= arch/mips/pci/
 
@@ -794,6 +844,27 @@
 vmlinux.32: vmlinux
 	$(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
 
+ifdef CONFIG_IDT_BOARDS
+zImage rImage: vmlinux $(TOPDIR)/.config
+ifdef CONFIG_IDT_EB438
+	$(Q)$(MAKE) $(build)=arch/mips/idt-boards/rc32438/EB438/boot $@
+endif
+
+ifdef CONFIG_IDT_EB434
+	$(Q)$(MAKE) $(build)=arch/mips/idt-boards/rc32434/EB434/boot $@
+endif
+ifdef CONFIG_IDT_EB365
+	$(Q)$(MAKE) $(build)=arch/mips/idt-boards/rc32300/EB365/boot $@
+endif
+ifdef CONFIG_IDT_EB355
+	$(Q)$(MAKE) $(build)=arch/mips/idt-boards/rc32300/EB355/boot $@
+endif
+
+ifdef CONFIG_IDT_S334
+	$(Q)$(MAKE) $(build)=arch/mips/idt-boards/rc32300/S334/boot $@
+endif
+endif
+
 #
 # The 64-bit ELF tools are pretty broken so at this time we generate 64-bit
 # ELF files from 32-bit files by conversion.
diff -uNr linux-2.6.16-rc5/arch/mips/mm/c-r4k.c idtlinux/arch/mips/mm/c-r4k.c
--- linux-2.6.16-rc5/arch/mips/mm/c-r4k.c	2006-02-27 02:56:56.000000000 -0800
+++ idtlinux/arch/mips/mm/c-r4k.c	2006-03-09 16:25:53.000000000 -0800
@@ -732,6 +732,20 @@
 	unsigned int lsize;
 
 	switch (c->cputype) {
+	case CPU_RC32300:
+	        icache_size = 1 << (9 + ((config & CONF_IC) >> 9));
+                c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
+                c->icache.ways = 2;
+                c->icache.waybit = ffs(icache_size/2) - 1;
+
+                dcache_size = 1 << (9 + ((config & CONF_DC) >> 6));
+                c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
+                c->dcache.ways = 2;
+                c->dcache.waybit = 12;
+
+                c->options |= MIPS_CPU_CACHE_CDEX_P;
+                break;
+
 	case CPU_R4600:			/* QED style two way caches? */
 	case CPU_R4700:
 	case CPU_R5000:
diff -uNr linux-2.6.16-rc5/arch/mips/mm/Makefile idtlinux/arch/mips/mm/Makefile
--- linux-2.6.16-rc5/arch/mips/mm/Makefile	2006-02-27 02:56:56.000000000 -0800
+++ idtlinux/arch/mips/mm/Makefile	2006-03-09 16:25:53.000000000 -0800
@@ -26,6 +26,7 @@
 obj-$(CONFIG_CPU_TX39XX)	+= c-tx39.o pg-r4k.o tlb-r3k.o
 obj-$(CONFIG_CPU_TX49XX)	+= c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
 obj-$(CONFIG_CPU_VR41XX)	+= c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
+obj-$(CONFIG_CPU_RC32300)	+= c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
 
 obj-$(CONFIG_IP22_CPU_SCACHE)	+= sc-ip22.o
 obj-$(CONFIG_R5000_CPU_SCACHE)  += sc-r5k.o
diff -uNr linux-2.6.16-rc5/arch/mips/mm/tlbex.c idtlinux/arch/mips/mm/tlbex.c
--- linux-2.6.16-rc5/arch/mips/mm/tlbex.c	2006-02-27 02:56:56.000000000 -0800
+++ idtlinux/arch/mips/mm/tlbex.c	2006-03-09 16:25:52.000000000 -0800
@@ -818,6 +818,7 @@
 	case CPU_R4400PC:
 	case CPU_R4400SC:
 	case CPU_R4400MC:
+	case CPU_RC32300:  
 		/*
 		 * This branch uses up a mtc0 hazard nop slot and saves
 		 * two nops after the tlbw instruction.
diff -uNr linux-2.6.16-rc5/arch/mips/pci/fixup-rc32334.c idtlinux/arch/mips/pci/fixup-rc32334.c
--- linux-2.6.16-rc5/arch/mips/pci/fixup-rc32334.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/pci/fixup-rc32334.c	2006-03-09 16:25:52.000000000 -0800
@@ -0,0 +1,102 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     PCI fixups for IDT S334 board
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+
+#include <asm/mipsregs.h>
+
+#include <asm/idt-boards/rc32300/rc32300.h>
+#include <asm/idt-boards/rc32300/rc32334.h>
+
+extern void rc32300_ack_irq(unsigned int irq_nr);
+
+void __init pcibios_fixup_resources(struct pci_dev *dev)
+{
+}
+
+extern void __init pcibios_fixup(void)
+{
+	// ack any bus errors
+	
+	rc32300_ack_irq(GROUP4_IRQ_BASE+4); // ack timer 4 rollover intr
+	rc32300_ack_irq(GROUP4_IRQ_BASE+5); // ack timer 5 rollover intr
+	rc32300_ack_irq(GROUP1_IRQ_BASE);   // ack bus error intr
+	
+	/*
+	 * Enable CPU and IP Bus Error exceptions, and disable WatchDog.
+	 */
+	rc32300_writel(0x18, CPU_IP_BUSERR_CNTL);
+}
+
+int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+	
+	if (dev->bus->number != 0) {
+		return 0;
+	}
+	
+	slot = PCI_SLOT(dev->devfn);
+	dev->irq = 0;
+	
+	if (slot > 0 && slot <= 4) {
+		unsigned char pin;
+		pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
+		
+		switch (pin) {
+		case 1: /* pin A */
+			dev->irq = RC32334_PCI_INTA_IRQ;
+			break;
+		case 2: /* pin B */
+			dev->irq = RC32334_PCI_INTB_IRQ;
+			break;
+		case 3: /* pin C */
+			dev->irq = RC32334_PCI_INTC_IRQ;
+			break;
+		case 4: /* pin D */
+			dev->irq = RC32334_PCI_INTD_IRQ;
+			break;
+		default:
+			dev->irq = 0xff;
+			break;
+		}
+#ifdef DEBUG
+		printk("irq fixup: slot %d, pin %d, irq %d\n",
+		       slot, pin, dev->irq);
+#endif
+		pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
+				      dev->irq);
+	}
+	return(dev->irq);
+}
+struct pci_fixup pcibios_fixups[] = {
+	{0}
+};
diff -uNr linux-2.6.16-rc5/arch/mips/pci/fixup-rc32365.c idtlinux/arch/mips/pci/fixup-rc32365.c
--- linux-2.6.16-rc5/arch/mips/pci/fixup-rc32365.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/pci/fixup-rc32365.c	2006-03-09 16:25:52.000000000 -0800
@@ -0,0 +1,124 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     PCI fixups for IDT EB365 board
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/idt-boards/rc32300/rc32300.h>
+#include <asm/idt-boards/rc32300/rc32365.h>
+
+int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+
+    if (dev->bus->number != 0) {
+      return 0;
+    }
+    
+    slot = PCI_SLOT(dev->devfn);
+    dev->irq = 0;
+
+    if (slot >= 2 && slot <= 4) {
+      pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
+      switch (slot) {
+      case 2: /* first SLOT*/
+	switch (pin) {
+	case 1: /* INTA*/
+	  dev->irq = RC32365_PCI_INTB_IRQ;
+	  break;
+	case 2: /* INTB */
+	  dev->irq = RC32365_PCI_INTC_IRQ;
+	  break;
+	case 3: /* INTC */
+	  dev->irq = RC32365_PCI_INTD_IRQ;
+	  break;
+	case 4: /* INTD */
+	  dev->irq = RC32365_PCI_INTA_IRQ;
+	  break;
+	default:
+	  dev->irq = 0xff; 
+	  break;
+	}
+	break;
+	
+      case 3: /* second SLOT */
+	switch (pin) {
+	case 1: /* INTA*/
+	  dev->irq = RC32365_PCI_INTC_IRQ;
+	  break;
+	case 2: /* INTB */
+	  dev->irq = RC32365_PCI_INTD_IRQ;
+	  break;
+	case 3: /* INTC */
+	  dev->irq = RC32365_PCI_INTA_IRQ;
+	  break;
+	case 4: /* INTD */
+	  dev->irq = RC32365_PCI_INTB_IRQ;
+	  break;
+	default:
+	  dev->irq = 0xff; 
+	  break;
+	}
+	break;
+	
+      case 4: /* miniPCI SLOT */
+	switch (pin) {
+	case 1: /* INTA*/
+	  dev->irq = RC32365_PCI_INTA_IRQ;
+	  break;
+	case 2: /* INTB */
+	  dev->irq = RC32365_PCI_INTB_IRQ;
+	  break;
+	case 3: /* INTC */
+	  dev->irq = RC32365_PCI_INTC_IRQ;
+	  break;
+	case 4: /* INTD */
+	  dev->irq = RC32365_PCI_INTD_IRQ;
+	  break;
+	default:
+	  dev->irq = 0xff; 
+	  break;
+	}
+	break;
+      
+#ifdef DEBUG
+      printk("irq fixup: slot %d, pin %d, irq %d\n",
+	     slot, pin, dev->irq);
+#endif
+      pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+      }
+    }
+    return(dev->irq);
+}
+struct pci_fixup pcibios_fixups[] __initdata  = {
+  {0}
+};
diff -uNr linux-2.6.16-rc5/arch/mips/pci/fixup-rc32434.c idtlinux/arch/mips/pci/fixup-rc32434.c
--- linux-2.6.16-rc5/arch/mips/pci/fixup-rc32434.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/pci/fixup-rc32434.c	2006-03-09 16:25:51.000000000 -0800
@@ -0,0 +1,93 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     PCI fixups for IDT EB434/435 board
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <asm/idt-boards/rc32434/rc32434.h>
+#include <asm/idt-boards/rc32434/rc32434_pci.h> 
+
+int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+	
+	if (dev->bus->number != 0) {
+		return 0;
+	}
+	
+	slot = PCI_SLOT(dev->devfn);
+	dev->irq = 0;
+	
+	if (slot > 0 && slot <= 5) {
+		unsigned char pin;
+		pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
+		
+		switch (pin) {
+		case 1: /* INTA*/
+			dev->irq = GROUP4_IRQ_BASE + 11;
+			break;
+		case 2: /* INTB */
+			dev->irq = GROUP4_IRQ_BASE + 11;
+			break;
+		case 3: /* INTC */
+			dev->irq = GROUP4_IRQ_BASE + 11;
+			break;
+		case 4: /* INTD */
+			dev->irq = GROUP4_IRQ_BASE + 11;
+			break;
+		default:
+			dev->irq = 0xff; 
+			break;
+		}
+#ifdef DEBUG
+		printk("irq fixup: slot %d, pin %d, irq %d\n",
+		       slot, pin, dev->irq);
+#endif
+		pci_write_config_byte(dev, PCI_INTERRUPT_LINE,dev->irq);
+	}
+	return (dev->irq);
+}
+
+struct pci_fixup pcibios_fixups[] = {
+	{0}
+};
+
+
+
+
+
+
+
+
+
+
+
diff -uNr linux-2.6.16-rc5/arch/mips/pci/fixup-rc32438.c idtlinux/arch/mips/pci/fixup-rc32438.c
--- linux-2.6.16-rc5/arch/mips/pci/fixup-rc32438.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/pci/fixup-rc32438.c	2006-03-09 16:25:51.000000000 -0800
@@ -0,0 +1,84 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     PCI fixups for IDT EB438 board
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/idt-boards/rc32438/rc32438.h>
+#include <asm/idt-boards/rc32438/rc32438_pci.h>
+#include <asm/idt-boards/rc32438/rc32438_pci_v.h>
+
+int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+
+  if (dev->bus->number != 0) {
+    return 0;
+  }
+
+  slot = PCI_SLOT(dev->devfn);
+  dev->irq = 0;
+
+  if (slot > 0 && slot <= 5) {
+    unsigned char pin;
+    pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
+
+    switch (pin) {
+    case 1: /* INTA*/
+      dev->irq = GROUP4_IRQ_BASE + 27;
+      break;
+    case 2: /* INTB */
+      dev->irq = GROUP4_IRQ_BASE + 27;
+      break;
+    case 3: /* INTC */
+      dev->irq = GROUP4_IRQ_BASE + 27;
+      break;
+    case 4: /* INTD */
+      dev->irq = GROUP4_IRQ_BASE + 27;
+      break;
+    default:
+      dev->irq = 0xff; 
+      break;
+    }
+#ifdef DEBUG
+    printk("irq fixup: slot %d, pin %d, irq %d\n",
+	   slot, pin, dev->irq);
+#endif
+    pci_write_config_byte(dev, PCI_INTERRUPT_LINE,dev->irq);
+  }
+  return (dev->irq);
+}
+
+struct pci_fixup pcibios_fixups[] = {
+  {0}
+};
diff -uNr linux-2.6.16-rc5/arch/mips/pci/Makefile idtlinux/arch/mips/pci/Makefile
--- linux-2.6.16-rc5/arch/mips/pci/Makefile	2006-02-27 02:56:56.000000000 -0800
+++ idtlinux/arch/mips/pci/Makefile	2006-03-09 16:25:52.000000000 -0800
@@ -57,3 +57,8 @@
 obj-$(CONFIG_TOSHIBA_RBTX4938)	+= fixup-tx4938.o ops-tx4938.o
 obj-$(CONFIG_VICTOR_MPC30X)	+= fixup-mpc30x.o
 obj-$(CONFIG_ZAO_CAPCELLA)	+= fixup-capcella.o
+
+obj-$(CONFIG_IDT_EB438)         += pci-rc32438.o ops-rc32438.o fixup-rc32438.o
+obj-$(CONFIG_IDT_EB434)         += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
+obj-$(CONFIG_IDT_EB365)         += pci-rc32365.o ops-rc32365.o fixup-rc32365.o
+obj-$(CONFIG_IDT_S334)          += pci-rc32334.o ops-rc32334.o fixup-rc32334.o
diff -uNr linux-2.6.16-rc5/arch/mips/pci/ops-rc32334.c idtlinux/arch/mips/pci/ops-rc32334.c
--- linux-2.6.16-rc5/arch/mips/pci/ops-rc32334.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/pci/ops-rc32334.c	2006-03-09 16:25:51.000000000 -0800
@@ -0,0 +1,184 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     pci_ops for IDT S334 board
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+
+#include <asm/cpu.h>
+#include <asm/io.h>
+
+#include <asm/idt-boards/rc32300/rc32300.h>
+#include <asm/idt-boards/rc32300/rc32334.h>
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+#define PCI_CFG_SET(slot,func,off) \
+        rc32300_writel((0x80000000 | ((slot)<<11) | ((func)<<8) | (off)), \
+                       PCI_CFG_CNTL)
+
+static int config_access(unsigned char access_type, struct pci_bus *bus,
+                         unsigned int devfn, unsigned char where,
+                         u32 * data)
+{
+	/* 
+	 * config cycles are on 4 byte boundary only
+	 */
+	unsigned int slot = PCI_SLOT(devfn);
+	u8 func = PCI_FUNC(devfn);
+	
+	if ( slot <2 || slot > 4) {
+		*data = 0xFFFFFFFF;
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	}
+	
+	/* Setup address */
+	PCI_CFG_SET(slot, func, where);
+	rc32300_sync();
+	
+	if (access_type == PCI_ACCESS_WRITE)
+		rc32300_writel(*data, PCI_CFG_DATA);
+	else
+		*data = rc32300_readl(PCI_CFG_DATA);
+	
+	return 0;
+}
+
+/*
+ * We can't address 8 and 16 bit words directly.  Instead we have to
+ * read/write a 32bit word and mask/modify the data we actually want.
+ */
+static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
+                            int where, u8 * val)
+{
+	u32 data;
+	int ret;
+	
+	ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
+	*val = (data >> ((where & 3) << 3)) & 0xff;
+	return ret;
+}
+
+static int read_config_word(struct pci_bus *bus, unsigned int devfn,
+                            int where, u16 * val)
+{
+	u32 data;
+	int ret;
+	
+	ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
+	*val = (data >> ((where & 3) << 3)) & 0xffff;
+	return ret;
+}
+
+static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
+                             int where, u32 * val)
+{
+	int ret;
+	
+	ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
+	return ret;
+}
+static int write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
+                  u8 val)
+{
+	u32 data = 0;
+	
+	if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+		return -1;
+	
+	data = (data & ~(0xff << ((where & 3) << 3))) |
+		(val << ((where & 3) << 3));
+	
+	if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
+		return -1;
+	
+	return PCIBIOS_SUCCESSFUL;
+}
+static int write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
+                  u16 val)
+{
+	u32 data = 0;
+	
+	if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+		return -1;
+	
+	data = (data & ~(0xffff << ((where & 3) << 3))) |
+		(val << ((where & 3) << 3));
+	
+	if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
+		return -1;
+	
+	
+	return PCIBIOS_SUCCESSFUL;
+}
+static int write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
+                   u32 val)
+{
+	if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
+		return -1;
+	
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
+			   int where, int size, u32 * val)
+{
+	switch (size) {
+	case 1: 
+		return read_config_byte(bus, devfn, where, (u8 *) val);
+	case 2: 
+		return read_config_word(bus, devfn, where, (u16 *) val);
+	default:
+		return read_config_dword(bus, devfn, where, val);
+	}
+}
+
+static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
+			    int where, int size, u32 val)
+{
+	switch (size) {
+	case 1: 
+		return write_config_byte(bus, devfn, where, (u8) val);
+	case 2: 
+		return write_config_word(bus, devfn, where, (u16) val);
+	default:
+		return write_config_dword(bus, devfn, where, val);
+	}
+}
+
+struct pci_ops rc32334_pci_ops = {
+	.read =  pci_config_read,
+	.write = pci_config_write,
+};
+
diff -uNr linux-2.6.16-rc5/arch/mips/pci/ops-rc32365.c idtlinux/arch/mips/pci/ops-rc32365.c
--- linux-2.6.16-rc5/arch/mips/pci/ops-rc32365.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/pci/ops-rc32365.c	2006-03-09 16:25:52.000000000 -0800
@@ -0,0 +1,189 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     pci_ops for IDT EB365 board
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/idt-boards/rc32300/rc32300.h>
+#include <asm/idt-boards/rc32300/rc32365_pci.h>
+#include <asm/idt-boards/rc32300/rc32365_pci_v.h>
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+#define PCI_CFG_SET(slot,func,off) \
+	(rc32365_pci->pcicfga = (0x80000000 | ((slot) << 11) | \
+			    ((func) << 8) | (off)))
+static int config_access(unsigned char access_type, struct pci_bus *bus,
+                         unsigned int devfn, unsigned char where,
+                         u32 * data)
+{
+  /* 
+   * config cycles are on 4 byte boundary only
+   */
+  unsigned int slot = PCI_SLOT(devfn);
+  u8 func = PCI_FUNC(devfn);
+
+  if (slot < 2 || slot > 5) {
+    *data = 0xFFFFFFFF;
+    return -1;
+  }
+  /* Setup address */
+  PCI_CFG_SET(slot, func, where);
+  rc32300_sync();
+  
+  if (access_type == PCI_ACCESS_WRITE)
+    rc32365_pci->pcicfgd = *data;
+  
+  else
+    *data = rc32365_pci->pcicfgd;
+  
+  rc32300_sync();
+
+  /*
+   * Revisit: check for master or target abort.
+   */
+  return 0;
+}
+
+/*
+ * We can't address 8 and 16 bit words directly.  Instead we have to
+ * read/write a 32bit word and mask/modify the data we actually want.
+ */
+static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
+                            int where, u8 * val)
+{
+  u32 data;
+  int ret;
+
+  ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
+  *val = (data >> ((where & 3) << 3)) & 0xff;
+  return ret;
+}
+
+static int read_config_word(struct pci_bus *bus, unsigned int devfn,
+                            int where, u16 * val)
+{
+  u32 data;
+  int ret;
+
+  ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
+  *val = (data >> ((where & 3) << 3)) & 0xffff;
+  return ret;
+}
+
+static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
+                             int where, u32 * val)
+{
+  int ret;
+
+  ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
+  return ret;
+}
+static int
+write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
+                  u8 val)
+{
+  u32 data = 0;
+
+  if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+    return -1;
+
+  data = (data & ~(0xff << ((where & 3) << 3))) |
+    (val << ((where & 3) << 3));
+
+  if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
+    return -1;
+
+  return PCIBIOS_SUCCESSFUL;
+}
+static int
+write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
+                  u16 val)
+{
+  u32 data = 0;
+
+  if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+    return -1;
+
+  data = (data & ~(0xffff << ((where & 3) << 3))) |
+    (val << ((where & 3) << 3));
+
+  if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
+    return -1;
+
+
+  return PCIBIOS_SUCCESSFUL;
+}
+static int
+write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
+                   u32 val)
+{
+  if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
+    return -1;
+
+  return PCIBIOS_SUCCESSFUL;
+}
+
+static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
+                       int where, int size, u32 * val)
+{
+   switch (size) {
+  case 1: 
+   return read_config_byte(bus, devfn, where, (u8 *) val);
+  case 2: 
+    return read_config_word(bus, devfn, where, (u16 *) val);
+  default:
+    return read_config_dword(bus, devfn, where, val);
+  }
+}
+
+static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
+                        int where, int size, u32 val)
+{
+  switch (size) {
+  case 1: 
+    return write_config_byte(bus, devfn, where, (u8) val);
+  case 2: 
+    return write_config_word(bus, devfn, where, (u16) val);
+  default:
+    return write_config_dword(bus, devfn, where, val);
+  }
+}
+
+struct pci_ops rc32365_pci_ops = {
+  .read =  pci_config_read,
+  .write = pci_config_write,
+};
+
diff -uNr linux-2.6.16-rc5/arch/mips/pci/ops-rc32434.c idtlinux/arch/mips/pci/ops-rc32434.c
--- linux-2.6.16-rc5/arch/mips/pci/ops-rc32434.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/pci/ops-rc32434.c	2006-03-09 16:25:51.000000000 -0800
@@ -0,0 +1,196 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     pci_ops for IDT EB434/435 board
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+
+#include <asm/cpu.h>
+#include <asm/io.h>
+
+#include <asm/idt-boards/rc32434/rc32434.h>
+#include <asm/idt-boards/rc32434/rc32434_pci.h>
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+
+#define PCI_CFG_SET(slot,func,off) \
+	(rc32434_pci->pcicfga = (0x80000000 | ((slot)<<11) | \
+			    ((func)<<8) | (off)))
+
+static int config_access(unsigned char access_type, struct pci_bus *bus,
+                         unsigned int devfn, unsigned char where,
+                         u32 * data)
+{ 
+	/*
+	 * config cycles are on 4 byte boundary only
+	 */
+	unsigned int slot = PCI_SLOT(devfn);
+	u8 func = PCI_FUNC(devfn);
+	
+	if (slot < 2 || slot > 5) {
+		*data = 0xFFFFFFFF;
+		return -1;
+	}
+	/* Setup address */
+	PCI_CFG_SET(slot, func, where);
+	rc32434_sync();
+	
+	if (access_type == PCI_ACCESS_WRITE)
+		rc32434_pci->pcicfgd = *data;
+	
+	else
+		*data = rc32434_pci->pcicfgd;
+	
+	rc32434_sync();
+	
+	return 0;
+}
+
+
+/*
+ * We can't address 8 and 16 bit words directly.  Instead we have to
+ * read/write a 32bit word and mask/modify the data we actually want.
+ */
+static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
+                            int where, u8 * val)
+{
+	u32 data;
+	int ret;
+	
+	ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
+	*val = (data >> ((where & 3) << 3)) & 0xff;
+	return ret;
+}
+
+static int read_config_word(struct pci_bus *bus, unsigned int devfn,
+                            int where, u16 * val)
+{
+	u32 data;
+	int ret;
+	
+	ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
+	*val = (data >> ((where & 3) << 3)) & 0xffff;
+	return ret;
+}
+
+static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
+                             int where, u32 * val)
+{
+	int ret;
+	
+	ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
+	return ret;
+}
+
+static int
+write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
+                  u8 val)
+{
+	u32 data = 0;
+	
+	if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+		return -1;
+	
+	data = (data & ~(0xff << ((where & 3) << 3))) |
+		(val << ((where & 3) << 3));
+	
+	if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
+		return -1;
+	
+	return PCIBIOS_SUCCESSFUL;
+}
+
+
+static int
+write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
+                  u16 val)
+{
+	u32 data = 0;
+	
+	if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+		return -1;
+	
+	data = (data & ~(0xffff << ((where & 3) << 3))) |
+		(val << ((where & 3) << 3));
+	
+	if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
+		return -1;
+	
+	
+	return PCIBIOS_SUCCESSFUL;
+}
+
+
+static int 
+write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
+                   u32 val)
+{
+	if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
+		return -1;
+	
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
+			   int where, int size, u32 * val)
+{
+	switch (size) {
+	case 1: 
+		return read_config_byte(bus, devfn, where, (u8 *) val);
+	case 2: 
+		return read_config_word(bus, devfn, where, (u16 *) val);
+	default:
+		return read_config_dword(bus, devfn, where, val);
+	}
+}
+
+static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
+			    int where, int size, u32 val)
+{
+	switch (size) {
+	case 1: 
+		return write_config_byte(bus, devfn, where, (u8) val);
+	case 2: 
+		return write_config_word(bus, devfn, where, (u16) val);
+	default:
+		return write_config_dword(bus, devfn, where, val);
+	}
+}
+
+struct pci_ops rc32434_pci_ops = {
+	.read =  pci_config_read,
+	.write = pci_config_write,
+};
diff -uNr linux-2.6.16-rc5/arch/mips/pci/ops-rc32438.c idtlinux/arch/mips/pci/ops-rc32438.c
--- linux-2.6.16-rc5/arch/mips/pci/ops-rc32438.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/pci/ops-rc32438.c	2006-03-09 16:25:52.000000000 -0800
@@ -0,0 +1,195 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     pci_ops for IDT EB438 board
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+
+#include <asm/cpu.h>
+#include <asm/io.h>
+
+#include <asm/idt-boards/rc32438/rc32438.h>
+#include <asm/idt-boards/rc32438/rc32438_pci.h>
+#include <asm/idt-boards/rc32438/rc32438_pci_v.h>
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+
+#define PCI_CFG_SET(slot,func,off) \
+	(rc32438_pci->pcicfga = (0x80000000 | ((slot)<<11) | \
+			    ((func)<<8) | (off)))
+
+static int config_access(unsigned char access_type, struct pci_bus *bus,
+                         unsigned int devfn, unsigned char where,
+                         u32 * data)
+{ 
+  /*
+   * config cycles are on 4 byte boundary only
+   */
+  unsigned int slot = PCI_SLOT(devfn);
+  u8 func = PCI_FUNC(devfn);
+
+  if (slot < 2 || slot > 5) {
+    *data = 0xFFFFFFFF;
+    return -1;
+  }
+  /* Setup address */
+  PCI_CFG_SET(slot, func, where);
+  rc32438_sync();
+
+  if (access_type == PCI_ACCESS_WRITE)
+    rc32438_pci->pcicfgd = *data;
+
+  else
+    *data = rc32438_pci->pcicfgd;
+
+  rc32438_sync();
+
+  /*
+   * Revisit: check for master or target abort.
+   */
+  return 0;
+}
+
+
+/*
+ * We can't address 8 and 16 bit words directly.  Instead we have to
+ * read/write a 32bit word and mask/modify the data we actually want.
+ */
+static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
+                            int where, u8 * val)
+{
+  u32 data;
+  int ret;
+
+  ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
+  *val = (data >> ((where & 3) << 3)) & 0xff;
+  return ret;
+}
+
+static int read_config_word(struct pci_bus *bus, unsigned int devfn,
+                            int where, u16 * val)
+{
+  u32 data;
+  int ret;
+
+  ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
+  *val = (data >> ((where & 3) << 3)) & 0xffff;
+  return ret;
+}
+
+static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
+                             int where, u32 * val)
+{
+  int ret;
+
+  ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
+  return ret;
+}
+static int
+write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
+                  u8 val)
+{
+  u32 data = 0;
+
+  if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+    return -1;
+
+  data = (data & ~(0xff << ((where & 3) << 3))) |
+    (val << ((where & 3) << 3));
+
+  if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
+    return -1;
+
+  return PCIBIOS_SUCCESSFUL;
+}
+static int
+write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
+                  u16 val)
+{
+  u32 data = 0;
+
+  if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+    return -1;
+
+  data = (data & ~(0xffff << ((where & 3) << 3))) |
+    (val << ((where & 3) << 3));
+
+  if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
+    return -1;
+
+
+  return PCIBIOS_SUCCESSFUL;
+}
+static int
+write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
+                   u32 val)
+{
+  if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
+    return -1;
+
+  return PCIBIOS_SUCCESSFUL;
+}
+
+static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
+                       int where, int size, u32 * val)
+{
+   switch (size) {
+  case 1: 
+   return read_config_byte(bus, devfn, where, (u8 *) val);
+  case 2: 
+    return read_config_word(bus, devfn, where, (u16 *) val);
+  default:
+    return read_config_dword(bus, devfn, where, val);
+  }
+}
+
+static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
+                        int where, int size, u32 val)
+{
+  switch (size) {
+  case 1: 
+    return write_config_byte(bus, devfn, where, (u8) val);
+  case 2: 
+    return write_config_word(bus, devfn, where, (u16) val);
+  default:
+    return write_config_dword(bus, devfn, where, val);
+  }
+}
+
+struct pci_ops rc32438_pci_ops = {
+  .read =  pci_config_read,
+  .write = pci_config_write,
+};
diff -uNr linux-2.6.16-rc5/arch/mips/pci/pci-rc32334.c idtlinux/arch/mips/pci/pci-rc32334.c
--- linux-2.6.16-rc5/arch/mips/pci/pci-rc32334.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/pci/pci-rc32334.c	2006-03-09 16:25:52.000000000 -0800
@@ -0,0 +1,195 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     PCI initialization for IDT S334 board
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+
+#include <asm/cpu.h>
+#include <asm/io.h>
+
+#include <asm/idt-boards/rc32300/rc32300.h>
+#include <asm/idt-boards/rc32300/rc32334.h>
+
+#define PCI_DEVICE_ID_IDT_RC32334       0x0204
+#define PCI_DEVICE_ID_IDT_79S334        0x0134
+#undef DEBUG
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+#ifdef __MIPSEB__
+#define SWAP_BIT 1
+#else
+#define SWAP_BIT 0
+#endif
+
+struct resource rc32334_res_pci_mem1 = {
+	.name = "PCI Mem1",
+	.start = 0x40000000,
+	.end = 0x5FFFFFFF,
+	.flags = IORESOURCE_MEM,
+};
+
+struct resource rc32334_res_pci_io1 = {
+	.name = "PCI I/O1",
+	.start = 0x18800000,
+	.end = 0x188FFFFF,
+	.flags = IORESOURCE_IO,
+};
+
+extern struct pci_ops rc32334_pci_ops;
+struct pci_controller rc32334_controller = {
+	.pci_ops = &rc32334_pci_ops,
+	.mem_resource = &rc32334_res_pci_mem1,
+	.io_resource = &rc32334_res_pci_io1,
+	.mem_offset     = 0x00000000UL,
+	.io_offset      = 0x00000000UL,
+};
+
+static void local_config_write(u8 where, u32 data)
+{
+
+	rc32300_writel((0x80000000 | (where)), PCI_CFG_CNTL);
+	rc32300_sync();
+	rc32300_writel(data, PCI_CFG_DATA);
+}
+
+static int __init rc32334_pcibridge_init(void)
+{
+  
+	printk("Initializing PCI\n");
+	
+	ioport_resource.start = rc32334_res_pci_io1.start;
+	ioport_resource.end = rc32334_res_pci_io1.end;
+/*
+	iomem_resource.start = rc32334_res_pci_mem1.start;
+	iomem_resource.end = rc32334_res_pci_mem1.end;
+*/
+	
+	/* allow writes to bridge config space */
+	rc32300_writel(4, PCI_ARBITRATION);
+	
+	local_config_write(PCI_VENDOR_ID, 
+			   PCI_VENDOR_ID_IDT | (PCI_DEVICE_ID_IDT_RC32334 << 16));
+	local_config_write(PCI_COMMAND,  
+			   PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+			   PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
+			   PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
+			   ((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
+			     PCI_STATUS_DEVSEL_MEDIUM) << 16));
+	local_config_write(PCI_CLASS_REVISION, 0x06800001);
+	local_config_write(PCI_CACHE_LINE_SIZE, 0x0000ff04);
+	local_config_write(PCI_BASE_ADDRESS_0, 0);    // mem bar
+	local_config_write(PCI_BASE_ADDRESS_1, 0);    // reserved bar
+	local_config_write(PCI_BASE_ADDRESS_2,
+			   0 | PCI_BASE_ADDRESS_SPACE_IO);  // I/O bar
+	local_config_write(PCI_BASE_ADDRESS_3, 0);    // reserved bar
+	local_config_write(PCI_BASE_ADDRESS_4, 0);    // reserved bar
+	local_config_write(PCI_BASE_ADDRESS_5, 0);    // reserved bar
+	local_config_write(PCI_CARDBUS_CIS, 0);       // reserved
+	local_config_write(PCI_SUBSYSTEM_VENDOR_ID,
+			   PCI_VENDOR_ID_IDT | (PCI_DEVICE_ID_IDT_79S334 << 16));
+	local_config_write(PCI_ROM_ADDRESS, 0);       // reserved
+	local_config_write(PCI_CAPABILITY_LIST, 0);   // reserved
+	local_config_write(PCI_CAPABILITY_LIST+4, 0); // reserved
+	
+	local_config_write(PCI_INTERRUPT_LINE, 0x38080101);
+	/* retry timeout, trdy timeout */
+	local_config_write(PCI_INTERRUPT_LINE+4, 0x00008080);
+	
+	rc32300_writel(0x00000000, PCI_CFG_CNTL);
+	
+	/*
+	 * CPU -> PCI address translation. Make CPU physical and
+	 * PCI bus addresses the same.
+	 */
+	
+	/*
+	 * Note!
+	 *
+	 * Contrary to the RC32334 documentation, the behavior of
+	 * the PCI byte-swapping bits appears to be the following:
+	 *
+	 *   when cpu is in LE: 0 = don't swap, 1 = swap
+	 *   when cpu is in BE: 1 = don't swap, 0 = swap
+	 *
+	 * This is true both when the cpu/DMA accesses PCI device
+	 * memory/io, and when a PCI bus master accesses system memory.
+	 *
+	 * Furthermore, byte-swapping doesn't even seem to work
+	 * correctly when it is enabled.
+	 *
+	 * The solution to all this is to disable h/w byte-swapping,
+	 * use s/w swapping (CONFIG_SWAP_IO_SPACE) for the in/out/read/
+	 * write macros (which takes care of device accesses by cpu/dma)
+	 * and hope that drivers swap device data in memory (which takes
+	 * care of memory accesses by bus-masters).
+	 *
+	 * Finally, despite the above workaround, there are still
+	 * PCI h/w problems on the 79S334A. PCI bus timeouts and
+	 * system/parity errors have been encountered.
+	 */
+	
+	/* mem space 1 */
+	rc32300_writel(rc32334_res_pci_mem1.start | SWAP_BIT, PCI_MEM1_BASE);
+	
+	/* i/o space */
+	rc32300_writel(rc32334_res_pci_io1.start | SWAP_BIT, PCI_IO1_BASE);
+	
+	/* use internal arbiter, 0=round robin, 1=fixed */
+	rc32300_writel(0, PCI_ARBITRATION);
+	
+	/*
+	 * PCI -> CPU accesses
+	 *
+	 * Let PCI see system memory at 0x00000000 physical
+	 */
+	
+	rc32300_writel(0x0 | SWAP_BIT, PCI_CPU_MEM1_BASE); /* mem space */
+	rc32300_writel(0x0 | SWAP_BIT, PCI_CPU_IO_BASE);   /* i/o space */
+	
+	register_pci_controller(&rc32334_controller);
+	
+	rc32300_sync();   
+	return 0;
+}
+arch_initcall(rc32334_pcibridge_init);
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+        return 0;
+}
diff -uNr linux-2.6.16-rc5/arch/mips/pci/pci-rc32365.c idtlinux/arch/mips/pci/pci-rc32365.c
--- linux-2.6.16-rc5/arch/mips/pci/pci-rc32365.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/pci/pci-rc32365.c	2006-03-09 16:25:52.000000000 -0800
@@ -0,0 +1,379 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     PCI initialization for IDT EB365 board
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+
+#include <asm/idt-boards/rc32300/rc32300.h>
+#include <asm/idt-boards/rc32300/rc32365_pci.h> 
+#include <asm/idt-boards/rc32300/rc32365_pci_v.h> 
+#include <asm/idt-boards/rc32300/rc32365_dma_v.h> 
+#include <linux/byteorder/swab.h>
+#include <linux/interrupt.h>
+
+/* define an unsigned array for the PCI registers */
+static unsigned int cedarCnfgRegs[25] = {
+  CEDAR_CNFG1,  CEDAR_CNFG2,  CEDAR_CNFG3,  CEDAR_CNFG4,	
+  CEDAR_CNFG5,  CEDAR_CNFG6,  CEDAR_CNFG7,  CEDAR_CNFG8,
+  CEDAR_CNFG9,  CEDAR_CNFG10, CEDAR_CNFG11, CEDAR_CNFG12,
+  CEDAR_CNFG13,	CEDAR_CNFG14, CEDAR_CNFG15, CEDAR_CNFG16,
+  CEDAR_CNFG17,	CEDAR_CNFG18, CEDAR_CNFG19, CEDAR_CNFG20,
+  CEDAR_CNFG21,	CEDAR_CNFG22, CEDAR_CNFG23, CEDAR_CNFG24
+};
+
+
+static struct resource rc32365_res_pci_mem1;
+static struct resource rc32365_res_pci_io1;
+
+static struct resource rc32365_res_pci_mem1 = {
+  .name = "PCI MEM1",
+  .start = 0x50000000,
+  .end = 0x5FFFFFFF,
+  .flags = IORESOURCE_MEM,
+};
+static struct resource rc32365_res_pci_io1 = {
+  .name = "PCI I/O1",
+  .start = 0x18800000,
+  .end = 0x188FFFFF,
+  .flags = IORESOURCE_IO,
+};
+
+extern struct pci_ops rc32365_pci_ops;
+static struct pci_controller rc32365_controller = {
+  .pci_ops = &rc32365_pci_ops,
+  .mem_resource = &rc32365_res_pci_mem1,
+  .io_resource = &rc32365_res_pci_io1,
+  .mem_offset     = 0x00000000UL,
+  .io_offset      = 0x00000000UL,
+};
+
+static __init int rc32365_pcibridge_init(void)
+{
+  
+  unsigned int pciConfigAddr;/*used for writing pci config values */
+  int	     loopCount    ;/*used for the loop */
+  unsigned int pcicValue, pcicData = 0;
+  unsigned int dummyRead, pciCntlVal;
+
+  printk("Initialising PCI.\n");
+  ioport_resource.start = rc32365_res_pci_io1.start;
+  ioport_resource.end = rc32365_res_pci_io1.end;
+/*
+  iomem_resource.start = rc32365_res_pci_mem1.start;
+  iomem_resource.end = rc32365_res_pci_mem1.end;
+*/
+
+  /* Disable the IP bus error for PCI scaning */
+  pciCntlVal=rc32365_pci->pcic;
+  pciCntlVal &= 0xFFFFFF7;
+  rc32365_pci->pcic = pciCntlVal;
+
+  pcicValue = rc32365_pci->pcic;
+  pcicValue = (pcicValue >> PCIM_SHFT) & PCIM_BIT_LEN;
+  if (!((pcicValue == PCIM_H_EA) ||
+	(pcicValue == PCIM_H_IA_FIX) ||
+	(pcicValue == PCIM_H_IA_RR))) {
+    /* Not in Host Mode, return ERROR */
+    return -1 ;
+  }
+  
+  /* Enables the Idle Grant mode, Arbiter Parking */
+  pcicData |= (PCIC_igm_m | PCIC_eap_m | PCIC_en_m);
+  rc32365_pci->pcic = pcicData; /* Enable the PCI bus Interface */
+  /* Zero out the PCI status & PCI Status Mask */
+  for (;;)
+    {
+      pcicData = rc32365_pci->pcis;
+      if (!(pcicData & PCIS_rip_m))
+	break;
+    }
+  
+  rc32365_pci->pcis = 0;
+  rc32365_pci->pcism = 0xFFFFFFFF;
+  /* Zero out the PCI decoupled registers */
+  rc32365_pci->pcidac=0; /* disable PCI decoupled accesses at initialization */
+  rc32365_pci->pcidas=0; /* clear the status */
+  rc32365_pci->pcidasm=0x0000007F; /* Mask all the interrupts */
+  /* Mask PCI Messaging Interrupts */
+  rc32365_pci_msg->pciiic = 0;
+  rc32365_pci_msg->pciiim = 0xFFFFFFFF;
+  rc32365_pci_msg->pciioic = 0;
+  rc32365_pci_msg->pciioim = 0;
+  
+  /* Setup PCILB0 as Memory Window */
+  rc32365_pci->pcilba[0].a = (unsigned int)(PCI_ADDR_START);
+  
+  /* setup the PCI map address as same as the local address */
+  
+  rc32365_pci->pcilba[0].m = (unsigned int)(PCI_ADDR_START);
+  
+  /* Setup PCILBA0 as MEM */
+#ifdef __MIPSEB__
+  rc32365_pci->pcilba[0].c = (((SIZE_16MB & 0x1f) << PCILBAC_size_b) | PCILBAC_sb_m);
+#else
+  rc32365_pci->pcilba[0].c = ((SIZE_16MB & 0x1f) << PCILBAC_size_b);
+#endif
+  dummyRead = rc32365_pci->pcilba[0].c; /* flush the CPU write Buffers */
+
+  
+  rc32365_pci->pcilba[1].a = 0x60000000;
+  
+  rc32365_pci->pcilba[1].m = 0x60000000;
+  /* setup PCILBA1 as MEM */
+#ifdef __MIPSEB__
+  rc32365_pci->pcilba[1].c = (((SIZE_256MB & 0x1f) << PCILBAC_size_b) | PCILBAC_sb_m);
+#else
+  rc32365_pci->pcilba[1].c = ((SIZE_256MB & 0x1f) << PCILBAC_size_b);
+#endif
+  dummyRead = rc32365_pci->pcilba[1].c; /* flush the CPU write Buffers */
+
+  rc32365_pci->pcilba[2].a = 0x18C00000;
+  
+  rc32365_pci->pcilba[2].m = 0x18FFFFFF;
+  /* setup PCILBA2 as MEM */
+#ifdef __MIPSEB__
+  rc32365_pci->pcilba[2].c = (((SIZE_4MB & 0x1f) << PCILBAC_size_b)  | PCILBAC_sb_m);
+#else
+  rc32365_pci->pcilba[2].c = ((SIZE_4MB & 0x1f) << PCILBAC_size_b);
+#endif    
+  dummyRead = rc32365_pci->pcilba[2].c; /* flush the CPU write Buffers */
+    
+  rc32365_pci->pcilba[3].a = 0x18800000;
+  
+  rc32365_pci->pcilba[3].m = 0x18800000;
+
+  /* Setup PCILBA3 as IO Window */
+#ifdef __MIPSEB__
+  rc32365_pci->pcilba[3].c = ((((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m)  | PCILBAC_sb_m);
+#else
+  rc32365_pci->pcilba[3].c = (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) |PCILBAC_msi_m);
+#endif
+  dummyRead = rc32365_pci->pcilba[2].c; /* flush the CPU write Buffers */
+  
+  pciConfigAddr = (unsigned int)(0x80000004);
+  for (loopCount = 0; loopCount < 24; loopCount++) {
+    rc32365_pci->pcicfga = pciConfigAddr;
+    dummyRead = rc32365_pci->pcicfga;
+    if (loopCount == 16 && cedar_za == 0) /* CEDAR_CNFG17 */
+      rc32365_pci->pcicfgd = cedarCnfgRegs[loopCount] | PCIPBAC_pp_m | (PCIPBAC_mr_readMult_v << PCIPBAC_mr_b) | PCIPBAC_mrl_m | PCIPBAC_mrm_m;
+    else
+      rc32365_pci->pcicfgd = cedarCnfgRegs[loopCount];
+    dummyRead = rc32365_pci->pcicfgd;
+    pciConfigAddr += 4;
+  }
+  rc32365_pci->pcitc = (unsigned int)((PCITC_RTIMER_VAL & 0xff) << PCITC_rtimer_b) |
+    ((PCITC_DTIMER_VAL & 0xff) << PCITC_dtimer_b);
+  
+  pciCntlVal = rc32365_pci->pcic;
+  pciCntlVal &= ~(PCIC_tnr_m);
+  rc32365_pci->pcic = pciCntlVal;
+  pciCntlVal = rc32365_pci->pcic;
+  
+  register_pci_controller(&rc32365_controller);
+
+  rc32300_sync();   
+  return 0;
+}
+arch_initcall(rc32365_pcibridge_init);
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+        return 0;
+}
+
+unsigned char rc32365_pci_inb(unsigned long port, int slow)
+{
+	if (cedar_za) {
+		volatile DMA_Chan_t pci_dma_regs = (DMA_Chan_t)(DMA0_VirtualAddress + DMACH_pciToMem * DMA_CHAN_OFFSET);
+		volatile struct DMAD_s desc;
+		DMAD_t pdesc = (DMAD_t)KSEG1ADDR(&desc);
+		u32 data;
+		volatile u32 *pdata = (u32 *)KSEG1ADDR(&data);
+		unsigned long flags;
+
+		*pdata = 0;
+		pdesc->control = 0x01c00001;
+		pdesc->ca      = CPHYSADDR(pdata);
+		pdesc->devcs   = port;
+		pdesc->link    = 0;
+
+		local_irq_save(flags);
+		while (pci_dma_regs->dmac & DMAC_run_m);
+
+		pci_dma_regs->dmas = 0;
+		pci_dma_regs->dmandptr = 0;
+		pci_dma_regs->dmadptr = CPHYSADDR(pdesc);
+
+		while (!pci_dma_regs->dmas);
+		local_irq_restore(flags);
+
+		if (slow) SLOW_DOWN_IO;
+
+		return (unsigned char)(*pdata >> 24);
+	}
+	else if (slow)
+	  SLOW_DOWN_IO;
+	else
+		return (inb(port));
+}
+
+void rc32365_pci_outb(unsigned char val, unsigned long port, int slow)
+{
+	if (cedar_za) {
+		volatile DMA_Chan_t pci_dma_regs = (DMA_Chan_t)(DMA0_VirtualAddress + DMACH_memToPci * DMA_CHAN_OFFSET);
+		volatile struct DMAD_s desc;
+		DMAD_t pdesc = (DMAD_t)KSEG1ADDR(&desc);
+		u32 data;
+		volatile u32 *pdata = (u32 *)KSEG1ADDR(&data);
+		unsigned long flags;
+
+		*pdata = val << 24;
+		pdesc->control = 0x01c00001;
+		pdesc->ca      = CPHYSADDR(pdata);
+		pdesc->devcs   = port;
+		pdesc->link    = 0;
+
+		local_irq_save(flags);
+		while (pci_dma_regs->dmac & DMAC_run_m);
+
+		pci_dma_regs->dmas = 0;
+		pci_dma_regs->dmandptr = 0;
+		pci_dma_regs->dmadptr = CPHYSADDR(pdesc);
+
+		while (!pci_dma_regs->dmas);
+		local_irq_restore(flags);
+
+		if (slow) SLOW_DOWN_IO;
+	}
+	else if (slow)
+	  SLOW_DOWN_IO;
+	else
+	  outb(val, port);
+}
+
+unsigned short rc32365_pci_inw(unsigned long port, int slow)
+{
+	if (cedar_za) {
+		volatile DMA_Chan_t pci_dma_regs = (DMA_Chan_t)(DMA0_VirtualAddress + DMACH_pciToMem * DMA_CHAN_OFFSET);
+		volatile struct DMAD_s desc;
+		DMAD_t pdesc = (DMAD_t)KSEG1ADDR(&desc);
+		u32 data;
+		volatile u32 *pdata = (u32 *)KSEG1ADDR(&data);
+		unsigned long flags;
+
+		*pdata = 0;
+		pdesc->control = 0x01c00002;
+		pdesc->ca      = CPHYSADDR(pdata);
+		pdesc->devcs   = port;
+		pdesc->link    = 0;
+
+		local_irq_save(flags);
+		while (pci_dma_regs->dmac & DMAC_run_m);
+
+		pci_dma_regs->dmas = 0;
+		pci_dma_regs->dmandptr = 0;
+		pci_dma_regs->dmadptr = CPHYSADDR(pdesc);
+
+		while (!pci_dma_regs->dmas);
+		local_irq_restore(flags);
+
+		if (slow) SLOW_DOWN_IO;
+
+#ifdef __MIPSEB__
+		return (unsigned short)(*pdata >> 16);
+#else
+		return (unsigned short)((*pdata >> 24) | ((*pdata >> 8) & 0x0000ff00));
+#endif
+	}
+	else
+	{
+		unsigned short	val;
+		if (slow)
+			val = (inw_p(port));
+		else
+			val = (inw(port));
+#ifdef __MIPSEB__
+		val = swab16(val);
+#endif
+		return val;
+	}
+}
+
+void rc32365_pci_outw(unsigned short val, unsigned long port, int slow)
+{
+	if (cedar_za) {
+		volatile DMA_Chan_t pci_dma_regs = (DMA_Chan_t)(DMA0_VirtualAddress + DMACH_memToPci * DMA_CHAN_OFFSET);
+		volatile struct DMAD_s desc;
+		DMAD_t pdesc = (DMAD_t)KSEG1ADDR(&desc);
+		u32 data;
+		volatile u32 *pdata = (u32 *)KSEG1ADDR(&data);
+		unsigned long flags;
+
+#ifdef __MIPSEB__
+		*pdata = (val << 16);
+#else
+		*pdata = (val << 24) | ((val << 8) & 0x00ff0000);
+#endif
+		pdesc->control = 0x01c00002;
+		pdesc->ca      = CPHYSADDR(pdata);
+		pdesc->devcs   = port;
+		pdesc->link    = 0;
+
+		local_irq_save(flags);
+		while (pci_dma_regs->dmac & DMAC_run_m);
+
+		pci_dma_regs->dmas = 0;
+		pci_dma_regs->dmandptr = 0;
+		pci_dma_regs->dmadptr = CPHYSADDR(pdesc);
+
+		while (!pci_dma_regs->dmas);
+		local_irq_restore(flags);
+
+		if (slow) SLOW_DOWN_IO;
+	}
+	else
+	{
+#ifdef __MIPSEB__
+		val = swab16(val);
+#endif
+		if (slow)
+			outw_p(val, port);
+		else
+			outw(val, port);
+	}
+}
+
diff -uNr linux-2.6.16-rc5/arch/mips/pci/pci-rc32434.c idtlinux/arch/mips/pci/pci-rc32434.c
--- linux-2.6.16-rc5/arch/mips/pci/pci-rc32434.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/pci/pci-rc32434.c	2006-03-09 16:25:52.000000000 -0800
@@ -0,0 +1,212 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     PCI initialization for IDT EB434/435 board
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <asm/idt-boards/rc32434/rc32434.h>
+#include <asm/idt-boards/rc32434/rc32434_pci.h> 
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+#undef DEBUG
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+/* define an unsigned array for the PCI registers */
+unsigned int korinaCnfgRegs[25] = {
+	KORINA_CNFG1,	 KORINA_CNFG2,  KORINA_CNFG3,  KORINA_CNFG4,
+	KORINA_CNFG5,	 KORINA_CNFG6,  KORINA_CNFG7,  KORINA_CNFG8,
+	KORINA_CNFG9,	 KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
+	KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
+	KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
+	KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
+};
+static struct resource rc32434_res_pci_mem1 = {
+	.name = "PCI MEM1",
+	.start = 0x50000000,
+	.end = 0x5FFFFFFF,
+	.flags = IORESOURCE_MEM,
+};
+static struct resource rc32434_res_pci_io1 = {
+	.name = "PCI I/O1",
+	.start = 0x18800000,
+	.end = 0x188FFFFF,
+	.flags = IORESOURCE_IO,
+};
+
+extern struct pci_ops rc32434_pci_ops;
+
+struct pci_controller rc32434_controller = {
+	.pci_ops = &rc32434_pci_ops,
+	.mem_resource = &rc32434_res_pci_mem1,
+	.io_resource = &rc32434_res_pci_io1,
+	.mem_offset     = 0x00000000UL,
+	.io_offset      = 0x00000000UL,
+};
+
+static int __init rc32434_pcibridge_init(void)
+{
+	
+	unsigned int pciConfigAddr = 0;/*used for writing pci config values */
+	int	     loopCount=0    ;/*used for the loop */
+	
+	unsigned int pcicValue, pcicData=0;
+	unsigned int dummyRead, pciCntlVal = 0;
+	printk("PCI: Initializing PCI\n");
+	
+	/* Disable the IP bus error for PCI scaning */
+	pciCntlVal=rc32434_pci->pcic;
+	pciCntlVal &= 0xFFFFFF7;
+	rc32434_pci->pcic = pciCntlVal;
+	
+	ioport_resource.start = rc32434_res_pci_io1.start;
+	ioport_resource.end = rc32434_res_pci_io1.end;
+/*
+	iomem_resource.start = rc32434_res_pci_mem1.start;
+	iomem_resource.end = rc32434_res_pci_mem1.end;
+*/
+	
+	pcicValue = rc32434_pci->pcic;
+	pcicValue = (pcicValue >> PCIM_SHFT) & PCIM_BIT_LEN;
+	if (!((pcicValue == PCIM_H_EA) ||
+	      (pcicValue == PCIM_H_IA_FIX) ||
+	      (pcicValue == PCIM_H_IA_RR))) {
+		/* Not in Host Mode, return ERROR */
+		return -1;
+	}
+	
+	/* Enables the Idle Grant mode, Arbiter Parking */
+	pcicData |=(PCIC_igm_m|PCIC_eap_m|PCIC_en_m);
+	rc32434_pci->pcic = pcicData; /* Enable the PCI bus Interface */
+	/* Zero out the PCI status & PCI Status Mask */
+	for(;;) {
+		pcicData = rc32434_pci->pcis;
+		if (!(pcicData & PCIS_rip_m))
+			break;
+	}
+	
+	rc32434_pci->pcis = 0;
+	rc32434_pci->pcism = 0xFFFFFFFF;
+	/* Zero out the PCI decoupled registers */
+	rc32434_pci->pcidac=0; /* disable PCI decoupled accesses at initialization */
+	rc32434_pci->pcidas=0; /* clear the status */
+	rc32434_pci->pcidasm=0x0000007F; /* Mask all the interrupts */
+	/* Mask PCI Messaging Interrupts */
+	rc32434_pci_msg->pciiic = 0;
+	rc32434_pci_msg->pciiim = 0xFFFFFFFF;
+	rc32434_pci_msg->pciioic = 0;
+	rc32434_pci_msg->pciioim = 0;
+	
+	/* Setup PCILB0 as Memory Window */
+	rc32434_pci->pcilba[0].a = (unsigned int) (PCI_ADDR_START);
+	
+	/* setup the PCI map address as same as the local address */
+	
+	rc32434_pci->pcilba[0].m = (unsigned int) (PCI_ADDR_START);
+	
+	/* Setup PCILBA1 as MEM */
+#ifdef __MIPSEB__
+	rc32434_pci->pcilba[0].c = ( ((SIZE_16MB & 0x1f) << PCILBAC_size_b) | PCILBAC_sb_m);
+#else
+	rc32434_pci->pcilba[0].c = ( ((SIZE_16MB & 0x1f) << PCILBAC_size_b));
+#endif
+	dummyRead = rc32434_pci->pcilba[0].c; /* flush the CPU write Buffers */
+	
+	rc32434_pci->pcilba[1].a = 0x60000000;
+	
+	rc32434_pci->pcilba[1].m = 0x60000000;
+	/* setup PCILBA2 as IO Window*/
+#ifdef __MIPSEB__
+	rc32434_pci->pcilba[1].c = ( ((SIZE_256MB & 0x1f) << PCILBAC_size_b) |  PCILBAC_sb_m);
+#else
+	rc32434_pci->pcilba[1].c = ((SIZE_256MB & 0x1f) << PCILBAC_size_b);
+#endif
+	dummyRead = rc32434_pci->pcilba[1].c; /* flush the CPU write Buffers */
+	rc32434_pci->pcilba[2].a = 0x18C00000;
+	
+	rc32434_pci->pcilba[2].m = 0x18FFFFFF;
+	/* setup PCILBA2 as IO Window*/
+#ifdef __MIPSEB__
+	rc32434_pci->pcilba[2].c = ( ((SIZE_4MB & 0x1f) << PCILBAC_size_b)  |  PCILBAC_sb_m);
+#else
+	rc32434_pci->pcilba[2].c = ((SIZE_4MB & 0x1f) << PCILBAC_size_b);
+#endif  
+	
+	dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
+	
+	
+	rc32434_pci->pcilba[3].a = 0x18800000;
+	
+	rc32434_pci->pcilba[3].m = 0x18800000;
+	/* Setup PCILBA3 as IO Window */
+	
+#ifdef __MIPSEB__
+	rc32434_pci->pcilba[3].c = ( (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m)   |  PCILBAC_sb_m);
+#else
+	rc32434_pci->pcilba[3].c = (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m);
+#endif
+	dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
+	
+	pciConfigAddr = (unsigned int)(0x80000004);
+	for(loopCount = 0; loopCount < 24; loopCount++){
+		rc32434_pci->pcicfga = pciConfigAddr;
+		dummyRead = rc32434_pci->pcicfga;
+		rc32434_pci->pcicfgd = korinaCnfgRegs[loopCount];
+		dummyRead=rc32434_pci->pcicfgd;
+		pciConfigAddr += 4;
+	}
+	rc32434_pci->pcitc=(unsigned int)((PCITC_RTIMER_VAL&0xff) << PCITC_rtimer_b) |
+		((PCITC_DTIMER_VAL&0xff)<<PCITC_dtimer_b);
+	
+	pciCntlVal = rc32434_pci->pcic;
+	pciCntlVal &= ~(PCIC_tnr_m);
+	rc32434_pci->pcic = pciCntlVal;
+	pciCntlVal = rc32434_pci->pcic;
+	
+	register_pci_controller(&rc32434_controller);
+	
+	rc32434_sync();  
+	return 0;
+}
+
+arch_initcall(rc32434_pcibridge_init);
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+        return 0;
+}
diff -uNr linux-2.6.16-rc5/arch/mips/pci/pci-rc32438.c idtlinux/arch/mips/pci/pci-rc32438.c
--- linux-2.6.16-rc5/arch/mips/pci/pci-rc32438.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/arch/mips/pci/pci-rc32438.c	2006-03-09 16:25:51.000000000 -0800
@@ -0,0 +1,344 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     PCI initialization for IDT EB438 board
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <asm/idt-boards/rc32438/rc32438.h>
+#include <asm/idt-boards/rc32438/rc32438_pci.h>
+#include <asm/idt-boards/rc32438/rc32438_pci_v.h>
+#include <asm/idt-boards/rc32438/rc32438_dma_v.h>
+#include <linux/interrupt.h>
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+/* define an unsigned array for the PCI registers */
+unsigned int acaciaCnfgRegs[25] = {
+  ACACIA_CNFG1,	 ACACIA_CNFG2,  ACACIA_CNFG3,  ACACIA_CNFG4,
+  ACACIA_CNFG5,	 ACACIA_CNFG6,  ACACIA_CNFG7,  ACACIA_CNFG8,
+  ACACIA_CNFG9,	 ACACIA_CNFG10, ACACIA_CNFG11, ACACIA_CNFG12,
+  ACACIA_CNFG13, ACACIA_CNFG14, ACACIA_CNFG15, ACACIA_CNFG16,
+  ACACIA_CNFG17, ACACIA_CNFG18, ACACIA_CNFG19, ACACIA_CNFG20,
+  ACACIA_CNFG21, ACACIA_CNFG22, ACACIA_CNFG23, ACACIA_CNFG24
+};
+static struct resource rc32438_res_pci_mem1 = {
+  .name = "PCI MEM1",
+  .start = 0x50000000,
+  .end = 0x5FFFFFFF,
+  .flags = IORESOURCE_MEM,
+};
+static struct resource rc32438_res_pci_io1 = {
+  .name = "PCI I/O1",
+  .start = 0x18800000,
+  .end = 0x188FFFFF,
+  .flags = IORESOURCE_IO,
+};
+
+extern struct pci_ops rc32438_pci_ops;
+
+struct pci_controller rc32438_controller = {
+  .pci_ops = &rc32438_pci_ops,
+  .mem_resource = &rc32438_res_pci_mem1,
+  .io_resource = &rc32438_res_pci_io1,
+  .mem_offset     = 0x00000000UL,
+  .io_offset      = 0x00000000UL,
+};
+
+static int __init rc32438_pcibridge_init(void)
+{
+
+  unsigned int pciConfigAddr = 0;/*used for writing pci config values */
+  int	     loopCount=0    ;/*used for the loop */
+
+  unsigned int pcicValue, pcicData=0;
+  unsigned int dummyRead, pciCntlVal = 0;
+  printk("PCI: Initializing PCI\n");
+
+  /* Disable the IP bus error for PCI scaning */
+  pciCntlVal=rc32438_pci->pcic;
+  pciCntlVal &= 0xFFFFFF7;
+  rc32438_pci->pcic = pciCntlVal;
+
+  ioport_resource.start = rc32438_res_pci_io1.start;
+  ioport_resource.end = rc32438_res_pci_io1.end;
+/*
+  iomem_resource.start = rc32438_res_pci_mem1.start;
+  iomem_resource.end = rc32438_res_pci_mem1.end;
+*/
+
+  pcicValue = rc32438_pci->pcic;
+  pcicValue = (pcicValue >> PCIM_SHFT) & PCIM_BIT_LEN;
+  if (!((pcicValue == PCIM_H_EA) ||
+	(pcicValue == PCIM_H_IA_FIX) ||
+	(pcicValue == PCIM_H_IA_RR))) {
+    /* Not in Host Mode, return ERROR */
+    return -1;
+  }
+
+  /* Enables the Idle Grant mode, Arbiter Parking */
+  pcicData |=(PCIC_igm_m|PCIC_eap_m|PCIC_en_m);
+  rc32438_pci->pcic = pcicData; /* Enable the PCI bus Interface */
+  /* Zero out the PCI status & PCI Status Mask */
+  for(;;)
+    {
+      pcicData = rc32438_pci->pcis;
+      if (!(pcicData & PCIS_rip_m))
+	break;
+    }
+
+  rc32438_pci->pcis = 0;
+  rc32438_pci->pcism = 0xFFFFFFFF;
+  /* Zero out the PCI decoupled registers */
+  rc32438_pci->pcidac=0; /* disable PCI decoupled accesses at initialization */
+  rc32438_pci->pcidas=0; /* clear the status */
+  rc32438_pci->pcidasm=0x0000007F; /* Mask all the interrupts */
+  /* Mask PCI Messaging Interrupts */
+  rc32438_pci_msg->pciiic = 0;
+  rc32438_pci_msg->pciiim = 0xFFFFFFFF;
+  rc32438_pci_msg->pciioic = 0;
+  rc32438_pci_msg->pciioim = 0;
+
+  /* Setup PCILB0 as Memory Window */
+  rc32438_pci->pcilba[0].a = (unsigned int) (PCI_ADDR_START);
+
+  /* setup the PCI map address as same as the local address */
+
+  rc32438_pci->pcilba[0].m = (unsigned int) (PCI_ADDR_START);
+
+  /* Setup PCILBA1 as MEM */
+#ifdef __MIPSEB__
+  rc32438_pci->pcilba[0].c = ( ((SIZE_16MB & 0x1f) << PCILBAC_size_b) | PCILBAC_sb_m);
+#else
+  rc32438_pci->pcilba[0].c = ( ((SIZE_16MB & 0x1f) << PCILBAC_size_b));
+#endif
+  dummyRead = rc32438_pci->pcilba[0].c; /* flush the CPU write Buffers */
+
+  rc32438_pci->pcilba[1].a = 0x60000000;
+  
+  rc32438_pci->pcilba[1].m = 0x60000000;
+  /* setup PCILBA2 as IO Window*/
+#ifdef __MIPSEB__
+  rc32438_pci->pcilba[1].c = ( ((SIZE_256MB & 0x1f) << PCILBAC_size_b) |  PCILBAC_sb_m);
+#else
+  rc32438_pci->pcilba[1].c = ((SIZE_256MB & 0x1f) << PCILBAC_size_b);
+#endif
+  dummyRead = rc32438_pci->pcilba[1].c; /* flush the CPU write Buffers */
+  rc32438_pci->pcilba[2].a = 0x18C00000;
+    
+  rc32438_pci->pcilba[2].m = 0x18FFFFFF;
+  /* setup PCILBA2 as IO Window*/
+#ifdef __MIPSEB__
+  rc32438_pci->pcilba[2].c = ( ((SIZE_4MB & 0x1f) << PCILBAC_size_b)  |  PCILBAC_sb_m);
+#else
+  rc32438_pci->pcilba[2].c = ((SIZE_4MB & 0x1f) << PCILBAC_size_b);
+#endif  
+  
+  dummyRead = rc32438_pci->pcilba[2].c; /* flush the CPU write Buffers */
+
+
+  rc32438_pci->pcilba[3].a = 0x18800000;
+
+  rc32438_pci->pcilba[3].m = 0x18800000;
+  /* Setup PCILBA3 as IO Window */
+
+#ifdef __MIPSEB__
+  rc32438_pci->pcilba[3].c = ( (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m)   |  PCILBAC_sb_m);
+#else
+  rc32438_pci->pcilba[3].c = (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m);
+#endif
+  dummyRead = rc32438_pci->pcilba[2].c; /* flush the CPU write Buffers */
+
+  pciConfigAddr=(unsigned int)(0x80000004);
+  for(loopCount=0;loopCount<24;loopCount++){
+    rc32438_pci->pcicfga=pciConfigAddr;
+    dummyRead=rc32438_pci->pcicfga;
+    rc32438_pci->pcicfgd = acaciaCnfgRegs[loopCount];
+    dummyRead=rc32438_pci->pcicfgd;
+    pciConfigAddr += 4;
+  }
+  rc32438_pci->pcitc=(unsigned int)((PCITC_RTIMER_VAL&0xff) << PCITC_rtimer_b) |
+    ((PCITC_DTIMER_VAL&0xff)<<PCITC_dtimer_b);
+
+  pciCntlVal=rc32438_pci->pcic;
+  pciCntlVal &=~(PCIC_tnr_m);
+  rc32438_pci->pcic = pciCntlVal;
+  pciCntlVal=rc32438_pci->pcic;
+
+  register_pci_controller(&rc32438_controller);
+
+  rc32438_sync();  
+  return 0;
+}
+arch_initcall(rc32438_pcibridge_init);
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+        return 0;
+}
+
+unsigned char rc32438_pci_inb(unsigned long port, int slow)
+{
+	volatile DMA_Chan_t pci_dma_regs = (DMA_Chan_t)(DMA0_VirtualAddress + DMACH_pciToMem * DMA_CHAN_OFFSET);
+	volatile struct DMAD_s desc;
+	DMAD_t pdesc = (DMAD_t)KSEG1ADDR(&desc);
+	u32 data;
+	volatile u32 *pdata = (u32 *)KSEG1ADDR(&data);
+	unsigned long flags;
+
+	*pdata = 0;
+	pdesc->control = 0x01c00001;
+	pdesc->ca      = CPHYSADDR(pdata);
+	pdesc->devcs   = port;
+	pdesc->link    = 0;
+
+	local_irq_save(flags);
+	while (pci_dma_regs->dmac & DMAC_run_m);
+
+	pci_dma_regs->dmas = 0;
+	pci_dma_regs->dmandptr = 0;
+	pci_dma_regs->dmadptr = CPHYSADDR(pdesc);
+
+	while (!pci_dma_regs->dmas);
+	local_irq_restore(flags);
+
+	if (slow) SLOW_DOWN_IO;
+
+#if defined(__MIPSEB__)
+	return (unsigned char)(*pdata >> 24);
+#else
+	return (unsigned char)(*pdata);
+#endif
+}
+
+void rc32438_pci_outb(unsigned char val, unsigned long port, int slow)
+{
+	volatile DMA_Chan_t pci_dma_regs = (DMA_Chan_t)(DMA0_VirtualAddress + DMACH_memToPci * DMA_CHAN_OFFSET);
+	volatile struct DMAD_s desc;
+	DMAD_t pdesc = (DMAD_t)KSEG1ADDR(&desc);
+	u32 data;
+	volatile u32 *pdata = (u32 *)KSEG1ADDR(&data);
+	unsigned long flags;
+
+#if defined(__MIPSEB__)
+	*pdata = val << 24;
+#else
+	*pdata = val;
+#endif
+	pdesc->control = 0x01c00001;
+	pdesc->ca      = CPHYSADDR(pdata);
+	pdesc->devcs   = port;
+	pdesc->link    = 0;
+
+	local_irq_save(flags);
+	while (pci_dma_regs->dmac & DMAC_run_m);
+
+	pci_dma_regs->dmas = 0;
+	pci_dma_regs->dmandptr = 0;
+	pci_dma_regs->dmadptr = CPHYSADDR(pdesc);
+
+	while (!pci_dma_regs->dmas);
+	local_irq_restore(flags);
+
+	if (slow) SLOW_DOWN_IO;
+}
+
+unsigned short rc32438_pci_inw(unsigned long port, int slow)
+{
+	volatile DMA_Chan_t pci_dma_regs = (DMA_Chan_t)(DMA0_VirtualAddress + DMACH_pciToMem * DMA_CHAN_OFFSET);
+	volatile struct DMAD_s desc;
+	DMAD_t pdesc = (DMAD_t)KSEG1ADDR(&desc);
+	u32 data;
+	volatile u32 *pdata = (u32 *)KSEG1ADDR(&data);
+	unsigned long flags;
+
+	*pdata = 0;
+	pdesc->control = 0x01c00002;
+	pdesc->ca      = CPHYSADDR(pdata);
+	pdesc->devcs   = port;
+	pdesc->link    = 0;
+
+	local_irq_save(flags);
+	while (pci_dma_regs->dmac & DMAC_run_m);
+
+	pci_dma_regs->dmas = 0;
+	pci_dma_regs->dmandptr = 0;
+	pci_dma_regs->dmadptr = CPHYSADDR(pdesc);
+
+	while (!pci_dma_regs->dmas);
+	local_irq_restore(flags);
+
+	if (slow) SLOW_DOWN_IO;
+
+#if defined(__MIPSEB__)
+//	return (unsigned short)((*pdata >> 24) | ((*pdata >> 8) & 0x0000ff00));
+	return (unsigned short)(*pdata >> 16);
+#else
+	return (unsigned short)(*pdata);
+#endif
+}
+
+void rc32438_pci_outw(unsigned short val, unsigned long port, int slow)
+{
+	volatile DMA_Chan_t pci_dma_regs = (DMA_Chan_t)(DMA0_VirtualAddress + DMACH_memToPci * DMA_CHAN_OFFSET);
+	volatile struct DMAD_s desc;
+	DMAD_t pdesc = (DMAD_t)KSEG1ADDR(&desc);
+	u32 data;
+	volatile u32 *pdata = (u32 *)KSEG1ADDR(&data);
+	unsigned long flags;
+
+#if defined(__MIPSEB__)
+//	*pdata = (val << 24) | ((val << 8) & 0x00ff0000);
+	*pdata = (val << 16);
+#else
+	*pdata = val;
+#endif
+	pdesc->control = 0x01c00002;
+	pdesc->ca      = CPHYSADDR(pdata);
+	pdesc->devcs   = port;
+	pdesc->link    = 0;
+
+	local_irq_save(flags);
+	while (pci_dma_regs->dmac & DMAC_run_m);
+
+	pci_dma_regs->dmas = 0;
+	pci_dma_regs->dmandptr = 0;
+	pci_dma_regs->dmadptr = CPHYSADDR(pdesc);
+
+	while (!pci_dma_regs->dmas);
+	local_irq_restore(flags);
+
+	if (slow) SLOW_DOWN_IO;
+}
+
diff -uNr linux-2.6.16-rc5/Documentation/mips/IDT_RC32xxx.README idtlinux/Documentation/mips/IDT_RC32xxx.README
--- linux-2.6.16-rc5/Documentation/mips/IDT_RC32xxx.README	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/Documentation/mips/IDT_RC32xxx.README	2006-03-09 16:26:00.000000000 -0800
@@ -0,0 +1,78 @@
+README for arch/mips/idt-boards directory and sub directories
+
+Rakesh Tiwari, rtiwari@idt.com
+03/08, 2006
+
+
+1. ABOUT
+----------
+This file contains information about IDT Evaluation Boards based 
+on the Interprise family of Integrated Processors.
+
+
+2. PROCESSOR AND EVALUATION BOARD
+--------------------------------
+
+IDT's Interprise family consists of the following MIPS based processors.
+
+Core 	Processor	Eval Board   	PCI   ETHERNET	DEFAULT_CONFIG*
+-----	---------	-----------	---   --------	----------------
+4KC    	RC32438		EB438		yes	yes	rc32438_defconfig
+4KC    	RC32434/435	EB434/EB435	yes	yes	rc32434_defconfig
+RC32300	RC32365/336	EB365/EB336	yes	yes	rc32365_defconfig
+RC32300	RC32355		EB355		no	yes	rc32355_defconfig
+RC32300 RC32334		S334		yes	no	rc32334_defconfig
+
+*All default configurations are located in ~arch/mips/configs/ directory.
+
+
+3. LINUX BOOT MODE SUPPORT
+--------------------------
+All the evaluation boards support the following boot mode
+
+	a. Initramfs
+	b. NFS
+	c. Flash Boot (make zImage, required bootloader)
+	d. Self-Boot  (make rImage, doesn't need additional bootloader)
+
+
+4. I2C DRIVERS
+--------------
+Some boards supports I2C interface and the drivers
+can be found in the ~driver/i2c/busses/i2c_rc32xxx.x
+
+
+5. ETHERNET DRIVERS
+-------------------
+The processors on-board Ethernet interface drivers are located
+in ~drivers/net/rc32xxx.x
+
+
+6. ADDITIONAL INFORMATION
+-------------------------
+Additional information regarding IDT Interprise Processors and
+Evaluation boards can be obtained from
+
+Website: http://www.idt.com/?catID=58532
+Email: rischelp@idt.com
+
+
+
+7. ACKNOWLEDGEMENTS
+--------------------
+The following people have been involved in the development/testing
+of Linux on IDT development boards. Many thanks to all of them..
+
+Nebojsa Bjegovic
+Haofeng Kou
+Bernard Maruthanayagam
+Sadik Pallathu
+Kiran Rao
+Steve Shih
+Harpinder Singh
+Adisak Srinakarin
+Rakesh Tiwari
+Brandon Wong
+Calvin Young 
+
+
diff -uNr linux-2.6.16-rc5/drivers/i2c/busses/i2c-rc32355.c idtlinux/drivers/i2c/busses/i2c-rc32355.c
--- linux-2.6.16-rc5/drivers/i2c/busses/i2c-rc32355.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/drivers/i2c/busses/i2c-rc32355.c	2006-03-09 16:26:13.000000000 -0800
@@ -0,0 +1,335 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     I2C driver for IDT EB355 board
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/module.h>
+#include <linux/config.h>
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/timer.h>
+#include <linux/spinlock.h>
+#include <linux/completion.h>
+#include <linux/devfs_fs_kernel.h>
+#include <linux/i2c-dev.h>
+#include <asm/io.h>
+
+#include "i2c-rc32xxx.h"
+
+MODULE_AUTHOR("idt");
+MODULE_DESCRIPTION("I2C driver for IDT's 79RC32355 board");
+MODULE_LICENSE("GPL");
+
+
+static i2c_rc32xxx_iface 	*iface;
+static struct resource		*region;
+
+
+static u32 i2c_rc32xxx_func(struct i2c_adapter *adapter)
+{
+	return I2C_FUNC_I2C;
+}
+
+static void i2c_rc32xxx_master(void)
+{
+  	u32	i2cms = i2c->i2cms;
+
+	if (!(i2cms & I2CMS_D))
+		return;
+
+	iface->d_ints++;
+
+  	if (i2cms & I2CMS_LA) 
+	{
+		iface->la_ints++;
+    		printk ("\nI2C Master LA Detected!\n");
+  	}
+
+  	if (i2cms & I2CMS_ERR) 
+	{
+		iface->err_ints++;
+    		printk("\nI2C Master ERR Detected!\n");
+  	}
+
+  	switch (iface->state) 
+	{
+    		case I2C_STATE_IDLE:
+    		// No need to do anything...
+      			break;
+
+		case I2C_STATE_START:
+    		// DONE sending START, begin sending address
+      			i2c->i2cdo = I2CDO_DATA(iface->addr);
+      			i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_WD);
+			iface->state = I2C_STATE_ADDR;
+      			break;
+
+		case I2C_STATE_ADDR:
+    		// Count ACKs & NAKs - note, an ACK occurs when the ACK bit is cleared
+    		// (Because SDA is driven low)
+			if (i2cms & I2CMS_NA)
+				iface->num_naks++;
+			else
+				iface->num_acks++;
+
+      			// If No Slave ACknowledged the Address byte or
+		  	// Data Length is zero, then skip Write / Read Stage
+			if ((i2cms & I2CMS_NA) || !iface->len)
+			{
+        			if (iface->stop) 
+				{
+          				i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_STOP);
+          				iface->state = I2C_STATE_STOP;
+        			}
+        			else 
+				{
+  					// No STOP desired, so go to IDLE and set global variable
+          				iface->state = I2C_STATE_IDLE;
+        			}
+        			break;
+			}
+
+			iface->len--;
+			if (iface->xfer == I2C_XFER_WRITE) 
+			{
+		  		// DONE sending address, now send data
+		        	i2c->i2cdo =  I2CDO_DATA(*(iface->buf++));
+		        	i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_WD);
+		        	iface->state = I2C_STATE_WRITE_DATA;
+		        	iface->tx_bytes++;
+		      	}
+		      	else 
+			{
+		  		// DONE sending address, now read data
+				if (iface->len > 0)
+		    			// Read Another Data Byte (And ACK)
+		          		i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_RDACK);
+				else
+		    			// Almost done reading data, now send RD (not RDACK!)
+		          		i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_RD);
+		        	iface->state = I2C_STATE_READ_DATA;
+		      	}
+		      	break;
+			
+	    	case I2C_STATE_WRITE_DATA:
+    			// Count ACKs & NAKs - note, an ACK occurs when the ACK bit is cleared
+    			// (Because SDA is driven low)
+      			if (i2cms & I2CMS_NA)
+        			iface->num_naks++;
+      			else
+        			iface->num_acks++;
+
+      			if (iface->len-- > 0) 
+			{
+				// Send next data byte
+		        	i2c->i2cdo =  I2CDO_DATA(*(iface->buf++));
+				i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_WD);
+				iface->tx_bytes++;
+      			}
+      			else 
+			{
+  				// done sending data, now send STOP if desired.
+        			if (iface->stop) 
+				{
+					i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_STOP);
+					iface->state = I2C_STATE_STOP;
+        			}
+        			else 
+				{
+					// No STOP desired, so go to IDLE and set global variable
+					iface->state = I2C_STATE_IDLE;
+        			}
+      			}
+			break;
+			 
+		case I2C_STATE_READ_DATA:
+    			// Write Incoming Read data to buffer
+			*iface->buf++ = I2CDI_DATA(i2c->i2cdi);
+      			iface->rx_bytes++;
+
+    			// Count ACKs & NAKs - note, an ACK occurs when the ACK bit is cleared
+    			// (Because SDA is driven low)
+      			if (i2cms & I2CMS_NA)
+        			iface->num_naks++;
+      			else
+        			iface->num_acks++;
+				
+			if (iface->len > 0)
+			{
+        			if (iface->len-- > 1) 
+				{
+					// Read Another Data Byte (And ACK)
+					i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_RDACK);
+        			}
+        			else 
+				{
+      					// Almost done reading data, now send RD (not RDACK!)
+          				i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_RD);
+        			}
+			}
+      			else
+			{
+				// done sending data, now send STOP if desired.
+        			if (iface->stop) 
+				{
+          				i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_STOP);
+          				iface->state = I2C_STATE_STOP;
+        			}
+        			else 
+				{
+	  				// No STOP desired, so go to IDLE and set global variable
+	          			iface->state = I2C_STATE_IDLE;
+	        		}
+      			}
+      			break;
+
+    		case I2C_STATE_STOP:
+    			// Done with packet, set global variable, write NOP command, and go to idle
+      			i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_NOP);
+      			iface->state = I2C_STATE_IDLE;
+      			break;
+		
+    		default:
+      			printk ("\nErr in Default\n");
+      			break;
+  	}
+}
+
+static int i2c_rc32xxx_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
+{
+	int	i;
+
+	for (i = 0; i < num; i++, msg++) 
+	{
+		if (msg->flags & I2C_M_TEN) 
+		{
+			printk(KERN_ERR "i2c-rc32355: 10 bits addr not supported!\n");
+			break;
+		}
+
+		if (msg->flags & I2C_M_RD)
+		{
+			iface->xfer = I2C_XFER_READ;
+			iface->addr = I2CDO_ADDR(I2C_SLAVE_ADDR) | I2CDO_RD;
+		}
+		else
+		{
+			iface->xfer = I2C_XFER_WRITE;
+			iface->addr = I2CDO_ADDR(I2C_SLAVE_ADDR);
+		}
+		iface->len = msg->len;
+		iface->buf = msg->buf;
+		iface->stop = TRUE;
+
+		// Update Master State
+		i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_START);
+		iface->state = I2C_STATE_START;
+
+	  	while (iface->state != I2C_STATE_IDLE) 
+		{
+			if (i2c->i2cms & I2CMS_D)
+				i2c_rc32xxx_master();
+	 	}
+	}
+
+	return i;
+}
+
+int __init i2c_rc32355_init(void)
+{
+	int	rc;
+
+	printk("i2c-rc32355: loading driver module\n");
+
+	region = request_region(I2C_BASE, I2C_REGION, "rc32355-i2c IO");
+	
+	iface = (i2c_rc32xxx_iface *)kmalloc(sizeof(i2c_rc32xxx_iface), GFP_KERNEL);
+	if (!iface) 
+	{
+		release_region(I2C_BASE, I2C_REGION);
+		printk(KERN_ERR "i2c-rc32355: can't allocate inteface!\n");
+		return -ENOMEM;
+	}
+	memset(iface, 0, sizeof(i2c_rc32xxx_iface));
+
+	iface->algo.functionality = i2c_rc32xxx_func;
+	iface->algo.master_xfer = i2c_rc32xxx_xfer;
+
+	sprintf(iface->adap.name, "%s", "RC32355 I2C");
+	iface->adap.algo = &iface->algo;
+	i2c_set_adapdata(&iface->adap, iface);
+
+	rc = i2c_add_adapter(&iface->adap);
+	if (rc)
+	{
+		kfree(iface);
+		release_region(I2C_BASE, I2C_REGION);
+		printk(KERN_ERR "i2c-rc32355: can't add adapter!\n");
+		return rc;
+	}
+	
+	iface->state = I2C_STATE_IDLE;
+
+    	// Initialize master interface
+  	i2c->i2cc = I2CC_MEN;
+  	i2c->i2ccp =  I2CCP_DIV(I2C_PRESCALER);
+	i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_NOP);
+  	i2c->i2cmsm = I2CMS_MASK;
+  	i2c->i2cssm = I2CSS_MASK;
+
+	// Enable GPIO Alternate Function for csn[4]
+	rc355_gpiofunc |= RC355_GPIOFUNC_ALT_CSN4;
+
+	// Enable GPIO pins for I2C Bus (Alternte Functions)
+	rc355_gpiofunc |= RC355_GPIOFUNC_I2C_PINS;
+
+	return rc;
+}
+
+void __exit i2c_rc32355_exit(void)
+{
+	printk("i2c-rc32355: unloading driver module\n");
+
+	i2c_del_adapter(&iface->adap);
+	kfree(iface);		
+	if (region)
+		release_region(I2C_BASE, I2C_REGION);
+}
+
+
+module_init(i2c_rc32355_init);
+module_exit(i2c_rc32355_exit);
+
diff -uNr linux-2.6.16-rc5/drivers/i2c/busses/i2c-rc32434.c idtlinux/drivers/i2c/busses/i2c-rc32434.c
--- linux-2.6.16-rc5/drivers/i2c/busses/i2c-rc32434.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/drivers/i2c/busses/i2c-rc32434.c	2006-03-09 16:26:13.000000000 -0800
@@ -0,0 +1,330 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     I2C driver for IDT EB434 board
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+
+#include <linux/module.h>
+#include <linux/config.h>
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/timer.h>
+#include <linux/spinlock.h>
+#include <linux/completion.h>
+#include <linux/devfs_fs_kernel.h>
+#include <linux/i2c-dev.h>
+#include <asm/io.h>
+
+#include "i2c-rc32xxx.h"
+
+MODULE_AUTHOR("idt");
+MODULE_DESCRIPTION("I2C driver for IDT's 79RC32434/435 board");
+MODULE_LICENSE("GPL");
+
+
+static i2c_rc32xxx_iface 	*iface;
+static struct resource 		*region;
+
+
+static u32 i2c_rc32xxx_func(struct i2c_adapter *adapter)
+{
+	return I2C_FUNC_I2C;
+}
+
+static void i2c_rc32xxx_master(void)
+{
+  	u32	i2cms = i2c->i2cms;
+
+	if (!(i2cms & I2CMS_D))
+		return;
+
+	iface->d_ints++;
+
+  	if (i2cms & I2CMS_LA) 
+	{
+		iface->la_ints++;
+    		printk ("\nI2C Master LA Detected!\n");
+  	}
+
+  	if (i2cms & I2CMS_ERR) 
+	{
+		iface->err_ints++;
+    		printk("\nI2C Master ERR Detected!\n");
+  	}
+
+  	switch (iface->state) 
+	{
+    		case I2C_STATE_IDLE:
+    		// No need to do anything...
+      			break;
+
+		case I2C_STATE_START:
+    		// DONE sending START, begin sending address
+      			i2c->i2cdo = I2CDO_DATA(iface->addr);
+      			i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_WD);
+			iface->state = I2C_STATE_ADDR;
+      			break;
+
+		case I2C_STATE_ADDR:
+    		// Count ACKs & NAKs - note, an ACK occurs when the ACK bit is cleared
+    		// (Because SDA is driven low)
+			if (i2cms & I2CMS_NA)
+				iface->num_naks++;
+			else
+				iface->num_acks++;
+
+      			// If No Slave ACknowledged the Address byte or
+		  	// Data Length is zero, then skip Write / Read Stage
+			if ((i2cms & I2CMS_NA) || !iface->len)
+			{
+        			if (iface->stop) 
+				{
+          				i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_STOP);
+          				iface->state = I2C_STATE_STOP;
+        			}
+        			else 
+				{
+  					// No STOP desired, so go to IDLE and set global variable
+          				iface->state = I2C_STATE_IDLE;
+        			}
+        			break;
+			}
+
+			iface->len--;
+			if (iface->xfer == I2C_XFER_WRITE) 
+			{
+		  		// DONE sending address, now send data
+		        	i2c->i2cdo =  I2CDO_DATA(*(iface->buf++));
+		        	i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_WD);
+		        	iface->state = I2C_STATE_WRITE_DATA;
+		        	iface->tx_bytes++;
+		      	}
+		      	else 
+			{
+		  		// DONE sending address, now read data
+				if (iface->len > 0)
+		    			// Read Another Data Byte (And ACK)
+		          		i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_RDACK);
+				else
+		    			// Almost done reading data, now send RD (not RDACK!)
+		          		i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_RD);
+		        	iface->state = I2C_STATE_READ_DATA;
+		      	}
+		      	break;
+			
+	    	case I2C_STATE_WRITE_DATA:
+    			// Count ACKs & NAKs - note, an ACK occurs when the ACK bit is cleared
+    			// (Because SDA is driven low)
+      			if (i2cms & I2CMS_NA)
+        			iface->num_naks++;
+      			else
+        			iface->num_acks++;
+
+      			if (iface->len-- > 0) 
+			{
+				// Send next data byte
+		        	i2c->i2cdo =  I2CDO_DATA(*(iface->buf++));
+				i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_WD);
+				iface->tx_bytes++;
+      			}
+      			else 
+			{
+  				// done sending data, now send STOP if desired.
+        			if (iface->stop) 
+				{
+					i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_STOP);
+					iface->state = I2C_STATE_STOP;
+        			}
+        			else 
+				{
+					// No STOP desired, so go to IDLE and set global variable
+					iface->state = I2C_STATE_IDLE;
+        			}
+      			}
+			break;
+			 
+		case I2C_STATE_READ_DATA:
+    			// Write Incoming Read data to buffer
+			*iface->buf++ = I2CDI_DATA(i2c->i2cdi);
+      			iface->rx_bytes++;
+
+    			// Count ACKs & NAKs - note, an ACK occurs when the ACK bit is cleared
+    			// (Because SDA is driven low)
+      			if (i2cms & I2CMS_NA)
+        			iface->num_naks++;
+      			else
+        			iface->num_acks++;
+				
+			if (iface->len > 0)
+			{
+        			if (iface->len-- > 1) 
+				{
+					// Read Another Data Byte (And ACK)
+					i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_RDACK);
+        			}
+        			else 
+				{
+      					// Almost done reading data, now send RD (not RDACK!)
+          				i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_RD);
+        			}
+			}
+      			else
+			{
+				// done sending data, now send STOP if desired.
+        			if (iface->stop) 
+				{
+          				i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_STOP);
+          				iface->state = I2C_STATE_STOP;
+        			}
+        			else 
+				{
+	  				// No STOP desired, so go to IDLE and set global variable
+	          			iface->state = I2C_STATE_IDLE;
+	        		}
+      			}
+      			break;
+
+    		case I2C_STATE_STOP:
+    			// Done with packet, set global variable, write NOP command, and go to idle
+      			i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_NOP);
+      			iface->state = I2C_STATE_IDLE;
+      			break;
+		
+    		default:
+      			printk ("\nErr in Default\n");
+      			break;
+  	}
+}
+
+static int i2c_rc32xxx_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
+{
+	int	i;
+
+	for (i = 0; i < num; i++, msg++) 
+	{
+		if (msg->flags & I2C_M_TEN) 
+		{
+			printk(KERN_ERR "i2c-rc32434: 10 bits addr not supported!\n");
+			break;
+		}
+
+		if (msg->flags & I2C_M_RD)
+		{
+			iface->xfer = I2C_XFER_READ;
+			iface->addr = I2CDO_ADDR(I2C_SLAVE_ADDR) | I2CDO_RD;
+		}
+		else
+		{
+			iface->xfer = I2C_XFER_WRITE;
+			iface->addr = I2CDO_ADDR(I2C_SLAVE_ADDR);
+		}
+		iface->len = msg->len;
+		iface->buf = msg->buf;
+		iface->stop = TRUE;
+
+		// Update Master State
+		i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_START);
+		iface->state = I2C_STATE_START;
+
+	  	while (iface->state != I2C_STATE_IDLE) 
+		{
+			if (i2c->i2cms & I2CMS_D)
+				i2c_rc32xxx_master();
+	 	}
+	}
+
+	return i;
+}
+
+int __init i2c_rc32434_init(void)
+{
+	int	rc;
+
+	printk("i2c-rc32434: loading driver module\n");
+
+	region = request_region(I2C_BASE, I2C_REGION, "rc32434-i2c IO");
+	
+	iface = (i2c_rc32xxx_iface *)kmalloc(sizeof(i2c_rc32xxx_iface), GFP_KERNEL);
+	if (!iface) 
+	{
+		release_region(I2C_BASE, I2C_REGION);
+		printk(KERN_ERR "i2c-rc32434: can't allocate inteface!\n");
+		return -ENOMEM;
+	}
+	memset(iface, 0, sizeof(i2c_rc32xxx_iface));
+
+	iface->algo.functionality = i2c_rc32xxx_func;
+	iface->algo.master_xfer = i2c_rc32xxx_xfer;
+
+	sprintf(iface->adap.name, "%s", "RC32434 I2C");
+	iface->adap.algo = &iface->algo;
+	i2c_set_adapdata(&iface->adap, iface);
+
+	rc = i2c_add_adapter(&iface->adap);
+	if (rc)
+	{
+		kfree(iface);
+		release_region(I2C_BASE, I2C_REGION);
+		printk(KERN_ERR "i2c-rc32434: can't add adapter!\n");
+		return rc;
+	}
+	
+	iface->state = I2C_STATE_IDLE;
+
+    	// Initialize master interface
+  	i2c->i2cc = I2CC_MEN;
+  	i2c->i2ccp =  I2CCP_DIV(I2C_PRESCALER);
+	i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_NOP);
+  	i2c->i2cmsm = I2CMS_MASK;
+  	i2c->i2cssm = I2CSS_MASK;
+
+	return rc;
+}
+
+void __exit i2c_rc32434_exit(void)
+{
+	printk("i2c-rc32434: unloading driver module\n");
+
+	i2c_del_adapter(&iface->adap);
+	kfree(iface);		
+	if (region)
+		release_region(I2C_BASE, I2C_REGION);
+}
+
+
+module_init(i2c_rc32434_init);
+module_exit(i2c_rc32434_exit);
+
diff -uNr linux-2.6.16-rc5/drivers/i2c/busses/i2c-rc32438.c idtlinux/drivers/i2c/busses/i2c-rc32438.c
--- linux-2.6.16-rc5/drivers/i2c/busses/i2c-rc32438.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/drivers/i2c/busses/i2c-rc32438.c	2006-03-09 16:26:13.000000000 -0800
@@ -0,0 +1,331 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     I2C driver IDT EB434 board
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+
+
+#include <linux/module.h>
+#include <linux/config.h>
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/timer.h>
+#include <linux/spinlock.h>
+#include <linux/completion.h>
+#include <linux/devfs_fs_kernel.h>
+#include <linux/i2c-dev.h>
+#include <asm/io.h>
+
+#include "i2c-rc32xxx.h"
+
+MODULE_AUTHOR("idt");
+MODULE_DESCRIPTION("I2C driver for IDT's 79RC32438 board");
+MODULE_LICENSE("GPL");
+
+
+static i2c_rc32xxx_iface 	*iface;
+static struct resource 		*region;
+
+
+static u32 i2c_rc32xxx_func(struct i2c_adapter *adapter)
+{
+	return I2C_FUNC_I2C;
+}
+
+static void i2c_rc32xxx_master(void)
+{
+  	u32	i2cms = i2c->i2cms;
+
+	if (!(i2cms & I2CMS_D))
+		return;
+
+	iface->d_ints++;
+
+  	if (i2cms & I2CMS_LA) 
+	{
+		iface->la_ints++;
+    		printk ("\nI2C Master LA Detected!\n");
+  	}
+
+  	if (i2cms & I2CMS_ERR) 
+	{
+		iface->err_ints++;
+    		printk("\nI2C Master ERR Detected!\n");
+  	}
+
+  	switch (iface->state) 
+	{
+    		case I2C_STATE_IDLE:
+    		// No need to do anything...
+      			break;
+
+		case I2C_STATE_START:
+    		// DONE sending START, begin sending address
+      			i2c->i2cdo = I2CDO_DATA(iface->addr);
+      			i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_WD);
+			iface->state = I2C_STATE_ADDR;
+      			break;
+
+		case I2C_STATE_ADDR:
+    		// Count ACKs & NAKs - note, an ACK occurs when the ACK bit is cleared
+    		// (Because SDA is driven low)
+			if (i2cms & I2CMS_NA)
+				iface->num_naks++;
+			else
+				iface->num_acks++;
+
+      			// If No Slave ACknowledged the Address byte or
+		  	// Data Length is zero, then skip Write / Read Stage
+			if ((i2cms & I2CMS_NA) || !iface->len)
+			{
+        			if (iface->stop) 
+				{
+          				i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_STOP);
+          				iface->state = I2C_STATE_STOP;
+        			}
+        			else 
+				{
+  					// No STOP desired, so go to IDLE and set global variable
+          				iface->state = I2C_STATE_IDLE;
+        			}
+        			break;
+			}
+
+			iface->len--;
+			if (iface->xfer == I2C_XFER_WRITE) 
+			{
+		  		// DONE sending address, now send data
+		        	i2c->i2cdo =  I2CDO_DATA(*(iface->buf++));
+		        	i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_WD);
+		        	iface->state = I2C_STATE_WRITE_DATA;
+		        	iface->tx_bytes++;
+		      	}
+		      	else 
+			{
+		  		// DONE sending address, now read data
+				if (iface->len > 0)
+		    			// Read Another Data Byte (And ACK)
+		          		i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_RDACK);
+				else
+		    			// Almost done reading data, now send RD (not RDACK!)
+		          		i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_RD);
+		        	iface->state = I2C_STATE_READ_DATA;
+		      	}
+		      	break;
+			
+	    	case I2C_STATE_WRITE_DATA:
+    			// Count ACKs & NAKs - note, an ACK occurs when the ACK bit is cleared
+    			// (Because SDA is driven low)
+      			if (i2cms & I2CMS_NA)
+        			iface->num_naks++;
+      			else
+        			iface->num_acks++;
+
+      			if (iface->len-- > 0) 
+			{
+				// Send next data byte
+		        	i2c->i2cdo =  I2CDO_DATA(*(iface->buf++));
+				i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_WD);
+				iface->tx_bytes++;
+      			}
+      			else 
+			{
+  				// done sending data, now send STOP if desired.
+        			if (iface->stop) 
+				{
+					i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_STOP);
+					iface->state = I2C_STATE_STOP;
+        			}
+        			else 
+				{
+					// No STOP desired, so go to IDLE and set global variable
+					iface->state = I2C_STATE_IDLE;
+        			}
+      			}
+			break;
+			 
+		case I2C_STATE_READ_DATA:
+    			// Write Incoming Read data to buffer
+			*iface->buf++ = I2CDI_DATA(i2c->i2cdi);
+      			iface->rx_bytes++;
+
+    			// Count ACKs & NAKs - note, an ACK occurs when the ACK bit is cleared
+    			// (Because SDA is driven low)
+      			if (i2cms & I2CMS_NA)
+        			iface->num_naks++;
+      			else
+        			iface->num_acks++;
+				
+			if (iface->len > 0)
+			{
+        			if (iface->len-- > 1) 
+				{
+					// Read Another Data Byte (And ACK)
+					i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_RDACK);
+        			}
+        			else 
+				{
+      					// Almost done reading data, now send RD (not RDACK!)
+          				i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_RD);
+        			}
+			}
+      			else
+			{
+				// done sending data, now send STOP if desired.
+        			if (iface->stop) 
+				{
+          				i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_STOP);
+          				iface->state = I2C_STATE_STOP;
+        			}
+        			else 
+				{
+	  				// No STOP desired, so go to IDLE and set global variable
+	          			iface->state = I2C_STATE_IDLE;
+	        		}
+      			}
+      			break;
+
+    		case I2C_STATE_STOP:
+    			// Done with packet, set global variable, write NOP command, and go to idle
+      			i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_NOP);
+      			iface->state = I2C_STATE_IDLE;
+      			break;
+		
+    		default:
+      			printk ("\nErr in Default\n");
+      			break;
+  	}
+}
+
+static int i2c_rc32xxx_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
+{
+	int	i;
+
+	for (i = 0; i < num; i++, msg++) 
+	{
+		if (msg->flags & I2C_M_TEN) 
+		{
+			printk(KERN_ERR "i2c-rc32438: 10 bits addr not supported!\n");
+			break;
+		}
+
+		if (msg->flags & I2C_M_RD)
+		{
+			iface->xfer = I2C_XFER_READ;
+			iface->addr = I2CDO_ADDR(I2C_SLAVE_ADDR) | I2CDO_RD;
+		}
+		else
+		{
+			iface->xfer = I2C_XFER_WRITE;
+			iface->addr = I2CDO_ADDR(I2C_SLAVE_ADDR);
+		}
+		iface->len = msg->len;
+		iface->buf = msg->buf;
+		iface->stop = TRUE;
+
+		// Update Master State
+		i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_START);
+		iface->state = I2C_STATE_START;
+
+	  	while (iface->state != I2C_STATE_IDLE) 
+		{
+			if (i2c->i2cms & I2CMS_D)
+				i2c_rc32xxx_master();
+	 	}
+	}
+
+	return i;
+}
+
+int __init i2c_rc32438_init(void)
+{
+	int	rc;
+
+	printk("i2c-rc32438: loading driver module\n");
+
+	region = request_region(I2C_BASE, I2C_REGION, "rc32438-i2c IO");
+	
+	iface = (i2c_rc32xxx_iface *)kmalloc(sizeof(i2c_rc32xxx_iface), GFP_KERNEL);
+	if (!iface) 
+	{
+		release_region(I2C_BASE, I2C_REGION);
+		printk(KERN_ERR "i2c-rc32438: can't allocate inteface!\n");
+		return -ENOMEM;
+	}
+	memset(iface, 0, sizeof(i2c_rc32xxx_iface));
+
+	iface->algo.functionality = i2c_rc32xxx_func;
+	iface->algo.master_xfer = i2c_rc32xxx_xfer;
+
+	sprintf(iface->adap.name, "%s", "RC32438 I2C");
+	iface->adap.algo = &iface->algo;
+	i2c_set_adapdata(&iface->adap, iface);
+
+	rc = i2c_add_adapter(&iface->adap);
+	if (rc)
+	{
+		kfree(iface);
+		release_region(I2C_BASE, I2C_REGION);
+		printk(KERN_ERR "i2c-rc32438: can't add adapter!\n");
+		return rc;
+	}
+	
+	iface->state = I2C_STATE_IDLE;
+
+    	// Initialize master interface
+  	i2c->i2cc = I2CC_MEN;
+  	i2c->i2ccp =  I2CCP_DIV(I2C_PRESCALER);
+	i2c->i2cmcmd = I2CMCMD_CMD(I2CMCMD_NOP);
+  	i2c->i2cmsm = I2CMS_MASK;
+  	i2c->i2cssm = I2CSS_MASK;
+
+	return rc;
+}
+
+void __exit i2c_rc32438_exit(void)
+{
+	printk("i2c-rc32438: unloading driver module\n");
+
+	i2c_del_adapter(&iface->adap);
+	kfree(iface);		
+	if (region)
+		release_region(I2C_BASE, I2C_REGION);
+}
+
+
+module_init(i2c_rc32438_init);
+module_exit(i2c_rc32438_exit);
+
diff -uNr linux-2.6.16-rc5/drivers/i2c/busses/i2c-rc32xxx.h idtlinux/drivers/i2c/busses/i2c-rc32xxx.h
--- linux-2.6.16-rc5/drivers/i2c/busses/i2c-rc32xxx.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/drivers/i2c/busses/i2c-rc32xxx.h	2006-03-09 16:26:13.000000000 -0800
@@ -0,0 +1,237 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Low level driver for 79RC32xxx
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef _I2C_RC32xxx_
+#define _I2C_RC32xxx_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*	NOTE:!!!
+ *	Please assign your I2C device's Slave Adress here, 
+ *	otherwise it will use the default values
+ */
+#ifdef CONFIG_I2C_RC32438
+#define	I2C_SLAVE_ADDR		0x50
+#define I2C_PRESCALER		110
+#define I2C_BASE		0xb8070000
+#endif
+
+
+#ifdef CONFIG_I2C_RC32434
+#define	I2C_SLAVE_ADDR		0x50
+#define I2C_PRESCALER		250
+#define I2C_BASE		0xb8068000
+#endif
+
+#ifdef CONFIG_I2C_RC32355
+#define I2C_SLAVE_ADDR		0x57
+#define I2C_PRESCALER		63
+#define I2C_BASE		0xb8070000
+#endif
+
+
+/********************************************************************
+ * RC355 GPIO/I2C Interface
+ ********************************************************************/
+#define RC355_GPIOFUNC		0xb8040000
+
+#define RC355_GPIOFUNC_ALT_CSN4	0x00010000
+#define RC355_GPIOFUNC_I2C_PINS	0x0000c000
+
+#define rc355_gpiofunc 		(*(volatile u32*)RC355_GPIOFUNC)
+
+
+/********************************************************************
+ * I2C Interface
+ ********************************************************************/
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+typedef enum {
+	I2C_STATE_IDLE,
+	I2C_STATE_START,
+	I2C_STATE_ADDR,
+	I2C_STATE_READ_DATA,
+	I2C_STATE_WRITE_DATA,
+	I2C_STATE_STOP
+} I2C_STATE;
+
+typedef enum {
+	I2C_XFER_READ,
+	I2C_XFER_WRITE
+} I2C_XFER;
+
+typedef struct {
+	struct i2c_algorithm	algo;
+	struct i2c_adapter	adap;
+	I2C_STATE		state;
+	I2C_XFER		xfer;
+	unsigned		addr;
+	int			len;
+	u8			*buf;
+	int			stop;
+	unsigned		d_ints;
+	unsigned		la_ints;
+	unsigned		err_ints;
+	unsigned		num_acks;
+	unsigned		num_naks;
+	unsigned		tx_bytes;
+	unsigned		rx_bytes;
+} i2c_rc32xxx_iface;
+
+
+/********************************************************************
+ * I2C Registers
+ ********************************************************************/
+#define I2CC			0x00000000
+#define I2CDI			0x00000004
+#define I2CDO			0x00000008
+#define I2CCP			0x0000000c
+#define I2CMCMD			0x00000010
+#define I2CMS			0x00000014
+#define I2CMSM			0x00000018
+#define I2CSS			0x0000001c
+#define I2CSSM			0x00000020
+#define I2CSADDR		0x00000024
+#define I2CSACK			0x00000028
+
+#define I2C_REGION		0x00008000
+
+typedef struct {
+	u32	i2cc;
+	u32	i2cdi;
+	u32	i2cdo;
+	u32	i2ccp;
+	u32	i2cmcmd;
+	u32	i2cms;
+	u32	i2cmsm;
+	u32	i2css;
+	u32	i2cssm;
+	u32	i2csaddr;
+	u32	i2csack;
+} I2C;
+
+#define i2c 			((volatile I2C*)I2C_BASE)
+
+
+/********************************************************************
+ * I2CC Register
+ ********************************************************************/
+#define I2CC_MEN		(1<<0)
+#define I2CC_SEN		(1<<1)
+#define I2CC_IOM		(1<<2)
+
+
+/********************************************************************
+ * I2CDI Register
+ ********************************************************************/
+#define I2CDI_DATA(v)		((u8)((v) & 0x000000ff))
+
+
+/********************************************************************
+ * I2CDO Register
+ ********************************************************************/
+#define I2CDO_DATA(v)		((v) & 0x000000ff)
+
+#define I2CDO_ADDR(v)		((v) << 1)
+#define I2CDO_RD		1
+
+
+/********************************************************************
+ * I2CCP Register
+ ********************************************************************/
+#define I2CCP_DIV(v)		((v) & 0x0000ffff)
+
+
+/********************************************************************
+ * I2CMCMD Register
+ ********************************************************************/
+#define I2CMCMD_CMD(v)		((v) & 0x0000000f)
+
+#define I2CMCMD_NOP		0
+#define I2CMCMD_START		1
+#define I2CMCMD_STOP		2
+#define I2CMCMD_RD		4
+#define I2CMCMD_RDACK		5
+#define I2CMCMD_WD		6
+#define I2CMCMD_WDACK		7
+
+
+/********************************************************************
+ * I2CMS Register
+ ********************************************************************/
+#define I2CMS_D			(1<<0)
+#define I2CMS_NA		(1<<1)
+#define I2CMS_LA		(1<<2)
+#define I2CMS_ERR		(1<<3)
+
+#define I2CMS_MASK		0x0000000f
+
+
+/********************************************************************
+ * I2CSS Register
+ ********************************************************************/
+#define I2CSS_RR		(1<<0)
+#define I2CSS_WR		(1<<1)
+#define I2CSS_SA		(1<<2)
+#define I2CSS_TF		(1<<3)
+#define I2CSS_GC		(1<<4)
+#define I2CSS_NA		(1<<5)
+#define I2CSS_ERR		(1<<6)
+
+#define I2CSS_MASK		0x0000007f
+
+
+/********************************************************************
+ * I2CSADDR Register
+ ********************************************************************/
+#define I2CSADDR_ADDR(v)	((v) & 0x000003ff)
+#define I2CSADDR_GC		(1<<10)
+#define I2CSADDR_A10		(1<<11)
+
+
+/********************************************************************
+ * I2CSACK Register
+ ********************************************************************/
+#define I2CSACK_ACK		(1<<0)
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _I2C_RC32xxx_ */
+
diff -uNr linux-2.6.16-rc5/drivers/i2c/busses/Kconfig idtlinux/drivers/i2c/busses/Kconfig
--- linux-2.6.16-rc5/drivers/i2c/busses/Kconfig	2006-02-27 02:56:56.000000000 -0800
+++ idtlinux/drivers/i2c/busses/Kconfig	2006-03-09 16:26:13.000000000 -0800
@@ -511,4 +511,21 @@
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-mv64xxx.
 
+config I2C_RC32438
+        tristate "I2C IDT RC32438 interface"
+        depends on I2C_CHARDEV
+        depends on IDT_EB438
+	default y
+
+config I2C_RC32434
+        tristate "I2C IDT RC32434/435 interface"
+        depends on I2C_CHARDEV
+        depends on IDT_EB434
+	default y
+
+config I2C_RC32355
+        tristate "I2C IDT RC32355 interface"
+        depends on I2C_CHARDEV
+        depends on IDT_EB355
+	default y
 endmenu
diff -uNr linux-2.6.16-rc5/drivers/i2c/busses/Makefile idtlinux/drivers/i2c/busses/Makefile
--- linux-2.6.16-rc5/drivers/i2c/busses/Makefile	2006-02-27 02:56:56.000000000 -0800
+++ idtlinux/drivers/i2c/busses/Makefile	2006-03-09 16:26:13.000000000 -0800
@@ -42,6 +42,9 @@
 obj-$(CONFIG_I2C_VOODOO3)	+= i2c-voodoo3.o
 obj-$(CONFIG_SCx200_ACB)	+= scx200_acb.o
 obj-$(CONFIG_SCx200_I2C)	+= scx200_i2c.o
+obj-$(CONFIG_I2C_RC32438)       += i2c-rc32438.o
+obj-$(CONFIG_I2C_RC32434)       += i2c-rc32434.o
+obj-$(CONFIG_I2C_RC32355)       += i2c-rc32355.o
 
 ifeq ($(CONFIG_I2C_DEBUG_BUS),y)
 EXTRA_CFLAGS += -DDEBUG
diff -uNr linux-2.6.16-rc5/drivers/net/Kconfig idtlinux/drivers/net/Kconfig
--- linux-2.6.16-rc5/drivers/net/Kconfig	2006-02-27 02:56:56.000000000 -0800
+++ idtlinux/drivers/net/Kconfig	2006-03-09 16:26:07.000000000 -0800
@@ -185,6 +185,39 @@
 	  or internal device.  It is safe to say Y or M here even if your
 	  ethernet card lack MII.
 
+config IDT_RC32438_ETH
+        tristate "IDT RC32438 Local Ethernet support"
+        depends on NET_ETHERNET && (IDT_EB438 || IDT_PMC438)
+	default y
+        help
+        IDT RC32438 has two local ethernet ports. Say Y here to enable them.
+        To compile this driver as a module, choose M here.
+
+config IDT_RC32434_ETH
+        tristate "IDT RC32434/435 Local Ethernet support"
+        depends on NET_ETHERNET && (IDT_EB434 || IDT_PMC434)
+	default y
+        help
+        IDT RC32434/435 has one local ethernet port. Say Y here to enable it.
+        To compile this driver as a module, choose M here.
+
+config IDT_RC32355_ETH
+        tristate "IDT RC32355 Local Ethernet support"
+        depends on NET_ETHERNET && IDT_EB355
+	default y
+        help
+        IDT RC32365 has one local ethernet port. Say Y here to enable it.
+        To compile this driver as a module, choose M here.
+
+config IDT_RC32365_ETH
+        tristate "IDT RC32365/336 Local Ethernet support"
+        depends on NET_ETHERNET && IDT_EB365
+	default y
+        help
+        IDT RC32365/336 has two local ethernet ports. Say Y here to enable them.
+        To compile this driver as a module, choose M here.
+
+
 source "drivers/net/arm/Kconfig"
 
 config MACE
diff -uNr linux-2.6.16-rc5/drivers/net/Makefile idtlinux/drivers/net/Makefile
--- linux-2.6.16-rc5/drivers/net/Makefile	2006-02-27 02:56:56.000000000 -0800
+++ idtlinux/drivers/net/Makefile	2006-03-09 16:26:10.000000000 -0800
@@ -74,6 +74,12 @@
 # end link order section
 #
 
+obj-$(CONFIG_IDT_RC32438_ETH) += rc32438_eth.o
+obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
+obj-$(CONFIG_IDT_RC32365_ETH) += rc32365_eth.o
+obj-$(CONFIG_IDT_RC32355_ETH) += rc32355_eth.o
+
+
 obj-$(CONFIG_MII) += mii.o
 obj-$(CONFIG_PHYLIB) += phy/
 
diff -uNr linux-2.6.16-rc5/drivers/net/rc32355_eth.c idtlinux/drivers/net/rc32355_eth.c
--- linux-2.6.16-rc5/drivers/net/rc32355_eth.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/drivers/net/rc32355_eth.c	2006-03-09 16:26:04.000000000 -0800
@@ -0,0 +1,1196 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Driver for the IDT RC32355 on-chip ethernet controller.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/ctype.h>
+#include <linux/types.h>
+#include <linux/fcntl.h>
+#include <linux/interrupt.h>
+#include <linux/ptrace.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/proc_fs.h>
+#include <linux/in.h>
+#include <linux/slab.h> 
+#include <linux/string.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/errno.h>
+#include <asm/bootinfo.h>
+#include <asm/system.h>
+#include <asm/bitops.h>
+#include <asm/pgtable.h>
+#include <asm/segment.h>
+#include <asm/io.h>
+#include <asm/dma.h>
+
+#include "rc32355_eth.h"
+
+#define DRIVER_VERSION "(apr2904)"
+#define DRIVER_NAME "rc32355 Ethernet driver. " DRIVER_VERSION
+#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
+				   ((dev)->dev_addr[1]))
+#define STATION_ADDRESS_LOW(dev)  (((dev)->dev_addr[2] << 24) | \
+				   ((dev)->dev_addr[3] << 16) | \
+				   ((dev)->dev_addr[4] << 8)  | \
+				   ((dev)->dev_addr[5]))
+
+#define MII_CLOCK 1250000 					/* no more than 2.5MHz */
+#define NINTFC		2 						/* number of interface */
+static char mac[18] = "08:00:06:05:40:01"; 
+
+MODULE_AUTHOR ("IDT Inc");
+MODULE_DESCRIPTION ("rc32365 Ethernet driver");
+MODULE_LICENSE("GPL");
+MODULE_PARM(mac, "c18");
+MODULE_PARM_DESC(mac0, "MAC address for RC32355 ethernet");
+
+static struct rc32355_if_t 
+{
+	struct net_device *dev;
+  	char* mac_str;
+  	u32 iobase;
+  	int rx_dma_irq;
+  	int tx_dma_irq;
+  	int rx_ovr_irq;
+  	int tx_und_irq;		
+} rc32355_iflist[] = 
+{
+	{NULL, mac, RC32355_ETH_BASE, ETH_DMA_RX_IRQ, ETH_DMA_TX_IRQ, ETH_RX_OVR_IRQ, ETH_TX_UND_IRQ},
+	{NULL, NULL, 0, 0,0,0,0}
+};
+
+
+static int parse_mac_addr(struct net_device *dev, char* macstr)
+{
+  	int i, j;
+  	unsigned char result, value;
+	
+  	for (i=0; i<6; i++) 
+	{
+    		result = 0;
+    		if (i != 5 && *(macstr+2) != ':') {
+			ERR(__FILE__ "invalid mac address format: %d %c\n", i, *(macstr+2));
+      			return -EINVAL;
+    		}
+		
+	    	for (j=0; j<2; j++) {
+			if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' : toupper(*macstr)-'A'+10) < 16) {
+				result = result*16 + value;
+				macstr++;
+			} 
+			else {
+				ERR(__FILE__ "invalid mac address character: %c\n", *macstr);
+				return -EINVAL;
+			}
+		}
+		
+    		macstr++;
+    		dev->dev_addr[i] = result;
+  	}
+	
+  	return 0;
+}
+
+static inline void rc32355_abort_tx(struct net_device *dev)
+{
+	struct rc32355_local *lp = (struct rc32355_local *)dev->priv;
+	rc32355_abort_dma(dev, lp->tx_dma_regs);
+	
+}
+
+static inline void rc32355_abort_rx(struct net_device *dev)
+{
+	struct rc32355_local *lp = (struct rc32355_local *)dev->priv;
+	rc32355_abort_dma(dev, lp->rx_dma_regs);
+	
+}
+
+static inline void rc32355_halt_tx(struct net_device *dev)
+{
+	struct rc32355_local *lp = (struct rc32355_local *)dev->priv;
+	if (rc32355_halt_dma(lp->tx_dma_regs))
+		ERR(__FUNCTION__ ": timeout!\n");
+}
+
+static inline void rc32355_halt_rx(struct net_device *dev)
+{
+	struct rc32355_local *lp = (struct rc32355_local *)dev->priv;
+	if (rc32355_halt_dma(lp->rx_dma_regs))
+		ERR(__FUNCTION__ ": timeout!\n");
+}
+
+static inline void rc32355_start_tx(struct rc32355_local *lp, volatile rc32355_dma_desc_t* td)
+{
+  	rc32355_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
+}
+
+static inline void rc32355_start_rx(struct rc32355_local *lp, volatile rc32355_dma_desc_t* rd)
+{
+	rc32355_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
+}
+
+static inline void rc32355_chain_tx(struct rc32355_local *lp, volatile rc32355_dma_desc_t* td)
+{
+	rc32355_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
+}
+
+static inline void rc32355_chain_rx(struct rc32355_local *lp, volatile rc32355_dma_desc_t* rd)
+{
+	rc32355_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
+}
+
+#ifdef RC32355_PROC_DEBUG
+static int rc32355_read_proc(char *buf, char **start, off_t fpos,
+			     int length, int *eof, void *data)
+{
+  	struct net_device *dev = (struct net_device *)data;
+  	struct rc32355_local *lp = (struct rc32355_local *)dev->priv;
+  	int len = 0;
+	
+  	/* print out header */
+  	len += sprintf(buf + len, "\n\tRC32355 Ethernet Debug\n\n");
+	
+  	len += sprintf (buf + len,
+			"DMA halt count      = %10d, total pkt cnt = %10d\n",
+			lp->dma_halt_cnt, lp->halt_tx_count);
+  	len += sprintf (buf + len,
+			"DMA run count       = %10d, total pkt cnt = %10d\n",
+			lp->dma_run_cnt, lp->run_tx_count);
+  	len += sprintf (buf + len,
+			"DMA race count      = %10d, total pkt cnt = %10d\n",
+			lp->dma_race_cnt, lp->race_tx_count);
+  	len += sprintf (buf + len,
+			"DMA collision count = %10d, total pkt cnt = %10d\n",
+			lp->dma_collide_cnt, lp->collide_tx_count);
+	
+  	if (fpos >= len) {
+		*start = buf;
+    		*eof = 1;
+    		return 0;
+  	}
+  	*start = buf + fpos;
+  	if ((len -= fpos) > length)
+    		return length;
+	
+  	*eof = 1;
+  	return len;
+	
+}
+#endif
+
+
+/*
+ * Restart the RC32355 ethernet controller. Hold a spin lock
+ * before calling.
+ */
+static int rc32355_restart(struct net_device *dev)
+{
+  	struct rc32355_local *lp = (struct rc32355_local *)dev->priv;
+	
+  	/*
+	 * Disable interrupts
+	 */
+  	disable_irq(lp->rx_irq);
+  	disable_irq(lp->tx_irq);
+  	disable_irq(lp->ovr_irq);
+    	disable_irq(lp->und_irq);
+	
+  	/* Mask F bit in Tx DMA */
+  	local_writel(local_readl(&lp->tx_dma_regs->dmasm) | DMAS_F, &lp->tx_dma_regs->dmasm);
+    	/* Mask D bit in Rx DMA */
+  	local_writel(local_readl(&lp->rx_dma_regs->dmasm) | DMAS_D, &lp->rx_dma_regs->dmasm);
+	
+	rc32355_init(dev);
+	rc32355_multicast_list(dev);
+	
+  	enable_irq(lp->und_irq);
+  	enable_irq(lp->ovr_irq);
+  	enable_irq(lp->tx_irq);
+  	enable_irq(lp->rx_irq);
+	
+  	return 0;
+}
+
+int rc32355_init_module(void)
+{
+  	int retval=0;
+	
+	printk(KERN_INFO DRIVER_NAME " \n");
+	retval = rc32355_probe(0);
+	return retval;
+}
+
+static int rc32355_probe(int port_num)
+{
+  	struct rc32355_local *lp = NULL;
+  	struct rc32355_if_t *bif = NULL;
+  	struct net_device *dev = NULL;
+  	int i, retval,err;
+	
+	bif = &rc32355_iflist[port_num];
+	dev = alloc_etherdev(sizeof(struct rc32355_local));
+	if(!dev)
+	{ 
+		ERR("rc32438_eth: alloc_etherdev failed\n");
+		free_netdev(dev);
+		return -1;
+	}
+	
+	SET_MODULE_OWNER(dev);
+	
+	bif->dev = dev;
+	
+	
+  	if ((retval = parse_mac_addr(dev, bif->mac_str))) {
+		ERR(__FUNCTION__ ": MAC address parse failed\n");
+		retval = -EINVAL;
+		goto probe1_err_out;
+	}
+	
+	
+	/* Initialize the device structure. */
+  	if (dev->priv == NULL) {
+		lp = (struct rc32355_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
+		memset(lp, 0, sizeof(struct rc32355_local));
+	} 
+	else {
+		lp = (struct rc32355_local *)dev->priv;
+	}
+  	lp->rx_irq = bif->rx_dma_irq;
+  	lp->tx_irq = bif->tx_dma_irq;
+    	lp->ovr_irq = bif->rx_ovr_irq;
+  	lp->und_irq = bif->tx_und_irq;
+	
+  	lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
+	
+  	if (!lp->eth_regs) {
+		ERR("Can't remap eth registers\n");
+		retval = -ENXIO;
+		goto probe1_err_out;
+	}
+	
+	lp->rx_dma_regs =
+		ioremap_nocache(RC32355_DMA_BASE + 9*DMA_CHAN_OFFSET,
+				sizeof(rc32355_dma_ch_t));
+	if (!lp->rx_dma_regs) {
+		ERR("Can't remap Rx DMA registers\n");
+		retval = -ENXIO;
+		goto probe1_err_out;
+	}
+	
+	lp->tx_dma_regs =
+		ioremap_nocache(RC32355_DMA_BASE + 10*DMA_CHAN_OFFSET,
+				sizeof(rc32355_dma_ch_t));
+	if (!lp->tx_dma_regs) {
+		ERR("Can't remap Tx DMA registers\n");
+		retval = -ENXIO;
+		goto probe1_err_out;
+	}
+	
+  	lp->td_ring = (rc32355_dma_desc_t*)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
+  	
+	if (!lp->td_ring) {
+		ERR("Can't allocate descriptors\n");
+		retval = -ENOMEM;
+		goto probe1_err_out;
+	}
+	
+  	dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
+	
+  	/* now convert TD_RING pointer to KSEG1 */
+  	lp->td_ring = (rc32355_dma_desc_t *)KSEG1ADDR(lp->td_ring);
+  	lp->rd_ring = &lp->td_ring[RC32355_NUM_TDS];
+	
+  	spin_lock_init(&lp->lock);
+	dev->base_addr = bif->iobase;
+	/* just use the rx dma irq */
+	
+	dev->irq = bif->rx_dma_irq; 
+	dev->priv = lp;
+  	dev->open = rc32355_open;
+  	dev->stop = rc32355_close;
+  	dev->hard_start_xmit = rc32355_send_packet;
+  	dev->get_stats	= rc32355_get_stats;
+  	dev->set_multicast_list = &rc32355_multicast_list;
+  	dev->tx_timeout = rc32355_tx_timeout;
+  	dev->watchdog_timeo = RC32355_TX_TIMEOUT;
+	
+	lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
+	tasklet_init(lp->rx_tasklet, rc32355_rx_tasklet, (unsigned long)dev);
+	lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
+	tasklet_init(lp->tx_tasklet, rc32355_tx_tasklet, (unsigned long)dev);
+	
+	
+#ifdef RC32355_PROC_DEBUG
+  	lp->ps = create_proc_read_entry ("net/rc32355", 0, NULL,
+					 rc32355_read_proc, dev);
+#endif
+	
+	
+	if ((err = register_netdev(dev))) {
+		printk(KERN_ERR "rc32355 ethernet. Cannot register net device %d\n", err);
+		free_netdev(dev);
+		retval = -EINVAL;
+		goto probe1_err_out;
+	}
+	
+	INFO("HW Address ");
+  	for (i = 0; i < 6; i++) 
+	{
+		printk("%2.2x", dev->dev_addr[i]);
+		if (i<5)
+			printk(":");
+	}
+  	printk("\n");
+	INFO("Rx IRQ %d, Tx IRQ %d\n", bif->rx_dma_irq, bif->tx_dma_irq);
+	
+	/* Fill in the fields of the device structure with ethernet values. */
+  	ether_setup(dev);
+  	return 0;
+	
+ probe1_err_out:
+  	rc32355_cleanup_module();
+  	ERR(__FUNCTION__ " failed.  Returns %d\n", retval);
+  	return retval;
+	
+}
+
+
+/*
+ * Open/initialize the RC32355 controller.
+ *
+ * This routine should set everything up anew at each open, even
+ *  registers that "should" only need to be set once at boot, so that
+ *  there is non-reboot way to recover if something goes wrong.
+ */
+static int rc32355_open(struct net_device *dev)
+{
+	struct rc32355_local *lp = (struct rc32355_local *)dev->priv;
+	
+    	/*
+	 * Initialize
+	 */
+  	if (rc32355_init(dev)) {
+		ERR("Error: cannot open the Ethernet device\n");
+    		return -EAGAIN;
+  	}
+	
+	/*
+	 * Install the interrupt handler that handles the dma Done and
+	 * Finished Events.
+	 */
+    	if (request_irq(lp->rx_irq, &rc32355_rx_dma_interrupt,
+			SA_SHIRQ | SA_INTERRUPT,
+			"rc32355 ethernet Rx", dev)) {
+		
+    		ERR(__FUNCTION__ ": unable to get Rx DMA IRQ %d\n", lp->rx_irq);
+		return -EAGAIN;
+  	}
+  	if (request_irq(lp->tx_irq, &rc32355_tx_dma_interrupt,
+			SA_SHIRQ | SA_INTERRUPT,
+			"rc32355 ethernet Tx", dev)) {
+		ERR(__FUNCTION__ ": unable to get Tx DMA IRQ %d\n", lp->tx_irq);
+    		free_irq(lp->rx_irq, dev);
+		return -EAGAIN;
+  	}
+	
+  	/* Install handler for overrun error. */
+  	if (request_irq(lp->ovr_irq, &rc32355_ovr_interrupt,
+			SA_SHIRQ | SA_INTERRUPT,
+			"rc32355 ethernet Overflow", dev)) {
+		ERR(__FUNCTION__ ": unable to get OVR IRQ %d\n",	lp->ovr_irq);
+    		free_irq(lp->rx_irq, dev);
+    		free_irq(lp->tx_irq, dev);
+		return -EAGAIN;
+  	}
+	
+  	/* Install handler for underflow error. */
+	if (request_irq(lp->und_irq, &rc32355_und_interrupt,
+			SA_SHIRQ | SA_INTERRUPT,
+			"rc32355 ethernet Underflow", dev)) {
+		ERR(__FUNCTION__ ": unable to get UND IRQ %d\n",
+		    lp->und_irq);
+		free_irq(lp->rx_irq, dev);
+		free_irq(lp->tx_irq, dev);
+		free_irq(lp->ovr_irq, dev);
+		return -EAGAIN;
+	}
+	
+  	return 0;
+}
+
+
+
+/*
+ * Close the RC32355 device
+ */
+static int rc32355_close(struct net_device *dev)
+{
+  	struct rc32355_local *lp = (struct rc32355_local *)dev->priv;
+  	u32 tmp;
+	
+	/*
+	 * Disable interrupts
+	 */
+  	disable_irq(lp->rx_irq);
+  	disable_irq(lp->tx_irq);
+	disable_irq(lp->ovr_irq);
+    	disable_irq(lp->und_irq);
+	
+  	tmp = local_readl(&lp->tx_dma_regs->dmasm);
+  	tmp = tmp | DMAS_F | DMAS_E;
+  	local_writel(tmp, &lp->tx_dma_regs->dmasm);
+	
+  	tmp = local_readl(&lp->rx_dma_regs->dmasm);
+	tmp = tmp | DMAS_D | DMAS_H | DMAS_E;
+	local_writel(tmp, &lp->rx_dma_regs->dmasm);
+	
+  	free_irq(lp->rx_irq, dev);
+  	free_irq(lp->tx_irq, dev);
+  	free_irq(lp->ovr_irq, dev);
+    	free_irq(lp->und_irq, dev);	
+
+  	return 0;
+}
+
+
+/* transmit packet */
+static int rc32355_send_packet(struct sk_buff *skb, struct net_device *dev)
+{
+	struct rc32355_local	*lp = (struct rc32355_local *)dev->priv;
+	unsigned long 	flags;
+	u32			length;
+	volatile rc32355_dma_desc_t * td;
+	
+	spin_lock_irqsave(&lp->lock, flags);
+	
+	td = &lp->td_ring[lp->tx_chain_tail];
+	
+	//stop queue when full, drop pkts if queue already full
+	if(lp->tx_count >= (RC32355_NUM_TDS - 2)){
+		lp->tx_full = 1;
+		
+		if(lp->tx_count == (RC32355_NUM_TDS - 2)) {
+			//this pkt is about to fill the queue
+			//ERR("Tx Ring now full, queue stopped.\n");			
+			netif_stop_queue(dev);
+		}else{
+			//this pkt cannot be added to the full queue
+			//ERR("Tx ring full, packet dropped\n");
+			lp->stats.tx_dropped++;
+			dev_kfree_skb_any(skb);
+			spin_unlock_irqrestore(&lp->lock, flags);
+			return 1;
+		}	   
+	}	   
+	lp->tx_count ++;
+	
+	/* make sure payload gets written to memory */
+	dma_cache_wback_inv((unsigned long)skb->data, skb->len);
+	
+	if (lp->tx_skb[lp->tx_chain_tail] != NULL)
+		dev_kfree_skb_any(lp->tx_skb[lp->tx_chain_tail]);
+	
+	lp->tx_skb[lp->tx_chain_tail] = skb;
+	
+	length = skb->len; 
+	
+	//Setup the transmit descriptor.
+	td->curr_addr = CPHYSADDR(skb->data);
+	
+	/* Using the NDPTR to handl the DMA Race Condition */
+	if(local_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
+		if( lp->tx_chain_status == empty ) {
+			td->cmdstat = DMA_COUNT(length) |DMADESC_COF |DMADESC_IOF; /* Update tail */
+			lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32355_TDS_MASK; /* Move tail */
+			local_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
+			lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
+		}
+		else
+		{
+			td->cmdstat = DMA_COUNT(length) |DMADESC_COF|DMADESC_IOF; /* Update tail */
+			lp->td_ring[(lp->tx_chain_tail-1)& RC32355_TDS_MASK].cmdstat &=  ~(DMADESC_COF); /* Update prev */
+			lp->td_ring[(lp->tx_chain_tail-1)& RC32355_TDS_MASK].link =  CPHYSADDR(td); /* Link prev to this one */
+			lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32355_TDS_MASK; /* Move tail */
+			local_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
+			lp->tx_chain_head = lp->tx_chain_tail;  /* Move head to tail */
+			lp->tx_chain_status = empty;  
+		}
+	}
+	else
+	{
+		if( lp->tx_chain_status == empty ) {
+			td->cmdstat = DMA_COUNT(length) |DMADESC_COF|DMADESC_IOF; /* Update tail */
+			lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32355_TDS_MASK; /* Move tail */
+			lp->tx_chain_status = filled;		
+		}
+		else {
+			td->cmdstat = DMA_COUNT(length) |DMADESC_COF |DMADESC_IOF; /* Update tail */
+			lp->td_ring[(lp->tx_chain_tail-1)& RC32355_TDS_MASK].cmdstat &=  ~(DMADESC_COF);   /* Update prev */
+			lp->td_ring[(lp->tx_chain_tail-1)& RC32355_TDS_MASK].link =  CPHYSADDR(td);	 /* Link prev to this one*/
+			lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32355_TDS_MASK; /* Move tail */
+		}		
+	}
+	
+	
+	dev->trans_start = jiffies;
+	
+     	spin_unlock_irqrestore(&lp->lock, flags);
+	
+	
+  	return 0;
+}
+
+
+
+/* Ethernet Rx Overflow interrupt */
+static irqreturn_t rc32355_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+{
+  	struct net_device *dev = (struct net_device *)dev_id;
+  	struct rc32355_local *lp;
+  	unsigned int i;
+	irqreturn_t retval = IRQ_NONE;
+	
+	ASSERT(dev != NULL);
+	
+  	lp = (struct rc32355_local *)dev->priv;
+	netif_stop_queue(dev);
+	
+	//ERR("Rx overflow\n");
+	
+  	spin_lock(&lp->lock);
+	
+  	//clear OVR int (sticky bit)
+  	i = local_readl(&lp->eth_regs->ethintfc);
+  	i &= ~ETHERDMA_IN_OVR;
+  	local_writel(i, &lp->eth_regs->ethintfc);
+	
+  	// Restart interface
+  	rc32355_restart(dev);	  
+	retval = IRQ_HANDLED;
+  	spin_unlock(&lp->lock);
+	
+	return retval;
+	
+}
+
+/* Ethernet Tx Underflow interrupt */
+static irqreturn_t rc32355_und_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+{
+	struct net_device *dev = (struct net_device *)dev_id;
+	struct rc32355_local *lp;
+	unsigned int i;
+	irqreturn_t retval = IRQ_NONE;
+	
+	ASSERT(dev != NULL);
+	
+	printk(__FILE__" %d\n",__LINE__);
+	netif_stop_queue(dev);	
+	lp = (struct rc32355_local *)dev->priv;
+	
+	//ERR("Tx underflow - i/f reset\n");
+	spin_lock(&lp->lock);
+	
+	i = local_readl(&lp->eth_regs->ethintfc);
+  	i &= ~ETHERDMA_OUT_UND;
+	local_writel(i, &lp->eth_regs->ethintfc);
+	
+	/* Restart interface */
+	rc32355_restart(dev);     
+	retval = IRQ_HANDLED;
+	spin_unlock(&lp->lock);
+	return retval;
+	
+}
+
+/* Ethernet Rx DMA interrupt */
+static irqreturn_t
+rc32355_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+{
+  	struct net_device *dev = (struct net_device *)dev_id;
+  	struct rc32355_local *lp;
+  	volatile u32 dmas;
+	irqreturn_t retval = IRQ_NONE;
+	
+	ASSERT(dev != NULL);
+	
+  	lp = (struct rc32355_local *)dev->priv;
+	
+  	spin_lock(&lp->lock);
+	/* Mask D H & E bit in Rx DMA so that no interrupts are generated. The rx_tasklet
+	   will take care of un-masking them.	*/
+	
+	local_writel(local_readl(&lp->rx_dma_regs->dmasm) | DMAS_D | DMAS_E |DMAS_H, &lp->rx_dma_regs->dmasm);
+	
+  	dmas = local_readl(&lp->rx_dma_regs->dmas);
+	/* If DMA has halted, deal with it immediately. Else, process the packets in tasklet */
+	if(dmas & DMAS_H)
+	  rc32355_restart(dev);     
+	//		lp->rx_tasklet->func((unsigned long)dev);
+	
+  	else if(dmas & (DMAS_D|DMAS_E)) {
+		tasklet_hi_schedule(lp->rx_tasklet);
+		if(dmas & DMAS_E) {
+			lp->stats.rx_errors++;
+		}
+  	}
+	retval = IRQ_HANDLED;
+  	spin_unlock(&lp->lock);
+	return retval;
+}
+
+
+static void rc32355_rx_tasklet(unsigned long rx_data_dev)
+{
+	struct net_device *dev = (struct net_device *)rx_data_dev;	
+  	struct rc32355_local* lp = (struct rc32355_local *)dev->priv;
+  	volatile rc32355_dma_desc_t*  rd = &lp->rd_ring[lp->rx_next_done];
+  	struct sk_buff *skb, *skb_new;
+	u8* pkt_buf;
+  	u32 devcs, count, pkt_len;
+  	unsigned long 	flags;
+	volatile u32 dmas;
+	
+	spin_lock_irqsave(&lp->lock, flags);
+	
+  	/* keep going while we have received into more descriptors */
+        while ( (count = RC32355_RBSIZE - (u32)DMA_COUNT(rd->cmdstat)) != 0)
+    	{
+		
+		/* init the var. used for the later operations within the while loop */
+		skb_new = NULL;
+		devcs = rd->devcs;
+		pkt_len = RCVPKT_LENGTH(devcs);
+		skb = lp->rx_skb[lp->rx_next_done];
+		
+		//count = RC32355_RBSIZE - (u32)DMA_COUNT(rd->cmdstat);
+		
+		if( count != pkt_len) {
+			/*
+			 * Due to a bug in rc32355 processor, the packet length
+			 * given by devcs field and count field sometimes differ.
+			 * If that is the case, report Error.
+			 */				
+			lp->stats.rx_errors++;
+			lp->stats.rx_dropped++;
+			
+		}
+		else if (count < 64) {
+			lp->stats.rx_errors++;
+			lp->stats.rx_dropped++;
+		} 
+		else if ((devcs & ( ETHERDMA_IN_LD)) !=	ETHERDMA_IN_LD) {
+			/* Check that this is a whole packet */
+			/* WARNING: DMA_FD bit incorrectly set in rc32355 (errata ref #077) */
+			lp->stats.rx_errors++;
+			lp->stats.rx_dropped++;
+		} 
+		else if (devcs & ETHERDMA_IN_ROK) {
+					
+			/* must be the (first and) last descriptor then */
+			pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
+			
+			/* invalidate the cache before copying the buffer */
+			dma_cache_inv((unsigned long)pkt_buf, (pkt_len-4));
+			
+			/* Malloc up new buffer. */					  
+			skb_new = dev_alloc_skb(RC32355_RBSIZE + 2);							
+			
+			if (skb_new != NULL) {
+							
+				skb_new->dev = dev;
+				
+				/* Make room */
+				skb_put(skb_new, (pkt_len-4));		    
+				
+				eth_copy_and_sum(skb_new, skb->data, pkt_len-4, 0);
+				
+				skb_new->protocol = eth_type_trans(skb_new, dev);
+				
+				/* pass the packet to upper layers */
+				netif_rx(skb_new);
+				
+				dev->last_rx = jiffies;
+				lp->stats.rx_packets++;
+				lp->stats.rx_bytes += (pkt_len-4);
+				
+				if (IS_RCV_MP(devcs))
+					lp->stats.multicast++;
+			}
+			else {
+				//ERR("no memory, dropping rx packet.\n");
+				lp->stats.rx_errors++;				
+				lp->stats.rx_dropped++;				
+			}
+			
+		}				
+		else  { // Not O.K!
+			/* This should only happen if we enable accepting broken packets */
+			lp->stats.rx_errors++;
+			lp->stats.rx_dropped++;
+			
+			/* added statistics counters */
+			if (IS_RCV_CRC_ERR(devcs)) {
+				DBG(2, "RX CRC error\n");
+				lp->stats.rx_crc_errors++;
+			}
+			else if (IS_RCV_LOR_ERR(devcs)) {
+				DBG(2, "RX LOR error\n");
+				lp->stats.rx_length_errors++;
+			}
+			else if (IS_RCV_LE_ERR(devcs)) {
+				DBG(2, "RX LE error\n");
+				lp->stats.rx_length_errors++;
+			}
+			else if (IS_RCV_OVR_ERR(devcs)) {
+				/*
+				 * The overflow errors are handled through
+				 * an interrupt handler.
+				 */
+				
+				lp->stats.rx_over_errors++;
+			}
+			else if (IS_RCV_CV_ERR(devcs)) {
+				/* code violation */
+				DBG(2, "RX CV error\n");
+				lp->stats.rx_errors++;					
+			}
+			else if (IS_RCV_CES_ERR(devcs)) {
+				DBG(2, "RX Preamble error\n");
+				lp->stats.rx_errors++;					
+			}
+		}
+		
+		/* Restore current descriptor */
+		rd->devcs = 0;
+		rd->curr_addr = CPHYSADDR(skb->data);
+		rd->cmdstat = DMA_COUNT(RC32355_RBSIZE) |DMADESC_COD |DMADESC_IOD;
+		
+		lp->rd_ring[(lp->rx_next_done-1)& RC32355_RDS_MASK].cmdstat &=  ~(DMADESC_COD); 	
+		
+		lp->rx_next_done = (lp->rx_next_done + 1) & RC32355_RDS_MASK;
+		rd = &lp->rd_ring[lp->rx_next_done];
+		
+	}	
+	
+        dmas = local_readl(&lp->rx_dma_regs->dmas);
+        if(dmas & DMAS_H) {
+		rc32355_start_rx(lp,rd);
+	}
+        local_writel(~dmas, &lp->rx_dma_regs->dmas);
+    	/* Enable D bit in Rx DMA */
+  	local_writel(local_readl(&lp->rx_dma_regs->dmasm) & ~(DMAS_D | DMAS_E | DMAS_H), &lp->rx_dma_regs->dmasm); 
+   	spin_unlock_irqrestore(&lp->lock, flags);
+}
+
+
+
+/* Ethernet Tx DMA interrupt */
+static irqreturn_t
+rc32355_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+{
+  	struct net_device	*dev = (struct net_device *)dev_id;
+  	struct rc32355_local	*lp;
+  	volatile u32			dmas;
+	irqreturn_t retval = IRQ_NONE;
+	
+	ASSERT(dev != NULL);
+   	lp = (struct rc32355_local *)dev->priv;
+	
+  	spin_lock(&lp->lock);
+	/* Mask F & E bit in Tx DMA */
+	local_writel(local_readl(&lp->tx_dma_regs->dmasm) | DMAS_F |DMAS_E, &lp->tx_dma_regs->dmasm);
+	
+	
+  	dmas = local_readl(&lp->tx_dma_regs->dmas);
+  	if (dmas & DMAS_F){
+		tasklet_hi_schedule(lp->tx_tasklet);
+	}
+  	if (dmas & DMAS_E)
+    		ERR(__FUNCTION__ ": DMA error\n");
+	
+	
+  	local_writel(~dmas, &lp->tx_dma_regs->dmas);
+	
+   	if(lp->tx_chain_status == filled && (local_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
+		local_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));			
+		lp->tx_chain_status = empty;
+		lp->tx_chain_head = lp->tx_chain_tail;
+	}
+	
+	retval = IRQ_HANDLED;
+  	spin_unlock(&lp->lock);
+	return retval;
+	
+}
+
+static void rc32355_tx_tasklet(unsigned long tx_data_dev)
+{
+	struct net_device *dev = (struct net_device *)tx_data_dev;	
+  	struct rc32355_local* lp = (struct rc32355_local *)dev->priv;
+  	volatile rc32355_dma_desc_t* td = &lp->td_ring[lp->tx_next_done];
+    	u32			dmas, devcs;
+    	unsigned long 	flags;
+	
+	
+	spin_lock_irqsave(&lp->lock, flags);
+	
+  	dmas = local_readl(&lp->tx_dma_regs->dmas);
+	
+  	//process all desc that are done
+  	while(IS_DMA_FINISHED(td->cmdstat)) {
+
+  		if (	lp->tx_full == 1){
+			netif_wake_queue(dev);
+			lp->tx_full = 0;
+		}
+		
+		devcs = lp->td_ring[lp->tx_next_done].devcs;    
+		if ((devcs & (ETHERDMA_OUT_FD | ETHERDMA_OUT_LD)) != (ETHERDMA_OUT_FD | ETHERDMA_OUT_LD)) {
+			lp->stats.tx_errors++;
+	      		lp->stats.tx_dropped++;				
+			
+	      		/* should never happen */
+	      		DBG(1, __FUNCTION__ ": split tx ignored\n");
+	    	} 
+		else if (IS_TX_TOK(devcs)) {
+			
+	      		/* transmit OK */
+	      		lp->stats.tx_packets++;
+	    	} 
+		else {
+			
+	      		lp->stats.tx_dropped++;				
+			
+		      	/* underflow */
+		  	if (IS_TX_UND_ERR(devcs)) 
+				lp->stats.tx_fifo_errors++;
+			
+		      	/* oversized frame */
+		      	if (IS_TX_OF_ERR(devcs))
+				lp->stats.tx_aborted_errors++;
+			
+		      	/* excessive deferrals */
+		      	if (IS_TX_ED_ERR(devcs))
+				lp->stats.tx_carrier_errors++;
+			
+		      	/* collisions: medium busy */
+		      	if (IS_TX_EC_ERR(devcs))
+				lp->stats.collisions++;
+			
+		      	/* late collision */
+		      	if (IS_TX_LC_ERR(devcs))
+				lp->stats.tx_window_errors++;
+			
+    		}
+		
+	    	/* We must always free the original skb */
+	    	if (lp->tx_skb[lp->tx_next_done] != NULL) {
+			dev_kfree_skb_irq(lp->tx_skb[lp->tx_next_done]);
+	      		lp->tx_skb[lp->tx_next_done] = NULL;
+	    	}
+		
+		lp->td_ring[lp->tx_next_done].cmdstat = DMADESC_IOF;
+		lp->td_ring[lp->tx_next_done].devcs = ETHERDMA_OUT_FD | ETHERDMA_OUT_LD;
+		lp->td_ring[lp->tx_next_done].link = 0;
+		lp->td_ring[lp->tx_next_done].curr_addr = 0;
+	    	lp->tx_count --;
+		
+	    	/* go on to next transmission */
+	    	lp->tx_next_done = (lp->tx_next_done + 1) & RC32355_TDS_MASK;
+	    	td = &lp->td_ring[lp->tx_next_done];
+		
+  	}
+	
+   	spin_unlock_irqrestore(&lp->lock, flags);
+	
+  	/* Enable F bit in Tx DMA */
+  	local_writel(local_readl(&lp->tx_dma_regs->dmasm) & ~(DMAS_F | DMAS_E), &lp->tx_dma_regs->dmasm); 
+	
+}	
+
+/*
+ * Get the current statistics.
+ * This may be called with the device open or closed.
+ */
+static struct net_device_stats *
+rc32355_get_stats(struct net_device *dev)
+{
+  	struct rc32355_local *lp = (struct rc32355_local *)dev->priv;
+	
+	return &lp->stats;
+}
+
+
+/*
+ * Set or clear the multicast filter for this adaptor.
+ */
+static void
+rc32355_multicast_list(struct net_device *dev)
+{   	
+	/* changed to listen to broadcasts always and to treat	*/
+  	/*	   IFF bits independantly	*/
+  	struct rc32355_local *lp = (struct rc32355_local *)dev->priv;
+  	unsigned long flags;
+  	u32 recognise = ETHERARC_AB; 			/* always accept broadcasts */
+	
+  	if (dev->flags & IFF_PROMISC) 				/* set promiscuous mode */
+    		recognise |= ETHERARC_PRO;
+	
+  	if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
+    		recognise |= ETHERARC_AM;		  	/* all multicast & bcast */
+	
+  	else if (dev->mc_count > 0) {
+		DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
+		
+    		recognise |= ETHERARC_AM;		  	/* for the time being */
+  	}
+	
+  	spin_lock_irqsave(&lp->lock, flags);
+	
+  	local_writel(recognise, &lp->eth_regs->etharc);
+	
+  	spin_unlock_irqrestore(&lp->lock, flags);
+	
+}
+
+
+static void
+rc32355_tx_timeout(struct net_device *dev)
+{
+  	struct rc32355_local *lp = (struct rc32355_local *)dev->priv;
+  	unsigned long flags;
+	
+  	spin_lock_irqsave(&lp->lock, flags);
+	printk(__FILE__" %d\n",__LINE__);
+  	rc32355_restart(dev);
+  	spin_unlock_irqrestore(&lp->lock, flags);
+	
+}
+
+
+/*
+ * Initialize the RC32355 ethernet controller.
+ */
+static int rc32355_init(struct net_device *dev)
+{
+	struct rc32355_local *lp = (struct rc32355_local *)dev->priv;
+	int i, j;
+	
+	/* Disable DMA */       
+	rc32355_abort_tx(dev);
+	rc32355_abort_rx(dev); 
+	
+	/* reset ethernet logic */ 
+	local_writel(0, &lp->eth_regs->ethintfc);
+	while((local_readl(&lp->eth_regs->ethintfc) & ETHERINTFC_RIP))
+		dev->trans_start = jiffies;		
+	/* Enable Ethernet Interface */ 
+	local_writel(ETHERINTFC_EN, &lp->eth_regs->ethintfc); 
+	
+	tasklet_disable(lp->rx_tasklet);
+	tasklet_disable(lp->tx_tasklet);
+	
+	/* Initialize the transmit Descriptors */
+	for (i = 0; i < RC32355_NUM_TDS; i++) {
+    		lp->td_ring[i].cmdstat = DMADESC_IOF;
+    		lp->td_ring[i].devcs = ETHERDMA_OUT_FD | ETHERDMA_OUT_LD;
+    		lp->td_ring[i].curr_addr = 0;
+    		lp->td_ring[i].link = 0;
+    		if (lp->tx_skb[i] != NULL) {
+			/* free dangling skb */
+      			dev_kfree_skb_any(lp->tx_skb[i]);
+      			lp->tx_skb[i] = NULL;
+    		}
+	}
+    	lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = 
+    		lp->tx_count = lp->tx_full = 0;
+	lp->	tx_chain_status = empty;
+	
+	/*
+	 * Initialize the receive descriptors so that they
+	 * become a circular linked list, ie. let the last
+	 * descriptor point to the first again.
+	 */
+  	for (i=0; i<RC32355_NUM_RDS; i++) {
+		struct sk_buff *skb = lp->rx_skb[i];
+		
+		if (lp->rx_skb[i] == NULL) {
+			skb = dev_alloc_skb(RC32355_RBSIZE + 2);
+			if (skb == NULL) {
+				//ERR("No memory in the system\n");
+				for (j = 0; j < RC32355_NUM_RDS; j ++)
+					if (lp->rx_skb[j] != NULL) 
+						dev_kfree_skb_any(lp->rx_skb[j]);
+				
+				return 1;
+			}
+			else
+			{
+				skb->dev = dev;
+				lp->rx_skb[i] = skb;
+			}
+		}
+		lp->rd_ring[i].cmdstat =	DMADESC_IOD | DMA_COUNT(RC32355_RBSIZE);
+		lp->rd_ring[i].devcs = 0;
+		lp->rd_ring[i].curr_addr = CPHYSADDR(skb->data);
+		lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
+  	}
+    	/* loop back */
+  	lp->rd_ring[RC32355_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
+    	lp->rx_next_done   = 0;
+	
+#ifdef RX_DMA_CHAIN				
+  	lp->rd_ring[RC32355_NUM_RDS-1].cmdstat |= DMADESC_COD;
+  	lp->rx_chain_head = 0;
+  	lp->rx_chain_tail = 0;
+  	lp->rx_chain_status = empty;
+#endif
+	
+	local_writel(0, &lp->rx_dma_regs->dmas);
+	/* Start Rx DMA */
+	rc32355_start_rx(lp, &lp->rd_ring[0]);
+	
+  	/* Enable F bit in Tx DMA */
+  	local_writel(local_readl(&lp->tx_dma_regs->dmasm) & ~(DMAS_F | DMAS_E), &lp->tx_dma_regs->dmasm); 
+    	/* Enable D bit in Rx DMA */
+  	local_writel(local_readl(&lp->rx_dma_regs->dmasm) & ~(DMAS_D | DMAS_E), &lp->rx_dma_regs->dmasm); 
+	
+	
+	/* Accept only packets destined for this Ethernet device address */
+	local_writel(ETHERARC_AB, &lp->eth_regs->etharc); 
+	
+	/* Set all Ether station address registers to their initial values */ 
+	local_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0); 
+	local_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
+	
+	local_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1); 
+	local_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
+	
+	local_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2); 
+	local_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
+	
+	local_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3); 
+	local_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3); 
+	
+	/* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */ 
+	local_writel( ETHERMAC2_PE | ETHERMAC2_CEN | ETHERMAC2_FD,
+		&lp->eth_regs->ethmac2);  
+	//ETHERMAC2_FLC	lp->duplex_mode	ETHERMAC2_FD, 
+	
+	/* Back to back inter-packet-gap */ 
+	local_writel(0x15, &lp->eth_regs->ethipgt); 
+	/* Non - Back to back inter-packet-gap */ 
+	local_writel(0x12, &lp->eth_regs->ethipgr); 
+	
+	/* Management Clock Prescaler Divisor */
+	local_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1, &lp->eth_regs->ethmcp);	
+	
+	/* don't transmit until fifo contains 48b */
+	local_writel(48, &lp->eth_regs->ethfifott);
+	
+	local_writel(ETHERMAC1_RE, &lp->eth_regs->ethmac1);
+	
+	tasklet_enable(lp->rx_tasklet);
+	tasklet_enable(lp->tx_tasklet);
+	
+	netif_start_queue(dev);
+	
+	/* Enable Ethernet Interface */ 
+	local_writel(ETHERINTFC_EN, &lp->eth_regs->ethintfc); 
+	
+	
+	return 0; 
+	
+}
+
+
+static void rc32355_cleanup_module(void)
+{
+  	int i;
+	
+  	for (i = 0; rc32355_iflist[i].iobase; i++) {
+		struct rc32355_if_t * bif = &rc32355_iflist[i];
+    		if (bif->dev != NULL) {
+			struct rc32355_local *lp = (struct rc32355_local *)bif->dev->priv;
+      			if (lp != NULL) {
+				if (lp->eth_regs)
+					iounmap((void*)lp->eth_regs);
+				if (lp->rx_dma_regs)
+					iounmap((void*)lp->rx_dma_regs);
+				if (lp->tx_dma_regs)
+					iounmap((void*)lp->tx_dma_regs);
+				if (lp->td_ring)
+	  				kfree((void*)KSEG0ADDR(lp->td_ring));
+				
+#ifdef RC32355_PROC_DEBUG
+				if (lp->ps)
+	  				remove_proc_entry("net/rc32355", NULL);
+#endif
+				kfree(lp);
+      			}
+			
+      			unregister_netdev(bif->dev);
+			free_netdev(bif->dev);
+     			kfree(bif->dev);
+		}
+  	}
+}
+
+
+#ifndef MODULE
+
+static int __init rc32355_setup(char *options)
+{
+  	/* no options yet */
+  	return 1;
+}
+
+static int __init rc32355_setup_ethaddr(char *options)
+{
+  	memcpy(mac, options, 17);
+  	mac[17]= '\0';
+  	return 1;
+}
+
+__setup("rc3255eth=", rc32355_setup);
+
+__setup("ethaddr=", rc32355_setup_ethaddr);
+
+#endif /* !MODULE */
+
+module_init(rc32355_init_module);
+module_exit(rc32355_cleanup_module);
+
diff -uNr linux-2.6.16-rc5/drivers/net/rc32355_eth.h idtlinux/drivers/net/rc32355_eth.h
--- linux-2.6.16-rc5/drivers/net/rc32355_eth.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/drivers/net/rc32355_eth.h	2006-03-09 16:26:05.000000000 -0800
@@ -0,0 +1,203 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Driver for the IDT RC32355 on-chip ethernet controller.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+
+#ifndef RC32355_H
+#define RC32355_H
+
+#include  <asm/idt-boards/rc32300/rc32355_eth.h> 
+#include  <asm/idt-boards/rc32300/rc32355_dma.h> 
+#include  <asm/idt-boards/rc32300/rc32355.h> 
+
+
+#define RC32355_DEBUG	2
+#define RC32355_PROC_DEBUG
+
+#undef	RC32355_DEBUG
+#if 0
+#undef	RC32355_PROC_DEBUG
+#endif
+
+#ifdef RC32355_DEBUG
+
+/* use 0 for production, 1 for verification, >2 for debug */
+static int rc32355_debug = RC32355_DEBUG;
+
+/*ASSERT*/
+#define ASSERT(expr) \
+	if(!(expr)) {	\
+		printk( "Assertion failed! %s,%s,%s,line=%d\n",	\
+		#expr,__FILE__,__FUNCTION__,__LINE__);		}
+
+/*DBG*/
+#define DBG(lvl, format, arg...) if (rc32355_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
+#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
+#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)		
+
+#else
+
+#define ASSERT(expr) do {} while (0)
+#define DBG(lvl, format, arg...) do {} while (0)
+#define ERR(format, arg...) do {} while (0)
+#define WARN(format, arg...) do {} while (0)
+
+#endif
+
+/* INFO */
+#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
+
+
+
+#define ETH_DMA_RX_IRQ   GROUP1_IRQ_BASE + 9
+#define ETH_DMA_TX_IRQ   GROUP1_IRQ_BASE + 10
+#define ETH_RX_OVR_IRQ   GROUP3_IRQ_BASE + 22
+#define ETH_TX_UND_IRQ   GROUP3_IRQ_BASE + 23
+
+extern unsigned int idt_cpu_freq;
+
+/* Index to functions, as function prototypes. */
+static int rc32355_open(struct net_device *dev);
+static int rc32355_send_packet(struct sk_buff *skb, struct net_device *dev);
+//static void rc32355_mii_handler(unsigned long data);
+static irqreturn_t rc32355_ovr_interrupt(int irq, void *dev_id,
+					 struct pt_regs * regs);
+static irqreturn_t rc32355_und_interrupt(int irq, void *dev_id,
+					 struct pt_regs * regs);
+static irqreturn_t rc32355_rx_dma_interrupt(int irq, void *dev_id,
+					    struct pt_regs * regs);
+static irqreturn_t rc32355_tx_dma_interrupt(int irq, void *dev_id,
+					    struct pt_regs * regs);
+//static void rc32355_rx(struct net_device *dev);
+//static void rc32355_tx(struct net_device *dev);
+static int  rc32355_close(struct net_device *dev);
+static struct net_device_stats *rc32355_get_stats(struct net_device *dev);
+static void rc32355_multicast_list(struct net_device *dev);
+static int  rc32355_init(struct net_device *dev);
+static void rc32355_tx_timeout(struct net_device *dev);
+static void rc32355_tx_tasklet(unsigned long tx_data_dev);
+static void rc32355_rx_tasklet(unsigned long rx_data_dev);
+static void rc32355_cleanup_module(void);
+static int rc32355_probe(int port_num);
+int rc32355_init_module(void);
+
+
+/* the following must be powers of two */
+#define RC32355_NUM_RDS	 128    	/* number of receive descriptors */
+#define RC32355_NUM_TDS	 128    	/* number of transmit descriptors */
+
+#define RC32355_RBSIZE	 1536  		/* size of one resource buffer = Ether MTU */
+#define RC32355_RDS_MASK	 (RC32355_NUM_RDS-1)
+#define RC32355_TDS_MASK	 (RC32355_NUM_TDS-1)
+#define RD_RING_SIZE (RC32355_NUM_RDS * sizeof(rc32355_dma_desc_t))
+#define TD_RING_SIZE (RC32355_NUM_TDS * sizeof(rc32355_dma_desc_t))
+
+#define RC32355_TX_TIMEOUT HZ * 100
+
+enum status	{ filled,	empty};
+#define RX_DMA_CHAIN		
+
+
+/* Information that need to be kept for each board. */
+struct rc32355_local {
+	rc32355_eth_regs_t* eth_regs;
+	rc32355_dma_ch_t* rx_dma_regs;
+	rc32355_dma_ch_t* tx_dma_regs;
+ 	volatile rc32355_dma_desc_t * td_ring;  		/* transmit descriptor ring */ 
+	volatile rc32355_dma_desc_t * rd_ring;  		/* receive descriptor ring  */
+
+	struct sk_buff* tx_skb[RC32355_NUM_TDS]; 	/* skbuffs for pkt to trans */
+	struct sk_buff* rx_skb[RC32355_NUM_RDS]; 	/* skbuffs for pkt to trans */
+
+	struct tasklet_struct * rx_tasklet;
+	struct tasklet_struct * tx_tasklet;
+	
+	int	rx_next_done;
+	int	rx_chain_head;
+	int	rx_chain_tail;
+	enum status	rx_chain_status;
+	
+	int	tx_next_done;
+	int	tx_chain_head;
+	int	tx_chain_tail;
+	enum status	tx_chain_status;
+	int	tx_count;	   						/* current # of pkts waiting to be sent */
+	int	tx_full;
+	
+	struct timer_list    mii_phy_timer;
+	unsigned long duplex_mode;
+	
+	int	rx_irq;
+	int	tx_irq;
+	int  	ovr_irq;
+	int  	und_irq;		
+	
+	struct net_device_stats stats;
+	spinlock_t lock; 							/* Serialise access to device */
+	
+	/* debug /proc entry */
+	struct proc_dir_entry *ps;
+	int dma_halt_cnt;    u32 halt_tx_count;
+	int dma_collide_cnt; u32 collide_tx_count;
+	int dma_run_cnt;     u32 run_tx_count;
+	int dma_race_cnt;    u32 race_tx_count;
+};
+
+
+static inline void rc32355_abort_dma(struct net_device *dev, rc32355_dma_ch_t* ch)
+{
+	
+	if (readl(&ch->dmac) & DMAC_RUN) 
+	{
+		writel(0x10, &ch->dmac); 	
+		while (!(readl(&ch->dmas) & DMAS_H))
+			dev->trans_start = jiffies;			
+		writel(0, &ch->dmas);  
+	}
+	
+	writel(0, &ch->dmadptr); 
+	writel(0, &ch->dmandptr); 
+	
+}
+
+
+#endif /* RC32355_H */
+
+
+
+
+
+
+
+
+
+
+
+
+
diff -uNr linux-2.6.16-rc5/drivers/net/rc32365_eth.c idtlinux/drivers/net/rc32365_eth.c
--- linux-2.6.16-rc5/drivers/net/rc32365_eth.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/drivers/net/rc32365_eth.c	2006-03-09 16:26:06.000000000 -0800
@@ -0,0 +1,1300 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Driver for the IDT RC32365 on-chip ethernet controller.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/moduleparam.h>
+#include <linux/sched.h>
+#include <linux/ctype.h>
+#include <linux/types.h>
+#include <linux/fcntl.h>
+#include <linux/interrupt.h>
+#include <linux/ptrace.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/proc_fs.h>
+#include <linux/in.h>
+#include <linux/slab.h> 
+#include <linux/string.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/errno.h>
+#include <asm/bootinfo.h>
+#include <asm/system.h>
+#include <asm/bitops.h>
+#include <asm/pgtable.h>
+#include <asm/segment.h>
+#include <asm/io.h>
+#include <asm/dma.h>
+
+#include "rc32365_eth.h"
+
+#define CONFIG_IDT_NUM_ETH_PORTS 2
+
+#if CONFIG_IDT_NUM_ETH_PORTS > 2
+#error "Only 2 ports are available."
+#endif
+
+#define DRIVER_VERSION 
+
+#define DRIVER_NAME "rc32365 Ethernet driver" DRIVER_VERSION
+
+
+#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
+				   ((dev)->dev_addr[1]))
+#define STATION_ADDRESS_LOW(dev)  (((dev)->dev_addr[2] << 24) | \
+				   ((dev)->dev_addr[3] << 16) | \
+				   ((dev)->dev_addr[4] << 8)  | \
+				   ((dev)->dev_addr[5]))
+
+#define MII_CLOCK 1250000 			/* no more than 2.5MHz */
+static char mac0[18] = "08:00:06:05:40:01"; 
+static char mac1[18] = "08:00:06:05:50:01"; 
+
+MODULE_AUTHOR ("IDT Inc");
+MODULE_DESCRIPTION ("rc32365 Ethernet driver");
+MODULE_LICENSE("GPL");
+
+MODULE_PARM(mac0, "c18");
+MODULE_PARM_DESC(mac0, "MAC address for RC32365 ethernet port 0");
+MODULE_PARM(mac1, "c18");
+MODULE_PARM_DESC(mac1, "MAC address for RC32365 ethernet port 1");
+
+static void rc32365_remove(int);
+
+static struct rc32365_if_t 
+{
+	struct net_device *dev;
+	char *name;
+	char* mac_str;
+	u32 iobase;
+	u32 rxdmabase;
+	u32 txdmabase;
+	int rx_dma_irq;
+	int tx_dma_irq;
+	int rx_ovr_irq;
+	int tx_und_irq;
+	u32 ipabmc;
+} rc32365_iflist[] = 
+{
+	{
+		NULL,
+		"rc32365_eth0",
+		mac0, 
+		ETH0_PhysicalAddress, 
+		ETH0_RX_DMA_ADDR,
+		ETH0_TX_DMA_ADDR,
+		ETH0_DMA_RX_IRQ, 
+		ETH0_DMA_TX_IRQ, 
+		ETH0_RX_OVR_IRQ, 
+		ETH0_TX_UND_IRQ,
+		ETH0_IPABMC_PhysicalAddress
+	},
+	{
+		NULL, 
+		"rc32365_eth1", 
+		mac1, 
+		ETH1_PhysicalAddress, 
+		ETH1_RX_DMA_ADDR,
+		ETH1_TX_DMA_ADDR,
+		ETH1_DMA_RX_IRQ, 
+		ETH1_DMA_TX_IRQ, 
+		ETH1_RX_OVR_IRQ, 
+		ETH1_TX_UND_IRQ,
+		ETH1_IPABMC_PhysicalAddress
+	}
+};
+
+static int parse_mac_addr(struct net_device *dev, char* macstr)
+{
+	int i, j;
+	unsigned char result, value;
+	
+	for (i=0; i<6; i++) {
+		result = 0;
+		if (i != 5 && *(macstr+2) != ':') {
+			ERR("invalid mac address format: %d %c\n", i, *(macstr+2));
+			return -EINVAL;
+		}
+		
+		for (j=0; j<2; j++) {
+			if (isxdigit(*macstr) && (value = isdigit(*macstr) ? 
+						  *macstr-'0' : toupper(*macstr)-'A'+10) < 16) {
+				result = result*16 + value;
+				macstr++;
+			} 
+			else {
+				ERR("invalid mac address character: %c\n", *macstr);
+				return -EINVAL;
+			}
+		}
+		
+		macstr++;
+		dev->dev_addr[i] = result;
+	}
+	
+	return 0;
+}
+
+static inline void rc32365_abort_tx(struct net_device *dev)
+{
+	struct rc32365_local *lp = (struct rc32365_local *)dev->priv;
+	rc32365_abort_dma(dev, lp->tx_dma_regs,&lp->ipabmc->ipabmctx);
+}
+
+static inline void rc32365_abort_rx(struct net_device *dev)
+{
+	struct rc32365_local *lp = (struct rc32365_local *)dev->priv;
+	rc32365_abort_dma(dev, lp->rx_dma_regs,&lp->ipabmc->ipabmcrx);
+}
+
+static inline void rc32365_start_tx(struct rc32365_local *lp, volatile DMAD_t td)
+{
+	rc32365_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
+}
+static inline void rc32365_start_rx(struct rc32365_local *lp, volatile DMAD_t rd)
+{
+	rc32365_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
+}
+
+static inline void rc32365_chain_tx(struct rc32365_local *lp, volatile DMAD_t td)
+{
+	rc32365_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
+}
+static inline void rc32365_chain_rx(struct rc32365_local *lp, volatile DMAD_t rd)
+{
+	rc32365_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
+}
+
+#ifdef RC32365_PROC_DEBUG
+static int rc32365_read_proc(char *buf, char **start, off_t fpos,
+			     int length, int *eof, void *data)
+{
+	struct net_device *dev = (struct net_device *)data;
+	struct rc32365_local *lp = (struct rc32365_local *)dev->priv;
+	int len = 0;
+	
+	/* print out header */
+	
+	len += sprintf(buf + len, "\n\t rc32365 Ethernet Debug\n\n");
+	
+	len += sprintf (buf + len,
+			"DMA halt count      = %10d, DMA run count = %10d\n",
+			lp->dma_halt_cnt, lp->dma_run_cnt);
+	if (fpos >= len) 
+	{
+		*start = buf;
+		*eof = 1;
+		return 0;
+	}
+	*start = buf + fpos;
+	if ((len -= fpos) > length)
+		return length;
+	
+	*eof = 1;
+	return len;
+}
+#endif
+
+
+/*
+ * Restart the RC32365 ethernet controller. 
+ */
+static int rc32365_restart(struct net_device *dev)
+{
+	struct rc32365_local *lp = (struct rc32365_local *)dev->priv;
+	
+	/*
+	 * Disable interrupts
+	 */
+	disable_irq(lp->rx_irq);
+	disable_irq(lp->tx_irq);
+	if (cedar_za)
+		disable_irq(lp->ovr_irq);
+	disable_irq(lp->und_irq);
+	
+	/* Mask F Ebit in Tx DMA */
+	local_writel(local_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
+	/* Mask D H E bit in Rx DMA */
+	local_writel(local_readl(&lp->rx_dma_regs->dmasm) 
+		     | DMASM_d_m |DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
+	
+	rc32365_init(dev);
+	rc32365_multicast_list(dev);
+
+	enable_irq(lp->und_irq);
+	if (cedar_za)
+		enable_irq(lp->ovr_irq);
+	enable_irq(lp->tx_irq);
+	enable_irq(lp->rx_irq);
+	
+	return 0;
+}
+
+static int __init rc32365_init_module(void)
+{
+	int i;
+	for(i=0;i<CONFIG_IDT_NUM_ETH_PORTS;i++)
+		if (rc32365_probe(i))
+			printk(KERN_ERR DRIVER_NAME " Port 0 load failed.\n");
+	return 0;
+}
+
+static int rc32365_probe(int port_num)
+{
+	struct rc32365_if_t *bif = &rc32365_iflist[port_num];
+	struct rc32365_local *lp = NULL;
+	struct net_device *dev = NULL;
+	int i, retval;
+	
+	dev = alloc_etherdev(sizeof(struct rc32365_local));
+	if(!dev){
+		printk(KERN_ERR DRIVER_NAME "alloc_etherdev failed\n");
+		return -ENODEV;
+	}
+	
+	SET_MODULE_OWNER(dev);
+  
+	bif->dev = dev;
+  
+	if ((retval = parse_mac_addr(dev, bif->mac_str))) {
+		printk(KERN_ERR DRIVER_NAME" MAC address parse failed\n");
+		free_netdev(dev);
+		bif->dev = NULL;
+		return(-ENODEV);
+	}
+	/* Initialize the device structure. */
+	lp = (struct rc32365_local *)dev->priv;
+	
+	lp->rx_irq = bif->rx_dma_irq;
+	lp->tx_irq = bif->tx_dma_irq;
+	lp->ovr_irq = bif->rx_ovr_irq;
+	lp->und_irq = bif->tx_und_irq;
+	
+	lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
+	
+	if (!lp->eth_regs) {
+		printk(KERN_ERR DRIVER_NAME" Can't remap eth registers\n");
+		retval = -ENXIO;
+		goto probe_err_out;
+	}
+	
+	lp->ipabmc = ioremap_nocache(bif->ipabmc, sizeof(*lp->ipabmc));
+	
+	if (!lp->ipabmc){
+		printk(KERN_ERR DRIVER_NAME" Cannot map ipabmc registers.\n");
+		retval = -ENXIO;
+		goto probe_err_out;
+	}
+	
+	lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s));
+	
+	if (!lp->rx_dma_regs) {
+		printk(KERN_ERR DRIVER_NAME" Can't remap Rx DMA registers\n");
+		retval = -ENXIO;
+		goto probe_err_out;
+	}		
+
+	lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s));
+	
+	if (!lp->tx_dma_regs) {
+		printk(KERN_ERR DRIVER_NAME" Can't remap Tx DMA registers\n");
+		retval = -ENXIO;
+		goto probe_err_out;
+	}
+	
+#ifdef RC32365_PROC_DEBUG
+	lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
+					 rc32365_read_proc, dev);
+#endif
+	
+	lp->td_ring = (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
+	if (!lp->td_ring) {
+		printk(KERN_ERR DRIVER_NAME" Can't allocate descriptors\n");
+		retval = -ENOMEM;
+		goto probe_err_out;
+	}
+	dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
+  
+  	/* now convert TD_RING pointer to KSEG1 */
+	lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
+	lp->rd_ring = &lp->td_ring[RC32365_NUM_TDS];
+	
+	spin_lock_init(&lp->lock);
+  
+	/* Fill in the 'dev' fields. */
+	dev->base_addr = bif->iobase;
+	/* just use the rx dma irq */
+	dev->irq = bif->rx_dma_irq; 
+	
+	dev->priv = lp;
+	
+	dev->open = rc32365_open;
+	dev->stop = rc32365_close;
+	dev->hard_start_xmit = rc32365_send_packet;
+	dev->get_stats	= rc32365_get_stats;
+	dev->set_multicast_list = &rc32365_multicast_list;
+	dev->tx_timeout = rc32365_tx_timeout;
+	dev->watchdog_timeo = RC32365_TX_TIMEOUT;
+  
+	lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
+	if(lp->rx_tasklet == NULL){
+		printk(KERN_ERR DRIVER_NAME" Cannot allocate memory for rx_tasklet\n");
+		retval = -ENOMEM;
+		goto probe_err_out;
+	}
+	lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
+	if(lp->tx_tasklet == NULL){
+		printk(KERN_ERR DRIVER_NAME" Cannot allocate memory for tx_tasklet\n");
+		retval = -ENOMEM;
+		goto probe_err_out;
+	}
+
+	tasklet_init(lp->rx_tasklet, rc32365_rx_tasklet, (unsigned long)dev);
+	tasklet_init(lp->tx_tasklet, rc32365_tx_tasklet, (unsigned long)dev);
+	
+	if (register_netdev(dev)) {
+		printk(KERN_ERR DRIVER_NAME" Cannot register_netdev\n");
+		retval = -EINVAL;
+		goto probe_err_out;
+	}
+
+	INFO("Rx IRQ %d, Tx IRQ %d, ", bif->rx_dma_irq, bif->tx_dma_irq);
+	for (i = 0; i < 6; i++) {
+		printk("%2.2x", dev->dev_addr[i]);
+		if (i<5)
+			printk(":");
+	}
+	printk("\n");
+	return 0;
+	
+ probe_err_out:
+	rc32365_remove(port_num);
+	printk(KERN_ERR DRIVER_NAME " failed.  Returns %d\n", retval);
+	return retval;
+}
+
+/*
+ * Open/initialize the RC32365 Ethernet device.
+ *
+ * This routine should set everything up new at each open, even
+ *  registers that "should" only need to be set once at boot, so that
+ *  there is non-reboot way to recover if something goes wrong.
+ */
+static int rc32365_open(struct net_device *dev)
+{
+  struct rc32365_local *lp = (struct rc32365_local *)dev->priv;
+  
+  /*
+   * Initialize
+   */
+  if (rc32365_init(dev)) 
+    {
+      ERR("Erroe: cannot open the Ethernet device\n");
+      return -EAGAIN;
+    }
+
+  if (request_irq(lp->rx_irq, &rc32365_rx_dma_interrupt,
+		  SA_SHIRQ | SA_INTERRUPT,
+		  "rc32365 ethernet Rx", dev)) 
+    {
+      INFO("unable to get Rx DMA IRQ %d\n", lp->rx_irq);
+      return -EAGAIN;
+    }
+
+  if (request_irq(lp->tx_irq, &rc32365_tx_dma_interrupt,
+		  SA_SHIRQ | SA_INTERRUPT,
+		  "rc32365 ethernet Tx", dev)) 
+    {
+      INFO("unable to get Tx DMA IRQ %d\n", lp->tx_irq);
+      free_irq(lp->rx_irq, dev);
+      return -EAGAIN;
+    }
+
+  /* Install handler for overrun error. */
+  if (cedar_za)
+    if (request_irq(lp->ovr_irq, &rc32365_ovr_interrupt,
+		    SA_SHIRQ | SA_INTERRUPT,
+		    "Ethernet Overflow", dev)) 
+      {
+        INFO("unable to get OVR IRQ %d\n",	lp->ovr_irq);
+        free_irq(lp->rx_irq, dev);
+        free_irq(lp->tx_irq, dev);
+        return -EAGAIN;
+      }
+
+  /* Install handler for underflow error. */
+  if (request_irq(lp->und_irq, &rc32365_und_interrupt,
+		  SA_SHIRQ | SA_INTERRUPT,
+		  "Ethernet Underflow", dev)) 
+    {
+      INFO("unable to get UND IRQ %d\n",	lp->und_irq);
+      free_irq(lp->rx_irq, dev);
+      free_irq(lp->tx_irq, dev);
+      if (cedar_za)
+        free_irq(lp->ovr_irq, dev);		
+      return -EAGAIN;
+    }
+
+  /*
+    init_timer(&lp->mii_phy_timer);
+    lp->mii_phy_timer.expires = jiffies + 10 * HZ;	
+    lp->mii_phy_timer.data = (unsigned long)dev;
+    lp->mii_phy_timer.function	 = rc32365_mii_handler;
+    add_timer(&lp->mii_phy_timer);
+  */
+  
+  return 0;
+}
+
+/*
+ * Close the RC32365 ethernet device.
+ */
+static int rc32365_close(struct net_device *dev)
+{
+  struct rc32365_local *lp = (struct rc32365_local *)dev->priv;
+  u32 tmp;
+  
+  /*
+   * Disable interrupts
+   */
+  disable_irq(lp->rx_irq);
+  disable_irq(lp->tx_irq);
+  if (cedar_za)
+    disable_irq(lp->ovr_irq);
+  disable_irq(lp->und_irq);
+  
+  tmp = local_readl(&lp->tx_dma_regs->dmasm);
+  tmp = tmp | DMASM_f_m | DMASM_e_m;
+  local_writel(tmp, &lp->tx_dma_regs->dmasm);
+
+  tmp = local_readl(&lp->rx_dma_regs->dmasm);
+  tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
+  local_writel(tmp, &lp->rx_dma_regs->dmasm);
+  
+  free_irq(lp->rx_irq, dev);
+  free_irq(lp->tx_irq, dev);
+  if (cedar_za)
+    free_irq(lp->ovr_irq, dev);
+  free_irq(lp->und_irq, dev);
+
+  //Not enabled this feature at this time.
+  //del_timer(&lp->mii_phy_timer);
+  return 0;
+}
+
+
+/* transmit packet */
+static int rc32365_send_packet(struct sk_buff *skb, struct net_device *dev)
+{
+  struct rc32365_local	*lp = (struct rc32365_local *)dev->priv;
+  unsigned long 	flags;
+  u32			length;
+  DMAD_t		td;
+
+  spin_lock_irqsave(&lp->lock, flags);
+
+  td = &lp->td_ring[lp->tx_chain_tail];
+
+  /* stop queue when full, drop pkts if queue already full */
+  if(lp->tx_count >= (RC32365_NUM_TDS - 2))
+    {
+      lp->tx_full = 1;
+      
+      if(lp->tx_count == (RC32365_NUM_TDS - 2))
+	{
+	  /* this pkt is about to fill the queue */
+	  //	  ERR("Tx Ring now full, queue stopped.\n");
+	  netif_stop_queue(dev);
+	}
+      else{
+	/* this pkt cannot be added to the full queue */
+	//ERR("Tx ring full, packet dropped\n");
+	lp->stats.tx_dropped++;
+	dev_kfree_skb_any(skb);
+	spin_unlock_irqrestore(&lp->lock, flags);
+	return 1;
+      }
+    }
+  lp->tx_count ++;
+  
+  /* make sure payload gets written to memory */
+  dma_cache_wback_inv((unsigned long)skb->data, skb->len);
+
+  lp->tx_skb[lp->tx_chain_tail] = skb;
+  
+  length = skb->len;
+
+  /* Setup the transmit descriptor. */
+  td->ca = CPHYSADDR(skb->data);
+
+  if(local_readl(&(lp->tx_dma_regs->dmandptr)) == 0) 		
+    {
+      if( lp->tx_chain_status == empty ) 
+	{
+	  td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m;                                /*  Update tail      */
+	  lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32365_TDS_MASK;                           /*   Move tail       */
+	  local_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR    */
+	  lp->tx_chain_head = lp->tx_chain_tail;                                                  /* Move head to tail */
+	}
+      else
+	{
+	  td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m;                                 /* Update tail */
+	  lp->td_ring[(lp->tx_chain_tail-1)& RC32365_TDS_MASK].control &=  ~(DMAD_cof_m);           /* Link to prev */
+	  lp->td_ring[(lp->tx_chain_tail-1)& RC32365_TDS_MASK].link =  CPHYSADDR(td);               /* Link to prev */
+	  lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32365_TDS_MASK;                           /* Move tail */
+	  local_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
+	  lp->tx_chain_head = lp->tx_chain_tail;                                                  /* Move head to tail */
+	  lp->tx_chain_status = empty;  
+	}
+    }
+  else
+    {
+      if( lp->tx_chain_status == empty )
+	{
+	  td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m;                                /* Update tail */
+	  lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32365_TDS_MASK;                           /* Move tail */
+	  lp->tx_chain_status = filled;		
+	}
+      else
+	{
+	  td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m;                                /* Update tail */
+	  lp->td_ring[(lp->tx_chain_tail-1)& RC32365_TDS_MASK].control &=  ~(DMAD_cof_m);           /* Link to prev */
+	  lp->td_ring[(lp->tx_chain_tail-1)& RC32365_TDS_MASK].link =  CPHYSADDR(td);	          /* Link to prev */
+	  lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32365_TDS_MASK;                           /* Move tail */
+	}		
+    }
+
+  dev->trans_start = jiffies;
+  
+  spin_unlock_irqrestore(&lp->lock, flags);
+  
+  return 0;
+}
+
+
+/* Ethernet MII-PHY Handler */
+static void rc32365_mii_handler(unsigned long data)
+{
+  struct net_device *dev = (struct net_device *)data;		
+  struct rc32365_local *lp = (struct rc32365_local *)dev->priv;
+  unsigned long 	flags;
+  unsigned long duplex_status;
+  int port_addr = (lp->rx_irq == 0x2a? 1:0) << 8;
+
+  spin_lock_irqsave(&lp->lock, flags);
+
+  /* Two ports are using the same MII, the difference is the PHY address */
+  local_writel(0, &rc32365_eth0_regs->miimcfg);  
+  local_writel(0, &rc32365_eth0_regs->miimcmd);  
+  local_writel(port_addr |0x05, &rc32365_eth0_regs->miimaddr);  
+  local_writel(MIIMCMD_scn_m, &rc32365_eth0_regs->miimcmd);  
+  while(local_readl(&rc32365_eth0_regs->miimind) & MIIMIND_nv_m);
+
+  ERR("irq:%x		port_addr:%x	RDD:%x\n", 
+      lp->rx_irq, port_addr, local_readl(&rc32365_eth0_regs->miimrdd));
+  duplex_status = (local_readl(&rc32365_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
+  if(duplex_status != lp->duplex_mode)
+    {
+      ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", 
+	  duplex_status? "Full":"Half", lp->rx_irq == 0x2a? 1:0);		
+      lp->duplex_mode = duplex_status;
+      rc32365_restart(dev);		
+    }
+
+  lp->mii_phy_timer.expires = jiffies + 10 * HZ;	
+  add_timer(&lp->mii_phy_timer);
+  
+  spin_unlock_irqrestore(&lp->lock, flags);
+
+}
+
+/* Ethernet Rx Overflow interrupt */
+static irqreturn_t rc32365_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+{
+  struct net_device *dev = (struct net_device *)dev_id;
+  struct rc32365_local *lp;
+  unsigned int ovr;
+  irqreturn_t retval = IRQ_NONE;
+	
+  ASSERT(dev != NULL);
+  
+  lp = (struct rc32365_local *)dev->priv;
+  spin_lock(&lp->lock);
+  ovr = local_readl(&lp->eth_regs->ethintfc);
+
+  if(ovr & ETHINTFC_ovr_m)
+    {
+      netif_stop_queue(dev);
+
+      /* clear OVR bit */
+      local_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
+
+      /* Restart interface */
+      rc32365_restart(dev);	  
+      retval = IRQ_HANDLED;
+    }
+  spin_unlock(&lp->lock);
+
+  return retval;
+}
+
+/* Ethernet Tx Underflow interrupt */
+static irqreturn_t rc32365_und_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+{
+  struct net_device *dev = (struct net_device *)dev_id;
+  struct rc32365_local *lp;
+  unsigned int und;
+  irqreturn_t retval = IRQ_NONE;
+	
+  ASSERT(dev != NULL);
+	
+  lp = (struct rc32365_local *)dev->priv;
+  
+  spin_lock(&lp->lock);
+
+  und = local_readl(&lp->eth_regs->ethintfc);
+
+  if(und & ETHINTFC_und_m)
+    {
+      netif_stop_queue(dev);	
+      
+      local_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
+
+      /* Restart interface */
+      rc32365_restart(dev);    
+      retval = IRQ_HANDLED;
+    }
+	
+  spin_unlock(&lp->lock);
+	
+  return retval;
+
+}
+
+
+/* Ethernet Rx DMA interrupt */
+static irqreturn_t
+rc32365_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+{
+  struct net_device *dev = (struct net_device *)dev_id;
+  struct rc32365_local* lp;
+  volatile u32 dmas,dmasm;
+  irqreturn_t retval = IRQ_NONE;
+
+  ASSERT(dev != NULL);
+
+  lp = (struct rc32365_local *)dev->priv;
+
+  spin_lock(&lp->lock);
+  dmas = local_readl(&lp->rx_dma_regs->dmas);
+  if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m))
+    { 
+      if (cedar_za)
+        local_writel(~dmas, &lp->rx_dma_regs->dmas);
+
+      /* Mask D H E bit in Rx DMA */
+      dmasm = local_readl(&lp->rx_dma_regs->dmasm);
+      local_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
+      tasklet_hi_schedule(lp->rx_tasklet);
+
+      if (dmas & DMAS_e_m)
+	ERR(": DMA error\n");
+
+      retval = IRQ_HANDLED;
+    }
+
+  spin_unlock(&lp->lock);
+  return retval;
+}
+
+static void rc32365_rx_tasklet(unsigned long rx_data_dev)
+{
+  struct net_device *dev = (struct net_device *)rx_data_dev;	
+  struct rc32365_local* lp = (struct rc32365_local *)dev->priv;
+  volatile DMAD_t  rd = &lp->rd_ring[lp->rx_next_done];
+  struct sk_buff *skb, *skb_new;
+  u8* pkt_buf;
+  volatile u32 devcs;
+  volatile u32 dmas;
+  volatile u32 dmasm;
+  volatile u32 count;
+  volatile u32 pkt_len;
+  unsigned long 	flags;
+
+  spin_lock_irqsave(&lp->lock, flags);
+  /* keep going while we have received into more descriptors */
+  while ( (count = RC32365_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0)
+    {
+      /* init the var. used for the operations within the while loop later */
+      skb_new = NULL;
+      devcs = rd->devcs;
+      pkt_len = RCVPKT_LENGTH(devcs);
+      skb = lp->rx_skb[lp->rx_next_done];
+
+      if( count != pkt_len) 
+	{	
+	  lp->stats.rx_errors++;
+	  lp->stats.rx_dropped++;
+	}
+      else if (count < 64) 
+	{
+	  lp->stats.rx_errors++;
+	  lp->stats.rx_dropped++;
+	}
+      else if ((devcs & ( ETHRX_ld_m)) !=	ETHRX_ld_m)
+	{
+	  lp->stats.rx_errors++; 
+	}
+      else if (devcs & ETHRX_rok_m) 
+	{				
+	  pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
+	      
+	  /* invalidate the cache before copying the buffer */
+	  dma_cache_inv((unsigned long)pkt_buf, (pkt_len-4));
+	      
+	  /* Malloc up new buffer. */					  
+	  skb_new = dev_alloc_skb(RC32365_RBSIZE + 2);
+
+	  if (skb_new != NULL)
+	    {
+	      /* Make room */
+	      skb_put(skb, (pkt_len-4));		    
+	      
+	      skb->protocol = eth_type_trans(skb, dev);
+	      /* pass the packet to upper layers */
+	      netif_rx(skb);
+	      dev->last_rx = jiffies;
+	      lp->stats.rx_packets++;
+	      lp->stats.rx_bytes += (pkt_len-4);
+	      
+	      if (IS_RCV_MP(devcs))
+		lp->stats.multicast++;
+
+	      /* 16 bit align */
+	      skb_reserve(skb_new, 2);	
+
+	      skb_new->dev = dev;
+	      lp->rx_skb[lp->rx_next_done] = skb_new;
+	    }
+	  else
+	    {
+	      ERR("no memory, dropping rx packet.\n");
+	      lp->stats.rx_errors++;				
+	      lp->stats.rx_dropped++;				
+	    }
+	}				
+      else 
+	{
+
+	  /* This should only happen if we enable accepting broken packets */
+	  lp->stats.rx_errors++;
+	  lp->stats.rx_dropped++;
+	  
+	  /* added statistics counters */
+	  if (IS_RCV_CRC_ERR(devcs)) 
+	    {			  			
+	      DBG(2, "RX CRC error\n");
+	      lp->stats.rx_crc_errors++;
+	    }
+	  else if (IS_RCV_LOR_ERR(devcs)) 
+	    {			
+	      DBG(2, "RX LOR error\n");
+	      lp->stats.rx_length_errors++;
+	    }
+	  else if (IS_RCV_LE_ERR(devcs)) 
+	    {			
+	      DBG(2, "RX LE error\n");
+	      lp->stats.rx_length_errors++;
+	    }
+	  else if (IS_RCV_OVR_ERR(devcs)) 
+	    {
+	      /*
+	       * The overflow errors are handled through
+	       * an interrupt handler.
+	       */
+	      lp->stats.rx_over_errors++;
+	    }
+	  else if (IS_RCV_CV_ERR(devcs)) 
+	    {			
+	      /* code violation */
+	      DBG(2, "RX CV error\n");
+	      lp->stats.rx_errors++;					
+	    }
+	  else if (IS_RCV_CES_ERR(devcs)) 
+	    {
+	      DBG(2, "RX Preamble error\n");
+	      lp->stats.rx_errors++;					
+	    }
+	}
+      
+      /*
+       * clear the bits that let us see whether this
+       * descriptor has been used or not & reset reception
+       * length.
+       */		 
+      rd->devcs = 0;
+      /* restore descriptor's curr_addr */
+      if (skb_new)
+	rd->ca = CPHYSADDR(skb_new->data); 
+      else
+	rd->ca = CPHYSADDR(skb->data);
+
+      rd->control = DMA_COUNT(RC32365_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
+
+      lp->rd_ring[(lp->rx_next_done-1)& RC32365_RDS_MASK].control &=  ~(DMAD_cod_m); 	
+
+      lp->rx_next_done = (lp->rx_next_done + 1) & RC32365_RDS_MASK;
+      rd = &lp->rd_ring[lp->rx_next_done];
+
+    }	
+  if (!cedar_za) {
+  dmas = local_readl(&lp->rx_dma_regs->dmas);
+  if(dmas & DMAS_h_m)
+    {
+#ifdef RC32365_PROC_DEBUG
+      lp->dma_halt_cnt++;
+#endif
+      rd->devcs = 0;
+      skb = lp->rx_skb[lp->rx_next_done];
+      rd->ca = CPHYSADDR(skb->data);
+      rc32365_chain_rx(lp,rd);
+    }
+  }
+  local_writel(~dmas, &lp->rx_dma_regs->dmas);
+  /* Enable D H E bit in Rx DMA */
+  dmasm = local_readl(&lp->rx_dma_regs->dmasm);
+  local_writel(dmasm & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
+  spin_unlock_irqrestore(&lp->lock, flags);
+}
+
+
+
+/* Ethernet Tx DMA interrupt */
+static irqreturn_t
+rc32365_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+{
+  struct net_device *dev = (struct net_device *)dev_id;
+  struct rc32365_local *lp;
+  volatile u32 dmas,dmasm;
+  irqreturn_t retval = IRQ_NONE;
+
+  ASSERT(dev != NULL);
+
+  lp = (struct rc32365_local *)dev->priv;
+
+  spin_lock(&lp->lock);
+
+  dmas = local_readl(&lp->tx_dma_regs->dmas);
+
+  if (dmas & (DMAS_f_m | DMAS_e_m))
+    {
+      dmasm = local_readl(&lp->tx_dma_regs->dmasm);
+      /* Mask F E bit in Tx DMA */
+      local_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
+
+      tasklet_hi_schedule(lp->tx_tasklet);
+
+      if(lp->tx_chain_status == filled && (local_readl(&(lp->tx_dma_regs->dmandptr)) == 0))
+	{ 
+	  local_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
+	  lp->tx_chain_status = empty;
+	  lp->tx_chain_head = lp->tx_chain_tail;
+	  dev->trans_start = jiffies;
+	}
+
+      if (dmas & DMAS_e_m)
+	ERR(": DMA error\n");
+
+      retval = IRQ_HANDLED;
+    }
+
+  spin_unlock(&lp->lock);
+
+  return retval;
+}
+
+
+static void rc32365_tx_tasklet(unsigned long tx_data_dev)
+{
+  struct net_device *dev = (struct net_device *)tx_data_dev;	
+  struct rc32365_local* lp = (struct rc32365_local *)dev->priv;
+  volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
+  volatile u32	devcs;
+  unsigned long 	flags;
+  volatile u32 dmasm;
+
+  spin_lock_irqsave(&lp->lock, flags);
+
+  /* process all desc that are done */
+  while(IS_DMA_FINISHED(td->control)) 
+    {
+      if(lp->tx_full == 1)
+	{
+	  netif_wake_queue(dev);
+	  lp->tx_full = 0;
+	}
+
+      devcs = lp->td_ring[lp->tx_next_done].devcs;    
+      if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) 
+	{
+	  lp->stats.tx_errors++;
+	  lp->stats.tx_dropped++;				
+	  
+	  /* should never happen */
+	  INFO("split tx ignored\n");
+	} 
+      else if (IS_TX_TOK(devcs)) 
+	{
+	  /* transmit OK */
+	  lp->stats.tx_packets++;
+	} 
+      else 
+	{
+	  
+	  lp->stats.tx_dropped++;				
+	  
+	  /* underflow */
+	  if (IS_TX_UND_ERR(devcs)) 
+	    lp->stats.tx_fifo_errors++;
+	  
+	  /* oversized frame */
+	  if (IS_TX_OF_ERR(devcs))
+	    lp->stats.tx_aborted_errors++;
+
+	  /* excessive deferrals */
+	  if (IS_TX_ED_ERR(devcs))
+	    lp->stats.tx_carrier_errors++;
+
+	  /* collisions: medium busy */
+	  if (IS_TX_EC_ERR(devcs))
+	    lp->stats.collisions++;
+
+	  /* late collision */
+	  if (IS_TX_LC_ERR(devcs))
+	    lp->stats.tx_window_errors++;
+
+	}
+      /* We must always free the original skb */
+      if (lp->tx_skb[lp->tx_next_done] != NULL) 
+	{
+	  dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
+	  lp->tx_skb[lp->tx_next_done] = NULL;
+	}
+
+      lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
+      lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;	
+      lp->td_ring[lp->tx_next_done].link = 0;
+      lp->td_ring[lp->tx_next_done].ca = 0;
+
+      lp->tx_count--;
+
+      /* go on to next transmission */
+      lp->tx_next_done = (lp->tx_next_done + 1) & RC32365_TDS_MASK;
+      td = &lp->td_ring[lp->tx_next_done];
+      
+    }
+
+  /* Enable F E bit in Tx DMA */
+  dmasm = local_readl(&lp->tx_dma_regs->dmasm);
+  local_writel(dmasm & ~(DMASM_f_m | DMASM_e_m),&lp->tx_dma_regs->dmasm);
+	
+  spin_unlock_irqrestore(&lp->lock, flags);
+
+}
+
+/*
+ * Get the current statistics.
+ * This may be called with the device open or closed.
+ */
+static struct net_device_stats *
+rc32365_get_stats(struct net_device *dev)
+{
+  struct rc32365_local *lp = (struct rc32365_local *)dev->priv;
+  
+  return &lp->stats;
+}
+
+/*
+ * Set or clear the multicast filter for this adaptor.
+ */
+static void
+rc32365_multicast_list(struct net_device *dev)
+{   	
+  struct rc32365_local *lp = (struct rc32365_local *)dev->priv;
+  unsigned long flags;
+  u32 recognise = ETHARC_ab_m; 		/* always accept broadcasts */
+  
+  if (dev->flags & IFF_PROMISC) 			/* set promiscuous mode */
+    recognise |= ETHARC_pro_m;
+  
+  if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
+    recognise |= ETHARC_am_m;		/* all multicast & bcast */
+  
+  else if (dev->mc_count > 0) 
+    {
+      DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
+      
+      recognise |= ETHARC_am_m;		/* for the time being */
+    }
+  
+  spin_lock_irqsave(&lp->lock, flags);
+  
+  local_writel(recognise, &lp->eth_regs->etharc);
+	
+  spin_unlock_irqrestore(&lp->lock, flags);
+	
+}
+
+
+static void
+rc32365_tx_timeout(struct net_device *dev)
+{
+  struct rc32365_local *lp = (struct rc32365_local *)dev->priv;
+  unsigned long flags;
+  
+  spin_lock_irqsave(&lp->lock, flags);
+  dev->trans_start = jiffies;
+  rc32365_restart(dev);
+  spin_unlock_irqrestore(&lp->lock, flags);
+	
+}
+
+
+/*
+ * Initialize the RC32365 ethernet controller.
+ */
+static int rc32365_init(struct net_device *dev)
+{
+  struct rc32365_local *lp = (struct rc32365_local *)dev->priv;
+  int i, j;
+
+  /* Disable DMA */       
+  rc32365_abort_rx(dev);	
+  rc32365_abort_tx(dev);
+
+  /* reset ethernet logic */ 
+  local_writel(0, &lp->eth_regs->ethintfc);
+  while((local_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
+    dev->trans_start = jiffies;
+	
+  /* Enable Ethernet Interface */ 
+  local_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc); 
+
+  tasklet_disable(lp->rx_tasklet);
+  tasklet_disable(lp->tx_tasklet);
+
+  /* Initialize the transmit Descriptors */
+  for (i = 0; i < RC32365_NUM_TDS; i++) {
+    lp->td_ring[i].control = DMAD_iof_m;
+    lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
+    lp->td_ring[i].ca = 0;
+    lp->td_ring[i].link = 0;
+    if (lp->tx_skb[i] != NULL) 
+      {
+	/* free dangling skb */
+	dev_kfree_skb_any(lp->tx_skb[i]);
+	lp->tx_skb[i] = NULL;
+      }
+  }
+  lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = 
+    lp->tx_count = lp->tx_full = 0;
+  lp->tx_chain_status = empty;
+	
+  /*
+   * Initialize the receive descriptors so that they
+   * become a circular linked list, ie. let the last
+   * descriptor point to the first again.
+   */
+  for (i=0; i<RC32365_NUM_RDS; i++) 
+    {
+      struct sk_buff *skb = lp->rx_skb[i];
+
+      if (lp->rx_skb[i] == NULL) 
+	{
+	  skb = dev_alloc_skb(RC32365_RBSIZE + 2);
+	  if (skb == NULL)
+	    {
+	      printk("No memory in the system\n");
+	      for (j = 0; j < RC32365_NUM_RDS; j ++)
+		if (lp->rx_skb[j] != NULL) 
+		  dev_kfree_skb_any(lp->rx_skb[j]);
+	      return 1;
+	    }
+	  else
+	    {
+	      skb->dev = dev;
+	      skb_reserve(skb, 2);
+	      lp->rx_skb[i] = skb;
+	      lp->rd_ring[i].ca = CPHYSADDR(skb->data); 
+	    }
+	}
+      lp->rd_ring[i].control =	DMAD_iod_m | DMA_COUNT(RC32365_RBSIZE);
+      lp->rd_ring[i].devcs = 0;
+      lp->rd_ring[i].ca = CPHYSADDR(skb->data);
+      lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
+    }
+  /* loop back */
+  lp->rd_ring[RC32365_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
+  lp->rx_next_done   = 0;
+  lp->rd_ring[RC32365_NUM_RDS-1].control |= DMAD_cod_m;
+  lp->rx_chain_head = 0;
+  lp->rx_chain_tail = 0;
+  lp->rx_chain_status = empty;
+
+  local_writel(0, &lp->rx_dma_regs->dmas);
+  /* Start Rx DMA */
+  rc32365_start_rx(lp, &lp->rd_ring[0]);
+	
+  /* Enable F E bit in Tx DMA */
+  local_writel(local_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm); 
+  /* Enable D H E bit in Rx DMA */
+  local_writel(local_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m |DMASM_h_m| DMASM_e_m), &lp->rx_dma_regs->dmasm); 
+
+  /* Accept only packets destined for this Ethernet device address */
+  local_writel(ETHARC_ab_m, &lp->eth_regs->etharc); 
+ 
+  /* Set all Ether station address registers to their initial values */ 
+  local_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0); 
+  local_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
+  
+  local_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1); 
+  local_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
+	
+  local_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2); 
+  local_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
+	
+  local_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3); 
+  local_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3); 
+ 
+  /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */ 
+  local_writel( ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m,&lp->eth_regs->ethmac2);  
+
+  /* Back to back inter-packet-gap */ 
+  local_writel(0x15, &lp->eth_regs->ethipgt); 
+  /* Non - Back to back inter-packet-gap */ 
+  local_writel(0x12, &lp->eth_regs->ethipgr); 
+     
+  /* Management Clock Prescaler Divisor */
+  local_writel((idt_cpu_freq/MII_CLOCK+1) & ~1, &lp->eth_regs->ethmcp);
+
+  /* don't transmit until fifo contains 48b */
+  local_writel(48, &lp->eth_regs->ethfifott);
+  tasklet_enable(lp->rx_tasklet);
+  tasklet_enable(lp->tx_tasklet);
+
+  netif_start_queue(dev);
+
+  local_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
+
+  return 0; 
+
+}
+static void rc32365_remove(int port_num)
+{
+	struct rc32365_if_t * bif = &rc32365_iflist[port_num];
+	if (bif->dev != NULL) {
+		struct rc32365_local *lp = (struct rc32365_local *)bif->dev->priv;
+		if (lp != NULL) {
+			if (lp->rx_tasklet) {
+				tasklet_disable(lp->rx_tasklet);
+				tasklet_kill(lp->rx_tasklet);
+				kfree(lp->rx_tasklet);
+			}
+			if (lp->tx_tasklet) {
+				tasklet_disable(lp->tx_tasklet);
+				tasklet_kill(lp->tx_tasklet);
+				kfree(lp->tx_tasklet);
+			}
+			if (lp->eth_regs)
+				iounmap((void*)lp->eth_regs);
+			if (lp->ipabmc)
+				iounmap((void*)lp->ipabmc);
+			if (lp->rx_dma_regs)
+				iounmap((void*)lp->rx_dma_regs);
+			if (lp->tx_dma_regs)
+				iounmap((void*)lp->tx_dma_regs);
+			if (lp->td_ring)
+				kfree((void*)KSEG0ADDR(lp->td_ring));
+			
+#ifdef RC32365_PROC_DEBUG
+			if (lp->ps)
+				remove_proc_entry(bif->name, proc_net);
+#endif
+		}
+		unregister_netdev(bif->dev);
+		free_netdev(bif->dev);
+		bif->dev = NULL;
+	}
+}
+static void __exit rc32365_cleanup_module(void)
+{
+	int i;
+	printk(KERN_ERR " Removing.\n");
+	for(i=0;i<CONFIG_IDT_NUM_ETH_PORTS;i++)
+		rc32365_remove(i);
+	printk(KERN_INFO DRIVER_NAME " Un-loaded.\n");
+}
+
+
+#ifndef MODULE
+
+static int __init rc32365_setup(char *options)
+{
+  /* no options yet */
+  return 1;
+}
+
+static int __init rc32365_setup_ethaddr0(char *options)
+{
+  memcpy(mac0, options, 17);
+  mac0[17]= '\0';
+  return 1;
+}
+
+static int __init rc32365_setup_ethaddr1(char *options)
+{
+  memcpy(mac1, options, 17);
+  mac1[17]= '\0';
+  return 1;
+}
+
+__setup("rc32365eth=", rc32365_setup);
+
+__setup("ethaddr0=", rc32365_setup_ethaddr0);
+__setup("ethaddr1=", rc32365_setup_ethaddr1);
+
+#endif /* !MODULE */
+
+module_init(rc32365_init_module);
+module_exit(rc32365_cleanup_module);
+
diff -uNr linux-2.6.16-rc5/drivers/net/rc32365_eth.h idtlinux/drivers/net/rc32365_eth.h
--- linux-2.6.16-rc5/drivers/net/rc32365_eth.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/drivers/net/rc32365_eth.h	2006-03-09 16:26:00.000000000 -0800
@@ -0,0 +1,179 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Definitions for IDT RC32365 on-chip ethernet controller.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include  <asm/idt-boards/rc32300/rc32365_dma_v.h>
+#include  <asm/idt-boards/rc32300/rc32365_eth_v.h>
+#include  <asm/idt-boards/rc32300/rc32365_eth.h> 
+#include  <asm/idt-boards/rc32300/rc32365_dma.h> 
+#include  <asm/idt-boards/rc32300/rc32365.h> 
+
+#define RC32365_DEBUG	2
+#define RC32365_PROC_DEBUG
+#undef	RC32365_DEBUG
+//#undef	RC32365_PROC_DEBUG
+
+#ifdef RC32365_DEBUG
+
+static int rc32365_debug = RC32365_DEBUG;
+#define ASSERT(expr) \
+	if(!(expr)) {	\
+		printk( "Assertion failed! %s,%s,%s,line=%d\n",	\
+		#expr,__FILE__,__FUNCTION__,__LINE__);		}
+#define DBG(lvl, format, arg...) \
+         if (rc32365_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
+#else
+#define ASSERT(expr) do {} while (0)
+#define DBG(lvl, format, arg...) do {} while (0)
+#endif
+
+#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
+#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)		
+#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
+
+#define ETH0_DMA_RX_IRQ   (GROUP1_IRQ_BASE + 0)
+#define ETH0_DMA_TX_IRQ   (GROUP1_IRQ_BASE + 1)
+#define ETH0_RX_OVR_IRQ   (GROUP3_IRQ_BASE + 4)
+#define ETH0_TX_UND_IRQ   (GROUP3_IRQ_BASE + 5)
+#define ETH1_DMA_RX_IRQ   (GROUP1_IRQ_BASE + 2)
+#define ETH1_DMA_TX_IRQ   (GROUP1_IRQ_BASE + 3)
+#define ETH1_RX_OVR_IRQ   (GROUP3_IRQ_BASE + 7)
+#define ETH1_TX_UND_IRQ   (GROUP3_IRQ_BASE + 8)
+
+#define ETH0_RX_DMA_ADDR  (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
+#define ETH0_TX_DMA_ADDR  (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
+#define ETH1_RX_DMA_ADDR  (DMA0_PhysicalAddress + 2*DMA_CHAN_OFFSET)
+#define ETH1_TX_DMA_ADDR  (DMA0_PhysicalAddress + 3*DMA_CHAN_OFFSET)
+
+#define RC32365_NUM_RDS	 128    /* number of receive descriptors */
+#define RC32365_NUM_TDS	 128    /* number of transmit descriptors */
+
+#define RC32365_RBSIZE	 1536  /* size of one resource buffer = Ether MTU */
+#define RC32365_RDS_MASK (RC32365_NUM_RDS-1)
+#define RC32365_TDS_MASK (RC32365_NUM_TDS-1)
+#define RD_RING_SIZE	 (RC32365_NUM_RDS * sizeof(struct DMAD_s))
+#define TD_RING_SIZE	 (RC32365_NUM_TDS * sizeof(struct DMAD_s))
+
+//#define RC32365_TX_TIMEOUT HZ/4
+#define RC32365_TX_TIMEOUT HZ * 100
+
+#define rc32365_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
+#define rc32365_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
+
+enum status	{ filled,	empty};
+
+extern unsigned int idt_cpu_freq;
+
+
+/* Index to functions, as function prototypes. */
+static int rc32365_open(struct net_device *dev);
+static int rc32365_send_packet(struct sk_buff *skb, struct net_device *dev);
+static void rc32365_mii_handler(unsigned long data);
+static irqreturn_t rc32365_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs);
+static irqreturn_t rc32365_und_interrupt(int irq, void *dev_id, struct pt_regs * regs);
+static irqreturn_t rc32365_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
+static irqreturn_t rc32365_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
+static int  rc32365_close(struct net_device *dev);
+static struct net_device_stats *rc32365_get_stats(struct net_device *dev);
+static void rc32365_multicast_list(struct net_device *dev);
+static int  rc32365_init(struct net_device *dev);
+static void rc32365_tx_timeout(struct net_device *dev);
+static void rc32365_rx_tasklet(unsigned long rx_data_dev);
+static void rc32365_tx_tasklet(unsigned long tx_data_dev);
+static void rc32365_cleanup_module(void);
+static int rc32365_probe(int port_num);
+
+
+/* Information that need to be kept for each board. */
+struct rc32365_local {
+	ETH_t  eth_regs;
+	DMA_Chan_t  rx_dma_regs;
+	DMA_Chan_t  tx_dma_regs;
+	IPABM_ETH_t ipabmc;
+	
+	volatile DMAD_t   td_ring; 			/* transmit descriptor ring */ 
+	volatile DMAD_t   rd_ring; 			/* receive descriptor ring  */
+	
+	struct sk_buff* tx_skb[RC32365_NUM_TDS]; 	/* skbuffs for pkt to trans */
+	struct sk_buff* rx_skb[RC32365_NUM_RDS]; 	/* skbuffs for pkt to trans */
+	
+	struct tasklet_struct * rx_tasklet;
+	struct tasklet_struct * tx_tasklet;
+	struct tasklet_struct * ovr_tasklet;
+	
+	int	rx_next_done;
+	int	rx_chain_head;
+	int	rx_chain_tail;
+	enum status	rx_chain_status;
+	
+	int	tx_next_done;
+	int	tx_chain_head;
+	int	tx_chain_tail;
+	enum status	tx_chain_status;
+	int	tx_count;	                        /* current # of pkts waiting to be sent */
+	int	tx_full;
+	struct timer_list    mii_phy_timer;
+	unsigned long duplex_mode;
+	
+	int	rx_irq;
+	int	tx_irq;
+	int	ovr_irq;
+	int	und_irq;
+	
+	struct net_device_stats stats;
+	spinlock_t lock; 				
+	
+	/* debug /proc entry */
+	struct proc_dir_entry *ps;
+	int dma_halt_cnt;  int dma_run_cnt;
+};
+
+static inline void rc32365_abort_dma(struct net_device *dev, DMA_Chan_t ch, volatile u32 *ipabmcx)
+{
+	volatile u32 ipabmc;
+#ifdef RC32365_PROC_DEBUG
+	struct rc32365_local *lp = (struct rc32365_local *)dev->priv;
+#endif
+	if (local_readl(&ch->dmac) & DMAC_run_m) 
+	{
+		ipabmc = local_readl(ipabmcx);
+		local_writel(ipabmc|0x00004000,ipabmcx);
+		local_writel(0x10, &ch->dmac); 	
+		local_writel(ipabmc,ipabmcx);
+		while (!(local_readl(&ch->dmas) & DMAS_h_m))
+			dev->trans_start = jiffies;			
+		local_writel(0, &ch->dmas);  
+#ifdef RC32365_PROC_DEBUG
+		lp->dma_run_cnt++;
+#endif
+	}
+	local_writel(0, &ch->dmandptr); 
+	local_writel(0, &ch->dmadptr); 
+}
diff -uNr linux-2.6.16-rc5/drivers/net/rc32434_eth.c idtlinux/drivers/net/rc32434_eth.c
--- linux-2.6.16-rc5/drivers/net/rc32434_eth.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/drivers/net/rc32434_eth.c	2006-03-09 16:26:04.000000000 -0800
@@ -0,0 +1,1251 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Driver for the IDT RC32434/435 on-chip ethernet controller.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/moduleparam.h>
+#include <linux/sched.h>
+#include <linux/ctype.h>
+#include <linux/types.h>
+#include <linux/fcntl.h>
+#include <linux/interrupt.h>
+#include <linux/ptrace.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/proc_fs.h>
+#include <linux/in.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/errno.h>
+#include <asm/bootinfo.h>
+#include <asm/system.h>
+#include <asm/bitops.h>
+#include <asm/pgtable.h>
+#include <asm/segment.h>
+#include <asm/io.h>
+#include <asm/dma.h>
+
+#include "rc32434_eth.h"
+
+#define DRIVER_VERSION "(mar2904)"
+
+#define DRIVER_NAME "rc32434/435 Ethernet driver. " DRIVER_VERSION
+
+
+#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
+			           ((dev)->dev_addr[1]))
+#define STATION_ADDRESS_LOW(dev)  (((dev)->dev_addr[2] << 24) | \
+				   ((dev)->dev_addr[3] << 16) | \
+				   ((dev)->dev_addr[4] << 8)  | \
+				   ((dev)->dev_addr[5]))
+
+#define MII_CLOCK 1250000 				/* no more than 2.5MHz */
+static char mac0[18] = "08:00:06:05:40:01"; 
+
+MODULE_PARM(mac0, "c18");
+MODULE_PARM_DESC(mac0, "MAC address for RC32434/435 ethernet0");
+
+static struct rc32434_if_t {
+	char *name;
+	struct net_device *dev;
+	char* mac_str;
+	int weight;
+	u32 iobase;
+	u32 rxdmabase;
+	u32 txdmabase;
+	int rx_dma_irq;
+	int tx_dma_irq;
+	int rx_ovr_irq;
+	int tx_und_irq;			
+} rc32434_iflist[] = 
+{
+	{
+		"rc32434_eth0",      NULL,       mac0, 
+		64,
+		ETH0_PhysicalAddress,
+		ETH0_RX_DMA_ADDR,
+		ETH0_TX_DMA_ADDR,
+		ETH0_DMA_RX_IRQ,
+		ETH0_DMA_TX_IRQ,
+		ETH0_RX_OVR_IRQ,
+		ETH0_TX_UND_IRQ
+	}
+};
+
+
+static int parse_mac_addr(struct net_device *dev, char* macstr)
+{
+	int i, j;
+	unsigned char result, value;
+	
+	for (i=0; i<6; i++) {
+		result = 0;
+		if (i != 5 && *(macstr+2) != ':') {
+			ERR("invalid mac address format: %d %c\n",
+			    i, *(macstr+2));
+			return -EINVAL;
+		}				
+		for (j=0; j<2; j++) {
+			if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' : 
+						  toupper(*macstr)-'A'+10) < 16) {
+				result = result*16 + value;
+				macstr++;
+			} 
+			else {
+				ERR("invalid mac address "
+				    "character: %c\n", *macstr);
+				return -EINVAL;
+			}
+		}
+		
+		macstr++; 
+		dev->dev_addr[i] = result;
+	}
+	
+	return 0;
+}
+
+
+
+static inline void rc32434_abort_tx(struct net_device *dev)
+{
+	struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
+	rc32434_abort_dma(dev, lp->tx_dma_regs);
+	
+}
+
+static inline void rc32434_abort_rx(struct net_device *dev)
+{
+	struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
+	rc32434_abort_dma(dev, lp->rx_dma_regs);
+	
+}
+
+static inline void rc32434_start_tx(struct rc32434_local *lp,  volatile DMAD_t td)
+{
+	rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
+}
+
+static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
+{
+	rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
+}
+
+static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
+{
+	rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
+}
+
+static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
+{
+	rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
+}
+
+#ifdef RC32434_PROC_DEBUG
+static int rc32434_read_proc(char *buf, char **start, off_t fpos,
+			     int length, int *eof, void *data)
+{
+	struct net_device *dev = (struct net_device *)data;
+	struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
+	int len = 0;
+	
+	/* print out header */
+	len += sprintf(buf + len, "\n\tRC32434 Ethernet Debug\n\n");
+	len += sprintf (buf + len,
+			"DMA halt count      = %10d, DMA run count = %10d\n",
+			lp->dma_halt_cnt, lp->dma_run_cnt);
+	
+	if (fpos >= len) {
+		*start = buf;
+		*eof = 1;
+		return 0;
+	}
+	*start = buf + fpos;
+	
+	if ((len -= fpos) > length) 
+		return length;	
+	*eof = 1;
+	
+	return len;
+	
+}
+#endif
+
+
+/*
+ * Restart the RC32434 ethernet controller. 
+ */
+static int rc32434_restart(struct net_device *dev)
+{
+	struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
+	
+	/*
+	 * Disable interrupts
+	 */
+	disable_irq(lp->rx_irq);
+	disable_irq(lp->tx_irq);
+#ifdef	RC32434_REVISION
+	disable_irq(lp->ovr_irq);
+#endif	
+	disable_irq(lp->und_irq);
+	
+	/* Mask F E bit in Tx DMA */
+	rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
+	/* Mask D H E bit in Rx DMA */
+	rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
+	
+	rc32434_init(dev);
+	rc32434_multicast_list(dev);
+	
+	enable_irq(lp->und_irq);
+#ifdef	RC32434_REVISION
+	enable_irq(lp->ovr_irq);
+#endif
+	enable_irq(lp->tx_irq);
+	enable_irq(lp->rx_irq);
+	
+	return 0;
+}
+
+int rc32434_init_module(void)
+{
+	printk(KERN_INFO DRIVER_NAME " \n");
+	return rc32434_probe(0);
+}
+
+static int rc32434_probe(int port_num)
+{
+	struct rc32434_if_t *bif = &rc32434_iflist[port_num];
+	struct rc32434_local *lp = NULL;
+	struct net_device *dev = NULL;
+	int i, retval,err;
+	
+	dev = alloc_etherdev(sizeof(struct rc32434_local));
+	if(!dev) {
+		ERR("rc32434_eth: alloc_etherdev failed\n");
+		return -1;
+	}
+	
+	SET_MODULE_OWNER(dev);
+	bif->dev = dev;
+	
+	printk("mac: %s\n", bif->mac_str);
+	if ((retval = parse_mac_addr(dev, bif->mac_str))) {
+		ERR("MAC address parse failed\n");
+		free_netdev(dev);
+		return -1;
+	}
+	
+	
+	/* Initialize the device structure. */
+	if (dev->priv == NULL) {
+		lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
+		memset(lp, 0, sizeof(struct rc32434_local));
+	} 
+	else {
+		lp = (struct rc32434_local *)dev->priv;
+	}
+	
+	lp->rx_irq = bif->rx_dma_irq;
+	lp->tx_irq = bif->tx_dma_irq;
+	lp->ovr_irq = bif->rx_ovr_irq;
+	lp->und_irq = bif->tx_und_irq;
+	
+	lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
+
+	if (!lp->eth_regs) {
+		ERR("Can't remap eth registers\n");
+		retval = -ENXIO;
+		goto probe_err_out;
+	}
+	
+	lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s));
+	
+	if (!lp->rx_dma_regs) {
+		ERR("Can't remap Rx DMA registers\n");
+		retval = -ENXIO;
+		goto probe_err_out;
+	}
+	lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s));
+	
+	if (!lp->tx_dma_regs) {
+		ERR("Can't remap Tx DMA registers\n");
+		retval = -ENXIO;
+		goto probe_err_out;
+	}
+	
+#ifdef RC32434_PROC_DEBUG
+	lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
+					 rc32434_read_proc, dev);
+#endif
+	
+	lp->td_ring =	(DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
+	if (!lp->td_ring) {
+		ERR("Can't allocate descriptors\n");
+		retval = -ENOMEM;
+		goto probe_err_out;
+	}
+	
+	dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
+	
+	/* now convert TD_RING pointer to KSEG1 */
+	lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
+	lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
+	
+	
+	spin_lock_init(&lp->lock);
+	
+	dev->base_addr = bif->iobase;
+	/* just use the rx dma irq */
+	dev->irq = bif->rx_dma_irq; 
+	
+	dev->priv = lp;
+	
+	dev->open = rc32434_open;
+	dev->stop = rc32434_close;
+	dev->hard_start_xmit = rc32434_send_packet;
+	dev->get_stats	= rc32434_get_stats;
+	dev->set_multicast_list = &rc32434_multicast_list;
+	dev->tx_timeout = rc32434_tx_timeout;
+	dev->watchdog_timeo = RC32434_TX_TIMEOUT;
+
+#ifdef CONFIG_IDT_USE_NAPI
+	dev->poll = rc32434_poll;
+	dev->weight = bif->weight;
+	printk("Using NAPI with weight %d\n",dev->weight);
+#else
+	lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
+	tasklet_init(lp->rx_tasklet, rc32434_rx_tasklet, (unsigned long)dev);
+#endif
+	lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
+	tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
+	
+	if ((err = register_netdev(dev))) {
+		printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
+		free_netdev(dev);
+		retval = -EINVAL;
+		goto probe_err_out;
+	}
+	
+	INFO("Rx IRQ %d, Tx IRQ %d, ", bif->rx_dma_irq, bif->tx_dma_irq);
+	for (i = 0; i < 6; i++) {
+		printk("%2.2x", dev->dev_addr[i]);
+		if (i<5)
+			printk(":");
+	}
+	printk("\n");
+	
+	return 0;
+	
+ probe_err_out:
+	rc32434_cleanup_module();
+	ERR(" failed.  Returns %d\n", retval);
+	return retval;
+	
+}
+
+
+static void rc32434_cleanup_module(void)
+{
+	int i;
+	
+	for (i = 0; rc32434_iflist[i].iobase; i++) {
+		struct rc32434_if_t * bif = &rc32434_iflist[i];
+		if (bif->dev != NULL) {
+			struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
+			if (lp != NULL) {
+				if (lp->eth_regs)
+					iounmap((void*)lp->eth_regs);
+				if (lp->rx_dma_regs)
+					iounmap((void*)lp->rx_dma_regs);
+				if (lp->tx_dma_regs)
+					iounmap((void*)lp->tx_dma_regs);
+				if (lp->td_ring)
+					kfree((void*)KSEG0ADDR(lp->td_ring));
+				
+#ifdef RC32434_PROC_DEBUG
+				if (lp->ps) {
+					remove_proc_entry(bif->name, proc_net);
+				}
+#endif
+				kfree(lp);
+			}
+			
+			unregister_netdev(bif->dev);
+			free_netdev(bif->dev);
+			kfree(bif->dev);
+		}
+	}
+}
+
+
+
+static int rc32434_open(struct net_device *dev)
+{
+	struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
+	
+	/* Initialize */
+	if (rc32434_init(dev)) {
+		ERR("Error: cannot open the Ethernet device\n");
+		return -EAGAIN;
+	}
+	
+	/* Install the interrupt handler that handles the Done Finished Ovr and Und Events */	
+	if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
+		  SA_SHIRQ | SA_INTERRUPT,
+			"rc32434 ethernet Rx", dev)) {
+		ERR(": unable to get Rx DMA IRQ %d\n",
+		    lp->rx_irq);
+		return -EAGAIN;
+	}
+	if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
+		  SA_SHIRQ | SA_INTERRUPT,
+			"rc32434 ethernet Tx", dev)) {
+		ERR(": unable to get Tx DMA IRQ %d\n",
+		    lp->tx_irq);
+		free_irq(lp->rx_irq, dev);
+		return -EAGAIN;
+	}
+	
+#ifdef	RC32434_REVISION
+	/* Install handler for overrun error. */
+	if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
+			SA_SHIRQ | SA_INTERRUPT,
+			"Ethernet Overflow", dev)) {
+		ERR(": unable to get OVR IRQ %d\n",
+		    lp->ovr_irq);
+		free_irq(lp->rx_irq, dev);
+		free_irq(lp->tx_irq, dev);
+		return -EAGAIN;
+	}
+#endif
+	
+	/* Install handler for underflow error. */
+	if (request_irq(lp->und_irq, &rc32434_und_interrupt,
+			SA_SHIRQ | SA_INTERRUPT,
+			"Ethernet Underflow", dev)) {
+		ERR(": unable to get UND IRQ %d\n",
+		    lp->und_irq);
+		free_irq(lp->rx_irq, dev);
+		free_irq(lp->tx_irq, dev);
+#ifdef	RC32434_REVISION		
+		free_irq(lp->ovr_irq, dev);		
+#endif
+		return -EAGAIN;
+	}
+	
+	
+	return 0;
+}
+
+
+
+
+static int rc32434_close(struct net_device *dev)
+{
+	struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
+	u32 tmp;
+	
+	/* Disable interrupts */
+	disable_irq(lp->rx_irq);
+	disable_irq(lp->tx_irq);
+#ifdef	RC32434_REVISION
+	disable_irq(lp->ovr_irq);
+#endif
+	disable_irq(lp->und_irq);
+	
+	tmp = rc32434_readl(&lp->tx_dma_regs->dmasm);
+	tmp = tmp | DMASM_f_m | DMASM_e_m;
+	rc32434_writel(tmp, &lp->tx_dma_regs->dmasm);
+	
+	tmp = rc32434_readl(&lp->rx_dma_regs->dmasm);
+	tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
+	rc32434_writel(tmp, &lp->rx_dma_regs->dmasm);
+	
+	free_irq(lp->rx_irq, dev);
+	free_irq(lp->tx_irq, dev);
+#ifdef	RC32434_REVISION	
+	free_irq(lp->ovr_irq, dev);
+#endif
+	free_irq(lp->und_irq, dev);
+	return 0;
+}
+
+
+/* transmit packet */
+static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
+{
+	struct rc32434_local		*lp = (struct rc32434_local *)dev->priv;
+	unsigned long 			flags;
+	u32					length;
+	DMAD_t				td;
+	
+	
+	spin_lock_irqsave(&lp->lock, flags);
+	
+	td = &lp->td_ring[lp->tx_chain_tail];
+	
+	/* stop queue when full, drop pkts if queue already full */
+	if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
+		lp->tx_full = 1;
+		
+		if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
+			netif_stop_queue(dev);
+		}
+		else {
+			lp->stats.tx_dropped++;
+			dev_kfree_skb_any(skb);
+			spin_unlock_irqrestore(&lp->lock, flags);
+			return 1;
+		}	   
+	}	 
+	
+	lp->tx_count ++;
+	
+	lp->tx_skb[lp->tx_chain_tail] = skb;
+	
+	length = skb->len;
+	
+	/* Setup the transmit descriptor. */
+	td->ca = CPHYSADDR(skb->data);
+	
+	if(rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
+		if( lp->tx_chain_status == empty ) {
+			td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m;                                /*  Update tail      */
+			lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK;                          /*   Move tail       */
+			rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR    */
+			lp->tx_chain_head = lp->tx_chain_tail;                                                  /* Move head to tail */
+		}
+		else {
+			td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m;                                 /* Update tail */
+			lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &=  ~(DMAD_cof_m);          /* Link to prev */
+			lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link =  CPHYSADDR(td);              /* Link to prev */
+			lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK;                          /* Move tail */
+			rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
+			lp->tx_chain_head = lp->tx_chain_tail;                                                  /* Move head to tail */
+			lp->tx_chain_status = empty;
+		}
+	}
+	else {
+		if( lp->tx_chain_status == empty ) {
+			td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m;                                /* Update tail */
+			lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK;                          /* Move tail */
+			lp->tx_chain_status = filled;
+		}
+		else {
+			td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m;                                /* Update tail */
+			lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &=  ~(DMAD_cof_m);          /* Link to prev */
+			lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link =  CPHYSADDR(td);              /* Link to prev */
+			lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK;                          /* Move tail */
+		}
+	}
+	
+	dev->trans_start = jiffies;				
+	
+	spin_unlock_irqrestore(&lp->lock, flags);
+	
+	return 0;
+}
+
+
+//Experimental, not enabled yet
+
+#if 0
+/* Ethernet MII-PHY Handler */
+static void rc32434_mii_handler(unsigned long data)
+{
+	struct net_device *dev = (struct net_device *)data;		
+	struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
+	unsigned long 	flags;
+	unsigned long duplex_status;
+	int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
+	
+	spin_lock_irqsave(&lp->lock, flags);
+	
+	/* Two ports are using the same MII, the difference is the PHY address */
+	rc32434_writel(0, &rc32434_eth0_regs->miimcfg);  
+	rc32434_writel(0, &rc32434_eth0_regs->miimcmd);  
+	rc32434_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);  
+	rc32434_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);  
+	while(rc32434_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
+	
+	ERR("irq:%x		port_addr:%x	RDD:%x\n", 
+	    lp->rx_irq, port_addr, rc32434_readl(&rc32434_eth0_regs->miimrdd));
+	duplex_status = (rc32434_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
+	if(duplex_status != lp->duplex_mode) {
+		ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);		
+		lp->duplex_mode = duplex_status;
+		rc32434_restart(dev);		
+	}
+	
+	lp->mii_phy_timer.expires = jiffies + 10 * HZ;	
+	add_timer(&lp->mii_phy_timer);
+	
+	spin_unlock_irqrestore(&lp->lock, flags);
+	
+}
+#endif
+
+
+#ifdef	RC32434_REVISION	
+/* Ethernet Rx Overflow interrupt */
+static irqreturn_t
+rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+{
+	struct net_device *dev = (struct net_device *)dev_id;
+	struct rc32434_local *lp;
+	unsigned int ovr;
+	irqreturn_t retval = IRQ_NONE;
+	
+	ASSERT(dev != NULL);
+	
+	lp = (struct rc32434_local *)dev->priv;
+	spin_lock(&lp->lock);
+	ovr = rc32434_readl(&lp->eth_regs->ethintfc);
+	
+	if(ovr & ETHINTFC_ovr_m) {
+		netif_stop_queue(dev);
+		
+		/* clear OVR bit */
+		rc32434_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
+		
+		/* Restart interface */
+		rc32434_restart(dev);
+		retval = IRQ_HANDLED;
+	}
+	spin_unlock(&lp->lock);
+	
+	return retval;
+}
+
+#endif
+
+
+/* Ethernet Tx Underflow interrupt */
+static irqreturn_t
+rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+{
+	struct net_device *dev = (struct net_device *)dev_id;
+	struct rc32434_local *lp;
+	unsigned int und;
+	irqreturn_t retval = IRQ_NONE;
+	
+	ASSERT(dev != NULL);
+	
+	lp = (struct rc32434_local *)dev->priv;
+	
+	spin_lock(&lp->lock);
+	
+	und = rc32434_readl(&lp->eth_regs->ethintfc);
+	
+	if(und & ETHINTFC_und_m) {
+		netif_stop_queue(dev);
+		
+		rc32434_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
+		
+		/* Restart interface */
+		rc32434_restart(dev);
+		retval = IRQ_HANDLED;
+	}
+	
+	spin_unlock(&lp->lock);
+	
+	return retval;
+}
+
+
+/* Ethernet Rx DMA interrupt */
+static irqreturn_t
+rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+{
+	struct net_device *dev = (struct net_device *)dev_id;
+	struct rc32434_local* lp;
+	volatile u32 dmas,dmasm;
+	irqreturn_t retval;
+	
+	ASSERT(dev != NULL);
+	
+	lp = (struct rc32434_local *)dev->priv;
+	
+	spin_lock(&lp->lock);
+	dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
+	if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
+		/* Mask D H E bit in Rx DMA */
+		dmasm = rc32434_readl(&lp->rx_dma_regs->dmasm);
+		rc32434_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
+#ifdef CONFIG_IDT_USE_NAPI
+		if(netif_rx_schedule_prep(dev))
+                        __netif_rx_schedule(dev);
+#else
+		tasklet_hi_schedule(lp->rx_tasklet);
+#endif
+		
+		if (dmas & DMAS_e_m)
+			ERR(": DMA error\n");
+		
+		retval = IRQ_HANDLED;
+	}
+	else
+		retval = IRQ_NONE;
+	
+	spin_unlock(&lp->lock);
+	return retval;
+}
+
+#ifdef CONFIG_IDT_USE_NAPI
+static int rc32434_poll(struct net_device *rx_data_dev, int *budget)
+#else
+static void rc32434_rx_tasklet(unsigned long rx_data_dev)
+#endif
+{
+	struct net_device *dev = (struct net_device *)rx_data_dev;	
+	struct rc32434_local* lp = netdev_priv(dev);
+	volatile DMAD_t  rd = &lp->rd_ring[lp->rx_next_done];
+	struct sk_buff *skb, *skb_new;
+	u8* pkt_buf;
+	u32 devcs, count, pkt_len, pktuncrc_len;
+	volatile u32 dmas;
+#ifdef CONFIG_IDT_USE_NAPI
+	u32 received = 0;
+	int rx_work_limit = min(*budget,dev->quota);
+#else
+	unsigned long 	flags;
+	spin_lock_irqsave(&lp->lock, flags);
+#endif
+	
+	while ( (count = RC32434_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) {
+#ifdef CONFIG_IDT_USE_NAPI
+		if(--rx_work_limit <0)
+                {
+                        break;
+                }
+#endif
+		/* init the var. used for the later operations within the while loop */
+		skb_new = NULL;
+		devcs = rd->devcs;
+		pkt_len = RCVPKT_LENGTH(devcs);
+		skb = lp->rx_skb[lp->rx_next_done];
+      
+		if (count < 64) {
+			lp->stats.rx_errors++;
+			lp->stats.rx_dropped++;			
+		}
+		else if ((devcs & ( ETHRX_ld_m)) !=	ETHRX_ld_m) {
+			/* check that this is a whole packet */
+			/* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
+			lp->stats.rx_errors++;
+			lp->stats.rx_dropped++;
+		}
+		else if ( (devcs & ETHRX_rok_m)  ) {
+			
+			{
+				/* must be the (first and) last descriptor then */
+				pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
+				
+				pktuncrc_len = pkt_len - 4;
+				/* invalidate the cache */
+				dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
+				
+				/* Malloc up new buffer. */					  
+				skb_new = dev_alloc_skb(RC32434_RBSIZE + 2);					             	
+				
+				if (skb_new != NULL){
+					/* Make room */
+					skb_put(skb, pktuncrc_len);		    
+					
+					skb->protocol = eth_type_trans(skb, dev);
+					
+					/* pass the packet to upper layers */
+#ifdef CONFIG_IDT_USE_NAPI
+					netif_receive_skb(skb);
+#else
+					netif_rx(skb);
+#endif
+					
+					dev->last_rx = jiffies;
+					lp->stats.rx_packets++;
+					lp->stats.rx_bytes += pktuncrc_len;
+					
+					if (IS_RCV_MP(devcs))
+						lp->stats.multicast++;
+					
+					/* 16 bit align */						  
+					skb_reserve(skb_new, 2);	
+					
+					skb_new->dev = dev;
+					lp->rx_skb[lp->rx_next_done] = skb_new;
+				}
+				else {
+					ERR("no memory, dropping rx packet.\n");
+					lp->stats.rx_errors++;		
+					lp->stats.rx_dropped++;					
+				}
+			}
+			
+		}			
+		else {
+			/* This should only happen if we enable accepting broken packets */
+			lp->stats.rx_errors++;
+			lp->stats.rx_dropped++;
+			
+			/* add statistics counters */
+			if (IS_RCV_CRC_ERR(devcs)) {
+				DBG(2, "RX CRC error\n");
+				lp->stats.rx_crc_errors++;
+			} 
+			else if (IS_RCV_LOR_ERR(devcs)) {
+				DBG(2, "RX LOR error\n");
+				lp->stats.rx_length_errors++;
+			}				
+			else if (IS_RCV_LE_ERR(devcs)) {
+				DBG(2, "RX LE error\n");
+				lp->stats.rx_length_errors++;
+			}
+			else if (IS_RCV_OVR_ERR(devcs)) {
+				lp->stats.rx_over_errors++;
+			}
+			else if (IS_RCV_CV_ERR(devcs)) {
+				/* code violation */
+				DBG(2, "RX CV error\n");
+				lp->stats.rx_frame_errors++;
+			}
+			else if (IS_RCV_CES_ERR(devcs)) {
+				DBG(2, "RX Preamble error\n");
+			}
+		}
+		
+		rd->devcs = 0;
+		
+		/* restore descriptor's curr_addr */
+		if(skb_new)
+			rd->ca = CPHYSADDR(skb_new->data); 
+		else
+			rd->ca = CPHYSADDR(skb->data);
+		
+		rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
+		lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &=  ~(DMAD_cod_m); 	
+		
+		lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
+		rd = &lp->rd_ring[lp->rx_next_done];
+		rc32434_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
+	}	
+#ifdef CONFIG_IDT_USE_NAPI
+        dev->quota -= received;
+        *budget =- received;
+        if(rx_work_limit < 0)
+                goto not_done;
+#endif
+	
+	dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
+	
+	if(dmas & DMAS_h_m) {
+		rc32434_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
+#ifdef RC32434_PROC_DEBUG
+		lp->dma_halt_cnt++;
+#endif
+		rd->devcs = 0;
+		skb = lp->rx_skb[lp->rx_next_done];
+		rd->ca = CPHYSADDR(skb->data);
+		rc32434_chain_rx(lp,rd);
+	}
+	
+#ifdef CONFIG_IDT_USE_NAPI
+	netif_rx_complete(dev);
+#endif
+	/* Enable D H E bit in Rx DMA */
+	rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm); 
+#ifdef CONFIG_IDT_USE_NAPI
+	return 0;
+ not_done:
+	return 1;
+#else
+	spin_unlock_irqrestore(&lp->lock, flags);
+	return;
+#endif
+
+	
+}	
+
+
+
+/* Ethernet Tx DMA interrupt */
+static irqreturn_t
+rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+{
+	struct net_device *dev = (struct net_device *)dev_id;
+	struct rc32434_local *lp;
+	volatile u32 dmas,dmasm;
+	irqreturn_t retval;
+	
+	ASSERT(dev != NULL);
+	
+	lp = (struct rc32434_local *)dev->priv;
+	
+	spin_lock(&lp->lock);
+	
+	dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
+	
+	if (dmas & (DMAS_f_m | DMAS_e_m)) {
+		dmasm = rc32434_readl(&lp->tx_dma_regs->dmasm);
+		/* Mask F E bit in Tx DMA */
+		rc32434_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
+		
+		tasklet_hi_schedule(lp->tx_tasklet);
+		
+		if(lp->tx_chain_status == filled && (rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
+			rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));			
+			lp->tx_chain_status = empty;
+			lp->tx_chain_head = lp->tx_chain_tail;
+			dev->trans_start = jiffies;
+		}
+		
+		if (dmas & DMAS_e_m)
+			ERR(": DMA error\n");
+		
+		retval = IRQ_HANDLED;
+	}
+	else
+		retval = IRQ_NONE;
+	
+	spin_unlock(&lp->lock);
+	
+	return retval;
+}
+
+
+static void rc32434_tx_tasklet(unsigned long tx_data_dev)
+{
+	struct net_device *dev = (struct net_device *)tx_data_dev;	
+	struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
+	volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
+	u32 devcs;
+	unsigned long 	flags;
+	volatile u32 dmas;
+	
+	spin_lock_irqsave(&lp->lock, flags);
+	
+	/* process all desc that are done */
+	while(IS_DMA_FINISHED(td->control)) {
+		if(lp->tx_full == 1) {
+			netif_wake_queue(dev);
+			lp->tx_full = 0;
+		}
+		
+		devcs = lp->td_ring[lp->tx_next_done].devcs;    
+		if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
+			lp->stats.tx_errors++;
+			lp->stats.tx_dropped++;				
+			
+			/* should never happen */
+			DBG(1, __FUNCTION__ ": split tx ignored\n");
+		}
+		else if (IS_TX_TOK(devcs)) {
+			lp->stats.tx_packets++;
+		}
+		else {
+			lp->stats.tx_errors++;
+			lp->stats.tx_dropped++;				
+			
+			/* underflow */
+			if (IS_TX_UND_ERR(devcs)) 
+				lp->stats.tx_fifo_errors++;
+			
+			/* oversized frame */
+			if (IS_TX_OF_ERR(devcs))
+				lp->stats.tx_aborted_errors++;
+			
+			/* excessive deferrals */
+			if (IS_TX_ED_ERR(devcs))
+				lp->stats.tx_carrier_errors++;
+			
+			/* collisions: medium busy */
+			if (IS_TX_EC_ERR(devcs))
+				lp->stats.collisions++;
+			
+			/* late collision */
+			if (IS_TX_LC_ERR(devcs))
+				lp->stats.tx_window_errors++;
+			
+		}
+		
+		/* We must always free the original skb */
+		if (lp->tx_skb[lp->tx_next_done] != NULL) {
+			dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
+			lp->tx_skb[lp->tx_next_done] = NULL;
+		}
+		
+		lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
+		lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;	
+		lp->td_ring[lp->tx_next_done].link = 0;
+		lp->td_ring[lp->tx_next_done].ca = 0;
+		lp->tx_count --;
+		
+		/* go on to next transmission */
+		lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
+		td = &lp->td_ring[lp->tx_next_done];
+		
+	}
+	
+	dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
+	rc32434_writel( ~dmas, &lp->tx_dma_regs->dmas);
+	
+	/* Enable F E bit in Tx DMA */
+	rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm); 
+	spin_unlock_irqrestore(&lp->lock, flags);
+	
+}
+
+
+static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
+{
+	struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
+	return &lp->stats;
+}
+
+
+/*
+ * Set or clear the multicast filter for this adaptor.
+ */
+static void rc32434_multicast_list(struct net_device *dev)
+{   
+	/* listen to broadcasts always and to treat 	*/
+	/*       IFF bits independantly	*/
+	struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
+	unsigned long flags;
+	u32 recognise = ETHARC_ab_m; 		/* always accept broadcasts */
+	
+	if (dev->flags & IFF_PROMISC)         		/* set promiscuous mode */
+		recognise |= ETHARC_pro_m;
+	
+	if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
+		recognise |= ETHARC_am_m;    	  	/* all multicast & bcast */
+	else if (dev->mc_count > 0) {
+		DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
+		recognise |= ETHARC_am_m;    	  	/* for the time being */
+	}
+	
+	spin_lock_irqsave(&lp->lock, flags);
+	rc32434_writel(recognise, &lp->eth_regs->etharc);
+	spin_unlock_irqrestore(&lp->lock, flags);
+}
+
+
+static void rc32434_tx_timeout(struct net_device *dev)
+{
+	struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
+	unsigned long flags;
+	
+	spin_lock_irqsave(&lp->lock, flags);
+	rc32434_restart(dev);
+	spin_unlock_irqrestore(&lp->lock, flags);
+	
+}
+
+
+/*
+ * Initialize the RC32434 ethernet controller.
+ */
+static int rc32434_init(struct net_device *dev)
+{
+	struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
+	int i, j;
+	
+	/* Disable DMA */       
+	rc32434_abort_tx(dev);
+	rc32434_abort_rx(dev); 
+	
+	/* reset ethernet logic */ 
+	rc32434_writel(0, &lp->eth_regs->ethintfc);
+	while((rc32434_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
+		dev->trans_start = jiffies;	
+	
+	/* Enable Ethernet Interface */ 
+	rc32434_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc); 
+	
+#ifndef CONFIG_IDT_USE_NAPI
+	tasklet_disable(lp->rx_tasklet);
+#endif
+	tasklet_disable(lp->tx_tasklet);
+	
+	/* Initialize the transmit Descriptors */
+	for (i = 0; i < RC32434_NUM_TDS; i++) {
+		lp->td_ring[i].control = DMAD_iof_m;
+		lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
+		lp->td_ring[i].ca = 0;
+		lp->td_ring[i].link = 0;
+		if (lp->tx_skb[i] != NULL) {
+			dev_kfree_skb_any(lp->tx_skb[i]);
+			lp->tx_skb[i] = NULL;
+		}
+	}
+	lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = 	lp->tx_full = lp->tx_count = 0;
+	lp->	tx_chain_status = empty;
+	
+	/*
+	 * Initialize the receive descriptors so that they
+	 * become a circular linked list, ie. let the last
+	 * descriptor point to the first again.
+	 */
+	for (i=0; i<RC32434_NUM_RDS; i++) {
+		struct sk_buff *skb = lp->rx_skb[i];
+		
+		if (lp->rx_skb[i] == NULL) {
+			skb = dev_alloc_skb(RC32434_RBSIZE + 2);
+			if (skb == NULL) {
+				ERR("No memory in the system\n");
+				for (j = 0; j < RC32434_NUM_RDS; j ++)
+					if (lp->rx_skb[j] != NULL) 
+						dev_kfree_skb_any(lp->rx_skb[j]);
+				
+				return 1;
+			}
+			else {
+				skb->dev = dev;
+				skb_reserve(skb, 2);
+				lp->rx_skb[i] = skb;
+				lp->rd_ring[i].ca = CPHYSADDR(skb->data); 
+				
+			}
+		}
+		lp->rd_ring[i].control =	DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
+		lp->rd_ring[i].devcs = 0;
+		lp->rd_ring[i].ca = CPHYSADDR(skb->data);
+		lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
+		
+	}
+	/* loop back */
+	lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
+	lp->rx_next_done   = 0;
+	
+	lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
+	lp->rx_chain_head = 0;
+	lp->rx_chain_tail = 0;
+	lp->rx_chain_status = empty;
+	
+	rc32434_writel(0, &lp->rx_dma_regs->dmas);
+	/* Start Rx DMA */
+	rc32434_start_rx(lp, &lp->rd_ring[0]);
+	
+	/* Enable F E bit in Tx DMA */
+	rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm); 
+	/* Enable D H E bit in Rx DMA */
+	rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm); 
+	
+	/* Accept only packets destined for this Ethernet device address */
+	rc32434_writel(ETHARC_ab_m, &lp->eth_regs->etharc); 
+	
+	/* Set all Ether station address registers to their initial values */ 
+	rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0); 
+	rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
+	
+	rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1); 
+	rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
+	
+	rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2); 
+	rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
+	
+	rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3); 
+	rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3); 
+	
+	
+	/* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */ 
+	rc32434_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);  
+	//ETHMAC2_flc_m		ETHMAC2_fd_m	lp->duplex_mode
+	
+	/* Back to back inter-packet-gap */ 
+	rc32434_writel(0x15, &lp->eth_regs->ethipgt); 
+	/* Non - Back to back inter-packet-gap */ 
+	rc32434_writel(0x12, &lp->eth_regs->ethipgr); 
+	
+	/* Management Clock Prescaler Divisor */
+	/* Clock independent setting */
+	rc32434_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
+		       &lp->eth_regs->ethmcp);
+	
+	/* don't transmit until fifo contains 48b */
+	rc32434_writel(48, &lp->eth_regs->ethfifott);
+	
+	rc32434_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
+	
+#ifndef CONFIG_IDT_USE_NAPI
+	tasklet_enable(lp->rx_tasklet);
+#endif
+	tasklet_enable(lp->tx_tasklet);
+	
+	netif_start_queue(dev);
+	
+	
+	return 0; 
+	
+}
+
+
+#ifndef MODULE
+
+static int __init rc32434_setup(char *options)
+{
+	/* no options yet */
+	return 1;
+}
+
+static int __init rc32434_setup_ethaddr0(char *options)
+{
+	memcpy(mac0, options, 17);
+	mac0[17]= '\0';
+	return 1;
+}
+
+__setup("rc32434eth=", rc32434_setup);
+__setup("ethaddr0=", rc32434_setup_ethaddr0);
+
+
+#endif /* MODULE */
+
+module_init(rc32434_init_module);
+module_exit(rc32434_cleanup_module);
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff -uNr linux-2.6.16-rc5/drivers/net/rc32434_eth.h idtlinux/drivers/net/rc32434_eth.h
--- linux-2.6.16-rc5/drivers/net/rc32434_eth.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/drivers/net/rc32434_eth.h	2006-03-09 16:26:06.000000000 -0800
@@ -0,0 +1,178 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Definitions for IDT RC32434 on-chip ethernet controller.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+
+#include  <asm/idt-boards/rc32434/rc32434.h>
+#include  <asm/idt-boards/rc32434/rc32434_dma_v.h>
+#include  <asm/idt-boards/rc32434/rc32434_eth_v.h>
+
+
+#define RC32434_DEBUG	2
+//#define RC32434_PROC_DEBUG
+#undef	RC32434_DEBUG
+
+#ifdef RC32434_DEBUG
+
+/* use 0 for production, 1 for verification, >2 for debug */
+static int rc32434_debug = RC32434_DEBUG;
+#define ASSERT(expr) \
+	if(!(expr)) {	\
+		printk( "Assertion failed! %s,%s,%s,line=%d\n",	\
+		#expr,__FILE__,__FUNCTION__,__LINE__);		}
+#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
+#else
+#define ASSERT(expr) do {} while (0)
+#define DBG(lvl, format, arg...) do {} while (0)
+#endif
+
+#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
+#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
+#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)		
+
+#define ETH0_DMA_RX_IRQ   	GROUP1_IRQ_BASE + 0
+#define ETH0_DMA_TX_IRQ   	GROUP1_IRQ_BASE + 1 
+#define ETH0_RX_OVR_IRQ   	GROUP3_IRQ_BASE + 9
+#define ETH0_TX_UND_IRQ   	GROUP3_IRQ_BASE + 10
+
+#define ETH0_RX_DMA_ADDR  (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
+#define ETH0_TX_DMA_ADDR  (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
+
+/* the following must be powers of two */
+#ifdef CONFIG_IDT_USE_NAPI
+#define RC32434_NUM_RDS    64    		/* number of receive descriptors */
+#define RC32434_NUM_TDS    64    		/* number of transmit descriptors */
+#else
+#define RC32434_NUM_RDS    128    		/* number of receive descriptors */
+#define RC32434_NUM_TDS    128    		/* number of transmit descriptors */
+#endif
+
+#define RC32434_RBSIZE     1536  		/* size of one resource buffer = Ether MTU */
+#define RC32434_RDS_MASK   (RC32434_NUM_RDS-1)
+#define RC32434_TDS_MASK   (RC32434_NUM_TDS-1)
+#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
+#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
+
+#define RC32434_TX_TIMEOUT HZ * 100
+
+#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
+#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
+
+enum status	{ filled,	empty};
+#define IS_DMA_FINISHED(X)   (((X) & (DMAD_f_m)) != 0)
+#define IS_DMA_DONE(X)   (((X) & (DMAD_d_m)) != 0)
+
+
+/* Information that need to be kept for each board. */
+struct rc32434_local {
+	ETH_t  eth_regs;
+	DMA_Chan_t  rx_dma_regs;
+	DMA_Chan_t  tx_dma_regs;
+	volatile DMAD_t   td_ring;			/* transmit descriptor ring */ 
+	volatile DMAD_t   rd_ring;			/* receive descriptor ring  */
+	
+	struct sk_buff* tx_skb[RC32434_NUM_TDS]; 	/* skbuffs for pkt to trans */
+	struct sk_buff* rx_skb[RC32434_NUM_RDS]; 	/* skbuffs for pkt to trans */
+	
+#ifndef CONFIG_IDT_USE_NAPI
+	struct tasklet_struct * rx_tasklet;
+#endif
+	struct tasklet_struct * tx_tasklet;
+	
+	int	rx_next_done;
+	int	rx_chain_head;
+	int	rx_chain_tail;
+	enum status	rx_chain_status;
+	
+	int	tx_next_done;
+	int	tx_chain_head;
+	int	tx_chain_tail;
+	enum status	tx_chain_status;
+	int tx_count;			
+	int	tx_full;
+	
+	struct timer_list    mii_phy_timer;
+	unsigned long duplex_mode;
+	
+	int   	rx_irq;
+	int    tx_irq;
+	int    ovr_irq;
+	int    und_irq;
+	
+	struct net_device_stats stats;
+	spinlock_t lock; 
+	
+	/* debug /proc entry */
+	struct proc_dir_entry *ps;
+	int dma_halt_cnt;  int dma_run_cnt;
+};
+
+extern unsigned int idt_cpu_freq;
+
+/* Index to functions, as function prototypes. */
+static int rc32434_open(struct net_device *dev);
+static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
+//static void rc32434_mii_handler(unsigned long data);
+static irqreturn_t  rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs);
+static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
+static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
+#ifdef	RC32434_REVISION	
+static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs);
+#endif
+static int  rc32434_close(struct net_device *dev);
+static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
+static void rc32434_multicast_list(struct net_device *dev);
+static int  rc32434_init(struct net_device *dev);
+static void rc32434_tx_timeout(struct net_device *dev);
+
+static void rc32434_tx_tasklet(unsigned long tx_data_dev);
+#ifdef CONFIG_IDT_USE_NAPI
+static int rc32434_poll(struct net_device *rx_data_dev, int *budget);
+#else
+static void rc32434_rx_tasklet(unsigned long rx_data_dev);
+#endif
+static void rc32434_cleanup_module(void);
+static int rc32434_probe(int port_num);
+int rc32434_init_module(void);
+
+
+static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
+{
+	if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
+		rc32434_writel(0x10, &ch->dmac); 
+		
+		while (!(rc32434_readl(&ch->dmas) & DMAS_h_m))
+			dev->trans_start = jiffies;		
+		
+		rc32434_writel(0, &ch->dmas);  
+	}
+	
+	rc32434_writel(0, &ch->dmadptr); 
+	rc32434_writel(0, &ch->dmandptr); 
+}
diff -uNr linux-2.6.16-rc5/drivers/net/rc32438_eth.c idtlinux/drivers/net/rc32438_eth.c
--- linux-2.6.16-rc5/drivers/net/rc32438_eth.c	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/drivers/net/rc32438_eth.c	2006-03-09 16:26:04.000000000 -0800
@@ -0,0 +1,1379 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Driver for the IDT RC32438 on-chip ethernet controller.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/errno.h>
+#include <linux/proc_fs.h>
+#include <linux/in.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/ethtool.h>
+#include <linux/skbuff.h>
+#include <linux/delay.h>
+#include <linux/ctype.h>
+#include <linux/mii.h>
+
+#include <asm/irq.h>
+#include <asm/bitops.h>
+#include <asm/io.h>
+#include <asm/uaccess.h>
+
+#include "rc32438_eth.h"
+#define DRIVER_VERSION "(July04)"
+
+#define DRIVER_NAME "rc32438 Ethernet driver. " DRIVER_VERSION
+
+
+#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
+			           ((dev)->dev_addr[1]))
+#define STATION_ADDRESS_LOW(dev)  (((dev)->dev_addr[2] << 24) | \
+				   ((dev)->dev_addr[3] << 16) | \
+				   ((dev)->dev_addr[4] << 8)  | \
+				   ((dev)->dev_addr[5]))
+
+#define MII_CLOCK 1250000 				/* no more than 2.5MHz */
+static char mac0[18] = "08:00:06:05:40:01";
+static char mac1[18] = "08:00:06:05:50:01";
+
+MODULE_PARM(mac0, "c18");
+MODULE_PARM(mac1, "c18");
+MODULE_PARM_DESC(mac0, "MAC address for RC32438 ethernet0");
+MODULE_PARM_DESC(mac1, "MAC address for RC32438 ethernet1");
+
+static struct rc32438_if_t {
+	char *name;
+	struct net_device *dev;
+	int weight;
+	char* mac_str;
+	u32 iobase;
+	u32 rxdmabase;
+	u32 txdmabase;
+	int rx_dma_irq;
+	int tx_dma_irq;
+	int rx_ovr_irq;
+	int tx_und_irq;
+} rc32438_iflist[] =
+{
+	{
+		"rc32438_eth0",
+		NULL,
+		300,
+		mac0,
+		ETH0_PhysicalAddress,
+		ETH0_RX_DMA_ADDR,
+		ETH0_TX_DMA_ADDR,
+		ETH0_DMA_RX_IRQ,
+		ETH0_DMA_TX_IRQ,
+		ETH0_RX_OVR_IRQ,
+		ETH0_TX_UND_IRQ
+	},
+	{
+		"rc32438_eth1",
+		NULL,
+		300,
+		mac1,
+		ETH1_PhysicalAddress,
+		ETH1_RX_DMA_ADDR,
+		ETH1_TX_DMA_ADDR,
+		ETH1_DMA_RX_IRQ,
+		ETH1_DMA_TX_IRQ,
+		ETH1_RX_OVR_IRQ,
+		ETH1_TX_UND_IRQ
+	}
+};
+
+
+static int parse_mac_addr(struct net_device *dev, char* macstr)
+{
+	int i, j;
+	unsigned char result, value;
+
+	for (i=0; i<6; i++)
+	{
+		result = 0;
+		if (i != 5 && *(macstr+2) != ':')
+		{
+			ERR("invalid mac address format: %d %c\n",
+			    i, *(macstr+2));
+			return -EINVAL;
+		}
+		for (j=0; j<2; j++)
+		{
+			if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
+						  toupper(*macstr)-'A'+10) < 16)
+			{
+				result = result*16 + value;
+				macstr++;
+			}
+			else
+			{
+				ERR("invalid mac address "
+				    "character: %c\n", *macstr);
+				return -EINVAL;
+			}
+		}
+
+		macstr++;
+		dev->dev_addr[i] = result;
+	}
+
+	return 0;
+}
+
+static inline void rc32438_abort_tx(struct net_device *dev)
+{
+	struct rc32438_local *lp = netdev_priv(dev);
+
+	rc32438_abort_dma(dev, lp->tx_dma_regs);
+
+}
+
+static inline void rc32438_abort_rx(struct net_device *dev)
+{
+	struct rc32438_local *lp = netdev_priv(dev);
+
+	rc32438_abort_dma(dev, lp->rx_dma_regs);
+
+}
+
+static inline void rc32438_start_tx(struct rc32438_local *lp,  volatile DMAD_t td)
+{
+	rc32438_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
+}
+
+static inline void rc32438_start_rx(struct rc32438_local *lp, volatile DMAD_t rd)
+{
+	rc32438_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
+}
+
+static inline void rc32438_chain_tx(struct rc32438_local *lp, volatile DMAD_t td)
+{
+	rc32438_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
+}
+static inline void rc32438_chain_rx(struct rc32438_local *lp, volatile DMAD_t rd)
+{
+	rc32438_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
+}
+
+#ifdef RC32438_PROC_DEBUG
+static int rc32438_read_proc(char *buf, char **start, off_t fpos,
+			     int length, int *eof, void *data)
+{
+	struct net_device *dev = (struct net_device *)data;
+
+	struct rc32438_local *lp = netdev_priv(dev);
+
+	int len = 0;
+
+	/* print out header */
+	len += sprintf(buf + len, "\n\tRC32438 Ethernet Debug\n\n");
+
+ 	len += sprintf (buf + len,
+			"DMA halt count  = %10d, DMA ovr count  = %10d\n",
+			lp->dma_halt_cnt,lp->dma_ovr_count);
+
+
+        len += sprintf (buf + len,
+			"note_done_cnt   = %10d, DMA halt_nd_count = %10d\n",
+			lp->not_done_cnt,lp->dma_halt_nd_cnt);
+
+        len += sprintf (buf + len,
+			"budget          = %10d, quota             = %10d\n",
+			lp->ibudget,lp->iquota);
+
+        len += sprintf (buf + len,
+			"tx_stopped          = %10d, quota             = %10d\n",
+			lp->tx_stopped,lp->iquota);
+
+	if (fpos >= len)
+	{
+		*start = buf;
+		*eof = 1;
+		return 0;
+	}
+	*start = buf + fpos;
+
+	if ((len -= fpos) > length)
+		return length;
+	*eof = 1;
+
+	return len;
+
+}
+#endif
+
+/*
+ * Restart the RC32438 ethernet controller.
+ */
+static int rc32438_restart(struct net_device *dev)
+{
+	struct rc32438_local *lp = netdev_priv(dev);
+
+	/*
+	 * Disable interrupts
+	 */
+	disable_irq(lp->rx_irq);
+	disable_irq(lp->tx_irq);
+
+	/* Mask F E bit in Tx DMA */
+	rc32438_writel(rc32438_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
+	/* Mask D H E bit in Rx DMA */
+	rc32438_writel(rc32438_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
+
+	rc32438_init(dev);
+	rc32438_multicast_list(dev);
+
+	enable_irq(lp->tx_irq);
+	enable_irq(lp->rx_irq);
+
+	return 0;
+}
+
+int rc32438_init_module(void)
+{
+	int retval;
+
+	printk(KERN_INFO DRIVER_NAME " \n");
+
+	retval  = rc32438_probe(0);
+	retval |= rc32438_probe(1);
+
+	return retval;
+}
+
+static int rc32438_probe(int port_num)
+{
+	struct rc32438_if_t *bif = &rc32438_iflist[port_num];
+	struct rc32438_local *lp = NULL;
+	struct net_device *dev = NULL;
+	int i, retval,err;
+
+	dev = alloc_etherdev(sizeof(struct rc32438_local));
+	if(!dev)
+	{
+		ERR("rc32438_eth: alloc_etherdev failed\n");
+		return -1;
+	}
+
+	SET_MODULE_OWNER(dev);
+
+	bif->dev = dev;
+
+	if ((retval = parse_mac_addr(dev, bif->mac_str)))
+	{
+		ERR("MAC address parse failed\n");
+		free_netdev(dev);
+		return -1;
+	}
+
+	/* Initialize the device structure. */
+	if (dev->priv == NULL)
+	{
+		lp = (struct rc32438_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
+		memset(lp, 0, sizeof(struct rc32438_local));
+	}
+	else
+	{
+		lp = (struct rc32438_local *)dev->priv;
+	}
+
+	lp->rx_irq = bif->rx_dma_irq;
+	lp->tx_irq = bif->tx_dma_irq;
+
+	lp->weight = bif->weight;
+
+	lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
+
+	if (!lp->eth_regs)
+	{
+		ERR("Can't remap eth registers\n");
+		retval = -ENXIO;
+		goto probe_err_out;
+	}
+
+	lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s));
+
+	if (!lp->rx_dma_regs)
+	{
+		ERR("Can't remap Rx DMA registers\n");
+		retval = -ENXIO;
+		goto probe_err_out;
+	}
+	lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s));
+
+	if (!lp->tx_dma_regs)
+	{
+		ERR("Can't remap Tx DMA registers\n");
+		retval = -ENXIO;
+		goto probe_err_out;
+	}
+
+#ifdef RC32438_PROC_DEBUG
+	lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
+					 rc32438_read_proc, dev);
+#endif
+
+	lp->td_ring =	(DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
+	if (!lp->td_ring)
+	{
+		ERR("Can't allocate descriptors\n");
+		retval = -ENOMEM;
+		goto probe_err_out;
+	}
+
+	dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
+
+	/* now convert TD_RING pointer to KSEG1 */
+	lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
+	lp->rd_ring = &lp->td_ring[RC32438_NUM_TDS];
+
+#ifdef CONFIG_SMP
+	spin_lock_init(&lp->lock);
+#endif
+	dev->base_addr = bif->iobase;
+	/* just use the rx dma irq */
+	dev->irq = bif->rx_dma_irq;
+
+	dev->priv = lp;
+
+	dev->open = rc32438_open;
+	dev->stop = rc32438_close;
+	dev->hard_start_xmit = rc32438_send_packet;
+	dev->get_stats	= rc32438_get_stats;
+	dev->set_multicast_list = &rc32438_multicast_list;
+	dev->tx_timeout = rc32438_tx_timeout;
+	dev->watchdog_timeo = RC32438_TX_TIMEOUT;
+
+	dev->poll = rc32438_poll;
+	dev->weight = lp->weight;
+
+	lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
+	tasklet_init(lp->tx_tasklet, rc32438_tx_tasklet, (unsigned long)dev);
+
+#ifdef CONFIG_RC32438_REVISION_ZA
+	lp->ovr_und_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
+	tasklet_init(lp->ovr_und_tasklet, rc32438_ovr_und_tasklet, (unsigned long)dev);
+#endif
+
+	if ((err = register_netdev(dev))) {
+		printk(KERN_ERR "rc32438 ethernet. Cannot register net device %d\n", err);
+		free_netdev(dev);
+		retval = -EINVAL;
+		goto probe_err_out;
+	}
+
+	INFO("Rx IRQ %d, Tx IRQ %d, TDS %d RDS %d weight %d ",
+	     bif->rx_dma_irq, bif->tx_dma_irq,RC32438_NUM_TDS, RC32438_NUM_RDS,dev->weight);
+	for (i = 0; i < 6; i++)
+	{
+		printk("%2.2x", dev->dev_addr[i]);
+		if (i<5)
+			printk(":");
+	}
+	printk("\n");
+
+	return 0;
+
+ probe_err_out:
+	rc32438_cleanup_module();
+	ERR(" failed.  Returns %d\n", retval);
+	return retval;
+
+}
+
+
+static void rc32438_cleanup_module(void)
+{
+	int i;
+
+	for (i = 0; rc32438_iflist[i].iobase; i++)
+	{
+		struct rc32438_if_t * bif = &rc32438_iflist[i];
+		if (bif->dev != NULL)
+		{
+			struct rc32438_local *lp = (struct rc32438_local *)bif->dev->priv;
+			if (lp != NULL)
+			{
+				if (lp->eth_regs)
+					iounmap((void*)lp->eth_regs);
+				if (lp->rx_dma_regs)
+					iounmap((void*)lp->rx_dma_regs);
+				if (lp->tx_dma_regs)
+					iounmap((void*)lp->tx_dma_regs);
+				if (lp->td_ring)
+					kfree((void*)KSEG0ADDR(lp->td_ring));
+
+#ifdef RC32438_PROC_DEBUG
+				if (lp->ps)
+				{
+					remove_proc_entry(bif->name, proc_net);
+				}
+#endif
+				kfree(lp);
+			}
+
+			unregister_netdev(bif->dev);
+			free_netdev(bif->dev);
+			kfree(bif->dev);
+		}
+	}
+}
+
+/*
+ * Open/initialize the RC32438 controller.
+ *
+ * This routine should set everything up anew at each open, even
+ *  registers that "should" only need to be set once at boot, so that
+ *  there is non-reboot way to recover if something goes wrong.
+ */
+
+static int rc32438_open(struct net_device *dev)
+{
+	struct rc32438_local *lp = netdev_priv(dev);
+
+	/* Initialize */
+	if (rc32438_init(dev))
+	{
+		ERR("Erroe: cannot open the Ethernet device\n");
+		return -EAGAIN;
+	}
+
+	/* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
+	if (request_irq(lp->rx_irq, &rc32438_rx_dma_interrupt,
+			SA_INTERRUPT,
+			"rc32438 ethernet Rx", dev))
+	{
+		ERR(": unable to get Rx DMA IRQ %d\n",
+		    lp->rx_irq);
+		return -EAGAIN;
+	}
+	if (request_irq(lp->tx_irq, &rc32438_tx_dma_interrupt,
+			SA_INTERRUPT,
+			"rc32438 ethernet Tx", dev))
+	{
+		ERR(": unable to get Tx DMA IRQ %d\n",
+		    lp->tx_irq);
+		free_irq(lp->rx_irq, dev);
+		return -EAGAIN;
+	}
+
+	/*Start MII-PHY Timer*/
+	//Not enabled this feature at this time.
+	/*
+	  init_timer(&lp->mii_phy_timer);
+	  lp->mii_phy_timer.expires = jiffies + 10 * HZ;
+	  lp->mii_phy_timer.data = (unsigned long)dev;
+	  lp->mii_phy_timer.function	 = rc32438_mii_handler;
+	  add_timer(&lp->mii_phy_timer);
+	*/
+
+#ifdef RC32438_PROC_DEBUG
+	lp->dma_halt_cnt = 0;
+      	lp->dma_halt_nd_cnt = 0;
+	lp->not_done_cnt = 0;
+        lp->ibudget = 0;
+        lp->iquota  = 0;
+        lp->done_cnt    =0;
+        lp->firstTime = 0;
+	lp->tx_stopped = 0;
+#endif
+	return 0;
+}
+
+/*
+ * Close the RC32438 device
+ */
+static int rc32438_close(struct net_device *dev)
+{
+	struct rc32438_local *lp = netdev_priv(dev);
+	u32 tmp;
+
+	/* Disable interrupts */
+	disable_irq(lp->rx_irq);
+	disable_irq(lp->tx_irq);
+
+	tmp = rc32438_readl(&lp->tx_dma_regs->dmasm);
+	tmp = tmp | DMASM_f_m | DMASM_e_m;
+	rc32438_writel(tmp, &lp->tx_dma_regs->dmasm);
+
+	tmp = rc32438_readl(&lp->rx_dma_regs->dmasm);
+	tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
+	rc32438_writel(tmp, &lp->rx_dma_regs->dmasm);
+
+	free_irq(lp->rx_irq, dev);
+	free_irq(lp->tx_irq, dev);
+
+	//Not enabled this feature at this time.
+	//del_timer(&lp->mii_phy_timer);
+
+	return 0;
+}
+
+
+/* transmit packet */
+static int rc32438_send_packet(struct sk_buff *skb, struct net_device *dev)
+{
+	struct rc32438_local *lp = netdev_priv(dev);
+	unsigned long 			flags;
+	u32				length;
+	volatile DMAD_t				td;
+
+#ifdef CONFIG_SMP
+	spin_lock_irqsave(&lp->lock, flags);
+#else
+	local_irq_save(flags);
+#endif
+	td = &lp->td_ring[lp->tx_chain_tail];
+
+	/* stop queue when full, drop pkts if queue already full */
+	if(lp->tx_count >= (RC32438_NUM_TDS - 2))
+	{
+		lp->tx_full = 1;
+
+		if(lp->tx_count == (RC32438_NUM_TDS - 2))
+		{
+			/* this pkt is about to fill the queue*/
+			lp->tx_stopped++;
+			netif_stop_queue(dev);
+		}
+		else
+		{
+			/* this pkt cannot be added to the full queue */
+			printk("Tx ring full, packet dropped\n");
+			lp->stats.tx_dropped++;
+			dev_kfree_skb_any(skb);
+#ifdef CONFIG_SMP
+			spin_unlock_irqrestore(&lp->lock, flags);
+#else
+			local_irq_restore(flags);
+#endif
+			return 1;
+		}
+	}
+
+	lp->tx_count ++;
+
+	lp->tx_skb[lp->tx_chain_tail] = skb;
+
+	length = skb->len;
+
+	/* Setup the transmit descriptor. */
+	td->ca = CPHYSADDR(skb->data);
+
+	if(rc32438_readl(&(lp->tx_dma_regs->dmandptr)) == 0)
+	{
+		if( lp->tx_chain_status == empty )
+		{
+			td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m;                                /*  Update tail      */
+			lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32438_TDS_MASK;                          /*   Move tail       */
+			rc32438_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR    */
+			lp->tx_chain_head = lp->tx_chain_tail;                                                  /* Move head to tail */
+		}
+		else
+		{
+			td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m;                                 /* Update tail */
+			lp->td_ring[(lp->tx_chain_tail-1)& RC32438_TDS_MASK].control &=  ~(DMAD_cof_m);          /* Link to prev */
+			lp->td_ring[(lp->tx_chain_tail-1)& RC32438_TDS_MASK].link =  CPHYSADDR(td);              /* Link to prev */
+			lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32438_TDS_MASK;                          /* Move tail */
+			rc32438_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
+			lp->tx_chain_head = lp->tx_chain_tail;                                                  /* Move head to tail */
+			lp->tx_chain_status = empty;
+		}
+	}
+	else
+	{
+		if( lp->tx_chain_status == empty )
+		{
+			td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m;                                /* Update tail */
+			lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32438_TDS_MASK;                          /* Move tail */
+			lp->tx_chain_status = filled;
+		}
+		else
+		{
+			td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m;                                /* Update tail */
+			lp->td_ring[(lp->tx_chain_tail-1)& RC32438_TDS_MASK].control &=  ~(DMAD_cof_m);          /* Link to prev */
+			lp->td_ring[(lp->tx_chain_tail-1)& RC32438_TDS_MASK].link =  CPHYSADDR(td);              /* Link to prev */
+			lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32438_TDS_MASK;                          /* Move tail */
+		}
+	}
+
+	dev->trans_start = jiffies;
+
+#ifdef CONFIG_SMP
+	spin_unlock_irqrestore(&lp->lock, flags);
+#else
+	local_irq_restore(flags);
+#endif
+
+	return 0;
+}
+
+//Experimental, not enables right now
+
+#if 0
+/* Ethernet MII-PHY Handler */
+static void rc32438_mii_handler(unsigned long data)
+{
+	struct net_device *dev = (struct net_device *)data;
+	struct rc32438_local *lp = netdev_priv(dev);
+	unsigned long 	flags;
+	unsigned long duplex_status;
+	int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
+
+#ifdef CONFIG_SMP
+	spin_lock_irqsave(&lp->lock, flags);
+#else
+	local_irq_save(flags);
+#endif
+
+	/* Two ports are using the same MII, the difference is the PHY address */
+	rc32438_writel(0, &rc32438_eth0_regs->miimcfg);
+	rc32438_writel(0, &rc32438_eth0_regs->miimcmd);
+	rc32438_writel(port_addr |0x05, &rc32438_eth0_regs->miimaddr);
+	rc32438_writel(MIIMCMD_scn_m, &rc32438_eth0_regs->miimcmd);
+	while(rc32438_readl(&rc32438_eth0_regs->miimind) & MIIMIND_nv_m);
+
+	ERR("irq:%x		port_addr:%x	RDD:%x\n",
+	    lp->rx_irq, port_addr, rc32438_readl(&rc32438_eth0_regs->miimrdd));
+	duplex_status = (rc32438_readl(&rc32438_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
+	if(duplex_status != lp->duplex_mode)
+	{
+		ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
+		lp->duplex_mode = duplex_status;
+		rc32438_restart(dev);
+	}
+
+	lp->mii_phy_timer.expires = jiffies + 10 * HZ;
+	add_timer(&lp->mii_phy_timer);
+
+#ifdef CONFIG_SMP
+	spin_unlock_irqrestore(&lp->lock, flags);
+#else
+	local_irq_restore(flags);
+#endif
+
+}
+#endif
+
+
+#ifdef CONFIG_RC32438_REVISION_ZA
+static void rc32438_ovr_und_tasklet(unsigned long dev_id)
+{
+	struct net_device *dev = (struct net_device *)dev_id;
+	struct rc32438_local *lp = netdev_priv(dev);
+
+	unsigned int status;
+	unsigned long flags;
+
+	ASSERT(dev != NULL);
+#ifdef CONFIG_SMP
+	spin_lock_irqsave(&lp->lock,flags);
+#else
+	local_irq_save(flags);
+#endif
+	status = rc32438_readl(&lp->eth_regs->ethintfc);
+
+	lp->dma_ovr_count++;
+	if(status & (ETHINTFC_und_m | ETHINTFC_ovr_m) )
+	{
+		netif_stop_queue(dev);
+
+		/* clear OVR bit */
+		rc32438_writel((status & ~(ETHINTFC_und_m | ETHINTFC_ovr_m)), &lp->eth_regs->ethintfc);
+
+		/* Restart interface */
+		rc32438_restart(dev);
+	}
+#ifdef CONFIG_SMP
+	spin_unlock_irqrestore(&lp->lock,flags);
+#else
+	local_irq_restore(flags);
+#endif
+}
+#endif
+/* Ethernet Rx DMA interrupt */
+static irqreturn_t
+rc32438_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+{
+	struct net_device *dev = (struct net_device *)dev_id;
+	struct rc32438_local *lp = netdev_priv(dev);
+	volatile u32 dmas,dmasm;
+	irqreturn_t retval = IRQ_NONE;
+
+	ASSERT(dev != NULL);
+
+#ifdef CONFIG_SMP
+	spin_lock(&lp->lock);
+#endif
+	dmas = rc32438_readl(&lp->rx_dma_regs->dmas);
+	if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m))
+	{
+		/* Mask D H E bit in Rx DMA */
+		dmasm = rc32438_readl(&lp->rx_dma_regs->dmasm);
+		rc32438_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
+
+		if (dmas & DMAS_h_m){
+		  printk("DMA Halted\n");
+		  rc32438_restart(dev);
+		}
+		if(netif_rx_schedule_prep(dev))
+		  __netif_rx_schedule(dev);
+		
+		if (dmas & DMAS_e_m)
+		  ERR(": DMA error\n");
+
+		retval = IRQ_HANDLED;
+	}
+#ifdef CONFIG_SMP
+	spin_unlock(&lp->lock);
+#endif
+	return retval;
+}
+
+static int rc32438_poll(struct net_device *dev, int *budget)
+{
+	struct rc32438_local* lp = netdev_priv(dev);
+	volatile DMAD_t  rd;
+	u32 rx_next_done;
+	struct sk_buff *skb, *skb_new;
+	u8* pkt_buf;
+	u32 count, pkt_len, pktuncrc_len;
+	volatile u32 dmas,devcs;
+#ifdef CONFIG_RC32438_REVISION_ZA
+	volatile u32 ovr_und;
+#endif
+	u32 received = 0;
+	int rx_work_limit = 0;
+
+	rx_next_done  = lp->rx_next_done;
+	rd = &lp->rd_ring[rx_next_done];
+
+	rx_work_limit = min(*budget,dev->quota);
+
+        while ( (count = RC32438_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0)
+        {
+                if(--rx_work_limit <0)
+                {
+#ifdef RC32438_PROC_DEBUG
+                        if(lp->firstTime == 0)
+                        {
+                                lp->ibudget = *budget;
+                                lp->iquota  = dev->quota;
+                                lp->firstTime = 1;
+                        }
+#endif
+			break;
+                }
+                /* init the var. used for the later operations within the while loop */
+                skb_new = NULL;
+                devcs = rd->devcs;
+                pkt_len = RCVPKT_LENGTH(devcs);
+		skb = lp->rx_skb[rx_next_done];
+
+		if ((devcs & ( ETHRX_ld_m)) !=	ETHRX_ld_m)
+		{
+			/* check that this is a whole packet */
+			/* WARNING: DMA_FD bit incorrectly set in Rc32438 (errata ref #077) */
+			lp->stats.rx_errors++;
+			lp->stats.rx_dropped++;
+		}
+		else if (pkt_len < 64)
+		{
+			lp->stats.rx_errors++;
+			lp->stats.rx_dropped++;
+		}
+		else if ( (devcs & ETHRX_rok_m)  )
+		{
+			/* must be the (first and) last descriptor then */
+			pkt_buf = (u8*)lp->rx_skb[rx_next_done]->data;
+
+			pktuncrc_len = pkt_len - 4;
+			/* invalidate the cache */
+			dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
+
+			/* Malloc up new buffer. */
+			skb_new = dev_alloc_skb(RC32438_RBSIZE + 2);
+
+			if (skb_new != NULL)
+			{
+				/* Make room */
+				skb_put(skb, pktuncrc_len);
+
+				skb->protocol = eth_type_trans(skb, dev);
+
+				/* pass the packet to upper layers */
+				netif_receive_skb(skb);
+				dev->last_rx = jiffies;
+				lp->stats.rx_packets++;
+				lp->stats.rx_bytes += pktuncrc_len;
+
+				if (IS_RCV_MP(devcs))
+					lp->stats.multicast++;
+
+				/* 16 bit align */
+				skb_reserve(skb_new, 2);
+
+				skb_new->dev = dev;
+				lp->rx_skb[rx_next_done] = skb_new;
+				received++;
+			}
+			else
+			{
+				ERR("no memory, dropping rx packet.\n");
+				lp->stats.rx_errors++;
+				lp->stats.rx_dropped++;
+			}
+		}
+		else
+		{
+			/* This should only happen if we enable accepting broken packets */
+			lp->stats.rx_errors++;
+			lp->stats.rx_dropped++;
+
+			/* add statistics counters */
+			if (IS_RCV_CRC_ERR(devcs))
+			{
+				DBG(2, "RX CRC error\n");
+				lp->stats.rx_crc_errors++;
+			}
+			else if (IS_RCV_LOR_ERR(devcs))
+			{
+				DBG(2, "RX LOR error\n");
+				lp->stats.rx_length_errors++;
+			}
+			else if (IS_RCV_LE_ERR(devcs))
+			{
+				DBG(2, "RX LE error\n");
+				lp->stats.rx_length_errors++;
+			}
+			else if (IS_RCV_OVR_ERR(devcs))
+			{
+				/*
+				 * The overflow errors are handled through
+				 * an interrupt handler.
+				 */
+				lp->stats.rx_over_errors++;
+			}
+			else if (IS_RCV_CV_ERR(devcs))
+			{
+				/* code violation */
+				DBG(2, "RX CV error\n");
+				lp->stats.rx_frame_errors++;
+			}
+			else if (IS_RCV_CES_ERR(devcs))
+			{
+				DBG(2, "RX Preamble error\n");
+			}
+		}
+
+		rd->devcs = 0;
+
+		/* restore descriptor's curr_addr */
+		if(skb_new)
+			rd->ca = CPHYSADDR(skb_new->data);
+		else
+			rd->ca = CPHYSADDR(skb->data);
+
+		rd->control = DMA_COUNT(RC32438_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
+
+		/* There is a race condition here. See below */
+		lp->rd_ring[(rx_next_done-1)& RC32438_RDS_MASK].control &=  ~(DMAD_cod_m);
+
+		rx_next_done = (rx_next_done + 1) & RC32438_RDS_MASK;
+		rd = &lp->rd_ring[rx_next_done];
+		rc32438_writel(~DMAS_d_m, &lp->rx_dma_regs->dmas);
+	}
+
+	dev->quota -= received;
+	*budget =- received;
+
+	lp->rx_next_done = rx_next_done;
+	if(rx_work_limit < 0)
+		goto not_done;
+
+	dmas = rc32438_readl(&lp->rx_dma_regs->dmas);
+
+#if 0
+	if(dmas & DMAS_h_m)
+	{
+#ifdef CONFIG_RC32438_REVISION_ZA
+		ovr_und = rc32438_readl(&lp->eth_regs->ethintfc);
+		if(ovr_und & (ETHINTFC_ovr_m | ETHINTFC_und_m))
+			goto over_under_flow;
+#endif
+
+#ifdef RC32438_PROC_DEBUG
+		lp->dma_halt_cnt++;
+#endif
+
+/***********************************************************************************
+  There is a race condition here. Imagine software completed processing 0 descriptor
+  and is updating the control field of N-1 descriptor. At the same time, DMA 
+  processed N-1 descriptor and is also updating the descriptor. If Software is
+  updating the descriptor after DMA, the D bit in the descriptor gets cleared,
+  though DMA has set it and halted. Now, when Software arrives to N-1, it sees
+  D bit not being set. However, it finds the DMA halted. The Software, in order
+  to start the DMA again, loads this descriptor. Though the control field of
+  this descriptor is fine, the devcs and ca fields are wrong. Hence, the software
+  needs to update those fields before loading DMA.
+***********************************************************************************/
+		rd->devcs = 0;
+		skb = lp->rx_skb[rx_next_done];
+		rd->ca = CPHYSADDR(skb->data);
+		rc32438_chain_rx(lp,rd);
+	}
+#endif
+
+	rc32438_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
+
+	netif_rx_complete(dev);
+	/* Enable D H E bit in Rx DMA */
+	rc32438_writel(rc32438_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm);
+
+	return 0;
+
+ not_done:
+#ifdef RC32438_PROC_DEBUG
+	lp->not_done_cnt++;
+#endif
+	return 1;
+
+#ifdef CONFIG_RC32438_REVISION_ZA
+ over_under_flow:
+ 	netif_rx_complete(dev);
+	tasklet_hi_schedule(lp->ovr_und_tasklet);
+	return 0;
+#endif
+}
+
+/* Ethernet Tx DMA interrupt */
+static irqreturn_t
+rc32438_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+{
+	struct net_device *dev = (struct net_device *)dev_id;
+	struct rc32438_local *lp = netdev_priv(dev);
+	volatile u32 dmas,dmasm;
+	irqreturn_t retval = IRQ_NONE;
+
+	ASSERT(dev != NULL);
+
+//	spin_lock(&lp->lock);
+
+	dmas = rc32438_readl(&lp->tx_dma_regs->dmas);
+
+	if (dmas & (DMAS_f_m | DMAS_e_m))
+	{
+		dmasm = rc32438_readl(&lp->tx_dma_regs->dmasm);
+		/* Mask F E bit in Tx DMA */
+		rc32438_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
+
+		tasklet_schedule(lp->tx_tasklet);
+
+		if(lp->tx_chain_status == filled && (rc32438_readl(&(lp->tx_dma_regs->dmandptr)) == 0))
+		{
+			rc32438_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
+			lp->tx_chain_status = empty;
+			lp->tx_chain_head = lp->tx_chain_tail;
+			dev->trans_start = jiffies;
+		}
+
+		if (dmas & DMAS_e_m)
+			ERR(": DMA error\n");
+
+		retval = IRQ_HANDLED;
+	}
+
+//	spin_unlock(&lp->lock);
+
+	return retval;
+}
+
+static void rc32438_tx_tasklet(unsigned long tx_data_dev)
+{
+        struct net_device *dev = (struct net_device *)tx_data_dev;
+	struct rc32438_local *lp = netdev_priv(dev);
+        volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
+        unsigned long   flags;
+        volatile u32 dmas;
+        volatile u32 devcs;
+
+	u32 tx_next_done = lp->tx_next_done;
+#ifdef CONFIG_SMP
+        spin_lock_irqsave(&lp->lock, flags);
+#else
+	local_irq_save(flags);
+#endif
+
+        /* process all desc that are done */
+        while(IS_DMA_FINISHED(td->control))
+        {
+                if(lp->tx_full == 1)
+                {
+                        netif_wake_queue(dev);
+                        lp->tx_full = 0;
+                }
+
+                devcs = lp->td_ring[tx_next_done].devcs;
+                if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m))
+                {
+                        lp->stats.tx_errors++;
+                        lp->stats.tx_dropped++;
+
+                        /* should never happen */
+                        DBG(1, __FUNCTION__ ": split tx ignored\n");
+                }
+                else if (IS_TX_TOK(devcs))
+                {
+                        /* transmit OK */
+                        lp->stats.tx_packets++;
+                }
+                else
+                {
+                        lp->stats.tx_errors++;
+                        lp->stats.tx_dropped++;
+
+                        /* underflow */
+                        if (IS_TX_UND_ERR(devcs))
+                                lp->stats.tx_fifo_errors++;
+
+                        /* oversized frame */
+                        if (IS_TX_OF_ERR(devcs))
+                                lp->stats.tx_aborted_errors++;
+
+                        /* excessive deferrals */
+                        if (IS_TX_ED_ERR(devcs))
+                                lp->stats.tx_carrier_errors++;
+
+                        /* collisions: medium busy */
+                        if (IS_TX_EC_ERR(devcs))
+                                lp->stats.collisions++;
+
+                        /* late collision */
+                        if (IS_TX_LC_ERR(devcs))
+                                lp->stats.tx_window_errors++;
+
+                }
+
+                /* We must always free the original skb */
+                if (lp->tx_skb[tx_next_done] != NULL)
+                {
+                        dev_kfree_skb_any(lp->tx_skb[tx_next_done]);
+                        lp->tx_skb[tx_next_done] = NULL;
+                }
+
+                lp->td_ring[tx_next_done].control = DMAD_iof_m;
+                lp->td_ring[tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
+                lp->td_ring[tx_next_done].link = 0;
+                lp->td_ring[tx_next_done].ca = 0;
+                lp->tx_count --;
+
+                /* go on to next transmission */
+                tx_next_done = (tx_next_done + 1) & RC32438_TDS_MASK;
+                td = &lp->td_ring[tx_next_done];
+
+        }
+	lp->tx_next_done = tx_next_done;
+        dmas = rc32438_readl(&lp->tx_dma_regs->dmas);
+	rc32438_writel( ~dmas, &lp->tx_dma_regs->dmas);
+
+        /* Enable F E bit in Tx DMA */
+        rc32438_writel(rc32438_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
+#ifdef CONFIG_SMP
+        spin_unlock_irqrestore(&lp->lock, flags);
+#else
+	local_irq_restore(flags);
+#endif
+}
+/*
+ * Get the current statistics.
+ * This may be called with the device open or closed.
+ */
+static struct net_device_stats * rc32438_get_stats(struct net_device *dev)
+{
+	struct rc32438_local *lp = netdev_priv(dev);
+	return &lp->stats;
+}
+
+
+/*
+ * Set or clear the multicast filter for this adaptor.
+ */
+static void rc32438_multicast_list(struct net_device *dev)
+{
+	/* listen to broadcasts always and to treat 	*/
+	/*       IFF bits independantly	*/
+
+	struct rc32438_local *lp = netdev_priv(dev);
+	unsigned long flags;
+	u32 recognise = ETHARC_ab_m; 		/* always accept broadcasts */
+
+	if (dev->flags & IFF_PROMISC)         		/* set promiscuous mode */
+		recognise |= ETHARC_pro_m;
+
+	if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
+		recognise |= ETHARC_am_m;    	  	/* all multicast & bcast */
+	else if (dev->mc_count > 0)
+	{
+		DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
+		recognise |= ETHARC_am_m;    	  	/* for the time being */
+	}
+
+#ifdef CONFIG_SMP
+	spin_lock_irqsave(&lp->lock, flags);
+#else
+	local_irq_save(flags);
+#endif
+	rc32438_writel(recognise, &lp->eth_regs->etharc);
+#ifdef CONFIG_SMP
+	spin_unlock_irqrestore(&lp->lock, flags);
+#else
+	local_irq_restore(flags);
+#endif
+}
+
+
+static void rc32438_tx_timeout(struct net_device *dev)
+{
+	unsigned long flags;
+
+#ifdef CONFIG_SMP
+	struct rc32438_local *lp = netdev_priv(dev);
+	spin_lock_irqsave(&lp->lock, flags);
+#else
+	local_irq_save(flags);
+#endif
+	rc32438_restart(dev);
+#ifdef CONFIG_SMP
+	spin_unlock_irqrestore(&lp->lock, flags);
+#else
+	local_irq_restore(flags);
+#endif
+
+}
+
+
+/*
+ * Initialize the RC32438 ethernet controller.
+ */
+static int rc32438_init(struct net_device *dev)
+{
+	struct rc32438_local *lp = netdev_priv(dev);
+	int i, j;
+
+	/* Disable DMA */
+	rc32438_abort_tx(dev);
+	rc32438_abort_rx(dev);
+
+	/* reset ethernet logic */
+	rc32438_writel(0, &lp->eth_regs->ethintfc);
+	while((rc32438_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
+		dev->trans_start = jiffies;
+
+	/* Enable Ethernet Interface */
+	rc32438_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
+#ifdef CONFIG_RC32438_REVISION_ZA
+	tasklet_disable(lp->ovr_und_tasklet);
+#endif
+	tasklet_disable(lp->tx_tasklet);
+
+	/* Initialize the transmit Descriptors */
+	for (i = 0; i < RC32438_NUM_TDS; i++)
+	{
+		lp->td_ring[i].control = DMAD_iof_m;
+		lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
+		lp->td_ring[i].ca = 0;
+		lp->td_ring[i].link = 0;
+		if (lp->tx_skb[i] != NULL)
+		{
+			/* free dangling skb */
+			dev_kfree_skb_any(lp->tx_skb[i]);
+			lp->tx_skb[i] = NULL;
+		}
+	}
+	lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = 	lp->tx_full = lp->tx_count = 0;
+	lp->tx_chain_status = empty;
+
+	/*
+	 * Initialize the receive descriptors so that they
+	 * become a circular linked list, ie. let the last
+	 * descriptor point to the first again.
+	 */
+	for (i=0; i<RC32438_NUM_RDS; i++)
+	{
+		struct sk_buff *skb = lp->rx_skb[i];
+
+		if (lp->rx_skb[i] == NULL)
+		{
+			skb = dev_alloc_skb(RC32438_RBSIZE + 2);
+			if (skb == NULL)
+			{
+				ERR("No memory in the system\n");
+				for (j = 0; j < RC32438_NUM_RDS; j ++)
+					if (lp->rx_skb[j] != NULL)
+						dev_kfree_skb_any(lp->rx_skb[j]);
+
+				return 1;
+			}
+			else
+			{
+				skb->dev = dev;
+				skb_reserve(skb, 2);
+				lp->rx_skb[i] = skb;
+				lp->rd_ring[i].ca = CPHYSADDR(skb->data);
+
+			}
+		}
+		lp->rd_ring[i].control =	DMAD_iod_m | DMA_COUNT(RC32438_RBSIZE);
+		lp->rd_ring[i].devcs = 0;
+		lp->rd_ring[i].ca = CPHYSADDR(skb->data);
+		lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
+
+	}
+	/* loop back */
+	lp->rd_ring[RC32438_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
+	lp->rx_next_done   = 0;
+
+	lp->rd_ring[RC32438_NUM_RDS-1].control |= DMAD_cod_m;
+	lp->rx_chain_head = 0;
+	lp->rx_chain_tail = 0;
+	lp->rx_chain_status = empty;
+
+	rc32438_writel(0, &lp->rx_dma_regs->dmas);
+	/* Start Rx DMA */
+	rc32438_start_rx(lp, &lp->rd_ring[0]);
+
+	/* Enable F E bit in Tx DMA */
+	rc32438_writel(rc32438_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
+	/* Enable D H E bit in Rx DMA */
+	rc32438_writel(rc32438_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
+
+	/* Accept only packets destined for this Ethernet device address */
+	rc32438_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
+
+	/* Set all Ether station address registers to their initial values */
+	rc32438_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
+	rc32438_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
+
+	rc32438_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
+	rc32438_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
+
+	rc32438_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
+	rc32438_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
+
+	rc32438_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
+	rc32438_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
+
+
+	/* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
+	rc32438_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
+	//ETHMAC2_flc_m		ETHMAC2_fd_m	lp->duplex_mode
+
+	/* Back to back inter-packet-gap */
+	rc32438_writel(0x15, &lp->eth_regs->ethipgt);
+	/* Non - Back to back inter-packet-gap */
+	rc32438_writel(0x12, &lp->eth_regs->ethipgr);
+
+	/* Management Clock Prescaler Divisor */
+	/* Clock independent setting */
+	rc32438_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
+		       &lp->eth_regs->ethmcp);
+
+	/* don't transmit until fifo contains 48b */
+	rc32438_writel(48, &lp->eth_regs->ethfifott);
+
+	rc32438_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
+
+#ifdef CONFIG_RC32438_REVISION_ZA
+	tasklet_enable(lp->ovr_und_tasklet);
+#endif
+	tasklet_enable(lp->tx_tasklet);
+
+	netif_start_queue(dev);
+
+
+	return 0;
+
+}
+
+
+#ifndef MODULE
+
+static int __init rc32438_setup(char *options)
+{
+	/* no options yet */
+	return 1;
+}
+
+static int __init rc32438_setup_ethaddr0(char *options)
+{
+	memcpy(mac0, options, 17);
+	mac0[17]= '\0';
+	return 1;
+}
+
+static int __init rc32438_setup_ethaddr1(char *options)
+{
+	memcpy(mac1, options, 17);
+	mac1[17]= '\0';
+	return 1;
+}
+
+__setup("rc32438eth=", rc32438_setup);
+__setup("ethaddr0=", rc32438_setup_ethaddr0);
+__setup("ethaddr1=", rc32438_setup_ethaddr1);
+
+
+#endif /* MODULE */
+
+module_init(rc32438_init_module);
+module_exit(rc32438_cleanup_module);
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff -uNr linux-2.6.16-rc5/drivers/net/rc32438_eth.h idtlinux/drivers/net/rc32438_eth.h
--- linux-2.6.16-rc5/drivers/net/rc32438_eth.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/drivers/net/rc32438_eth.h	2006-03-09 16:26:04.000000000 -0800
@@ -0,0 +1,183 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Definitions for IDT RC32438 on-chip ethernet controller.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THEg POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#include  <asm/idt-boards/rc32438/rc32438.h>
+#include  <asm/idt-boards/rc32438/rc32438_dma_v.h>
+#include  <asm/idt-boards/rc32438/rc32438_eth_v.h>
+
+#define RC32438_PROC_DEBUG
+//#define RC32438_DEBUG	2
+
+#ifdef RC32438_DEBUG
+
+/* use 0 for production, 1 for verification, >2 for debug */
+static int rc32438_debug = RC32438_DEBUG;
+#define ASSERT(expr) \
+	if(!(expr)) {	\
+		printk( "Assertion failed! %s,%s,%s,line=%d\n",	\
+		#expr,__FILE__,__FUNCTION__,__LINE__);		}
+#define DBG(lvl, format, arg...) if (rc32438_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
+#else
+#define ASSERT(expr) do {} while (0)
+#define DBG(lvl, format, arg...) do {} while (0)
+#endif
+
+#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
+#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
+#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
+
+#define ETH0_DMA_RX_IRQ   GROUP1_IRQ_BASE + 2
+#define ETH0_DMA_TX_IRQ   GROUP1_IRQ_BASE + 3
+#define ETH0_RX_OVR_IRQ   GROUP3_IRQ_BASE + 12
+#define ETH0_TX_UND_IRQ   GROUP3_IRQ_BASE + 13
+#define ETH1_DMA_RX_IRQ   GROUP1_IRQ_BASE + 4
+#define ETH1_DMA_TX_IRQ   GROUP1_IRQ_BASE + 5
+#define ETH1_RX_OVR_IRQ   GROUP3_IRQ_BASE + 15
+#define ETH1_TX_UND_IRQ   GROUP3_IRQ_BASE + 16
+
+#define ETH0_RX_DMA_ADDR  (DMA0_PhysicalAddress + 2*DMA_CHAN_OFFSET)
+#define ETH0_TX_DMA_ADDR  (DMA0_PhysicalAddress + 3*DMA_CHAN_OFFSET)
+#define ETH1_RX_DMA_ADDR  (DMA0_PhysicalAddress + 4*DMA_CHAN_OFFSET)
+#define ETH1_TX_DMA_ADDR  (DMA0_PhysicalAddress + 5*DMA_CHAN_OFFSET)
+
+/* the following must be powers of two */
+#define RC32438_NUM_RDS    64    		/* number of receive descriptors */
+#define RC32438_NUM_TDS    64    		/* number of transmit descriptors */
+
+#define RC32438_RBSIZE     1536  		/* size of one resource buffer = Ether MTU */
+#define RC32438_RDS_MASK   (RC32438_NUM_RDS-1)
+#define RC32438_TDS_MASK   (RC32438_NUM_TDS-1)
+#define RD_RING_SIZE (RC32438_NUM_RDS * sizeof(struct DMAD_s))
+#define TD_RING_SIZE (RC32438_NUM_TDS * sizeof(struct DMAD_s))
+
+#define RC32438_TX_TIMEOUT HZ * 100
+
+#define rc32438_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
+#define rc32438_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
+
+enum status	{ filled,	empty};
+#define IS_DMA_FINISHED(X)   (((X) & (DMAD_f_m)) != 0)
+#define IS_DMA_DONE(X)   (((X) & (DMAD_d_m)) != 0)
+
+
+/* Information that need to be kept for each board. */
+struct rc32438_local {
+	ETH_t  eth_regs;
+	DMA_Chan_t  rx_dma_regs;
+	DMA_Chan_t  tx_dma_regs;
+	volatile DMAD_t   td_ring;			/* transmit descriptor ring */
+	volatile DMAD_t   rd_ring;			/* receive descriptor ring  */
+
+	struct sk_buff* tx_skb[RC32438_NUM_TDS]; 	/* skbuffs for pkt to trans */
+	struct sk_buff* rx_skb[RC32438_NUM_RDS]; 	/* skbuffs for pkt to trans */
+
+	int weight;
+#ifdef CONFIG_RC32438_REVISION_ZA
+	struct tasklet_struct * ovr_und_tasklet;
+#endif
+	struct tasklet_struct * tx_tasklet;
+
+	int	rx_next_done;
+	int	rx_chain_head;
+	int	rx_chain_tail;
+	enum status	rx_chain_status;
+
+	int	tx_next_done;
+	int	tx_chain_head;
+	int	tx_chain_tail;
+	enum status	tx_chain_status;
+	int tx_count;
+	int	tx_full;
+
+	struct timer_list    mii_phy_timer;
+	unsigned long duplex_mode;
+
+	int   	rx_irq;
+	int    tx_irq;
+	int    ovr_irq;
+	int    und_irq;
+
+	struct net_device_stats stats;
+#ifdef CONFIG_SMP
+	spinlock_t lock;
+#endif
+
+	/* debug /proc entry */
+	struct proc_dir_entry *ps;
+	int dma_halt_cnt;
+        int ibudget;
+        int iquota;
+        int done_cnt;
+        int firstTime;
+        int not_done_cnt;
+        int dma_halt_nd_cnt;
+        int dma_ovr_count;
+        int dma_und_count;
+	int tx_stopped;
+};
+
+extern unsigned int idt_cpu_freq;
+
+/* Index to functions, as function prototypes. */
+static int rc32438_open(struct net_device *dev);
+static int rc32438_send_packet(struct sk_buff *skb, struct net_device *dev);
+//static void rc32438_mii_handler(unsigned long data);
+static irqreturn_t rc32438_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
+static irqreturn_t rc32438_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
+static int rc32438_poll(struct net_device *dev, int *budget);
+static int  rc32438_close(struct net_device *dev);
+static struct net_device_stats *rc32438_get_stats(struct net_device *dev);
+static void rc32438_multicast_list(struct net_device *dev);
+static int  rc32438_init(struct net_device *dev);
+static void rc32438_tx_timeout(struct net_device *dev);
+static void rc32438_tx_tasklet(unsigned long dev_id);
+#ifdef CONFIG_RC32438_REVISION_ZA
+static void rc32438_ovr_und_tasklet(unsigned long dev_id);
+#endif
+static void rc32438_cleanup_module(void);
+static int rc32438_probe(int port_num);
+int rc32438_init_module(void);
+
+static inline void rc32438_abort_dma(struct net_device *dev, DMA_Chan_t ch)
+{
+	if (rc32438_readl(&ch->dmac) & DMAC_run_m)
+	{
+		rc32438_writel(0x10, &ch->dmac);
+
+		while (!(rc32438_readl(&ch->dmas) & DMAS_h_m))
+			dev->trans_start = jiffies;
+
+		rc32438_writel(0, &ch->dmas);
+	}
+
+	rc32438_writel(0, &ch->dmadptr);
+	rc32438_writel(0, &ch->dmandptr);
+}
diff -uNr linux-2.6.16-rc5/.gitignore idtlinux/.gitignore
--- linux-2.6.16-rc5/.gitignore	2006-02-27 02:56:56.000000000 -0800
+++ idtlinux/.gitignore	1969-12-31 16:00:00.000000000 -0800
@@ -1,37 +0,0 @@
-#
-# NOTE! Don't add files that are generated in specific
-# subdirectories here. Add them in the ".gitignore" file
-# in that subdirectory instead.
-#
-# Normal rules
-#
-.*
-*.o
-*.a
-*.s
-*.ko
-*.so
-*.mod.c
-
-#
-# Top-level generic files
-#
-vmlinux*
-System.map
-Module.symvers
-
-#
-# Generated include files
-#
-include/asm
-include/asm-*/asm-offsets.h
-include/config
-include/linux/autoconf.h
-include/linux/compile.h
-include/linux/version.h
-include/asm-*/asm-offsets.h
-
-#
-# Quilt
-#
-patches
diff -uNr linux-2.6.16-rc5/include/asm-mips/bootinfo.h idtlinux/include/asm-mips/bootinfo.h
--- linux-2.6.16-rc5/include/asm-mips/bootinfo.h	2006-02-27 02:56:56.000000000 -0800
+++ idtlinux/include/asm-mips/bootinfo.h	2006-03-09 16:26:31.000000000 -0800
@@ -218,6 +218,20 @@
 #define MACH_GROUP_TITAN       22	/* PMC-Sierra Titan		*/
 #define  MACH_TITAN_YOSEMITE	1	/* PMC-Sierra Yosemite		*/
 
+
+/*                                                                                                                                                                                                                
+ * Valid machtype for group IDT boards                                                                                                                                                                            
+ */
+#define MACH_GROUP_IDT       23 /* IDT chips */
+
+#define  MACH_IDT_S334       0 /*  S334 */
+#define  MACH_IDT_EB355       1 /* EB355 */
+#define  MACH_IDT_EB438       2 /* EB438 */
+#define  MACH_IDT_EB365       3 /* EB365 */
+#define  MACH_IDT_EB434       4 /* EB434 */
+
+
+
 #define CL_SIZE			COMMAND_LINE_SIZE
 
 const char *get_system_type(void);
diff -uNr linux-2.6.16-rc5/include/asm-mips/cpu.h idtlinux/include/asm-mips/cpu.h
--- linux-2.6.16-rc5/include/asm-mips/cpu.h	2006-02-27 02:56:56.000000000 -0800
+++ idtlinux/include/asm-mips/cpu.h	2006-03-09 16:26:31.000000000 -0800
@@ -53,6 +53,9 @@
 #define PRID_IMP_R12000		0x0e00
 #define PRID_IMP_R8000		0x1000
 #define PRID_IMP_PR4450		0x1200
+#define PRID_IMP_RC32334        0x1800
+#define PRID_IMP_RC32355        0x1900
+#define PRID_IMP_RC32365        0x1900
 #define PRID_IMP_R4600		0x2000
 #define PRID_IMP_R4700		0x2100
 #define PRID_IMP_TX39		0x2200
@@ -196,7 +199,8 @@
 #define CPU_34K			60
 #define CPU_PR4450		61
 #define CPU_SB1A		62
-#define CPU_LAST		62
+#define CPU_RC32300             63
+#define CPU_LAST		63
 
 /*
  * ISA Level encodings
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32300.h idtlinux/include/asm-mips/idt-boards/rc32300/rc32300.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32300.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32300/rc32300.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,135 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   RC32300 helper routines
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_RC32300_H__
+#define __IDT_RC32300_H__
+
+#include <linux/delay.h>
+#include <asm/io.h>
+
+
+/* cpu pipeline flush */
+static inline void rc32300_sync(void)
+{
+	__asm__ volatile ("sync");
+}
+
+static inline void rc32300_sync_udelay(int us)
+{
+	__asm__ volatile ("sync");
+	udelay(us);
+}
+
+static inline void rc32300_sync_delay(int ms)
+{
+	__asm__ volatile ("sync");
+	mdelay(ms);
+}
+
+/*
+ * Macros to access internal RC32300 registers. No byte
+ * swapping should be done when accessing the internal
+ * registers.
+ */
+
+static inline u8 rc32300_readb(unsigned long pa)
+{
+	return *((volatile u8 *)KSEG1ADDR(pa));
+}
+static inline u16 rc32300_readw(unsigned long pa)
+{
+	return *((volatile u16 *)KSEG1ADDR(pa));
+}
+static inline u32 rc32300_readl(unsigned long pa)
+{
+	return *((volatile u32 *)KSEG1ADDR(pa));
+}
+static inline void rc32300_writeb(u8 val, unsigned long pa)
+{
+	*((volatile u8 *)KSEG1ADDR(pa)) = val;
+}
+static inline void rc32300_writew(u16 val, unsigned long pa)
+{
+	*((volatile u16 *)KSEG1ADDR(pa)) = val;
+}
+static inline void rc32300_writel(u32 val, unsigned long pa)
+{
+	*((volatile u32 *)KSEG1ADDR(pa)) = val;
+}
+
+
+#define local_readb __raw_readb
+#define local_readw __raw_readw
+#define local_readl __raw_readl
+
+#define local_writeb __raw_writeb
+#define local_writew __raw_writew
+#define local_writel __raw_writel
+
+
+/*
+ * C access to CLZ and CLO instructions
+ * (count leading zeroes/ones).
+ */
+static inline int rc32300_clz(unsigned long val)
+{
+	int ret;
+	__asm__ volatile (
+		".set\tnoreorder\n\t"
+		".set\tnoat\n\t"
+		".set\tmips32\n\t"
+		"clz\t%0,%1\n\t"
+		".set\tmips0\n\t"
+		".set\tat\n\t"
+		".set\treorder"
+		: "=r" (ret)
+		: "r" (val));
+	
+	return ret;
+}
+static inline int rc32300_clo(unsigned long val)
+{
+	int ret;
+	__asm__ volatile (
+		    ".set\tnoreorder\n\t"
+		    ".set\tnoat\n\t"
+		    ".set\tmips32\n\t"
+		    "clo\t%0,%1\n\t"
+		    ".set\tmips0\n\t"
+		    ".set\tat\n\t"
+		    ".set\treorder"
+		    : "=r" (ret)
+		    : "r" (val));
+	
+	return ret;
+}
+
+#endif  // __IDT_RC32300_H__
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32334.h idtlinux/include/asm-mips/idt-boards/rc32300/rc32334.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32334.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32300/rc32334.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,200 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Definitions for IDT RC32334 CPU.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+
+#ifndef __IDT_RC32334_H__
+#define __IDT_RC32334_H__
+
+#include <linux/delay.h>
+#include <asm/io.h>
+
+/* Base address of internal registers */
+#define RC32334_REG_BASE   0x18000000
+
+/* CPU and IP Bus Control */
+#define CPU_PORT_WIDTH     0xffffe200 // virtual!
+#define CPU_BTA            0xffffe204 // virtual!
+#define CPU_BUSERR_ADDR    0xffffe208 // virtual!
+#define CPU_IP_BTA         (RC32334_REG_BASE + 0x0000)
+#define CPU_IP_ADDR_LATCH  (RC32334_REG_BASE + 0x0004)
+#define CPU_IP_ARBITRATION (RC32334_REG_BASE + 0x0008)
+#define CPU_IP_BUSERR_CNTL (RC32334_REG_BASE + 0x0010)
+#define CPU_IP_BUSERR_ADDR (RC32334_REG_BASE + 0x0014)
+#define CPU_IP_SYSID       (RC32334_REG_BASE + 0x0018)
+
+/* Memory Controller */
+#define MEM_BASE_BANK0     (RC32334_REG_BASE + 0x0080)
+#define MEM_MASK_BANK0     (RC32334_REG_BASE + 0x0084)
+#define MEM_CNTL_BANK0     (RC32334_REG_BASE + 0x0200)
+#define MEM_BASE_BANK1     (RC32334_REG_BASE + 0x0088)
+#define MEM_MASK_BANK1     (RC32334_REG_BASE + 0x008c)
+#define MEM_CNTL_BANK1     (RC32334_REG_BASE + 0x0204)
+#define MEM_CNTL_BANK2     (RC32334_REG_BASE + 0x0208)
+#define MEM_CNTL_BANK3     (RC32334_REG_BASE + 0x020c)
+#define MEM_CNTL_BANK4     (RC32334_REG_BASE + 0x0210)
+#define MEM_CNTL_BANK5     (RC32334_REG_BASE + 0x0214)
+
+/* PCI Controller */
+#define PCI_INTR_PEND      (RC32334_REG_BASE + 0x05b0)
+#define PCI_INTR_MASK      (RC32334_REG_BASE + 0x05b4)
+#define PCI_INTR_CLEAR     (RC32334_REG_BASE + 0x05b8)
+#define CPU2PCI_INTR_PEND  (RC32334_REG_BASE + 0x05c0)
+#define CPU2PCI_INTR_MASK  (RC32334_REG_BASE + 0x05c4)
+#define CPU2PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05c8)
+#define PCI2CPU_INTR_PEND  (RC32334_REG_BASE + 0x05d0)
+#define PCI2CPU_INTR_MASK  (RC32334_REG_BASE + 0x05d4)
+#define PCI2CPU_INTR_CLEAR (RC32334_REG_BASE + 0x05d8)
+#define PCI_MEM1_BASE      (RC32334_REG_BASE + 0x20b0)
+#define PCI_MEM2_BASE      (RC32334_REG_BASE + 0x20b8)
+#define PCI_MEM3_BASE      (RC32334_REG_BASE + 0x20c0)
+#define PCI_IO1_BASE       (RC32334_REG_BASE + 0x20c8)
+#define PCI_ARBITRATION    (RC32334_REG_BASE + 0x20e0)
+#define PCI_CPU_MEM1_BASE  (RC32334_REG_BASE + 0x20e8)
+#define PCI_CPU_IO_BASE    (RC32334_REG_BASE + 0x2100)
+#define PCI_CFG_CNTL	   (RC32334_REG_BASE + 0x2cf8)
+#define PCI_CFG_DATA	   (RC32334_REG_BASE + 0x2cfc)
+
+/* Timers */
+#define TIMER0_CNTL        (RC32334_REG_BASE + 0x0700)
+#define TIMER0_COUNT       (RC32334_REG_BASE + 0x0704)
+#define TIMER0_COMPARE     (RC32334_REG_BASE + 0x0708)
+#define TIMER_REG_OFFSET   0x10
+
+/* Programmable I/O */
+#define PIO_DATA0          (RC32334_REG_BASE + 0x0600)
+#define PIO_DATA1          (RC32334_REG_BASE + 0x0610)
+
+/*
+ * DMA
+ *
+ * NOTE: DMA_IO is a trick for non linear RC32300_IO_DMA stuff
+ *
+ * DMA0: 18001400
+ * DMA1: 18001440
+ * DMA2: 18001900
+ * DMA3: 18001940
+ * NB: dma number must be immediate value or variable.
+ *      It MUST NOT be a function since it would get called twice!
+ */
+#define DMA_IO(n)       (((n)>1?0x500:0)+((n)&1?0x40:0))
+ 
+#define RC32300_IO_DMA(n)       (RC32334_REG_BASE + 0x1400 + DMA_IO(n))
+#define RC32300_DMA_CONFREG(n)  RC32300_IO_DMA(n)
+#define RC32300_DMA_BASEREG(n)  (RC32300_IO_DMA(n)+0x4)
+
+#define RC32300_DMA_CURRREG(n)  (RC32300_IO_DMA(n)+0x8)
+#define RC32300_DMA_STATREG(n)  (RC32300_IO_DMA(n)+0x10)
+#define RC32300_DMA_SRCREG(n)   (RC32300_IO_DMA(n)+0x14)
+#define RC32300_DMA_DSTREG(n)   (RC32300_IO_DMA(n)+0x18)
+#define RC32300_DMA_NEXTREG(n)  (RC32300_IO_DMA(n)+0x1c)
+
+#define RC32300_DMA_IRQ(n)  (GROUP7_IRQ_BASE+5*(n))
+
+/* Expansion Interrupt Controller */
+#define IC_GROUP0_PEND     (RC32334_REG_BASE + 0x0500)
+#define IC_GROUP0_MASK     (RC32334_REG_BASE + 0x0504)
+#define IC_GROUP0_CLEAR    (RC32334_REG_BASE + 0x0508)
+#define IC_GROUP_OFFSET    0x10
+
+#define NUM_INTR_GROUPS    15
+/*
+ * The IRQ mapping is as follows:
+ *
+ *    IRQ         Mapped To
+ *    ---     -------------------
+ *     0      SW0  (IP0) SW0 intr
+ *     1      SW1  (IP1) SW1 intr
+ *     2      Int0 (IP2) board-specific
+ *     3      Int1 (IP3) board-specific
+ *     4      Int2 (IP4) board-specific
+ *     -      Int3 (IP5) not used, mapped to IRQ's 8 and up
+ *     6      Int4 (IP6) board-specific
+ *     7      Int5 (IP7) CP0 Timer
+ *
+ * IRQ's 8 and up are all mapped to Int3 (IP5), which
+ * internally on the RC32334 is routed to the Expansion
+ * Interrupt Controller.
+ */
+#define MIPS_CPU_TIMER_IRQ 7
+
+#define GROUP1_IRQ_BASE  8                       // bus error
+#define GROUP2_IRQ_BASE  (GROUP1_IRQ_BASE + 1)   // PIO active low
+#define GROUP3_IRQ_BASE  (GROUP2_IRQ_BASE + 12)  // PIO active high
+#define GROUP4_IRQ_BASE  (GROUP3_IRQ_BASE + 8)   // Timer Rollovers
+#define GROUP5_IRQ_BASE  (GROUP4_IRQ_BASE + 8)   // UART0
+#define GROUP6_IRQ_BASE  (GROUP5_IRQ_BASE + 3)   // UART1
+#define GROUP7_IRQ_BASE  (GROUP6_IRQ_BASE + 3)   // DMA Ch0
+#define GROUP8_IRQ_BASE  (GROUP7_IRQ_BASE + 5)   // DMA Ch1
+#define GROUP9_IRQ_BASE  (GROUP8_IRQ_BASE + 5)   // DMA Ch2
+#define GROUP10_IRQ_BASE (GROUP9_IRQ_BASE + 5)   // DMA Ch3
+#define GROUP11_IRQ_BASE (GROUP10_IRQ_BASE + 5)  // PCI Ctlr errors
+#define GROUP12_IRQ_BASE (GROUP11_IRQ_BASE + 4)  // PCI Satellite Mode
+#define GROUP13_IRQ_BASE (GROUP12_IRQ_BASE + 16) // PCI to CPU Mailbox
+#define GROUP14_IRQ_BASE (GROUP13_IRQ_BASE + 4)  // SPI
+
+#define RC32334_NR_IRQS  (GROUP14_IRQ_BASE + 1)
+
+/* 16550 UARTs */
+#ifdef __MIPSEB__
+#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
+#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
+#else
+#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
+#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
+#endif
+
+#define RC32300_UART0_IRQ  GROUP5_IRQ_BASE
+#define RC32300_UART1_IRQ  GROUP6_IRQ_BASE
+
+#define IDT_CLOCK_MULT 2
+
+/* NVRAM */
+#define NVRAM_BASE         0x12000000
+#define NVRAM_ENVSIZE_OFF  4
+#define NVRAM_ENVSTART_OFF 0x40
+
+/* LCD 4-digit display */
+#define LCD_CLEAR          0x14000400
+#define LCD_DIGIT0         0x1400000f
+#define LCD_DIGIT1         0x14000008
+#define LCD_DIGIT2         0x14000007
+#define LCD_DIGIT3         0x14000003
+
+/* Interrupts routed on 79S334A board (see rc32334.h) */
+#define RC32334_SCC8530_IRQ  2
+#define RC32334_PCI_INTA_IRQ 3
+#define RC32334_PCI_INTB_IRQ 4
+#define RC32334_PCI_INTC_IRQ 6
+#define RC32334_PCI_INTD_IRQ 7
+
+#define RAM_SIZE	(32*1024*1024)
+
+#endif // __IDT_RC32334_H__
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32355_dma.h idtlinux/include/asm-mips/idt-boards/rc32300/rc32355_dma.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32355_dma.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32300/rc32355_dma.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,202 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     DMA controller defines on IDT RC32355
+ *
+ *  Copyright 2006 IDT Inc.
+ *  Author: Integrated Device Technology Inc. rischelp@idt.com
+ *
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#ifndef BANYAN_DMA_H
+#define BANYAN_DMA_H
+#include  <asm/idt-boards/rc32300/rc32300.h>
+
+/*
+ * An image of one RC32355 dma channel registers
+ */
+typedef struct {
+	u32 dmac;
+	u32 dmas;
+	u32 dmasm;
+	u32 dmadptr;
+	u32 dmandptr;
+} rc32355_dma_ch_t;
+
+/*
+ * An image of all RC32355 dma channel registers
+ */
+typedef struct {
+	rc32355_dma_ch_t ch[16];
+} rc32355_dma_regs_t;
+
+
+#define rc32355_dma_regs ((rc32355_dma_regs_t*)KSEG1ADDR(RC32355_DMA_BASE))
+
+
+/* DMAC register layout */
+
+#define DMAC_RUN	0x1	/* Halts processing when cleared	*/
+#define DMAC_DM		0x2	/* Done Mask, ignore DMA events		*/
+#define DMAC_MODE_MASK	0xC	/* DMA operating mode			*/
+
+#define DMAC_MODE_AUTO	0x0	/* DMA Auto Request Mode		*/
+#define DMAC_MODE_BURST	0x4	/* DMA Burst Request Mode		*/
+#define DMAC_MODE_TFER	0x8	/* DMA Transfer Request Mode		*/
+
+/* DMAS and DMASM register layout */
+
+#define DMAS_F		0x01	/* Finished */
+#define DMAS_D		0x02	/* Done */
+#define DMAS_C		0x04	/* Chain */
+#define DMAS_E		0x08	/* Error */
+#define DMAS_H		0x10	/* Halt */
+
+/* Polling count for DMAS_H bit in DMAS register after halting DMA */
+#define DMA_HALT_TIMEOUT 500
+
+
+static inline int rc32355_halt_dma(rc32355_dma_ch_t* ch)
+{
+	int timeout=1;
+	
+	if (local_readl(&ch->dmac) & DMAC_RUN) {
+		local_writel(0, &ch->dmac); 
+		for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
+			if (local_readl(&ch->dmas) & DMAS_H) {
+				local_writel(0, &ch->dmas);  
+				break;
+			}
+		}
+	}
+
+	return timeout ? 0 : 1;
+}
+
+static inline void rc32355_start_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
+{
+	local_writel(0, &ch->dmandptr); 
+	local_writel(dma_addr, &ch->dmadptr);
+}
+
+static inline void rc32355_chain_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
+{
+	local_writel(dma_addr, &ch->dmandptr);
+}
+
+
+/* The following can be used to describe DMA channels 0 to 15, and the	*/
+/* sub device's needed to select them in the DMADESC_DS_MASK field	*/
+
+#define DMA_CHAN_ATM01		0	     /* ATM interface 0,1 chan	*/
+
+#define DMA_CHAN_ATM0IN		0	     /* ATM interface 0 input	*/
+#define DMA_DEV_ATM0IN		0	     /* ATM interface 0 input	*/
+
+#define DMA_CHAN_ATM1IN		0	     /* ATM interface 1 input	*/
+#define DMA_DEV_ATM1IN		1	     /* ATM interface 1 input	*/
+
+#define DMA_CHAN_ATM0OUT	0	     /* ATM interface 0 output	*/
+#define DMA_DEV_ATM0OUT		2	     /* ATM interface 0 output	*/
+
+#define DMA_CHAN_ATM1OUT	0	     /* ATM interface 1 output	*/
+#define DMA_DEV_ATM1OUT		3	     /* ATM interface 1 output	*/
+
+/* for entry in {0,1,2,3,4,5,6,7} - note 5,6,7 share with those below */
+#define DMA_CHAN_ATMVCC(entry)	((entry)+1)  /* ATM VC cache entry 	*/
+#define DMA_DEV_ATMVCC(entry)	0
+
+#define DMA_CHAN_MEMTOMEM	6	     /* Memory to memory DMA 	*/
+#define DMA_DEV_MEMTOMEM	1	     /* Memory to memory DMA 	*/
+
+#define DMA_CHAN_ATMFMB0	7	     /* ATM Frame Mode Buffer 0	*/
+#define DMA_DEV_ATMFMB0		1	     /* ATM Frame Mode Buffer 0	*/
+
+#define DMA_CHAN_ATMFMB1	8	     /* ATM Frame Mode Buffer 1	*/
+#define DMA_DEV_ATMFMB1		1	     /* ATM Frame Mode Buffer 1	*/
+
+#define DMA_CHAN_ETHERIN	9	     /* Ethernet input		*/
+#define DMA_DEV_ETHERIN		0	     /* Ethernet input		*/
+
+#define DMA_CHAN_ETHEROUT	10	     /* Ethernet output		*/
+#define DMA_DEV_ETHEROUT	0	     /* Ethernet output		*/
+
+#define DMA_CHAN_TDMIN		11	     /* TDM Bus input		*/
+#define DMA_DEV_TDMIN		0	     /* TDM Bus input		*/
+
+#define DMA_CHAN_TDMOUT		12	     /* TDM Bus output		*/
+#define DMA_DEV_TDMOUT		0	     /* TDM Bus output		*/
+
+#define DMA_CHAN_USBIN		13	     /* USB input		*/
+#define DMA_DEV_USBIN		0	     /* USB input		*/
+
+#define DMA_CHAN_USBOUT		14	     /* USB output		*/
+#define DMA_DEV_USBOUT		0	     /* USB output		*/
+
+#define DMA_CHAN_EXTERN		15	     /* External DMA		*/
+#define DMA_DEV_EXTERN		0	     /* External DMA		*/
+
+/*
+ * An RC32355 dma descriptor in system memory
+ */
+typedef struct {
+	u32 cmdstat;	/* control and status */
+	u32 curr_addr;	/* current address of data */
+	u32 devcs;	/* peripheral-specific control and status */
+	u32 link;	/* link to next descriptor */
+} rc32355_dma_desc_t;
+
+/* Values for the descriptor cmdstat word */
+
+#define DMADESC_F		0x80000000u  /* Finished bit		*/
+#define DMADESC_D		0x40000000u  /* Done bit		*/
+#define DMADESC_T		0x20000000u  /* Terminated bit		*/
+#define DMADESC_IOD		0x10000000u  /* Interrupt On Done	*/
+#define DMADESC_IOF		0x08000000u  /* Interrupt On Finished	*/
+#define DMADESC_COD		0x04000000u  /* Chain On Done		*/
+#define DMADESC_COF		0x02000000u  /* Chain On Finished	*/
+
+#define DMADESC_DEVCMD_MASK	0x01C00000u  /* Device Command mask	*/
+#define DMADESC_DEVCMD_SHIFT	22	     /* Device Command shift	*/
+
+#define DMADESC_DS_MASK		0x00300000u  /* Device Select mask	*/
+#define DMADESC_DS_SHIFT	20	     /* Device Select shift	*/
+
+#define DMADESC_COUNT_MASK	0x0003FFFFu  /* Byte Count mask		*/
+#define DMADESC_COUNT_SHIFT	0	     /* Byte Count shift	*/
+
+#define IS_DMA_FINISHED(X)   ( ( (X) & DMADESC_F ) >> 31)   /* F Bit    */
+#define IS_DMA_DONE(X)       ( ( (X) & DMADESC_D ) >> 30)   /* D Bit    */
+#define IS_DMA_TERMINATED(X) ( ( (X) & DMADESC_T ) >> 29)   /* T Bit    */
+#define IS_DMA_USED(X) (((X) & (DMADESC_F | DMADESC_D | DMADESC_T)) != 0)
+
+#define DMA_DEVCMD(devcmd) \
+  (((devcmd) << DMADESC_DEVCMD_SHIFT) & DMADESC_DS_MASK)
+#define DMA_DS(ds)         \
+  (((ds) << DMADESC_DS_SHIFT) & DMADESC_DS_MASK)
+#define DMA_COUNT(count)   \
+  ((count) & DMADESC_COUNT_MASK)
+
+#endif /* RC32355_DMA_H */
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32355_eth.h idtlinux/include/asm-mips/idt-boards/rc32300/rc32355_eth.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32355_eth.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32300/rc32355_eth.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,438 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Ethernet registers on IDT RC32355
+ *
+ *  Copyright 2006 IDT Inc.
+ *  Author: Integrated Device Technology Inc. rischelp@idt.com
+ *
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+
+#ifndef RC32355_ETHER_H
+#define RC32355_ETHER_H
+
+#include <asm/idt-boards/rc32300/rc32355_dma.h>
+
+/*
+ * A partial image of the RC32355 ethernet registers
+ */
+typedef struct {
+	u32 ethintfc;
+	u32 ethfifott;
+	u32 etharc;
+	u32 ethhash0;
+	u32 ethhash1;
+	u32 ethfifost;
+	u32 ethfifos;
+	u32 ethodeops;
+	u32 ethis;
+	u32 ethos;
+	u32 ethmcp;
+	u32 _u1;
+	u32 ethid;
+	u32 _u2;
+	u32 _u3;
+	u32 _u4;
+	u32 ethod;
+	u32 _u5;
+	u32 _u6;
+	u32 _u7;
+	u32 ethodeop;
+	u32 _u8[43]; 
+	u32 ethsal0;
+	u32 ethsah0;
+	u32 ethsal1;
+	u32 ethsah1;
+	u32 ethsal2;
+	u32 ethsah2;
+	u32 ethsal3;
+	u32 ethsah3;
+	u32 ethrbc;
+	u32 ethrpc;
+	u32 ethrupc;
+	u32 ethrfc;
+	u32 ethtbc;
+	u32 ethgpf;
+	u32 _u9[50];
+	u32 ethmac1;
+	u32 ethmac2;
+	u32 ethipgt;
+	u32 ethipgr;
+	u32 ethclrt;
+	u32 ethmaxf;
+	u32 _u10;
+	u32 ethmtest;
+	u32 miimcfg;
+	u32 miimcmd;
+	u32 miimaddr;
+	u32 miimwtd;
+	u32 miimrdd;
+	u32 miimind;
+	u32 _u11;
+	u32 _u12;
+	u32 ethcfsa0;
+	u32 ethcfsa1;
+	u32 ethcfsa2;
+} rc32355_eth_regs_t;
+ 
+#define rc32355_eth_regs ((rc32355_eth_regs_t*)KSEG1ADDR(RC32355_ETH_BASE))
+
+#define ETH_INTFC   (RC32355_ETH_BASE + 0x000) /* INTerFace Control  */
+#define ETH_FIFOTT  (RC32355_ETH_BASE + 0x004) /* FIFO Transmit Threshold  */
+#define ETH_ARC     (RC32355_ETH_BASE + 0x008) /* Address Recognition Ctrl  */
+#define ETH_HASH0   (RC32355_ETH_BASE + 0x00C) /* 32 multicast Hash bits */
+#define ETH_HASH1   (RC32355_ETH_BASE + 0x010) /* another 32 Hash bits */
+#define ETH_FIFOST  (RC32355_ETH_BASE + 0x014) /* FIFO Status Threshold */
+#define ETH_FIFOS   (RC32355_ETH_BASE + 0x018) /* FIFO Status Register */
+#define ETH_ODEOPS  (RC32355_ETH_BASE + 0x01C) /* Out Data End-Of-Pkt Size */
+#define ETH_IS      (RC32355_ETH_BASE + 0x020) /* Input Status */
+#define ETH_OS      (RC32355_ETH_BASE + 0x024) /* Output Status  */
+#define ETH_MCP     (RC32355_ETH_BASE + 0x028) /* Managemt Clock Prescaler */
+#define ETH_ID      (RC32355_ETH_BASE + 0x030) /* Input Data register */
+#define ETH_OD      (RC32355_ETH_BASE + 0x040) /* Output Data register */
+#define ETH_ODEOP   (RC32355_ETH_BASE + 0x050) /* OD End-Of-Packet Size */
+
+/* for n in { 0, 1, 2, 3 } */
+#define ETH_SAL(n)  (RC32355_ETH_BASE + 0x100 + (n * 8)) /* Stn Address 2-5 */
+#define ETH_SAH(n)  (RC32355_ETH_BASE + 0x104 + (n * 8)) /* Stn Address 0-1 */
+
+#define ETH_RBC     (RC32355_ETH_BASE + 0x120) /* Receive Byte Count */
+#define ETH_RPC     (RC32355_ETH_BASE + 0x124) /* Receive Packet Count */
+#define ETH_RUPC    (RC32355_ETH_BASE + 0x128) /* Rx Undersized Pkt count */
+#define ETH_RFC     (RC32355_ETH_BASE + 0x12C) /* Receive Fragment Count */
+#define ETH_TBC     (RC32355_ETH_BASE + 0x130) /* Transmit Byte Count */
+#define ETH_GPF     (RC32355_ETH_BASE + 0x134) /* Generate Pause Frame */
+#define ETH_MAC1    (RC32355_ETH_BASE + 0x200) /* Medium Access Control 1 */
+#define ETH_MAC2    (RC32355_ETH_BASE + 0x204) /* Medium Access Control 2 */
+#define ETH_IPGT    (RC32355_ETH_BASE + 0x208) /* Back-to-back InterPkt Gap */
+#define ETH_IPGR    (RC32355_ETH_BASE + 0x20C) /* Non " InterPkt Gap */
+#define ETH_CLRT    (RC32355_ETH_BASE + 0x210) /* Collis'n Window and Retry */
+#define ETH_MAXF    (RC32355_ETH_BASE + 0x214) /* Maximum Frame Length */
+#define ETH_MTEST   (RC32355_ETH_BASE + 0x21C) /* MAC Test */
+
+#define ETHMIIM_CFG (RC32355_ETH_BASE + 0x220) /* MII Mgmt Configuration */
+#define ETHMIIM_CMD (RC32355_ETH_BASE + 0x224) /* MII Mgmt Command  */
+#define ETHMIIM_ADDR (RC32355_ETH_BASE + 0x228) /* MII Mgmt Address */
+#define ETHMIIM_WTD (RC32355_ETH_BASE + 0x22C) /* MII Mgmt Write Data */
+#define ETHMIIM_RDD (RC32355_ETH_BASE + 0x230) /* MII Mgmt Read Data */
+#define ETHMIIM_IND (RC32355_ETH_BASE + 0x234) /* MII Mgmt Indicators */
+
+/* for n in { 0, 1, 2 } */
+#define ETH_CFSA(n) (RC32355_ETH_BASE + 0x240 + ((n) * 4))  /* Station Addr */
+
+
+/*
+ * Register Interpretations follow
+ */
+
+/******************************************************************************
+ * ETHINTFC register
+ *****************************************************************************/
+
+#define ETHERINTFC_EN            (1<<0)
+#define ETHERINTFC_ITS           (1<<1)
+#define ETHERINTFC_RES           (1<<2)
+#define ETHERINTFC_RIP           (1<<2)
+#define ETHERINTFC_JAM           (1<<3)
+
+/******************************************************************************
+ * ETHFIFOTT register
+ *****************************************************************************/
+
+#define ETHERFIFOTT_TTH(v)      (((v)&0x3f)<<0)
+
+/******************************************************************************
+ * ETHARC register
+ *****************************************************************************/
+
+#define ETHERARC_PRO             (1<<0)
+#define ETHERARC_AM              (1<<1)
+#define ETHERARC_AFM             (1<<2)
+#define ETHERARC_AB              (1<<3)
+
+/******************************************************************************
+ * ETHHASH registers
+ *****************************************************************************/
+
+#define ETHERHASH0(v)            (((v)&0xffff)<<0)
+#define ETHERHASH1(v)            (((v)&0xffff)<<0)
+
+/******************************************************************************
+ * ETHSA registers
+ *****************************************************************************/
+
+#define ETHERSAL0(v)             (((v)&0xffff)<<0)
+#define ETHERSAL1(v)             (((v)&0xffff)<<0)
+#define ETHERSAL2(v)             (((v)&0xffff)<<0)
+#define ETHERSAL3(v)             (((v)&0xffff)<<0)
+#define ETHERSAH0(v)             (((v)&0xff)<<0)
+#define ETHERSAH1(v)             (((v)&0xff)<<0)
+#define ETHERSAH2(v)             (((v)&0xff)<<0)
+#define ETHERSAH3(v)             (((v)&0xff)<<0)
+
+/******************************************************************************
+ * ETHFIFOST register
+ *****************************************************************************/
+
+#define ETHERFIFOST_IRTH(v)      (((v)&0x3f)<<0)
+#define ETHERFIFOST_ORTH(v)      (((v)&0x3f)<<16)
+
+/******************************************************************************
+ * ETHFIFOS register
+ *****************************************************************************/
+
+#define ETHERFIFOS_IR            (1<<0)
+#define ETHERFIFOS_OR            (1<<1)  
+#define ETHERFIFOS_OVR           (1<<2)  
+#define ETHERFIFOS_UND           (1<<3)  
+
+/******************************************************************************
+ * DATA registers
+ *****************************************************************************/
+
+#define ETHERID(v)               (((v)&0xffff)<<0)
+#define ETHEROD(v)               (((v)&0xffff)<<0)
+
+/******************************************************************************
+ * ETHODEOPS register
+ *****************************************************************************/
+
+#define ETHERODEOPS_SIZE(v)      (((v)&0x3)<<0)
+
+/******************************************************************************
+ * ETHODEOP register
+ *****************************************************************************/
+
+#define ETHERODEOP(v)            (((v)&0xffff)<<0)
+
+/******************************************************************************
+ * ETHIS register
+ *****************************************************************************/
+
+#define ETHERIS_EOP              (1<<0)  
+#define ETHERIS_ROK              (1<<2)  
+#define ETHERIS_FM               (1<<3)  
+#define ETHERIS_MP               (1<<4)  
+#define ETHERIS_BP               (1<<5)  
+#define ETHERIS_VLT              (1<<6)  
+#define ETHERIS_CF               (1<<7)  
+#define ETHERIS_OVR              (1<<8)  
+#define ETHERIS_CRC              (1<<9)  
+#define ETHERIS_CV               (1<<10)  
+#define ETHERIS_DB               (1<<11)  
+#define ETHERIS_LE               (1<<12)  
+#define ETHERIS_LOR              (1<<13)  
+#define ETHERIS_SIZE(v)          (((v)&0x3)<<14)
+#define ETHERIS_LENGTH(v)        (((v)&0xff)<<16)
+
+/******************************************************************************
+ * ETHOS register
+ *****************************************************************************/
+
+#define ETHEROS_T                (1<<0)  
+#define ETHEROS_TOK              (1<<6)  
+#define ETHEROS_MP               (1<<7)  
+#define ETHEROS_BP               (1<<8)  
+#define ETHEROS_UND              (1<<9)  
+#define ETHEROS_OF               (1<<10)  
+#define ETHEROS_ED               (1<<11)  
+#define ETHEROS_EC               (1<<12)  
+#define ETHEROS_LC               (1<<13)  
+#define ETHEROS_TD               (1<<14)  
+#define ETHEROS_CRC              (1<<15)  
+#define ETHEROS_LE               (1<<16)  
+#define ETHEROS_CC(v)            (((v)&0xf)<<17)
+#define ETHEROS_PFD              (1<<21)  
+
+/******************************************************************************
+ * Statistics registers
+ *****************************************************************************/
+
+#define ETHERRBC(v)              (((v)&0xffff)<<0)
+#define ETHERRPC(v)              (((v)&0xffff)<<0)
+#define ETHERRUPC(v)             (((v)&0xffff)<<0)
+#define ETHERRFC(v)              (((v)&0xffff)<<0)
+#define ETHERTBC(v)              (((v)&0xffff)<<0)
+
+/******************************************************************************
+ * ETHGPF register
+ *****************************************************************************/
+
+#define ETHERGPF_PTV(v)          (((v)&0xff)<<0)
+
+/******************************************************************************
+ * MAC registers
+ *****************************************************************************/
+//ETHMAC1
+#define ETHERMAC1_RE             (1<<0)
+#define ETHERMAC1_PAF            (1<<1)
+#define ETHERMAC1_RFC            (1<<2)
+#define ETHERMAC1_TFC            (1<<3)
+#define ETHERMAC1_LB             (1<<4)
+#define ETHERMAC1_MR             (1<<15)
+
+//ETHMAC2
+#define ETHERMAC2_FD             (1<<0)
+#define ETHERMAC2_FLC            (1<<1)
+#define ETHERMAC2_HFE            (1<<2)
+#define ETHERMAC2_DC             (1<<3)
+#define ETHERMAC2_CEN            (1<<4)
+#define ETHERMAC2_PE             (1<<5)
+#define ETHERMAC2_VPE            (1<<6)
+#define ETHERMAC2_APE            (1<<7)
+#define ETHERMAC2_PPE            (1<<8)
+#define ETHERMAC2_LPE            (1<<9)
+#define ETHERMAC2_NB             (1<<12)
+#define ETHERMAC2_BP             (1<<13)
+#define ETHERMAC2_ED             (1<<14)
+
+//ETHIPGT
+#define ETHERIPGT(v)             (((v)&0x3f)<<0)
+
+//ETHIPGR
+#define ETHERIPGR_IPGR1(v)       (((v)&0x3f)<<0)
+#define ETHERIPGR_IPGR2(v)       (((v)&0x3f)<<8)
+
+//ETHCLRT
+#define ETHERCLRT_MAXRET(v)      (((v)&0x3f)<<0)
+#define ETHERCLRT_COLWIN(v)      (((v)&0x3f)<<8)
+
+//ETHMAXF
+#define ETHERMAXF(v)             (((v)&0x3f)<<0)
+
+//ETHMTEST
+#define ETHERMTEST_TB            (1<<2)
+
+//ETHMCP
+#define ETHERMCP_DIV(v)          (((v)&0xff)<<0)
+
+//MIIMCFG
+#define ETHERMIIMCFG_CS(v)          (((v)&0x3)<<2)
+#define ETHERMIIMCFG_R              (1<<15)
+
+//MIIMCMD
+#define ETHERMIIMCMD_RD             (1<<0)
+#define ETHERMIIMCMD_SCN            (1<<1)
+
+//MIIMADDR
+#define ETHERMIIMADDR_REGADDR(v)    (((v)&0x1f)<<0)
+#define ETHERMIIMADDR_PHYADDR(v)    (((v)&0x1f)<<8)
+
+//MIIMWTD
+#define ETHERMIIMWTD(v)             (((v)&0xff)<<0)
+
+//MIIMRDD
+#define ETHERMIIMRDD(v)             (((v)&0xff)<<0)
+
+//MIIMIND
+#define ETHERMIIMIND_BSY            (1<<0)
+#define ETHERMIIMIND_SCN            (1<<1)
+#define ETHERMIIMIND_NV             (1<<2)
+
+//DMA DEVCS IN
+#define ETHERDMA_IN_LENGTH(v)	(((v)&0xffff)<<16)
+#define ETHERDMA_IN_CES		(1<<14)
+#define ETHERDMA_IN_LOR		(1<<13)
+#define ETHERDMA_IN_LE		(1<<12)
+#define ETHERDMA_IN_DB		(1<<11)
+#define ETHERDMA_IN_CV		(1<<10)
+#define ETHERDMA_IN_CRC		(1<<9)
+#define ETHERDMA_IN_OVR		(1<<8)
+#define ETHERDMA_IN_CF		(1<<7)
+#define ETHERDMA_IN_VLT		(1<<6)
+#define ETHERDMA_IN_BP		(1<<5)
+#define ETHERDMA_IN_MP		(1<<4)
+#define ETHERDMA_IN_FM		(1<<3)
+#define ETHERDMA_IN_ROK		(1<<2)
+#define ETHERDMA_IN_LD		(1<<1)
+#define ETHERDMA_IN_FD		(1<<0)
+
+//DMA DEVCS OUT
+#define ETHERDMA_OUT_CC(v)	(((v)&0xf)<<17)
+#define ETHERDMA_OUT_CNT         0x001e0000
+#define ETHERDMA_OUT_SHFT       17
+#define ETHERDMA_OUT_LE		(1<<16)
+
+#define ETHERDMA_OUT_CRC	(1<<15)
+#define ETHERDMA_OUT_TD		(1<<14)
+#define ETHERDMA_OUT_LC		(1<<13)
+#define ETHERDMA_OUT_EC		(1<<12)
+#define ETHERDMA_OUT_ED		(1<<11)
+#define ETHERDMA_OUT_OF		(1<<10)
+#define ETHERDMA_OUT_UND	(1<<9)
+#define ETHERDMA_OUT_BP		(1<<8)
+#define ETHERDMA_OUT_MP		(1<<7)
+#define ETHERDMA_OUT_TOK	(1<<6)
+#define ETHERDMA_OUT_HEN	(1<<5)
+#define ETHERDMA_OUT_CEN	(1<<4)
+#define ETHERDMA_OUT_PEN	(1<<3)
+#define ETHERDMA_OUT_OEN	(1<<2)
+#define ETHERDMA_OUT_LD		(1<<1)
+#define ETHERDMA_OUT_FD		(1<<0)
+
+#define RCV_ERRS \
+  (ETHERDMA_IN_OVR | ETHERDMA_IN_CRC | ETHERDMA_IN_CV | ETHERDMA_IN_LE)
+#define TX_ERRS  \
+  (ETHERDMA_OUT_LC | ETHERDMA_OUT_EC | ETHERDMA_OUT_ED | \
+   ETHERDMA_OUT_OF | ETHERDMA_OUT_UND)
+
+#define IS_RCV_ROK(X)        (((X) & (1<<2)) >> 2)       /* Receive Okay     */
+#define IS_RCV_FM(X)         (((X) & (1<<3)) >> 3)       /* Is Filter Match  */
+#define IS_RCV_MP(X)         (((X) & (1<<4)) >> 4)       /* Is it MP         */
+#define IS_RCV_BP(X)         (((X) & (1<<5)) >> 5)       /* Is it BP         */
+#define IS_RCV_VLT(X)        (((X) & (1<<6)) >> 6)       /* VLAN Tag Detect  */
+#define IS_RCV_CF(X)         (((X) & (1<<7)) >> 7)       /* Control Frame    */
+#define IS_RCV_OVR_ERR(X)    (((X) & (1<<8)) >> 8)       /* Receive Overflow */
+#define IS_RCV_CRC_ERR(X)    (((X) & (1<<9)) >> 9)       /* CRC Error        */
+#define IS_RCV_CV_ERR(X)     (((X) & (1<<10))>>10)       /* Code Violation   */
+#define IS_RCV_DB_ERR(X)     (((X) & (1<<11))>>11)       /* Dribble Bits     */
+#define IS_RCV_LE_ERR(X)     (((X) & (1<<12))>>12)       /* Length error     */
+#define IS_RCV_LOR_ERR(X)    (((X) & (1<<13))>>13)       /* Length Out of
+                                                            Range            */
+#define IS_RCV_CES_ERR(X)    (((X) & (1<<14))>>14)       /* Preamble error   */
+#define RCVPKT_LENGTH(X)     (((X) & 0xFFFF0000)>>16)    /* Length of the
+                                                            received packet  */
+
+#define IS_TX_TOK(X)         (((X) & (1<<6) ) >> 6 )     /* Transmit Okay    */
+#define IS_TX_MP(X)          (((X) & (1<<7) ) >> 7 )     /* Multicast        */
+
+#define IS_TX_BP(X)          (((X) & (1<<8) ) >> 8 )     /* Broadcast        */
+#define IS_TX_UND_ERR(X)     (((X) & (1<<9) ) >> 9 )     /* Transmit FIFO
+                                                            Underflow        */
+#define IS_TX_OF_ERR(X)      (((X) & (1<<10)) >>10 )     /* Oversized frame  */
+#define IS_TX_ED_ERR(X)      (((X) & (1<<11)) >>11 )     /* Excessive
+							    deferral        */
+#define IS_TX_EC_ERR(X)      (((X) & (1<<12)) >>12 )     /* Excessive
+							    collisions      */
+#define IS_TX_LC_ERR(X)      (((X) & (1<<13)) >>13 )     /* Late Collision   */
+#define IS_TX_TD_ERR(X)      (((X) & (1<<14)) >>14 )     /* Transmit deferred*/
+#define IS_TX_CRC_ERR(X)     (((X) & (1<<15)) >>15 )     /* CRC Error        */
+#define IS_TX_LE_ERR(X)      (((X) & (1<<16)) >>16 )     /* Length Error     */
+
+#define TX_COLLISION_COUNT(X) (((X) & 0x001E0000u)>>17)  /* Collision Count  */
+
+#endif /* RC32355_ETHER_H */
+
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32355.h idtlinux/include/asm-mips/idt-boards/rc32300/rc32355.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32355.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32300/rc32355.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,174 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *     Definitions for IDT RC32355 CPU.
+ *
+ *  Copyright 2006 IDT Inc.
+ *  Author: Integrated Device Technology Inc. rischelp@idt.com
+ *
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+
+#ifndef _RC32355_H_
+#define _RC32355_H_
+
+#include <linux/delay.h>
+#include <asm/io.h>
+
+/* Base address of internal registers */
+#define RC32355_REG_BASE   0x18000000
+
+/* System ID Registers */
+#define CPU_SYSID          (RC32355_REG_BASE + 0x00018)
+#define CPU_BTADDR         (RC32355_REG_BASE + 0x0001c)
+#define CPU_REV            (RC32355_REG_BASE + 0x0002c)
+
+/* Reset Controller */
+#define RESET_CNTL         (RC32355_REG_BASE + 0x08000)
+
+/* Device Controller */
+#define DEV0_BASE          (RC32355_REG_BASE + 0x10000)
+#define DEV0_MASK          (RC32355_REG_BASE + 0x10004)
+#define DEV0_CNTL          (RC32355_REG_BASE + 0x10008)
+#define DEV0_TIMING        (RC32355_REG_BASE + 0x1000c)
+#define DEV_REG_OFFSET     0x10
+
+/* SDRAM Controller */
+#define SDRAM0_BASE        (RC32355_REG_BASE + 0x18000)
+#define SDRAM0_MASK        (RC32355_REG_BASE + 0x18004)
+#define SDRAM1_BASE        (RC32355_REG_BASE + 0x18008)
+#define SDRAM1_MASK        (RC32355_REG_BASE + 0x1800c)
+#define SDRAM_CNTL         (RC32355_REG_BASE + 0x18010)
+
+/* Bus Arbiter */
+#define BUS_ARB_CNTL0      (RC32355_REG_BASE + 0x20000)
+#define BUS_ARB_CNTL1      (RC32355_REG_BASE + 0x20004)
+
+/* Counters/Timers */
+#define TIMER0_COUNT       (RC32355_REG_BASE + 0x28000)
+#define TIMER0_COMPARE     (RC32355_REG_BASE + 0x28004)
+#define TIMER0_CNTL        (RC32355_REG_BASE + 0x28008)
+#define TIMER_REG_OFFSET   0x0C
+
+/* System Integrity */
+
+/* Interrupt Controller */
+#define IC_GROUP0_PEND     (RC32355_REG_BASE + 0x30000)
+#define IC_GROUP0_MASK     (RC32355_REG_BASE + 0x30004)
+#define IC_GROUP_OFFSET    0x08
+
+#define NUM_INTR_GROUPS    5
+/*
+ * The IRQ mapping is as follows:
+ *
+ *    IRQ         Mapped To
+ *    ---     -------------------
+ *     0      SW0  (IP0) SW0 intr
+ *     1      SW1  (IP1) SW1 intr
+ *     -      Int0 (IP2) mapped to GROUP0_IRQ_BASE
+ *     -      Int1 (IP3) mapped to GROUP1_IRQ_BASE
+ *     -      Int2 (IP4) mapped to GROUP2_IRQ_BASE
+ *     -      Int3 (IP5) mapped to GROUP3_IRQ_BASE
+ *     -      Int4 (IP6) mapped to GROUP4_IRQ_BASE
+ *     7      Int5 (IP7) CP0 Timer
+ *
+ * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
+ * internally on the RC32355 is routed to the Expansion
+ * Interrupt Controller.
+ */
+#define MIPS_CPU_TIMER_IRQ 7
+
+#define GROUP0_IRQ_BASE  8                      // Counter/Timers, UCW
+#define GROUP1_IRQ_BASE  (GROUP0_IRQ_BASE + 32) // DMA
+#define GROUP2_IRQ_BASE  (GROUP1_IRQ_BASE + 32) // ATM
+#define GROUP3_IRQ_BASE  (GROUP2_IRQ_BASE + 32) // TDM, Eth, USB, UARTs, I2C
+#define GROUP4_IRQ_BASE  (GROUP3_IRQ_BASE + 32) // GPIO
+
+#define RC32355_NR_IRQS  (GROUP4_IRQ_BASE + 32)
+
+/* DMA - see rc32355_dma.h for full list of registers */
+
+#define RC32355_DMA_BASE (RC32355_REG_BASE + 0x38000)
+#define DMA_CHAN_OFFSET  0x14
+
+/* GPIO Controller */
+
+/* TDM Bus */
+
+/* 16550 UARTs */
+#ifdef __MIPSEB__
+#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50003)
+#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50023)
+#else
+#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50000)
+#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50020)
+#endif
+
+#define RC32300_UART0_IRQ  (GROUP3_IRQ_BASE + 14)
+#define RC32300_UART1_IRQ  (GROUP3_IRQ_BASE + 17)
+
+/* ATM */
+
+/* Ethernet - see rc32355_eth.h for full list of registers */
+
+#define RC32355_ETH_BASE   (RC32355_REG_BASE + 0x60000)
+
+
+#define IDT_CLOCK_MULT 2
+
+/* Memory map of 79EB355 board */
+
+/* DRAM */
+#define RAM_BASE        0x00000000
+#define RAM_SIZE	(32*1024*1024)
+
+/* SRAM (device 1) */
+#define SRAM_BASE       0x02000000
+#define SRAM_SIZE       0x00100000
+
+/* FLASH (device 2) */
+#define FLASH_BASE      0x0C000000
+#define FLASH_SIZE      0x00C00000
+
+/* ATM PHY (device 4) */
+#define ATM_PHY_BASE    0x14000000
+
+/* TDM switch (device 3) */
+#define TDM_BASE        0x1A000000
+
+/* LCD panel (device 3) */
+#define LCD_BASE        0x1A002000
+
+/* RTC (DS1511W) (device 3) */
+#define RTC_BASE        0x1A004000
+
+/* NVRAM (256 bytes internal to the DS1511 RTC) */
+#define NVRAM_ADDR      RTC_BASE + 0x10
+#define NVRAM_DATA      RTC_BASE + 0x13
+#define NVRAM_ENVSIZE_OFF  4
+#define NVRAM_ENVSTART_OFF 32
+
+#endif /* _RC32355_H_ */
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32365_dma.h idtlinux/include/asm-mips/idt-boards/rc32300/rc32365_dma.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32365_dma.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32300/rc32365_dma.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,220 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   RC32365/336 DMA hardware abstraction.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_RC32365_DMA_H__
+#define __IDT_RC32365_DMA_H__
+
+enum
+{
+	DMA0_PhysicalAddress	= 0x18038000,
+	DMA_PhysicalAddress	= DMA0_PhysicalAddress,		// Default
+
+	DMA0_VirtualAddress	= 0xb8038000,
+	DMA_VirtualAddress	= DMA0_VirtualAddress,		// Default
+} ;
+
+/*
+ * DMA descriptor (in physical memory).
+ */
+
+typedef struct DMAD_s
+{
+	u32			control ;	// Control. use DMAD_*
+	u32			ca ;		// Current Address.
+	u32			devcs ; 	// Device control and status.
+	u32			link ;		// Next descriptor in chain.
+} volatile *DMAD_t ;
+
+enum
+{
+	DMAD_size		= sizeof (struct DMAD_s),
+	DMAD_count_b		= 0,		// in DMAD_t -> control
+	DMAD_count_m		= 0x0003ffff,	// in DMAD_t -> control
+	DMAD_ds_b		= 20,		// in DMAD_t -> control
+	DMAD_ds_m		= 0x00300000,	// in DMAD_t -> control
+	DMAD_ds_extToMem0_v	= 0,
+	DMAD_ds_memToExt0_v	= 1,
+	DMAD_ds_extToMem1_v	= 0,
+	DMAD_ds_memToExt1_v	= 1,
+	DMAD_ds_ethRcv0_v	= 0,
+	DMAD_ds_ethXmt0_v	= 0,
+	DMAD_ds_ethRcv1_v	= 0,
+	DMAD_ds_ethXmt2_v	= 0,
+	DMAD_ds_memToFifo_v	= 0,
+	DMAD_ds_fifoToMem_v	= 0,
+	DMAD_ds_rng_de_v	   = 1,//randomNumberGenerator on LC/DE
+	DMAD_ds_pciToMem_v	= 0,
+	DMAD_ds_memToPci_v	= 0,
+	DMAD_ds_securityInput_v = 0,
+	DMAD_ds_securityOutput_v = 0,
+	DMAD_ds_rng_se_v	= 0,//randomNumberGenerator on SE
+	
+	DMAD_devcmd_b		= 22,		// in DMAD_t -> control
+	DMAD_devcmd_m		= 0x01c00000,	// in DMAD_t -> control
+	DMAD_devcmd_byte_v	= 0,	//memory-to-memory
+	DMAD_devcmd_halfword_v	= 1,	//memory-to-memory
+	DMAD_devcmd_word_v	= 2,	//memory-to-memory
+	DMAD_devcmd_2words_v	= 3,	//memory-to-memory
+	DMAD_devcmd_4words_v	= 4,	//memory-to-memory
+	DMAD_devcmd_6words_v	= 5,	//memory-to-memory
+	DMAD_devcmd_8words_v	= 6,	//memory-to-memory
+	DMAD_devcmd_16words_v	= 7,	//memory-to-memory
+	DMAD_cof_b		= 25,		// chain on finished
+	DMAD_cof_m		= 0x02000000,	// 
+	DMAD_cod_b		= 26,		// chain on done
+	DMAD_cod_m		= 0x04000000,	// 
+	DMAD_iof_b		= 27,		// interrupt on finished
+	DMAD_iof_m		= 0x08000000,	// 
+	DMAD_iod_b		= 28,		// interrupt on done
+	DMAD_iod_m		= 0x10000000,	// 
+	DMAD_t_b		= 29,		// terminated
+	DMAD_t_m		= 0x20000000,	// 
+	DMAD_d_b		= 30,		// done
+	DMAD_d_m		= 0x40000000,	// 
+	DMAD_f_b		= 31,		// finished
+	DMAD_f_m		= 0x80000000,	// 
+} ;
+
+/*
+ * DMA register (within Internal Register Map).
+ */
+
+struct DMA_Chan_s
+{
+	u32		dmac ;		// Control.
+	u32		dmas ;		// Status.	
+	u32		dmasm ; 	// Mask.
+	u32		dmadptr ;	// Descriptor pointer.
+	u32		dmandptr ;	// Next descriptor pointer.
+};
+
+typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
+
+//DMA_Channels	  use DMACH_count instead
+
+enum
+{
+	DMAC_run_b	= 0,		// 
+	DMAC_run_m	= 0x00000001,	// 
+	DMAC_dm_b	= 1,		// done mask
+	DMAC_dm_m	= 0x00000002,	// 
+	DMAC_mode_b	= 2,		// 
+	DMAC_mode_m	= 0x0000000c,	// 
+	DMAC_mode_auto_v	= 0,
+	DMAC_mode_burst_v	= 1,
+	DMAC_mode_transfer_v	= 2, //usually used
+	DMAC_mode_reserved_v	= 3,
+	DMAC_a_b	= 4,		// 
+	DMAC_a_m	= 0x00000010,	// 
+	
+	DMAS_f_b	= 0,		// finished (sticky) 
+	DMAS_f_m	= 0x00000001,	//		     
+	DMAS_d_b	= 1,		// done (sticky)     
+	DMAS_d_m	= 0x00000002,	//		     
+	DMAS_c_b	= 2,		// chain (sticky)    
+	DMAS_c_m	= 0x00000004,	//		     
+	DMAS_e_b	= 3,		// error (sticky)    
+	DMAS_e_m	= 0x00000008,	//		     
+	DMAS_h_b	= 4,		// halt (sticky)     
+	DMAS_h_m	= 0x00000010,	//		     
+
+	DMASM_f_b	= 0,		// finished (1=mask)
+	DMASM_f_m	= 0x00000001,	// 
+	DMASM_d_b	= 1,		// done (1=mask)
+	DMASM_d_m	= 0x00000002,	// 
+	DMASM_c_b	= 2,		// chain (1=mask)
+	DMASM_c_m	= 0x00000004,	// 
+	DMASM_e_b	= 3,		// error (1=mask)
+	DMASM_e_m	= 0x00000008,	// 
+	DMASM_h_b	= 4,		// halt (1=mask)
+	DMASM_h_m	= 0x00000010,	// 
+} ;
+
+/*
+ * DMA channel definitions
+ */
+
+enum
+{
+	DMACH_ethRcv0 = 0,
+	DMACH_ethXmt0 = 1,
+	DMACH_ethRcv1 = 2,
+	DMACH_ethXmt2 = 3,
+	DMACH_pciToMem = 4,
+	DMACH_memToPci = 5,
+	DMACH_securityInput = 6,
+	DMACH_securityOutput = 7,
+	DMACH_rng = 8, 
+	
+	DMACH_count //must be last
+};
+
+
+typedef struct DMAC_s
+{
+	struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
+} volatile *DMA_t ;
+
+
+/*
+ * External DMA parameters
+*/
+
+enum
+{
+	DMADEVCMD_ts_b	= 0,		// ts field in devcmd
+	DMADEVCMD_ts_m	= 0x00000007,	// ts field in devcmd
+	DMADEVCMD_ts_byte_v	= 0,
+	DMADEVCMD_ts_halfword_v	= 1,
+	DMADEVCMD_ts_word_v	= 2,
+	DMADEVCMD_ts_2word_v	= 3,
+	DMADEVCMD_ts_4word_v	= 4,
+	DMADEVCMD_ts_6word_v	= 5,
+	DMADEVCMD_ts_8word_v	= 6,
+	DMADEVCMD_ts_16word_v	= 7
+};
+
+
+#if 1	// aws - Compatibility.
+#	define	EXTDMA_ts_b		DMADEVCMD_ts_b
+#	define	EXTDMA_ts_m		DMADEVCMD_ts_m
+#	define	EXTDMA_ts_byte_v	DMADEVCMD_ts_byte_v
+#	define	EXTDMA_ts_halfword_v	DMADEVCMD_ts_halfword_v
+#	define	EXTDMA_ts_word_v	DMADEVCMD_ts_word_v
+#	define	EXTDMA_ts_2word_v	DMADEVCMD_ts_2word_v
+#	define	EXTDMA_ts_4word_v	DMADEVCMD_ts_4word_v
+#	define	EXTDMA_ts_6word_v	DMADEVCMD_ts_6word_v
+#	define	EXTDMA_ts_8word_v	DMADEVCMD_ts_8word_v
+#	define	EXTDMA_ts_16word_v	DMADEVCMD_ts_16word_v
+#endif	// aws - Compatibility.
+
+#endif	// __IDT_RC32365_DMA_H__
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h idtlinux/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,78 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   RC32365/336 DMA interface routines.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_RC32365_DMA_V_H__
+#define __IDT_RC32365_DMA_V_H__
+
+
+#include  <asm/idt-boards/rc32300/rc32300.h>
+#include  <asm/idt-boards/rc32300/rc32365_dma.h> 
+#include  <asm/idt-boards/rc32300/rc32365.h>
+
+#define DMA_CHAN_OFFSET  0x14
+#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
+#define IS_DMA_FINISHED(X)   (((X) & (DMAD_f_m)) != 0)
+#define IS_DMA_DONE(X)   (((X) & (DMAD_d_m)) != 0)
+
+#define DMA_COUNT(count)   \
+  ((count) & DMAD_count_m)
+
+#define DMA_HALT_TIMEOUT 500
+
+static inline int rc32365_halt_dma(DMA_Chan_t ch)
+{
+	int timeout=1;
+	if (local_readl(&ch->dmac) & DMAC_run_m) {
+		local_writel(0, &ch->dmac); 
+		
+		for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
+			if (local_readl(&ch->dmas) & DMAS_h_m) {
+				local_writel(0, &ch->dmas);  
+				break;
+			}
+		}
+
+	}
+
+	return timeout ? 0 : 1;
+}
+
+
+static inline void rc32365_start_dma(DMA_Chan_t ch, u32 dma_addr)
+{
+	local_writel(0, &ch->dmandptr); 
+	local_writel(dma_addr, &ch->dmadptr);
+}
+
+static inline void rc32365_chain_dma(DMA_Chan_t ch, u32 dma_addr)
+{
+	local_writel(dma_addr, &ch->dmandptr);
+}
+#endif //__IDT_RC32365_DMA_V_H__
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32365_eth.h idtlinux/include/asm-mips/idt-boards/rc32300/rc32365_eth.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32365_eth.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32300/rc32365_eth.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,336 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   RC32365/336 Ethernet hardware abstraction.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#ifndef	__IDT_RC32365_ETH_H__
+#define	__IDT_RC32365_ETH_H__
+
+enum
+{
+	ETH0_PhysicalAddress	= 0x18058000,
+	ETH_PhysicalAddress	= ETH0_PhysicalAddress,		// Default
+	ETH0_VirtualAddress	= 0xb8058000,
+
+	ETH_VirtualAddress	= ETH0_VirtualAddress,		// Default
+
+	ETH1_PhysicalAddress	= 0x18060000,
+	ETH1_VirtualAddress	= 0xb8060000,			// Default
+} ;
+
+typedef struct
+{
+	u32 ethintfc		;
+	u32 ethfifott		;
+	u32 etharc		;
+	u32 ethhash0		;
+	u32 ethhash1		;
+	u32 ethu0 [4]		;	// Reserved.	
+	u32 ethpfs		;
+	u32 ethmcp		;
+	u32 eth_u1 [10]		;	// Reserved.
+	u32 ethspare		;
+	u32 eth_u2 [42]		;	// Reserved. 
+	u32 ethsal0		;
+	u32 ethsah0		;
+	u32 ethsal1		;
+	u32 ethsah1		;
+	u32 ethsal2		;
+	u32 ethsah2		;
+	u32 ethsal3		;
+	u32 ethsah3		;
+	u32 ethrbc		;
+	u32 ethrpc		;
+	u32 ethrupc		;
+	u32 ethrfc		;
+	u32 ethtbc		;
+	u32 ethgpf		;
+	u32 eth_u9 [50]		;	// Reserved.	
+	u32 ethmac1		;
+	u32 ethmac2		;
+	u32 ethipgt		;
+	u32 ethipgr		;
+	u32 ethclrt		;
+	u32 ethmaxf		;
+	u32 eth_u10		;	// Reserved.	
+	u32 ethmtest		;
+	u32 miimcfg		;
+	u32 miimcmd		;
+	u32 miimaddr		;
+	u32 miimwtd		;
+	u32 miimrdd		;
+	u32 miimind		;
+	u32 eth_u11		;	// Reserved.
+	u32 eth_u12		;	// Reserved.
+	u32 ethcfsa0		;
+	u32 ethcfsa1		;
+	u32 ethcfsa2		;
+} volatile *ETH_t;
+
+enum
+{
+	ETHINTFC_en_b		= 0,
+	ETHINTFC_en_m		= 0x00000001,
+	ETHINTFC_its_b		= 1,
+	ETHINTFC_its_m		= 0x00000002,
+	ETHINTFC_rip_b		= 2,
+	ETHINTFC_rip_m		= 0x00000004,
+	ETHINTFC_jam_b		= 3,
+	ETHINTFC_jam_m		= 0x00000008,
+	ETHINTFC_ovr_b		= 4,
+	ETHINTFC_ovr_m		= 0x00000010,
+	ETHINTFC_und_b		= 5,
+	ETHINTFC_und_m		= 0x00000020,
+
+	ETHFIFOTT_tth_b		= 0,
+	ETHFIFOTT_tth_m		= 0x0000007f,
+
+	ETHARC_pro_b		= 0,
+	ETHARC_pro_m		= 0x00000001,
+	ETHARC_am_b		= 1,
+	ETHARC_am_m		= 0x00000002,
+	ETHARC_afm_b		= 2,
+	ETHARC_afm_m		= 0x00000004,
+	ETHARC_ab_b		= 3,
+	ETHARC_ab_m		= 0x00000008,
+
+	ETHSAL_byte5_b		= 0,
+	ETHSAL_byte5_m		= 0x000000ff,
+	ETHSAL_byte4_b		= 8,
+	ETHSAL_byte4_m		= 0x0000ff00,
+	ETHSAL_byte3_b		= 16,
+	ETHSAL_byte3_m		= 0x00ff0000,
+	ETHSAL_byte2_b		= 24,
+	ETHSAL_byte2_m		= 0xff000000,
+
+	ETHSAH_byte1_b		= 0,
+	ETHSAH_byte1_m		= 0x000000ff,
+	ETHSAH_byte0_b		= 8,
+	ETHSAH_byte0_m		= 0x0000ff00,
+	
+	ETHGPF_ptv_b		= 0,
+	ETHGPF_ptv_m		= 0x0000ffff,
+
+	ETHPFS_pfd_b		= 0,
+	ETHPFS_pfd_m		= 0x00000001,
+
+	ETHCFSA0_cfsa4_b	= 0,
+	ETHCFSA0_cfsa4_m	= 0x000000ff,
+	ETHCFSA0_cfsa5_b	= 8,
+	ETHCFSA0_cfsa5_m	= 0x0000ff00,
+
+	ETHCFSA1_cfsa2_b	= 0,
+	ETHCFSA1_cfsa2_m	= 0x000000ff,
+	ETHCFSA1_cfsa3_b	= 8,
+	ETHCFSA1_cfsa3_m	= 0x0000ff00,
+
+	ETHCFSA2_cfsa0_b	= 0,
+	ETHCFSA2_cfsa0_m	= 0x000000ff,
+	ETHCFSA2_cfsa1_b	= 8,
+	ETHCFSA2_cfsa1_m	= 0x0000ff00,
+
+	ETHMAC1_re_b		= 0,
+	ETHMAC1_re_m		= 0x00000001,
+	ETHMAC1_paf_b		= 1,
+	ETHMAC1_paf_m		= 0x00000002,
+	ETHMAC1_rfc_b		= 2,
+	ETHMAC1_rfc_m		= 0x00000004,
+	ETHMAC1_tfc_b		= 3,
+	ETHMAC1_tfc_m		= 0x00000008,
+	ETHMAC1_lb_b		= 4,
+	ETHMAC1_lb_m		= 0x00000010,
+	ETHMAC1_mr_b		= 31,
+	ETHMAC1_mr_m		= 0x80000000,
+
+	ETHMAC2_fd_b		= 0,
+	ETHMAC2_fd_m		= 0x00000001,
+	ETHMAC2_flc_b		= 1,
+	ETHMAC2_flc_m		= 0x00000002,
+	ETHMAC2_hfe_b		= 2,
+	ETHMAC2_hfe_m		= 0x00000004,
+	ETHMAC2_dc_b		= 3,
+	ETHMAC2_dc_m		= 0x00000008,
+	ETHMAC2_cen_b		= 4,
+	ETHMAC2_cen_m		= 0x00000010,
+	ETHMAC2_pe_b		= 5,
+	ETHMAC2_pe_m		= 0x00000020,
+	ETHMAC2_vpe_b		= 6,
+	ETHMAC2_vpe_m		= 0x00000040,
+	ETHMAC2_ape_b		= 7,
+	ETHMAC2_ape_m		= 0x00000080,
+	ETHMAC2_ppe_b		= 8,
+	ETHMAC2_ppe_m		= 0x00000100,
+	ETHMAC2_lpe_b		= 9,
+	ETHMAC2_lpe_m		= 0x00000200,
+	ETHMAC2_nb_b		= 12,
+	ETHMAC2_nb_m		= 0x00001000,
+	ETHMAC2_bp_b		= 13,
+	ETHMAC2_bp_m		= 0x00002000,
+	ETHMAC2_ed_b		= 14,
+	ETHMAC2_ed_m		= 0x00004000,
+
+	ETHIPGT_ipgt_b		= 0,
+	ETHIPGT_ipgt_m		= 0x0000007f,
+
+	ETHIPGR_ipgr2_b		= 0,
+	ETHIPGR_ipgr2_m		= 0x0000007f,
+	ETHIPGR_ipgr1_b		= 8,
+	ETHIPGR_ipgr1_m		= 0x00007f00,
+
+	ETHCLRT_maxret_b	= 0,
+	ETHCLRT_maxret_m	= 0x0000000f,
+	ETHCLRT_colwin_b	= 8,
+	ETHCLRT_colwin_m	= 0x00003f00,
+
+	ETHMAXF_maxf_b		= 0,
+	ETHMAXF_maxf_m		= 0x0000ffff,
+
+	ETHMTEST_tb_b		= 2,
+	ETHMTEST_tb_m		= 0x00000004,
+
+	ETHMCP_div_b		= 0,
+	ETHMCP_div_m		= 0x000000ff,
+	
+	MIIMCFG_rsv_b		= 0,
+	MIIMCFG_rsv_m		= 0x0000000c,
+
+	MIIMCMD_rd_b		= 0,
+	MIIMCMD_rd_m		= 0x00000001,
+	MIIMCMD_scn_b		= 1,
+	MIIMCMD_scn_m		= 0x00000002,
+
+	MIIMADDR_regaddr_b	= 0,
+	MIIMADDR_regaddr_m	= 0x0000001f,
+	MIIMADDR_phyaddr_b	= 8,
+	MIIMADDR_phyaddr_m	= 0x00001f00,
+
+	MIIMWTD_wdata_b		= 0,
+	MIIMWTD_wdata_m		= 0x0000ffff,
+
+	MIIMRDD_rdata_b		= 0,
+	MIIMRDD_rdata_m		= 0x0000ffff,
+
+	MIIMIND_bsy_b		= 0,
+	MIIMIND_bsy_m		= 0x00000001,
+	MIIMIND_scn_b		= 1,
+	MIIMIND_scn_m		= 0x00000002,
+	MIIMIND_nv_b		= 2,
+	MIIMIND_nv_m		= 0x00000004,
+
+} ;
+
+/*
+ * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
+ */
+enum
+{
+	ETHRX_fd_b		= 0,
+	ETHRX_fd_m		= 0x00000001,
+	ETHRX_ld_b		= 1,
+	ETHRX_ld_m		= 0x00000002,
+	ETHRX_rok_b		= 2,
+	ETHRX_rok_m		= 0x00000004,
+	ETHRX_fm_b		= 3,
+	ETHRX_fm_m		= 0x00000008,
+	ETHRX_mp_b		= 4,
+	ETHRX_mp_m		= 0x00000010,
+	ETHRX_bp_b		= 5,
+	ETHRX_bp_m		= 0x00000020,
+	ETHRX_vlt_b		= 6,
+	ETHRX_vlt_m		= 0x00000040,
+	ETHRX_cf_b		= 7,
+	ETHRX_cf_m		= 0x00000080,
+	ETHRX_ovr_b		= 8,
+	ETHRX_ovr_m		= 0x00000100,
+	ETHRX_crc_b		= 9,
+	ETHRX_crc_m		= 0x00000200,
+	ETHRX_cv_b		= 10,
+	ETHRX_cv_m		= 0x00000400,
+	ETHRX_db_b		= 11,
+	ETHRX_db_m		= 0x00000800,
+	ETHRX_le_b		= 12,
+	ETHRX_le_m		= 0x00001000,
+	ETHRX_lor_b		= 13,
+	ETHRX_lor_m		= 0x00002000,
+	ETHRX_ces_b		= 14,
+	ETHRX_ces_m		= 0x00004000,
+	ETHRX_length_b		= 16,
+	ETHRX_length_m		= 0xffff0000,
+
+	ETHTX_fd_b		= 0,
+	ETHTX_fd_m		= 0x00000001,
+	ETHTX_ld_b		= 1,
+	ETHTX_ld_m		= 0x00000002,
+	ETHTX_oen_b		= 2,
+	ETHTX_oen_m		= 0x00000004,
+	ETHTX_pen_b		= 3,
+	ETHTX_pen_m		= 0x00000008,
+	ETHTX_cen_b		= 4,
+	ETHTX_cen_m		= 0x00000010,
+	ETHTX_hen_b		= 5,
+	ETHTX_hen_m		= 0x00000020,
+	ETHTX_tok_b		= 6,
+	ETHTX_tok_m		= 0x00000040,
+	ETHTX_mp_b		= 7,
+	ETHTX_mp_m		= 0x00000080,
+	ETHTX_bp_b		= 8,
+	ETHTX_bp_m		= 0x00000100,
+	ETHTX_und_b		= 9,
+	ETHTX_und_m		= 0x00000200,
+	ETHTX_of_b		= 10,
+	ETHTX_of_m		= 0x00000400,
+	ETHTX_ed_b		= 11,
+	ETHTX_ed_m		= 0x00000800,
+	ETHTX_ec_b		= 12,
+	ETHTX_ec_m		= 0x00001000,
+	ETHTX_lc_b		= 13,
+	ETHTX_lc_m		= 0x00002000,
+	ETHTX_td_b		= 14,
+	ETHTX_td_m		= 0x00004000,
+	ETHTX_crc_b		= 15,
+	ETHTX_crc_m		= 0x00008000,
+	ETHTX_le_b		= 16,
+	ETHTX_le_m		= 0x00010000,
+	ETHTX_cc_b		= 17,
+	ETHTX_cc_m		= 0x001E0000,
+} ;
+
+enum
+{
+	ETH0_IPABMC_PhysicalAddress	= 0x18040010,
+	ETH0_IPABMC_VirtualAddress	= 0xb8040000,
+	ETH1_IPABMC_PhysicalAddress	= 0x18040018,
+	ETH1_IPABMC_VirtualAddress	= 0xb8040018,
+} ;
+
+typedef struct
+{
+	u32 ipabmcrx		;
+	u32 ipabmctx		;
+}volatile *IPABM_ETH_t;
+#endif //__IDT_RC32365_ETH_H__
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h idtlinux/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,65 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   RC32365/336 Ethernet status checking.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_RC32365_ETH_V_H__
+#define __IDT_RC32365_ETH_V_H__
+#include  <asm/idt-boards/rc32300/rc32365_eth.h> 
+
+#define IS_TX_TOK(X)         (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b )   /* Transmit Okay    */
+#define IS_TX_MP(X)          (((X) & (1<<ETHTX_mp_b))  >> ETHTX_mp_b )    /* Multicast        */
+#define IS_TX_BP(X)          (((X) & (1<<ETHTX_bp_b))  >> ETHTX_bp_b )    /* Broadcast        */
+#define IS_TX_UND_ERR(X)     (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b )   /* Transmit FIFO Underflow */
+#define IS_TX_OF_ERR(X)      (((X) & (1<<ETHTX_of_b))  >> ETHTX_of_b )    /* Oversized frame  */
+#define IS_TX_ED_ERR(X)      (((X) & (1<<ETHTX_ed_b))  >> ETHTX_ed_b )    /* Excessive deferral  */
+#define IS_TX_EC_ERR(X)      (((X) & (1<<ETHTX_ec_b))  >> ETHTX_ec_b)     /* Excessive collisions  */
+#define IS_TX_LC_ERR(X)      (((X) & (1<<ETHTX_lc_b))  >> ETHTX_lc_b )    /* Late Collision   */
+#define IS_TX_TD_ERR(X)      (((X) & (1<<ETHTX_td_b))  >> ETHTX_td_b )    /* Transmit deferred*/
+#define IS_TX_CRC_ERR(X)     (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b )   /* CRC Error        */
+#define IS_TX_LE_ERR(X)      (((X) & (1<<ETHTX_le_b))  >>  ETHTX_le_b )    /* Length Error     */
+
+#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b)  /* Collision Count  */
+
+#define IS_RCV_ROK(X)        (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b)    /* Receive Okay     */
+#define IS_RCV_FM(X)         (((X) & (1<<ETHRX_fm_b))  >> ETHRX_fm_b)     /* Is Filter Match  */
+#define IS_RCV_MP(X)         (((X) & (1<<ETHRX_mp_b))  >> ETHRX_mp_b)     /* Is it MP         */
+#define IS_RCV_BP(X)         (((X) & (1<<ETHRX_bp_b))  >> ETHRX_bp_b)     /* Is it BP         */
+#define IS_RCV_VLT(X)        (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b)    /* VLAN Tag Detect  */
+#define IS_RCV_CF(X)         (((X) & (1<<ETHRX_cf_b))  >> ETHRX_cf_b)     /* Control Frame    */
+#define IS_RCV_OVR_ERR(X)    (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b)    /* Receive Overflow */
+#define IS_RCV_CRC_ERR(X)    (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b)    /* CRC Error        */
+#define IS_RCV_CV_ERR(X)     (((X) & (1<<ETHRX_cv_b))  >> ETHRX_cv_b)     /* Code Violation   */
+#define IS_RCV_DB_ERR(X)     (((X) & (1<<ETHRX_db_b))  >> ETHRX_db_b)     /* Dribble Bits     */
+#define IS_RCV_LE_ERR(X)     (((X) & (1<<ETHRX_le_b))  >> ETHRX_le_b)     /* Length error     */
+#define IS_RCV_LOR_ERR(X)    (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b)    /* Length Out of Range */
+#define IS_RCV_CES_ERR(X)    (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b)  /* Preamble error   */
+#define RCVPKT_LENGTH(X)     (((X) & ETHRX_length_m) >> ETHRX_length_b)   /* Length of the received packet */
+
+#endif //__IDT_RC32365_ETH_V_H__
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h idtlinux/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,175 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   RC32365/336 GPIO hardware abstraction.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef	__IDT_RC32365_GPIO_H__
+#define	__IDT_RC32365_GPIO_H__
+
+enum
+{
+	GPIO0_PhysicalAddress	= 0x18048000,
+	GPIO_PhysicalAddress	= GPIO0_PhysicalAddress,	// Default
+	
+	GPIO0_VirtualAddress	= 0xb8048000,
+	GPIO_VirtualAddress	= GPIO0_VirtualAddress,		// Default
+} ;
+
+typedef struct
+{
+	u32   gpiofunc;   /* GPIO Function Register
+			   * gpiofunc[x]==0 bit = gpio
+			   * func[x]==1  bit = altfunc
+			   */
+	u32   gpiocfg;    /* GPIO Configuration Register
+			   * gpiocfg[x]==0 bit = input
+			   * gpiocfg[x]==1 bit = output
+			   */
+	u32   gpiod;	    /* GPIO Data Register
+			     * gpiod[x] read/write gpio pinX status
+			     */
+	u32   gpioilevel; /* GPIO Interrupt Status Register
+			   * interrupt level (see gpioistat)
+			   */
+	u32   gpioistat;  /* Gpio Interrupt Status Register
+			   * istat[x] = (gpiod[x] == level[x])
+			   * cleared in ISR (STICKY bits)
+			   */
+	u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
+} volatile * GPIO_t ;
+
+typedef enum
+{
+	GPIO_gpio_v	    = 0,		// gpiofunc use pin as GPIO.
+	GPIO_alt_v	    = 1,		// gpiofunc use pin as alt.
+	GPIO_input_v	    = 0,		// gpiocfg use pin as input.
+	GPIO_output_v	    = 1,		// gpiocfg use pin as output.
+	GPIO_pin0_b	    = 0,
+	GPIO_pin0_m	    = 0x00000001,
+	GPIO_pin1_b	    = 1,
+	GPIO_pin1_m	    = 0x00000002,
+	GPIO_pin2_b	    = 2,
+	GPIO_pin2_m	    = 0x00000004,
+	GPIO_pin3_b	    = 3,
+	GPIO_pin3_m	    = 0x00000008,
+	GPIO_pin4_b	    = 4,
+	GPIO_pin4_m	    = 0x00000010,
+	GPIO_pin5_b	    = 5,
+	GPIO_pin5_m	    = 0x00000020,
+	GPIO_pin6_b	    = 6,
+	GPIO_pin6_m	    = 0x00000040,
+	GPIO_pin7_b	    = 7,
+	GPIO_pin7_m	    = 0x00000080,
+	GPIO_pin8_b	    = 8,
+	GPIO_pin8_m	    = 0x00000100,
+	GPIO_pin9_b	    = 9,
+	GPIO_pin9_m	    = 0x00000200,
+	GPIO_pin10_b	    = 10,
+	GPIO_pin10_m	    = 0x00000400,
+	GPIO_pin11_b	    = 11,
+	GPIO_pin11_m	    = 0x00000800,
+	GPIO_pin12_b	    = 12,
+	GPIO_pin12_m	    = 0x00001000,
+	GPIO_pin13_b	    = 13,
+	GPIO_pin13_m	    = 0x00002000,
+	GPIO_pin14_b	    = 14,
+	GPIO_pin14_m	    = 0x00004000,
+	GPIO_pin15_b	    = 15,
+	GPIO_pin15_m	    = 0x00008000,
+	
+// Alternate function pins.  Corrsponding gpiofunc bit set to GPIO_alt_v.
+	
+	GPIO_u0sout_b	    = GPIO_pin0_b,		// UART 0 serial out.
+	GPIO_u0sout_m	    = GPIO_pin0_m,
+	GPIO_u0sout_cfg_v   = GPIO_output_v,
+	
+	GPIO_u0sinp_b	    = GPIO_pin1_b,			// UART 0 serial in.
+	GPIO_u0sinp_m	    = GPIO_pin1_m,
+	GPIO_u0sinp_cfg_v   = GPIO_input_v,
+	
+	GPIO_maddr22_b	    = GPIO_pin2_b, 	// M&P bus bit 22.
+	GPIO_maddr22_m	    = GPIO_pin2_m,
+	GPIO_maddr22_cfg_v  = GPIO_output_v,
+	
+	GPIO_maddr23_b	    = GPIO_pin3_b, 	// M&P bus bit 23.
+	GPIO_maddr23_m	    = GPIO_pin3_m,
+	GPIO_maddr23_cfg_v  = GPIO_output_v,
+	
+	GPIO_maddr24_b	    = GPIO_pin4_b, 	// M&P bus bit 24.
+	GPIO_maddr24_m	    = GPIO_pin4_m,
+	GPIO_maddr24_cfg_v  = GPIO_output_v,
+	
+	GPIO_maddr25_b	    = GPIO_pin5_b, 	// M&P bus bit 25.
+	GPIO_maddr25_m	    = GPIO_pin5_m,
+	GPIO_maddr25_cfg_v  = GPIO_output_v,
+	
+	GPIO_rngclk_b 	    = GPIO_pin6_b, 	// reserved.
+	GPIO_rngclk_m 	    = GPIO_pin6_m,
+	GPIO_rngclk_cfg_v   = GPIO_input_v,
+
+	GPIO_sdckenp_b 	    = GPIO_pin7_b, 	// reserved.
+	GPIO_sdckenp_m 	    = GPIO_pin7_m,
+	GPIO_sdckenp_cfg_v  = GPIO_output_v,
+
+	GPIO_cen1_b 	    = GPIO_pin8_b, 	// reserved.
+	GPIO_cen1_m 	    = GPIO_pin8_m,
+	GPIO_cen1_cfg_v	    = GPIO_output_v,
+
+	GPIO_cen2_b 	    = GPIO_pin9_b, 	// reserved.
+	GPIO_cen2_m 	    = GPIO_pin9_m,
+	GPIO_cen2_cfg_v	    = GPIO_output_v,
+	
+	GPIO_regn_b 	    = GPIO_pin10_b, 	// reserved.
+	GPIO_regn_m 	    = GPIO_pin10_m,
+	GPIO_regn_cfg_v	    = GPIO_output_v,
+	
+	GPIO_iordn_b 	    = GPIO_pin11_b, 	// reserved.
+	GPIO_iordn_m 	    = GPIO_pin11_m,
+	GPIO_iordn_cfg_v    = GPIO_output_v,
+	
+	GPIO_iowrn_b 	    = GPIO_pin12_b, 	// reserved.
+	GPIO_iowrn_m 	    = GPIO_pin12_m,
+	GPIO_iowrn_cfg_v    = GPIO_output_v,
+    
+	GPIO_pcireqn2_b	    = GPIO_pin13_b, 	// PCI messaging int.
+	GPIO_pcireqn2_m	    = GPIO_pin13_m,
+	GPIO_pcireqn2_cfg_v = GPIO_input_v,
+	
+	GPIO_pcigntn2_b	    = GPIO_pin14_b, 	// PCI messaging int.
+	GPIO_pcigntn2_m	    = GPIO_pin14_m,
+	GPIO_pcigntn2_cfg_v = GPIO_output_v,
+	
+	GPIO_pcimuintn_b    = GPIO_pin15_b, 	// PCI messaging int.
+	GPIO_pcimuintn_m    = GPIO_pin15_m,
+	GPIO_pcimuintn_cfg_v= GPIO_output_v,
+	
+} GPIO_DEFS_t;
+
+#endif //__IDT_RC32365_GPIO_H__
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h idtlinux/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,84 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Routines to set/clear/toggle GPIO on RC32365
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+#ifndef	__IDT_RC32365_GPIO_V_H__
+#define	__IDT_RC32365_GPIO_V_H__
+
+
+#ifdef _LANGUAGE_ASSEMBLY
+#define SET_GPIO(pin) \
+	lui t5,0xb804 ; \
+	ori t5,t5,0x8000 ; \
+	lw  t4,8(t5) ; \
+	ori t4,t4,pin ; \
+	sw  t4,8(t5) ;
+
+#define CLEAR_GPIO(pin) \
+	lui t5,0xb804 ; \
+	ori t5,t5,0x8000 ; \
+	lw  t4,8(t5) ; \
+        lui t6,0xFFFF; \
+        ori t6,t6,0xFFFF; \
+	xori t6,t6,pin ; \
+        and  t4,t6 ; \
+	sw  t4,8(t5) ;
+
+#define TOGGLE_GPIO(pin) \
+	lui t5,0xb804 ; \
+	ori t5,t5,0x8000 ; \
+	lw  t4,8(t5) ; \
+	xori t4,t4,pin ; \
+	sw  t4,8(t5) ;
+
+#else // !_LANGUAGE_ASSEMBLY 
+#include  <asm/rc32300/types.h> 
+#include  <asm/rc32300/rc32365_gpio.h> 
+#include  <asm/rc32300/rc32365.h>
+
+static inline void set_gpio(unsigned long pin)
+{
+  gpio->gpiod |= pin;
+}
+ 
+static inline void clear_gpio(unsigned long pin)
+{
+  gpio->gpiod &= ~pin;
+}
+static inline void toggle_gpio(unsigned long pin)
+{
+  gpio->gpiod ^= pin;
+}
+#define SET_GPIO(pin) set_gpio(pin)
+#define CLEAR_GPIO(pin) clear_gpio(pin)
+#define TOGGLE_GPIO(pin) toggle_gpio(pin)
+#endif // _LANGUAGE_ASSEMBLY 
+
+#endif //__IDT_RC32365_GPIO_V_H__
+
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32365.h idtlinux/include/asm-mips/idt-boards/rc32300/rc32365.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32365.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32300/rc32365.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,154 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Definitions for IDT RC32365 CPU.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_RC32365_H__
+#define __IDT_RC32365_H__
+
+extern unsigned int cedar_za;
+
+/* Base address of internal registers */
+#define RC32365_REG_BASE   0x18000000
+
+/* System ID Registers */
+#define CPU_SYSID          (RC32365_REG_BASE + 0x00018)
+#define CPU_DEVTYPE        (RC32365_REG_BASE + 0x0001c)
+
+/* Reset Controller */
+#define RESET_CNTL         (RC32365_REG_BASE + 0x08000)
+#define BOOT_VECTOR        (RC32365_REG_BASE + 0x08004)
+
+/* Device Controller */
+#define DEV0_BASE          (RC32365_REG_BASE + 0x10000)
+#define DEV0_MASK          (RC32365_REG_BASE + 0x10004)
+#define DEV0_CNTL          (RC32365_REG_BASE + 0x10008)
+#define DEV0_TIMING        (RC32365_REG_BASE + 0x1000c)
+#define DEV_REG_OFFSET     0x10
+
+/* SDRAM Controller */
+#define SDRAM0_BASE        (RC32365_REG_BASE + 0x18000)
+#define SDRAM0_MASK        (RC32365_REG_BASE + 0x18004)
+#define SDRAM1_BASE        (RC32365_REG_BASE + 0x18008)
+#define SDRAM1_MASK        (RC32365_REG_BASE + 0x1800c)
+#define SDRAM_CNTL         (RC32365_REG_BASE + 0x18010)
+
+/* Counters/Timers */
+#define TIMER0_COUNT       (RC32365_REG_BASE + 0x20000)
+#define TIMER0_COMPARE     (RC32365_REG_BASE + 0x20004)
+#define TIMER0_CNTL        (RC32365_REG_BASE + 0x20008)
+#define TIMER0_SELECT      (RC32365_REG_BASE + 0x2000c)
+#define TIMER_REG_OFFSET   0x10
+
+/* System Integrity */
+
+/* Interrupt Controller */
+#define IC_GROUP0_PEND     (RC32365_REG_BASE + 0x30000)
+#define IC_GROUP0_TEST     (RC32365_REG_BASE + 0x30004)
+#define IC_GROUP0_MASK     (RC32365_REG_BASE + 0x30008)
+#define IC_GROUP_OFFSET    0x0c
+
+#define NUM_INTR_GROUPS    5
+/*
+ * The IRQ mapping is as follows:
+ *
+ *    IRQ         Mapped To
+ *    ---     -------------------
+ *     0      SW0  (IP0) SW0 intr
+ *     1      SW1  (IP1) SW1 intr
+ *     -      Int0 (IP2) mapped to GROUP0_IRQ_BASE
+ *     -      Int1 (IP3) mapped to GROUP1_IRQ_BASE
+ *     -      Int2 (IP4) mapped to GROUP2_IRQ_BASE
+ *     -      Int3 (IP5) mapped to GROUP3_IRQ_BASE
+ *     -      Int4 (IP6) mapped to GROUP4_IRQ_BASE
+ *     7      Int5 (IP7) CP0 Timer
+ *
+ * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
+ * internally on the RC32365 is routed to the Expansion
+ * Interrupt Controller.
+ */
+#define MIPS_CPU_TIMER_IRQ 7
+
+#define GROUP0_IRQ_BASE  8                      // Counter/Timers, UCW
+#define GROUP1_IRQ_BASE  (GROUP0_IRQ_BASE + 32) // DMA
+#define GROUP2_IRQ_BASE  (GROUP1_IRQ_BASE + 32) // RNG, SEC
+#define GROUP3_IRQ_BASE  (GROUP2_IRQ_BASE + 32) // Eth, PCI, UARTs
+#define GROUP4_IRQ_BASE  (GROUP3_IRQ_BASE + 32) // GPIO
+
+#define RC32365_NR_IRQS  (GROUP4_IRQ_BASE + 32)
+
+/* DMA - see rc32365_dma.h for full list of registers */
+
+#define RC32365_DMA_BASE (RC32365_REG_BASE + 0x38000)
+#define DMA_CHAN_OFFSET  0x14
+
+/* GPIO Controller */
+#define gpio              ((volatile GPIO_t) GPIO0_VirtualAddress)
+
+/* 16550 UARTs */
+#ifdef __MIPSEB__
+#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50003)
+#else
+#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50000)
+#endif
+#define RC32300_UART0_IRQ  (GROUP3_IRQ_BASE + 0)
+
+/* Ethernet - see rc32365_eth.h for full list of registers */
+
+#define RC32365_ETH_BASE   (RC32365_REG_BASE + 0x58000)
+
+#define IDT_CLOCK_MULT     2
+
+/* FLASH (device 1) */
+#define FLASH_BASE         0x08000000
+#define FLASH_SIZE         0x00800000
+
+/* LCD 4-digit display (device 2) */
+#define LCD_DIGIT0         0x0C000003
+#define LCD_DIGIT1         0x0C000002
+#define LCD_DIGIT2         0x0C000001
+#define LCD_DIGIT3         0x0C000000
+
+/* RTC (DS1553) (device 2) */
+#define RTC_BASE           0x0c800000
+/* NVRAM */
+#define NVRAM_BASE         RTC_BASE
+#define NVRAM_ENVSIZE_OFF  4
+#define NVRAM_ENVSTART_OFF 32
+
+/* Interrupts routed on 79EB365 board */
+#define RC32365_PCI_INTA_IRQ (GROUP4_IRQ_BASE +  8)
+#define RC32365_PCI_INTB_IRQ (GROUP4_IRQ_BASE +  9)
+#define RC32365_PCI_INTC_IRQ (GROUP4_IRQ_BASE + 10)
+#define RC32365_PCI_INTD_IRQ (GROUP4_IRQ_BASE + 11)
+
+#define RAM_SIZE	   (32 * 1024 * 1024)
+
+#endif //__IDT_RC32365_H__
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32365_pci.h idtlinux/include/asm-mips/idt-boards/rc32300/rc32365_pci.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32365_pci.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32300/rc32365_pci.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,509 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Datatype declaration for IDT 79EB365/336 PCI
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_RC32365_PCI_H__
+#define __IDT_RC32365_PCI_H__
+
+enum
+{
+	PCI0_PhysicalAddress	= 0x18068000,
+	PCI_PhysicalAddress	= PCI0_PhysicalAddress,
+	
+	PCI0_VirtualAddress	= 0xb8068000,
+	PCI_VirtualAddress	= PCI0_VirtualAddress,
+} ;
+
+enum
+{
+	PCI_LbaCount	= 4,		// Local base addresses.
+} ;
+
+typedef struct
+{
+	u32	a ;		// Address.
+	u32	c ;		// Control.
+	u32	m ;		// mapping.
+} PCI_Map_s ;
+
+typedef struct
+{
+	u32		pcic ;
+	u32		pcis ;
+	u32		pcism ;
+	u32		pcicfga ;
+	u32		pcicfgd ;
+	PCI_Map_s	pcilba [PCI_LbaCount] ;
+	u32		pcidac ;
+	u32		pcidas ;
+	u32		pcidasm ;
+	u32		pcidad ;
+	u32		pcidma8c ;
+	u32		pcidma9c ;
+	u32		pcitc ;
+} volatile *PCI_t ;
+
+// PCI messaging unit.
+enum
+{
+	PCIM_Count	= 2,
+} ;
+typedef struct
+{
+	u32		pciim [PCIM_Count] ;
+	u32		pciom [PCIM_Count] ;
+	u32		pciid ;
+	u32		pciiic ;
+	u32		pciiim ;
+	u32		pciiod ;
+	u32		pciioic ;
+	u32		pciioim ;
+} volatile *PCIM_t ;
+
+/*******************************************************************************
+ *
+ * PCI Control Register
+ *
+ ******************************************************************************/
+enum
+{
+	PCIC_en_b	= 0,
+	PCIC_en_m	= 0x00000001,
+	PCIC_tnr_b	= 1,
+	PCIC_tnr_m	= 0x00000002,
+	PCIC_sce_b	= 2,
+	PCIC_sce_m	= 0x00000004,
+	PCIC_ien_b	= 3,
+	PCIC_ien_m	= 0x00000008,
+	PCIC_aaa_b	= 4,
+	PCIC_aaa_m	= 0x00000010,
+	PCIC_eap_b	= 5,
+	PCIC_eap_m	= 0x00000020,
+	PCIC_pcim_b	= 6,
+	PCIC_pcim_m	= 0x000001c0,
+		PCIC_pcim_disabled_v	= 0,
+		PCIC_pcim_tnr_v 	= 1,	// Satellite - target not ready
+		PCIC_pcim_suspend_v	= 2,	// Satellite - suspended CPU.
+		PCIC_pcim_extern_v	= 3,	// Host - external arbiter.
+		PCIC_pcim_fixed_v	= 4,	// Host - fixed priority arb.
+		PCIC_pcim_roundrobin_v	= 5,	// Host - round robin priority.
+		PCIC_pcim_reserved6_v	= 6,
+		PCIC_pcim_reserved7_v	= 7,
+	PCIC_igm_b	= 9,
+	PCIC_igm_m	= 0x00000200,
+} ;
+
+/*******************************************************************************
+ *
+ * PCI Status Register
+ *
+ ******************************************************************************/
+enum {
+	PCIS_eed_b	= 0,
+	PCIS_eed_m	= 0x00000001,
+	PCIS_wr_b	= 1,
+	PCIS_wr_m	= 0x00000002,
+	PCIS_nmi_b	= 2,
+	PCIS_nmi_m	= 0x00000004,
+	PCIS_ii_b	= 3,
+	PCIS_ii_m	= 0x00000008,
+	PCIS_cwe_b	= 4,
+	PCIS_cwe_m	= 0x00000010,
+	PCIS_cre_b	= 5,
+	PCIS_cre_m	= 0x00000020,
+	PCIS_mdpe_b	= 6,
+	PCIS_mdpe_m	= 0x00000040,
+	PCIS_sta_b	= 7,
+	PCIS_sta_m	= 0x00000080,
+	PCIS_rta_b	= 8,
+	PCIS_rta_m	= 0x00000100,
+	PCIS_rma_b	= 9,
+	PCIS_rma_m	= 0x00000200,
+	PCIS_sse_b	= 10,
+	PCIS_sse_m	= 0x00000400,
+	PCIS_ose_b	= 11,
+	PCIS_ose_m	= 0x00000800,
+	PCIS_pe_b	= 12,
+	PCIS_pe_m	= 0x00001000,
+	PCIS_tae_b	= 13,
+	PCIS_tae_m	= 0x00002000,
+	PCIS_rle_b	= 14,
+	PCIS_rle_m	= 0x00004000,
+	PCIS_bme_b	= 15,
+	PCIS_bme_m	= 0x00008000,
+	PCIS_prd_b	= 16,
+	PCIS_prd_m	= 0x00010000,
+	PCIS_rip_b	= 17,
+	PCIS_rip_m	= 0x00020000,
+} ;
+
+/*******************************************************************************
+ *
+ * PCI Status Mask Register
+ *
+ ******************************************************************************/
+enum {
+	PCISM_eed_b		= 0,
+	PCISM_eed_m		= 0x00000001,
+	PCISM_wr_b		= 1,
+	PCISM_wr_m		= 0x00000002,
+	PCISM_nmi_b		= 2,
+	PCISM_nmi_m		= 0x00000004,
+	PCISM_ii_b		= 3,
+	PCISM_ii_m		= 0x00000008,
+	PCISM_cwe_b		= 4,
+	PCISM_cwe_m		= 0x00000010,
+	PCISM_cre_b		= 5,
+	PCISM_cre_m		= 0x00000020,
+	PCISM_mdpe_b		= 6,
+	PCISM_mdpe_m		= 0x00000040,
+	PCISM_sta_b		= 7,
+	PCISM_sta_m		= 0x00000080,
+	PCISM_rta_b		= 8,
+	PCISM_rta_m		= 0x00000100,
+	PCISM_rma_b		= 9,
+	PCISM_rma_m		= 0x00000200,
+	PCISM_sse_b		= 10,
+	PCISM_sse_m		= 0x00000400,
+	PCISM_ose_b		= 11,
+	PCISM_ose_m		= 0x00000800,
+	PCISM_pe_b		= 12,
+	PCISM_pe_m		= 0x00001000,
+	PCISM_tae_b		= 13,
+	PCISM_tae_m		= 0x00002000,
+	PCISM_rle_b		= 14,
+	PCISM_rle_m		= 0x00004000,
+	PCISM_bme_b		= 15,
+	PCISM_bme_m		= 0x00008000,
+	PCISM_prd_b		= 16,
+	PCISM_prd_m		= 0x00010000,
+	PCISM_rip_b		= 17,
+	PCISM_rip_m		= 0x00020000,
+} ;
+
+/*******************************************************************************
+ *
+ * PCI Configuration Address Register
+ *
+ ******************************************************************************/
+enum {
+	PCICFGA_reg_b		= 2,
+	PCICFGA_reg_m		= 0x000000fc,
+	PCICFGA_reg_id_v	= 0x00>>2, //use PCFGID_
+	PCICFGA_reg_04_v	= 0x04>>2, //use PCFG04_
+	PCICFGA_reg_08_v	= 0x08>>2, //use PCFG08_
+	PCICFGA_reg_0C_v	= 0x0C>>2, //use PCFG0C_
+	PCICFGA_reg_pba0_v	= 0x10>>2, //use PCIPBA_
+	PCICFGA_reg_pba1_v	= 0x14>>2, //use PCIPBA_
+	PCICFGA_reg_pba2_v	= 0x18>>2, //use PCIPBA_
+	PCICFGA_reg_pba3_v	= 0x1c>>2, //use PCIPBA_
+	PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
+	PCICFGA_reg_3C_v	= 0x3C>>2, //use PCFG3C_
+	PCICFGA_reg_pba0c_v	= 0x44>>2, //use PCIPBAC_
+	PCICFGA_reg_pba0m_v	= 0x48>>2,
+	PCICFGA_reg_pba1c_v	= 0x4c>>2, //use PCIPBAC_
+	PCICFGA_reg_pba1m_v	= 0x50>>2,
+	PCICFGA_reg_pba2c_v	= 0x54>>2, //use PCIPBAC_
+	PCICFGA_reg_pba2m_v	= 0x58>>2,
+	PCICFGA_reg_pba3c_v	= 0x5c>>2, //use PCIPBAC_
+	PCICFGA_reg_pba3m_v	= 0x60>>2,
+	PCICFGA_reg_pmgt_v	= 0x64>>2,
+	PCICFGA_func_b		= 8,
+	PCICFGA_func_m		= 0x00000700,
+	PCICFGA_dev_b		= 11,
+	PCICFGA_dev_m		= 0x0000f800,
+	PCICFGA_dev_internal_v	= 0,
+	PCICFGA_bus_b		= 16,
+	PCICFGA_bus_m		= 0x00ff0000,
+	PCICFGA_bus_type0_v	= 0,	//local bus
+	PCICFGA_en_b		= 31,		// read only
+	PCICFGA_en_m		= 0x80000000,
+} ;
+
+enum {
+	PCFGID_vendor_b 	= 0,
+	PCFGID_vendor_m 	= 0x0000ffff,
+	PCFGID_vendor_IDT_v		= 0x111d,
+	PCFGID_device_b 	= 16,
+	PCFGID_device_m 	= 0xffff0000,
+	PCFGID_device_Acaciade_v	= 0x0207,
+
+	PCFG04_command_ioena_b		= 1,
+	PCFG04_command_ioena_m		= 0x00000001,
+	PCFG04_command_memena_b 	= 2,
+	PCFG04_command_memena_m 	= 0x00000002,
+	PCFG04_command_bmena_b		= 3,
+	PCFG04_command_bmena_m		= 0x00000004,
+	PCFG04_command_mwinv_b		= 5,
+	PCFG04_command_mwinv_m		= 0x00000010,
+	PCFG04_command_parena_b 	= 7,
+	PCFG04_command_parena_m 	= 0x00000040,
+	PCFG04_command_serrena_b	= 9,
+	PCFG04_command_serrena_m	= 0x00000100,
+	PCFG04_command_fastbbena_b	= 10,
+	PCFG04_command_fastbbena_m	= 0x00000200,
+	PCFG04_status_b 		= 16,
+	PCFG04_status_m 		= 0xffff0000,
+	PCFG04_status_66MHz_b		= 21,	// 66 MHz enable
+	PCFG04_status_66MHz_m		= 0x00200000,
+	PCFG04_status_fbb_b		= 23,
+	PCFG04_status_fbb_m		= 0x00800000,
+	PCFG04_status_mdpe_b		= 24,
+	PCFG04_status_mdpe_m		= 0x01000000,
+	PCFG04_status_dst_b		= 25,
+	PCFG04_status_dst_m		= 0x06000000,
+	PCFG04_status_sta_b		= 27,
+	PCFG04_status_sta_m		= 0x08000000,
+	PCFG04_status_rta_b		= 28,
+	PCFG04_status_rta_m		= 0x10000000,
+	PCFG04_status_rma_b		= 29,
+	PCFG04_status_rma_m		= 0x20000000,
+	PCFG04_status_sse_b		= 30,
+	PCFG04_status_sse_m		= 0x40000000,
+	PCFG04_status_pe_b		= 31,
+	PCFG04_status_pe_m		= 0x40000000,
+
+	PCFG08_revId_b			= 0,
+	PCFG08_revId_m			= 0x000000ff,
+	PCFG08_classCode_b		= 0,
+	PCFG08_classCode_m		= 0xffffff00,
+	PCFG08_classCode_bridge_v	= 06,
+	PCFG08_classCode_proc_v 	= 0x0b3000, // processor-MIPS
+	PCFG0C_cacheline_b		= 0,
+	PCFG0C_cacheline_m		= 0x000000ff,
+	PCFG0C_masterLatency_b		= 8,
+	PCFG0C_masterLatency_m		= 0x0000ff00,
+	PCFG0C_headerType_b		= 16,
+	PCFG0C_headerType_m		= 0x00ff0000,
+	PCFG0C_bist_b			= 24,
+	PCFG0C_bist_m			= 0xff000000,
+
+	PCIPBA_msi_b			= 0,
+	PCIPBA_msi_m			= 0x00000001,
+	PCIPBA_p_b			= 3,
+	PCIPBA_p_m			= 0x00000004,
+	PCIPBA_baddr_b			= 8,
+	PCIPBA_baddr_m			= 0xffffff00,
+
+	PCFGSS_vendorId_b		= 0,
+	PCFGSS_vendorId_m		= 0x0000ffff,
+	PCFGSS_id_b			= 16,
+	PCFGSS_id_m			= 0xffff0000,
+
+	PCFG3C_interruptLine_b		= 0,
+	PCFG3C_interruptLine_m		= 0x000000ff,
+	PCFG3C_interruptPin_b		= 8,
+	PCFG3C_interruptPin_m		= 0x0000ff00,
+	PCFG3C_minGrant_b		= 16,
+	PCFG3C_minGrant_m		= 0x00ff0000,
+	PCFG3C_maxLat_b 		= 24,
+	PCFG3C_maxLat_m 		= 0xff000000,
+
+	PCIPBAC_msi_b			= 0,
+	PCIPBAC_msi_m			= 0x00000001,
+	PCIPBAC_p_b			= 1,
+	PCIPBAC_p_m			= 0x00000002,
+	PCIPBAC_size_b			= 2,
+	PCIPBAC_size_m			= 0x0000007c,
+	PCIPBAC_sb_b			= 7,
+	PCIPBAC_sb_m			= 0x00000080,
+	PCIPBAC_pp_b			= 8,
+	PCIPBAC_pp_m			= 0x00000100,
+	PCIPBAC_mr_b			= 9,
+	PCIPBAC_mr_m			= 0x00000600,
+	PCIPBAC_mr_read_v	=0,	//no prefetching
+	PCIPBAC_mr_readLine_v	=1,
+	PCIPBAC_mr_readMult_v	=2,
+	PCIPBAC_mrl_b			= 11,
+	PCIPBAC_mrl_m			= 0x00000800,
+	PCIPBAC_mrm_b			= 12,
+	PCIPBAC_mrm_m			= 0x00001000,
+	PCIPBAC_trp_b			= 13,
+	PCIPBAC_trp_m			= 0x00002000,
+
+	PCFG40_trdyTimeout_b		= 0,
+	PCFG40_trdyTimeout_m		= 0x000000ff,
+	PCFG40_retryLim_b		= 8,
+	PCFG40_retryLim_m		= 0x0000ff00,
+};
+
+/*******************************************************************************
+ *
+ * PCI Local Base Address [0|1|2|3] Register
+ *
+ ******************************************************************************/
+enum {
+	PCILBA_baddr_b		= 0,		// In PCI_t -> pcilba [] .a
+	PCILBA_baddr_m		= 0xffffff00,
+} ;
+/*******************************************************************************
+ *
+ * PCI Local Base Address Control Register
+ *
+ ******************************************************************************/
+enum {
+	PCILBAC_msi_b		= 0,		// In pPci->pcilba[i].c
+	PCILBAC_msi_m		= 0x00000001,
+	PCILBAC_msi_mem_v	= 0,
+	PCILBAC_msi_io_v	= 1,
+	PCILBAC_size_b		= 2,	// In pPci->pcilba[i].c
+	PCILBAC_size_m		= 0x0000007c,
+	PCILBAC_sb_b		= 7,	// In pPci->pcilba[i].c
+	PCILBAC_sb_m		= 0x00000080,
+	PCILBAC_rt_b		= 8,	// In pPci->pcilba[i].c
+	PCILBAC_rt_m		= 0x00000100,
+	PCILBAC_rt_noprefetch_v = 0, // mem read
+	PCILBAC_rt_prefetch_v	= 1, // mem readline
+} ;
+
+/*******************************************************************************
+ *
+ * PCI Local Base Address [0|1|2|3] Mapping Register
+ *
+ ******************************************************************************/
+enum {
+	PCILBAM_maddr_b 	= 8,
+	PCILBAM_maddr_m 	= 0xffffff00,
+} ;
+
+/*******************************************************************************
+ *
+ * PCI Decoupled Access Control Register
+ *
+ ******************************************************************************/
+enum {
+	PCIDAC_den_b		= 0,
+	PCIDAC_den_m		= 0x00000001,
+} ;
+
+/*******************************************************************************
+ *
+ * PCI Decoupled Access Status Register
+ *
+ ******************************************************************************/
+enum {
+	PCIDAS_d_b	= 0,
+	PCIDAS_d_m	= 0x00000001,
+	PCIDAS_b_b	= 1,
+	PCIDAS_b_m	= 0x00000002,
+	PCIDAS_e_b	= 2,
+	PCIDAS_e_m	= 0x00000004,
+	PCIDAS_ofe_b	= 3,
+	PCIDAS_ofe_m	= 0x00000008,
+	PCIDAS_off_b	= 4,
+	PCIDAS_off_m	= 0x00000010,
+	PCIDAS_ife_b	= 5,
+	PCIDAS_ife_m	= 0x00000020,
+	PCIDAS_iff_b	= 6,
+	PCIDAS_iff_m	= 0x00000040,
+} ;
+
+/*******************************************************************************
+ *
+ * PCI DMA Channel 8 Configuration Register
+ *
+ ******************************************************************************/
+enum
+{
+	PCIDMA8C_mbs_b	= 0,		// Maximum Burst Size.
+	PCIDMA8C_mbs_m	= 0x00000fff,	// { pcidma8c }
+	PCIDMA8C_our_b	= 12,		// Optimize Unaligned Burst Reads.
+	PCIDMA8C_our_m	= 0x00001000,	// { pcidma8c }
+} ;
+
+/*******************************************************************************
+ *
+ * PCI DMA Channel 9 Configuration Register
+ *
+ ******************************************************************************/
+enum
+{
+	PCIDMA9C_mbs_b	= 0,		// Maximum Burst Size.
+	PCIDMA9C_mbs_m	= 0x00000fff, // { pcidma9c }
+} ;
+
+/*******************************************************************************
+ *
+ * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
+ *
+ ******************************************************************************/
+enum {
+	PCIDMAD_pt_b		= 22,		// in DEVCMD field (descriptor)
+	PCIDMAD_pt_m		= 0x00c00000,	// preferred transaction field
+	// These are for reads (DMA channel 8)
+	PCIDMAD_devcmd_mr_v	= 0,	//memory read
+	PCIDMAD_devcmd_mrl_v	= 1,	//memory read line
+	PCIDMAD_devcmd_mrm_v	= 2,	//memory read multiple
+	PCIDMAD_devcmd_ior_v	= 3,	//I/O read
+	// These are for writes (DMA channel 9)
+	PCIDMAD_devcmd_mw_v	= 0,	//memory write
+	PCIDMAD_devcmd_mwi_v	= 1,	//memory write invalidate
+	PCIDMAD_devcmd_iow_v	= 3,	//I/O write
+	
+	// Swap byte field applies to both DMA channel 8 and 9
+	PCIDMAD_sb_b		= 24,		// in DEVCMD field (descriptor)
+	PCIDMAD_sb_m		= 0x01000000,	// swap byte field
+} ;
+
+
+/*******************************************************************************
+ *
+ * PCI Target Control Register
+ *
+ ******************************************************************************/
+enum
+{
+	PCITC_rtimer_b		= 0,		// In PCITC_t -> pcitc
+	PCITC_rtimer_m		= 0x000000ff,
+	PCITC_dtimer_b		= 8,		// In PCITC_t -> pcitc
+	PCITC_dtimer_m		= 0x0000ff00,
+	PCITC_rdr_b		= 18,		// In PCITC_t -> pcitc
+	PCITC_rdr_m		= 0x00040000,
+	PCITC_ddt_b		= 19,		// In PCITC_t -> pcitc
+	PCITC_ddt_m		= 0x00080000,
+} ;
+/*******************************************************************************
+ *
+ * PCI messaging unit [applies to both inbound and outbound registers ]
+ *
+ ******************************************************************************/
+enum
+{
+	PCIM_m0_b	= 0,		// In PCIM_t -> {pci{iic,iim,ioic,ioim}}
+	PCIM_m0_m	= 0x00000001,	// inbound or outbound message 0
+	PCIM_m1_b	= 1,		// In PCIM_t -> {pci{iic,iim,ioic,ioim}}
+	PCIM_m1_m	= 0x00000002,	// inbound or outbound message 1
+	PCIM_db_b	= 2,		// In PCIM_t -> {pci{iic,iim,ioic,ioim}}
+	PCIM_db_m	= 0x00000004,	// inbound or outbound doorbell
+};
+
+
+#endif	// __IDT_RC32365_PCI_H__
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h idtlinux/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,210 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   PCI header values for IDT 79EB365/336                                                   
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_RC32365_PCI_V_H__
+#define __IDT_RC32365_PCI_V_H__
+
+
+#define PCI_MSG_VirtualAddress	0xB806C010
+#define rc32365_pci ((volatile PCI_t) PCI0_VirtualAddress)
+#define rc32365_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
+
+#define PCIM_SHFT		0x6
+#define PCIM_BIT_LEN		0x7
+#define PCIM_H_EA		0x3
+#define PCIM_H_IA_FIX		0x4
+#define PCIM_H_IA_RR		0x5
+
+#define PCI_ADDR_START		0x50000000
+
+#define CPUTOPCI_MEM_WIN	0x02000000
+#define CPUTOPCI_IO_WIN		0x00100000
+#define PCILBA_SIZE_SHFT	2
+#define PCILBA_SIZE_MASK	0x1F
+#define SIZE_256MB		0x1C
+#define SIZE_128MB		0x1B
+#define SIZE_64MB               0x1A
+#define SIZE_32MB		0x19
+#define SIZE_16MB               0x18
+#define SIZE_4MB		0x16
+#define SIZE_2MB		0x15
+#define SIZE_1MB		0x14
+#define CEDAR_CONFIG0_ADDR	0x80000000
+#define CEDAR_CONFIG1_ADDR	0x80000004
+#define CEDAR_CONFIG2_ADDR	0x80000008
+#define CEDAR_CONFIG3_ADDR	0x8000000C
+#define CEDAR_CONFIG4_ADDR	0x80000010
+#define CEDAR_CONFIG5_ADDR	0x80000014
+#define CEDAR_CONFIG6_ADDR	0x80000018
+#define CEDAR_CONFIG7_ADDR	0x8000001C
+#define CEDAR_CONFIG8_ADDR	0x80000020
+#define CEDAR_CONFIG9_ADDR	0x80000024
+#define CEDAR_CONFIG10_ADDR	0x80000028
+#define CEDAR_CONFIG11_ADDR	0x8000002C
+#define CEDAR_CONFIG12_ADDR	0x80000030
+#define CEDAR_CONFIG13_ADDR	0x80000034
+#define CEDAR_CONFIG14_ADDR	0x80000038
+#define CEDAR_CONFIG15_ADDR	0x8000003C
+#define CEDAR_CONFIG16_ADDR	0x80000040
+#define CEDAR_CONFIG17_ADDR	0x80000044
+#define CEDAR_CONFIG18_ADDR	0x80000048
+#define CEDAR_CONFIG19_ADDR	0x8000004C
+#define CEDAR_CONFIG20_ADDR	0x80000050
+#define CEDAR_CONFIG21_ADDR	0x80000054
+#define CEDAR_CONFIG22_ADDR	0x80000058
+#define CEDAR_CONFIG23_ADDR	0x8000005C
+#define CEDAR_CONFIG24_ADDR	0x80000060
+#define CEDAR_CONFIG25_ADDR	0x80000064
+#define CEDAR_CMD 	       (PCFG04_command_ioena_m  | \
+				PCFG04_command_memena_m | \
+				PCFG04_command_bmena_m  | \
+				PCFG04_command_mwinv_m  | \
+				PCFG04_command_parena_m | \
+				PCFG04_command_serrena_m )
+
+#define CEDAR_STAT	       (PCFG04_status_mdpe_m | \
+				PCFG04_status_sta_m  | \
+				PCFG04_status_rta_m  | \
+				PCFG04_status_rma_m  | \
+				PCFG04_status_sse_m  | \
+				PCFG04_status_pe_m)
+
+#define CEDAR_CNFG1	      ((CEDAR_STAT << 16) | \
+                                CEDAR_CMD)
+
+#define CEDAR_REVID		0
+#define CEDAR_CLASS_CODE	0
+#define CEDAR_CNFG2	      ((CEDAR_CLASS_CODE << 8) | \
+				CEDAR_REVID)
+
+#define CEDAR_CACHE_LINE_SIZE	4
+#define CEDAR_MASTER_LAT	0x3c
+#define CEDAR_HEADER_TYPE	0
+#define CEDAR_BIST		0
+
+#define CEDAR_CNFG3           ((CEDAR_BIST        << 24) | \
+		               (CEDAR_HEADER_TYPE << 16) | \
+		               (CEDAR_MASTER_LAT  <<  8) | \
+		                CEDAR_CACHE_LINE_SIZE)
+
+#define CEDAR_BAR0	        0x00000008 /* 128 MB Memory */
+#define CEDAR_BAR1	        0x18800001 /* 1 MB IO */
+#define CEDAR_BAR2	        0x18000001 /* 2 MB IO window for Cedar
+				              internal Registers */
+#define CEDAR_BAR3	        0x48000008 /* Spare 128 MB Memory */
+
+#define CEDAR_CNFG4	        CEDAR_BAR0
+#define CEDAR_CNFG5             CEDAR_BAR1
+#define CEDAR_CNFG6 	        CEDAR_BAR2
+#define CEDAR_CNFG7	        CEDAR_BAR3
+
+#define CEDAR_SUBSYS_VENDOR_ID  0
+#define CEDAR_SUBSYSTEM_ID	0
+#define CEDAR_CNFG8		0
+#define CEDAR_CNFG9		0
+#define CEDAR_CNFG10		0
+#define CEDAR_CNFG11 	      ((CEDAR_SUBSYS_VENDOR_ID << 16) | \
+			        CEDAR_SUBSYSTEM_ID)
+#define CEDAR_INT_LINE		1
+#define CEDAR_INT_PIN		1
+#define CEDAR_MIN_GNT		8
+#define CEDAR_MAX_LAT		0x38
+#define CEDAR_CNFG12		0
+#define CEDAR_CNFG13 		0
+#define CEDAR_CNFG14		0
+#define CEDAR_CNFG15	      ((CEDAR_MAX_LAT << 24) | \
+			       (CEDAR_MIN_GNT << 16) | \
+			       (CEDAR_INT_PIN <<  8) | \
+			        CEDAR_INT_LINE)
+#define	CEDAR_RETRY_LIMIT	0x80
+#define CEDAR_TRDY_LIMIT	0x80
+#define CEDAR_CNFG16          ((CEDAR_RETRY_LIMIT << 8) | \
+			        CEDAR_TRDY_LIMIT)
+#define PCI_PBAxC_R		0x0
+#define PCI_PBAxC_RL		0x1
+#define PCI_PBAxC_RM		0x2
+#define SIZE_SHFT		2
+#ifdef __MIPSEB__
+#define CEDAR_PBA0C	       (((1 & 0x3) << PCIPBAC_mr_b) | \
+			        PCIPBAC_pp_m | \
+				PCIPBAC_sb_m | \
+			       (SIZE_128MB << SIZE_SHFT) | \
+			        PCIPBAC_p_m)
+#else
+
+#define CEDAR_PBA0C	       (((1 & 0x3) << PCIPBAC_mr_b) | \
+			        PCIPBAC_pp_m | \
+			       (SIZE_128MB << SIZE_SHFT) | \
+			        PCIPBAC_p_m)
+#endif
+#define CEDAR_CNFG17	        CEDAR_PBA0C
+#define CEDAR_PBA0M	        0x0
+#define CEDAR_CNFG18	        CEDAR_PBA0M
+
+#ifdef __MIPSEB__
+#define CEDAR_PBA1C	      ((SIZE_1MB << SIZE_SHFT) | \
+				PCIPBAC_sb_m | \
+			        PCIPBAC_msi_m)
+#else
+#define CEDAR_PBA1C	      ((SIZE_1MB << SIZE_SHFT) | \
+			        PCIPBAC_msi_m)
+#endif
+#define CEDAR_CNFG19	        CEDAR_PBA1C
+#define CEDAR_PBA1M	        0x0
+#define CEDAR_CNFG20	        CEDAR_PBA1M
+
+#ifdef __MIPSEB__
+#define CEDAR_PBA2C	      ((SIZE_2MB << SIZE_SHFT) |  \
+				PCIPBAC_sb_m | \
+			        PCIPBAC_msi_m)
+#else
+#define CEDAR_PBA2C	      ((SIZE_2MB << SIZE_SHFT) |  \
+			        PCIPBAC_msi_m)
+#endif
+
+#define CEDAR_CNFG21	        CEDAR_PBA2C
+#define CEDAR_PBA2M	        0x18000000
+#define CEDAR_CNFG22	        CEDAR_PBA2M
+
+#ifdef __MIPSEB__
+#define CEDAR_PBA3C	        PCIPBAC_sb_m
+#else
+#define CEDAR_PBA3C	        0 
+#endif
+
+#define CEDAR_CNFG23	        CEDAR_PBA3C
+#define CEDAR_PBA3M	        0
+#define CEDAR_CNFG24	        CEDAR_PBA3M
+
+#define	PCITC_DTIMER_VAL	8
+#define PCITC_RTIMER_VAL	0x10
+
+#endif //__IDT_RC32365_PCI_V_H__
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_dma.h idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_dma.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_dma.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_dma.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,198 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   DMA register definition
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_DMA_H__
+#define __IDT_DMA_H__
+
+enum
+{
+	DMA0_PhysicalAddress	= 0x18040000,
+	DMA_PhysicalAddress	= DMA0_PhysicalAddress,		// Default
+
+	DMA0_VirtualAddress	= 0xb8040000,
+	DMA_VirtualAddress	= DMA0_VirtualAddress,		// Default
+} ;
+
+/*
+ * DMA descriptor (in physical memory).
+ */
+
+typedef struct DMAD_s
+{
+	u32			control ;	// Control. use DMAD_*
+	u32			ca ;		// Current Address.
+	u32			devcs ; 	// Device control and status.
+	u32			link ;		// Next descriptor in chain.
+} volatile *DMAD_t ;
+
+enum
+{
+	DMAD_size		= sizeof (struct DMAD_s),
+	DMAD_count_b		= 0,		// in DMAD_t -> control
+	DMAD_count_m		= 0x0003ffff,	// in DMAD_t -> control
+	DMAD_ds_b		= 20,		// in DMAD_t -> control
+	DMAD_ds_m		= 0x00300000,	// in DMAD_t -> control
+		DMAD_ds_ethRcv0_v	= 0,
+		DMAD_ds_ethXmt0_v	= 0,
+		DMAD_ds_memToFifo_v	= 0,
+		DMAD_ds_fifoToMem_v	= 0,
+		DMAD_ds_pciToMem_v	= 0,
+		DMAD_ds_memToPci_v	= 0,
+	
+	DMAD_devcmd_b		= 22,		// in DMAD_t -> control
+	DMAD_devcmd_m		= 0x01c00000,	// in DMAD_t -> control
+		DMAD_devcmd_byte_v	= 0,	//memory-to-memory
+		DMAD_devcmd_halfword_v	= 1,	//memory-to-memory
+		DMAD_devcmd_word_v	= 2,	//memory-to-memory
+		DMAD_devcmd_2words_v	= 3,	//memory-to-memory
+		DMAD_devcmd_4words_v	= 4,	//memory-to-memory
+		DMAD_devcmd_6words_v	= 5,	//memory-to-memory
+		DMAD_devcmd_8words_v	= 6,	//memory-to-memory
+		DMAD_devcmd_16words_v	= 7,	//memory-to-memory
+	DMAD_cof_b		= 25,		// chain on finished
+	DMAD_cof_m		= 0x02000000,	// 
+	DMAD_cod_b		= 26,		// chain on done
+	DMAD_cod_m		= 0x04000000,	// 
+	DMAD_iof_b		= 27,		// interrupt on finished
+	DMAD_iof_m		= 0x08000000,	// 
+	DMAD_iod_b		= 28,		// interrupt on done
+	DMAD_iod_m		= 0x10000000,	// 
+	DMAD_t_b		= 29,		// terminated
+	DMAD_t_m		= 0x20000000,	// 
+	DMAD_d_b		= 30,		// done
+	DMAD_d_m		= 0x40000000,	// 
+	DMAD_f_b		= 31,		// finished
+	DMAD_f_m		= 0x80000000,	// 
+} ;
+
+/*
+ * DMA register (within Internal Register Map).
+ */
+
+struct DMA_Chan_s
+{
+	u32		dmac ;		// Control.
+	u32		dmas ;		// Status.	
+	u32		dmasm ; 	// Mask.
+	u32		dmadptr ;	// Descriptor pointer.
+	u32		dmandptr ;	// Next descriptor pointer.
+};
+
+typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
+
+//DMA_Channels	  use DMACH_count instead
+
+enum
+{
+	DMAC_run_b	= 0,		// 
+	DMAC_run_m	= 0x00000001,	// 
+	DMAC_dm_b	= 1,		// done mask
+	DMAC_dm_m	= 0x00000002,	// 
+	DMAC_mode_b	= 2,		// 
+	DMAC_mode_m	= 0x0000000c,	// 
+		DMAC_mode_auto_v	= 0,
+		DMAC_mode_burst_v	= 1,
+		DMAC_mode_transfer_v	= 2, //usually used
+		DMAC_mode_reserved_v	= 3,
+	DMAC_a_b	= 4,		// 
+	DMAC_a_m	= 0x00000010,	// 
+
+	DMAS_f_b	= 0,		// finished (sticky) 
+	DMAS_f_m	= 0x00000001,	//		     
+	DMAS_d_b	= 1,		// done (sticky)     
+	DMAS_d_m	= 0x00000002,	//		     
+	DMAS_c_b	= 2,		// chain (sticky)    
+	DMAS_c_m	= 0x00000004,	//		     
+	DMAS_e_b	= 3,		// error (sticky)    
+	DMAS_e_m	= 0x00000008,	//		     
+	DMAS_h_b	= 4,		// halt (sticky)     
+	DMAS_h_m	= 0x00000010,	//		     
+
+	DMASM_f_b	= 0,		// finished (1=mask)
+	DMASM_f_m	= 0x00000001,	// 
+	DMASM_d_b	= 1,		// done (1=mask)
+	DMASM_d_m	= 0x00000002,	// 
+	DMASM_c_b	= 2,		// chain (1=mask)
+	DMASM_c_m	= 0x00000004,	// 
+	DMASM_e_b	= 3,		// error (1=mask)
+	DMASM_e_m	= 0x00000008,	// 
+	DMASM_h_b	= 4,		// halt (1=mask)
+	DMASM_h_m	= 0x00000010,	// 
+} ;
+
+/*
+ * DMA channel definitions
+ */
+
+enum
+{
+	DMACH_ethRcv0 = 0,
+	DMACH_ethXmt0 = 1,
+	DMACH_memToFifo = 2,
+	DMACH_fifoToMem = 3,
+	DMACH_pciToMem = 4,
+	DMACH_memToPci = 5,
+
+	DMACH_count //must be last
+};
+
+
+typedef struct DMAC_s
+{
+	struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
+} volatile *DMA_t ;
+
+
+/*
+ * External DMA parameters
+*/
+
+enum
+{
+	DMADEVCMD_ts_b	= 0,		// ts field in devcmd
+	DMADEVCMD_ts_m	= 0x00000007,	// ts field in devcmd
+		DMADEVCMD_ts_byte_v	= 0,
+		DMADEVCMD_ts_halfword_v	= 1,
+		DMADEVCMD_ts_word_v	= 2,
+		DMADEVCMD_ts_2word_v	= 3,
+		DMADEVCMD_ts_4word_v	= 4,
+		DMADEVCMD_ts_6word_v	= 5,
+		DMADEVCMD_ts_8word_v	= 6,
+		DMADEVCMD_ts_16word_v	= 7
+};
+
+
+#endif	// __IDT_DMA_H__
+
+
+
+
+
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,81 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Definitions for DMA controller.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_DMA_V_H__
+#define __IDT_DMA_V_H__
+
+#include  <asm/idt-boards/rc32434/rc32434_dma.h> 
+#include  <asm/idt-boards/rc32434/rc32434.h>
+
+#define DMA_CHAN_OFFSET  0x14
+#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
+#define DMA_COUNT(count)   \
+  ((count) & DMAD_count_m)
+
+#define DMA_HALT_TIMEOUT 500
+
+
+static inline int rc32434_halt_dma(DMA_Chan_t ch)
+{
+	int timeout=1;
+	if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
+		rc32434_writel(0, &ch->dmac); 
+		
+		for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
+			if (rc32434_readl(&ch->dmas) & DMAS_h_m) {
+				rc32434_writel(0, &ch->dmas);  
+				break;
+			}
+		}
+
+	}
+	
+	return timeout ? 0 : 1;
+}
+
+static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
+{
+	rc32434_writel(0, &ch->dmandptr); 
+	rc32434_writel(dma_addr, &ch->dmadptr);
+}
+
+static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
+{
+	rc32434_writel(dma_addr, &ch->dmandptr);
+}
+
+#endif	// __IDT_DMA_V_H__
+
+
+
+
+
+
+
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_eth.h idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_eth.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_eth.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_eth.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,326 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Ethernet register definition
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef	__IDT_ETH_H__
+#define	__IDT_ETH_H__
+
+
+enum
+{
+	ETH0_PhysicalAddress	= 0x18060000,
+	ETH_PhysicalAddress	= ETH0_PhysicalAddress,		// Default
+
+	ETH0_VirtualAddress	= 0xb8060000,
+	ETH_VirtualAddress	= ETH0_VirtualAddress,		// Default
+} ;
+
+typedef struct
+{
+	u32 ethintfc		;
+	u32 ethfifott		;
+	u32 etharc		;
+	u32 ethhash0		;
+	u32 ethhash1		;
+	u32 ethu0 [4]		;	// Reserved.	
+	u32 ethpfs		;
+	u32 ethmcp		;
+	u32 eth_u1 [10]		;	// Reserved.
+	u32 ethspare		;
+	u32 eth_u2 [42]		;	// Reserved. 
+	u32 ethsal0		;
+	u32 ethsah0		;
+	u32 ethsal1		;
+	u32 ethsah1		;
+	u32 ethsal2		;
+	u32 ethsah2		;
+	u32 ethsal3		;
+	u32 ethsah3		;
+	u32 ethrbc		;
+	u32 ethrpc		;
+	u32 ethrupc		;
+	u32 ethrfc		;
+	u32 ethtbc		;
+	u32 ethgpf		;
+	u32 eth_u9 [50]		;	// Reserved.	
+	u32 ethmac1		;
+	u32 ethmac2		;
+	u32 ethipgt		;
+	u32 ethipgr		;
+	u32 ethclrt		;
+	u32 ethmaxf		;
+	u32 eth_u10		;	// Reserved.	
+	u32 ethmtest		;
+	u32 miimcfg		;
+	u32 miimcmd		;
+	u32 miimaddr		;
+	u32 miimwtd		;
+	u32 miimrdd		;
+	u32 miimind		;
+	u32 eth_u11		;	// Reserved.
+	u32 eth_u12		;	// Reserved.
+	u32 ethcfsa0		;
+	u32 ethcfsa1		;
+	u32 ethcfsa2		;
+} volatile *ETH_t;
+
+enum
+{
+	ETHINTFC_en_b		= 0,
+	ETHINTFC_en_m		= 0x00000001,
+	ETHINTFC_its_b		= 1,
+	ETHINTFC_its_m		= 0x00000002,
+	ETHINTFC_rip_b		= 2,
+	ETHINTFC_rip_m		= 0x00000004,
+	ETHINTFC_jam_b		= 3,
+	ETHINTFC_jam_m		= 0x00000008,
+	ETHINTFC_ovr_b		= 4,
+	ETHINTFC_ovr_m		= 0x00000010,
+	ETHINTFC_und_b		= 5,
+	ETHINTFC_und_m		= 0x00000020,
+
+	ETHFIFOTT_tth_b		= 0,
+	ETHFIFOTT_tth_m		= 0x0000007f,
+
+	ETHARC_pro_b		= 0,
+	ETHARC_pro_m		= 0x00000001,
+	ETHARC_am_b		= 1,
+	ETHARC_am_m		= 0x00000002,
+	ETHARC_afm_b		= 2,
+	ETHARC_afm_m		= 0x00000004,
+	ETHARC_ab_b		= 3,
+	ETHARC_ab_m		= 0x00000008,
+
+	ETHSAL_byte5_b		= 0,
+	ETHSAL_byte5_m		= 0x000000ff,
+	ETHSAL_byte4_b		= 8,
+	ETHSAL_byte4_m		= 0x0000ff00,
+	ETHSAL_byte3_b		= 16,
+	ETHSAL_byte3_m		= 0x00ff0000,
+	ETHSAL_byte2_b		= 24,
+	ETHSAL_byte2_m		= 0xff000000,
+
+	ETHSAH_byte1_b		= 0,
+	ETHSAH_byte1_m		= 0x000000ff,
+	ETHSAH_byte0_b		= 8,
+	ETHSAH_byte0_m		= 0x0000ff00,
+	
+	ETHGPF_ptv_b		= 0,
+	ETHGPF_ptv_m		= 0x0000ffff,
+
+	ETHPFS_pfd_b		= 0,
+	ETHPFS_pfd_m		= 0x00000001,
+
+	ETHCFSA0_cfsa4_b	= 0,
+	ETHCFSA0_cfsa4_m	= 0x000000ff,
+	ETHCFSA0_cfsa5_b	= 8,
+	ETHCFSA0_cfsa5_m	= 0x0000ff00,
+
+	ETHCFSA1_cfsa2_b	= 0,
+	ETHCFSA1_cfsa2_m	= 0x000000ff,
+	ETHCFSA1_cfsa3_b	= 8,
+	ETHCFSA1_cfsa3_m	= 0x0000ff00,
+
+	ETHCFSA2_cfsa0_b	= 0,
+	ETHCFSA2_cfsa0_m	= 0x000000ff,
+	ETHCFSA2_cfsa1_b	= 8,
+	ETHCFSA2_cfsa1_m	= 0x0000ff00,
+
+	ETHMAC1_re_b		= 0,
+	ETHMAC1_re_m		= 0x00000001,
+	ETHMAC1_paf_b		= 1,
+	ETHMAC1_paf_m		= 0x00000002,
+	ETHMAC1_rfc_b		= 2,
+	ETHMAC1_rfc_m		= 0x00000004,
+	ETHMAC1_tfc_b		= 3,
+	ETHMAC1_tfc_m		= 0x00000008,
+	ETHMAC1_lb_b		= 4,
+	ETHMAC1_lb_m		= 0x00000010,
+	ETHMAC1_mr_b		= 31,
+	ETHMAC1_mr_m		= 0x80000000,
+
+	ETHMAC2_fd_b		= 0,
+	ETHMAC2_fd_m		= 0x00000001,
+	ETHMAC2_flc_b		= 1,
+	ETHMAC2_flc_m		= 0x00000002,
+	ETHMAC2_hfe_b		= 2,
+	ETHMAC2_hfe_m		= 0x00000004,
+	ETHMAC2_dc_b		= 3,
+	ETHMAC2_dc_m		= 0x00000008,
+	ETHMAC2_cen_b		= 4,
+	ETHMAC2_cen_m		= 0x00000010,
+	ETHMAC2_pe_b		= 5,
+	ETHMAC2_pe_m		= 0x00000020,
+	ETHMAC2_vpe_b		= 6,
+	ETHMAC2_vpe_m		= 0x00000040,
+	ETHMAC2_ape_b		= 7,
+	ETHMAC2_ape_m		= 0x00000080,
+	ETHMAC2_ppe_b		= 8,
+	ETHMAC2_ppe_m		= 0x00000100,
+	ETHMAC2_lpe_b		= 9,
+	ETHMAC2_lpe_m		= 0x00000200,
+	ETHMAC2_nb_b		= 12,
+	ETHMAC2_nb_m		= 0x00001000,
+	ETHMAC2_bp_b		= 13,
+	ETHMAC2_bp_m		= 0x00002000,
+	ETHMAC2_ed_b		= 14,
+	ETHMAC2_ed_m		= 0x00004000,
+
+	ETHIPGT_ipgt_b		= 0,
+	ETHIPGT_ipgt_m		= 0x0000007f,
+
+	ETHIPGR_ipgr2_b		= 0,
+	ETHIPGR_ipgr2_m		= 0x0000007f,
+	ETHIPGR_ipgr1_b		= 8,
+	ETHIPGR_ipgr1_m		= 0x00007f00,
+
+	ETHCLRT_maxret_b	= 0,
+	ETHCLRT_maxret_m	= 0x0000000f,
+	ETHCLRT_colwin_b	= 8,
+	ETHCLRT_colwin_m	= 0x00003f00,
+
+	ETHMAXF_maxf_b		= 0,
+	ETHMAXF_maxf_m		= 0x0000ffff,
+
+	ETHMTEST_tb_b		= 2,
+	ETHMTEST_tb_m		= 0x00000004,
+
+	ETHMCP_div_b		= 0,
+	ETHMCP_div_m		= 0x000000ff,
+	
+	MIIMCFG_rsv_b		= 0,
+	MIIMCFG_rsv_m		= 0x0000000c,
+
+	MIIMCMD_rd_b		= 0,
+	MIIMCMD_rd_m		= 0x00000001,
+	MIIMCMD_scn_b		= 1,
+	MIIMCMD_scn_m		= 0x00000002,
+
+	MIIMADDR_regaddr_b	= 0,
+	MIIMADDR_regaddr_m	= 0x0000001f,
+	MIIMADDR_phyaddr_b	= 8,
+	MIIMADDR_phyaddr_m	= 0x00001f00,
+
+	MIIMWTD_wdata_b		= 0,
+	MIIMWTD_wdata_m		= 0x0000ffff,
+
+	MIIMRDD_rdata_b		= 0,
+	MIIMRDD_rdata_m		= 0x0000ffff,
+
+	MIIMIND_bsy_b		= 0,
+	MIIMIND_bsy_m		= 0x00000001,
+	MIIMIND_scn_b		= 1,
+	MIIMIND_scn_m		= 0x00000002,
+	MIIMIND_nv_b		= 2,
+	MIIMIND_nv_m		= 0x00000004,
+
+} ;
+
+/*
+ * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
+ */
+enum
+{
+	ETHRX_fd_b		= 0,
+	ETHRX_fd_m		= 0x00000001,
+	ETHRX_ld_b		= 1,
+	ETHRX_ld_m		= 0x00000002,
+	ETHRX_rok_b		= 2,
+	ETHRX_rok_m		= 0x00000004,
+	ETHRX_fm_b		= 3,
+	ETHRX_fm_m		= 0x00000008,
+	ETHRX_mp_b		= 4,
+	ETHRX_mp_m		= 0x00000010,
+	ETHRX_bp_b		= 5,
+	ETHRX_bp_m		= 0x00000020,
+	ETHRX_vlt_b		= 6,
+	ETHRX_vlt_m		= 0x00000040,
+	ETHRX_cf_b		= 7,
+	ETHRX_cf_m		= 0x00000080,
+	ETHRX_ovr_b		= 8,
+	ETHRX_ovr_m		= 0x00000100,
+	ETHRX_crc_b		= 9,
+	ETHRX_crc_m		= 0x00000200,
+	ETHRX_cv_b		= 10,
+	ETHRX_cv_m		= 0x00000400,
+	ETHRX_db_b		= 11,
+	ETHRX_db_m		= 0x00000800,
+	ETHRX_le_b		= 12,
+	ETHRX_le_m		= 0x00001000,
+	ETHRX_lor_b		= 13,
+	ETHRX_lor_m		= 0x00002000,
+	ETHRX_ces_b		= 14,
+	ETHRX_ces_m		= 0x00004000,
+	ETHRX_length_b		= 16,
+	ETHRX_length_m		= 0xffff0000,
+
+	ETHTX_fd_b		= 0,
+	ETHTX_fd_m		= 0x00000001,
+	ETHTX_ld_b		= 1,
+	ETHTX_ld_m		= 0x00000002,
+	ETHTX_oen_b		= 2,
+	ETHTX_oen_m		= 0x00000004,
+	ETHTX_pen_b		= 3,
+	ETHTX_pen_m		= 0x00000008,
+	ETHTX_cen_b		= 4,
+	ETHTX_cen_m		= 0x00000010,
+	ETHTX_hen_b		= 5,
+	ETHTX_hen_m		= 0x00000020,
+	ETHTX_tok_b		= 6,
+	ETHTX_tok_m		= 0x00000040,
+	ETHTX_mp_b		= 7,
+	ETHTX_mp_m		= 0x00000080,
+	ETHTX_bp_b		= 8,
+	ETHTX_bp_m		= 0x00000100,
+	ETHTX_und_b		= 9,
+	ETHTX_und_m		= 0x00000200,
+	ETHTX_of_b		= 10,
+	ETHTX_of_m		= 0x00000400,
+	ETHTX_ed_b		= 11,
+	ETHTX_ed_m		= 0x00000800,
+	ETHTX_ec_b		= 12,
+	ETHTX_ec_m		= 0x00001000,
+	ETHTX_lc_b		= 13,
+	ETHTX_lc_m		= 0x00002000,
+	ETHTX_td_b		= 14,
+	ETHTX_td_m		= 0x00004000,
+	ETHTX_crc_b		= 15,
+	ETHTX_crc_m		= 0x00008000,
+	ETHTX_le_b		= 16,
+	ETHTX_le_m		= 0x00010000,
+	ETHTX_cc_b		= 17,
+	ETHTX_cc_m		= 0x001E0000,
+} ;
+
+#endif	// __IDT_ETH_H__
+
+
+
+
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,70 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Ethernet register definition
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef	__IDT_ETH_V_H__
+#define	__IDT_ETH_V_H__
+
+#include  <asm/idt-boards/rc32434/rc32434_eth.h> 
+
+#define IS_TX_TOK(X)         (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b )   /* Transmit Okay    */
+#define IS_TX_MP(X)          (((X) & (1<<ETHTX_mp_b))  >> ETHTX_mp_b )    /* Multicast        */
+#define IS_TX_BP(X)          (((X) & (1<<ETHTX_bp_b))  >> ETHTX_bp_b )    /* Broadcast        */
+#define IS_TX_UND_ERR(X)     (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b )   /* Transmit FIFO Underflow */
+#define IS_TX_OF_ERR(X)      (((X) & (1<<ETHTX_of_b))  >> ETHTX_of_b )    /* Oversized frame  */
+#define IS_TX_ED_ERR(X)      (((X) & (1<<ETHTX_ed_b))  >> ETHTX_ed_b )    /* Excessive deferral  */
+#define IS_TX_EC_ERR(X)      (((X) & (1<<ETHTX_ec_b))  >> ETHTX_ec_b)     /* Excessive collisions  */
+#define IS_TX_LC_ERR(X)      (((X) & (1<<ETHTX_lc_b))  >> ETHTX_lc_b )    /* Late Collision   */
+#define IS_TX_TD_ERR(X)      (((X) & (1<<ETHTX_td_b))  >> ETHTX_td_b )    /* Transmit deferred*/
+#define IS_TX_CRC_ERR(X)     (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b )   /* CRC Error        */
+#define IS_TX_LE_ERR(X)      (((X) & (1<<ETHTX_le_b))  >>  ETHTX_le_b )    /* Length Error     */
+
+#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b)  /* Collision Count  */
+
+#define IS_RCV_ROK(X)        (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b)    /* Receive Okay     */
+#define IS_RCV_FM(X)         (((X) & (1<<ETHRX_fm_b))  >> ETHRX_fm_b)     /* Is Filter Match  */
+#define IS_RCV_MP(X)         (((X) & (1<<ETHRX_mp_b))  >> ETHRX_mp_b)     /* Is it MP         */
+#define IS_RCV_BP(X)         (((X) & (1<<ETHRX_bp_b))  >> ETHRX_bp_b)     /* Is it BP         */
+#define IS_RCV_VLT(X)        (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b)    /* VLAN Tag Detect  */
+#define IS_RCV_CF(X)         (((X) & (1<<ETHRX_cf_b))  >> ETHRX_cf_b)     /* Control Frame    */
+#define IS_RCV_OVR_ERR(X)    (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b)    /* Receive Overflow */
+#define IS_RCV_CRC_ERR(X)    (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b)    /* CRC Error        */
+#define IS_RCV_CV_ERR(X)     (((X) & (1<<ETHRX_cv_b))  >> ETHRX_cv_b)     /* Code Violation   */
+#define IS_RCV_DB_ERR(X)     (((X) & (1<<ETHRX_db_b))  >> ETHRX_db_b)     /* Dribble Bits     */
+#define IS_RCV_LE_ERR(X)     (((X) & (1<<ETHRX_le_b))  >> ETHRX_le_b)     /* Length error     */
+#define IS_RCV_LOR_ERR(X)    (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b)    /* Length Out of Range */
+#define IS_RCV_CES_ERR(X)    (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b)  /* Preamble error   */
+#define RCVPKT_LENGTH(X)     (((X) & ETHRX_length_m) >> ETHRX_length_b)   /* Length of the received packet */
+#endif	// __IDT_ETH_V_H__
+
+
+
+
+
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,160 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   GPIO register definition
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_GPIO_H__
+#define __IDT_GPIO_H__
+
+enum
+{
+	GPIO0_PhysicalAddress	= 0x18050000,
+	GPIO_PhysicalAddress	= GPIO0_PhysicalAddress,	// Default
+
+	GPIO0_VirtualAddress	= 0xb8050000,
+	GPIO_VirtualAddress	= GPIO0_VirtualAddress,		// Default
+} ;
+
+typedef struct
+{
+	u32   gpiofunc;   /* GPIO Function Register
+			   * gpiofunc[x]==0 bit = gpio
+			   * func[x]==1  bit = altfunc
+			   */
+	u32   gpiocfg;	  /* GPIO Configuration Register
+			   * gpiocfg[x]==0 bit = input
+			   * gpiocfg[x]==1 bit = output
+			   */
+	u32   gpiod;	  /* GPIO Data Register
+			   * gpiod[x] read/write gpio pinX status
+			   */
+	u32   gpioilevel; /* GPIO Interrupt Status Register
+			   * interrupt level (see gpioistat)
+			   */
+	u32   gpioistat;  /* Gpio Interrupt Status Register
+			   * istat[x] = (gpiod[x] == level[x])
+			   * cleared in ISR (STICKY bits)
+			   */
+	u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
+} volatile * GPIO_t ;
+
+typedef enum
+{
+	GPIO_gpio_v		= 0,		// gpiofunc use pin as GPIO.
+	GPIO_alt_v		= 1,		// gpiofunc use pin as alt.
+	GPIO_input_v		= 0,		// gpiocfg use pin as input.
+	GPIO_output_v		= 1,		// gpiocfg use pin as output.
+	GPIO_pin0_b		= 0,
+	GPIO_pin0_m		= 0x00000001,
+	GPIO_pin1_b		= 1,
+	GPIO_pin1_m		= 0x00000002,
+	GPIO_pin2_b		= 2,
+	GPIO_pin2_m		= 0x00000004,
+	GPIO_pin3_b		= 3,
+	GPIO_pin3_m		= 0x00000008,
+	GPIO_pin4_b		= 4,
+	GPIO_pin4_m		= 0x00000010,
+	GPIO_pin5_b		= 5,
+	GPIO_pin5_m		= 0x00000020,
+	GPIO_pin6_b		= 6,
+	GPIO_pin6_m		= 0x00000040,
+	GPIO_pin7_b		= 7,
+	GPIO_pin7_m		= 0x00000080,
+	GPIO_pin8_b		= 8,
+	GPIO_pin8_m		= 0x00000100,
+	GPIO_pin9_b		= 9,
+	GPIO_pin9_m		= 0x00000200,
+	GPIO_pin10_b		= 10,
+	GPIO_pin10_m		= 0x00000400,
+	GPIO_pin11_b		= 11,
+	GPIO_pin11_m		= 0x00000800,
+	GPIO_pin12_b		= 12,
+	GPIO_pin12_m		= 0x00001000,
+	GPIO_pin13_b		= 13,
+	GPIO_pin13_m		= 0x00002000,
+
+// Alternate function pins.  Corrsponding gpiofunc bit set to GPIO_alt_v.
+
+	GPIO_u0sout_b		= GPIO_pin0_b,		// UART 0 serial out.
+	GPIO_u0sout_m		= GPIO_pin0_m,
+		GPIO_u0sout_cfg_v	= GPIO_output_v,
+	GPIO_u0sinp_b	= GPIO_pin1_b,			// UART 0 serial in.
+	GPIO_u0sinp_m	= GPIO_pin1_m,
+		GPIO_u0sinp_cfg_v	= GPIO_input_v,
+	GPIO_u0rtsn_b	= GPIO_pin2_b,			// UART 0 req. to send.
+	GPIO_u0rtsn_m	= GPIO_pin2_m,
+		GPIO_u0rtsn_cfg_v	= GPIO_output_v,
+	GPIO_u0ctsn_b	= GPIO_pin3_b,			// UART 0 clear to send.
+	GPIO_u0ctsn_m	= GPIO_pin3_m,
+		GPIO_u0ctsn_cfg_v	= GPIO_input_v,
+
+	GPIO_maddr22_b		= GPIO_pin4_b, 	// M&P bus bit 22.
+	GPIO_maddr22_m		= GPIO_pin4_m,
+		GPIO_maddr22_cfg_v	= GPIO_output_v,
+
+	GPIO_maddr23_b		= GPIO_pin5_b, 	// M&P bus bit 23.
+	GPIO_maddr23_m		= GPIO_pin5_m,
+		GPIO_maddr23_cfg_v	= GPIO_output_v,
+
+	GPIO_maddr24_b		= GPIO_pin6_b, 	// M&P bus bit 24.
+	GPIO_maddr24_m		= GPIO_pin6_m,
+		GPIO_maddr24_cfg_v	= GPIO_output_v,
+
+	GPIO_maddr25_b		= GPIO_pin7_b, 	// M&P bus bit 25.
+	GPIO_maddr25_m		= GPIO_pin7_m,
+		GPIO_maddr25_cfg_v	= GPIO_output_v,
+
+	GPIO_cpudmadebug_b 	= GPIO_pin8_b, 	// CPU or DMA debug pin
+	GPIO_cpudmadebug_m 	= GPIO_pin8_m,
+		GPIO_cpudmadebug_cfg_v	= GPIO_output_v,
+
+	GPIO_pcireq4_b 	= GPIO_pin9_b, 	// PCI Request 4
+	GPIO_pcireq4_m 	= GPIO_pin9_m,
+		GPIO_pcireq4_cfg_v	= GPIO_input_v,
+
+	GPIO_pcigrant4_b 	= GPIO_pin10_b, 	// PCI Grant 4
+	GPIO_pcigrant4_m 	= GPIO_pin10_m,
+		GPIO_pcigrant4_cfg_v	= GPIO_output_v,
+
+	GPIO_pcireq5_b 	= GPIO_pin11_b, 	// PCI Request 5
+	GPIO_pcireq5_m 	= GPIO_pin11_m,
+		GPIO_pcireq5_cfg_v	= GPIO_input_v,
+
+	GPIO_pcigrant5_b 	= GPIO_pin12_b, 	// PCI Grant 5
+	GPIO_pcigrant5_m 	= GPIO_pin12_m,
+		GPIO_pcigrant5_cfg_v	= GPIO_output_v,
+
+	GPIO_pcimuintn_b	= GPIO_pin13_b, 	// PCI messaging int.
+	GPIO_pcimuintn_m	= GPIO_pin13_m,
+		GPIO_pcimuintn_cfg_v	= GPIO_output_v,
+
+} GPIO_DEFS_t;
+
+#endif	// __IDT_GPIO_H__
+
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434.h idtlinux/include/asm-mips/idt-boards/rc32434/rc32434.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32434/rc32434.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,192 @@
+ /**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Definitions for IDT RC32434 CPU
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#ifndef _RC32434_H_
+#define _RC32434_H_
+
+#include <linux/config.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <asm/idt-boards/rc32434/rc32434_timer.h>
+
+#define RC32434_REG_BASE   0x18000000
+
+
+#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
+#define idt_timer     ((volatile TIM_t)  TIM0_VirtualAddress)
+#define gpio	  ((volatile GPIO_t) GPIO0_VirtualAddress)
+
+#define IDT_CLOCK_MULT 2
+#define MIPS_CPU_TIMER_IRQ 7
+/* Interrupt Controller */
+#define IC_GROUP0_PEND     (RC32434_REG_BASE + 0x38000)
+#define IC_GROUP0_MASK     (RC32434_REG_BASE + 0x38008)
+#define IC_GROUP_OFFSET    0x0C
+#define RTC_BASE           0xBA001FF0
+
+#define NUM_INTR_GROUPS    5
+/* 16550 UARTs */
+
+#define GROUP0_IRQ_BASE 8		/* GRP2 IRQ numbers start here */
+#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
+#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
+#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32)	/* GRP5 IRQ numbers start here */
+#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
+
+#ifdef __MIPSEB__
+#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
+#define EB434_UART1_BASE   (0x19800003)
+#else
+#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
+#define EB434_UART1_BASE   (0x19800000)
+#endif
+
+#define RC32434_UART0_IRQ  GROUP3_IRQ_BASE + 0
+#define EB434_UART1_IRQ    GROUP4_IRQ_BASE + 11
+
+#if 0
+#define local_readl(addr) __raw_readl(addr)
+#define local_writel(l,addr) __raw_writel(l,addr)
+#endif 
+
+#define RC32434_NR_IRQS  (GROUP4_IRQ_BASE + 32)
+
+/* cpu pipeline flush */
+static inline void rc32434_sync(void)
+{
+        __asm__ volatile ("sync");
+}
+
+static inline void rc32434_sync_udelay(int us)
+{
+        __asm__ volatile ("sync");
+        udelay(us);
+}
+
+static inline void rc32434_sync_delay(int ms)
+{
+        __asm__ volatile ("sync");
+        mdelay(ms);
+}
+
+
+
+/*
+ * Macros to access internal RC32434 registers. No byte
+ * swapping should be done when accessing the internal
+ * registers.
+ */
+
+#define rc32434_readb __raw_readb
+#define rc32434_readw __raw_readw
+#define rc32434_readl __raw_readl
+
+#define rc32434_writeb __raw_writeb
+#define rc32434_writew __raw_writew
+#define rc32434_writel __raw_writel
+
+#if 0
+static inline u8 rc32434_readb(unsigned long pa)
+{
+	return *((volatile u8 *)KSEG1ADDR(pa));
+}
+static inline u16 rc32434_readw(unsigned long pa)
+{
+	return *((volatile u16 *)KSEG1ADDR(pa));
+}
+static inline u32 rc32434_readl(unsigned long pa)
+{
+	return *((volatile u32 *)KSEG1ADDR(pa));
+}
+static inline void rc32434_writeb(u8 val, unsigned long pa)
+{
+	*((volatile u8 *)KSEG1ADDR(pa)) = val;
+}
+static inline void rc32434_writew(u16 val, unsigned long pa)
+{
+	*((volatile u16 *)KSEG1ADDR(pa)) = val;
+}
+static inline void rc32434_writel(u32 val, unsigned long pa)
+{
+	*((volatile u32 *)KSEG1ADDR(pa)) = val;
+}
+
+#endif
+
+
+/*
+ * C access to CLZ and CLO instructions
+ * (count leading zeroes/ones).
+ */
+static inline int rc32434_clz(unsigned long val)
+{
+	int ret;
+        __asm__ volatile (
+		".set\tnoreorder\n\t"
+		".set\tnoat\n\t"
+		".set\tmips32r2\n\t"
+		"clz\t%0,%1\n\t"
+                ".set\tmips0\n\t"
+                ".set\tat\n\t"
+                ".set\treorder"
+                : "=r" (ret)
+		: "r" (val));
+
+	return ret;
+}
+static inline int rc32434_clo(unsigned long val)
+{
+	int ret;
+        __asm__ volatile (
+		".set\tnoreorder\n\t"
+		".set\tnoat\n\t"
+		".set\tmips32r2\n\t"
+		"clo\t%0,%1\n\t"
+                ".set\tmips0\n\t"
+                ".set\tat\n\t"
+                ".set\treorder"
+                : "=r" (ret)
+		: "r" (val));
+
+	return ret;
+}
+#endif /* _RC32434_H_ */
+
+
+
+
+
+
+
+
+
+
+
+
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_integ.h idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_integ.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_integ.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_integ.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,83 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   System Integrity register definition
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_INTEG_H__
+#define __IDT_INTEG_H__
+
+enum
+{
+	INTEG0_PhysicalAddress	= 0x18030000,
+	INTEG_PhysicalAddress	= INTEG0_PhysicalAddress,	// Default
+
+	INTEG0_VirtualAddress	= 0xB8030000,
+	INTEG_VirtualAddress	= INTEG0_VirtualAddress,	// Default
+} ;
+
+// if you are looking for CEA, try rst.h
+typedef struct
+{
+	u32 filler [0xc] ;		// 0x30 bytes unused.
+	u32 errcs ;			// sticky use ERRCS_
+	u32 wtcount ;			// Watchdog timer count reg.
+	u32 wtcompare ;			// Watchdog timer timeout value.
+	u32 wtc ;			// Watchdog timer control. use WTC_
+} volatile *INTEG_t ;
+
+enum
+{
+	ERRCS_wto_b		= 0,		// In INTEG_t -> errcs
+	ERRCS_wto_m		= 0x00000001,
+	ERRCS_wne_b		= 1,		// In INTEG_t -> errcs
+	ERRCS_wne_m		= 0x00000002,
+	ERRCS_ucw_b		= 2,		// In INTEG_t -> errcs
+	ERRCS_ucw_m		= 0x00000004,
+	ERRCS_ucr_b		= 3,		// In INTEG_t -> errcs
+	ERRCS_ucr_m		= 0x00000008,
+	ERRCS_upw_b		= 4,		// In INTEG_t -> errcs
+	ERRCS_upw_m		= 0x00000010,
+	ERRCS_upr_b		= 5,		// In INTEG_t -> errcs
+	ERRCS_upr_m		= 0x00000020,
+	ERRCS_udw_b		= 6,		// In INTEG_t -> errcs
+	ERRCS_udw_m		= 0x00000040,
+	ERRCS_udr_b		= 7,		// In INTEG_t -> errcs
+	ERRCS_udr_m		= 0x00000080,
+	ERRCS_sae_b		= 8,		// In INTEG_t -> errcs
+	ERRCS_sae_m		= 0x00000100,
+	ERRCS_wre_b		= 9,		// In INTEG_t -> errcs
+	ERRCS_wre_m		= 0x00000200,
+
+	WTC_en_b		= 0,		// In INTEG_t -> wtc
+	WTC_en_m		= 0x00000001,
+	WTC_to_b		= 1,		// In INTEG_t -> wtc
+	WTC_to_m		= 0x00000002,
+} ;
+
+#endif	// __IDT_INTEG_H__
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_int.h idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_int.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_int.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_int.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,166 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Interrupt Controller register definition.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_INT_H__
+#define __IDT_INT_H__
+
+enum
+{
+	INT0_PhysicalAddress	= 0x18038000,
+	INT_PhysicalAddress	= INT0_PhysicalAddress,		// Default
+
+	INT0_VirtualAddress	= 0xB8038000,
+	INT_VirtualAddress	= INT0_VirtualAddress,		// Default
+} ;
+
+struct INT_s
+{
+	u32		ipend ;		//Pending interrupts. use INT?_
+	u32		itest ;		//Test bits.		use INT?_
+	u32		imask ;		//Interrupt disabled when set. use INT?_
+} ;
+
+enum
+{
+	IPEND2	= 0,			// HW 2 interrupt to core. use INT2_
+	IPEND3	= 1,			// HW 3 interrupt to core. use INT3_
+	IPEND4	= 2,			// HW 4 interrupt to core. use INT4_
+	IPEND5	= 3,			// HW 5 interrupt to core. use INT5_
+	IPEND6	= 4,			// HW 6 interrupt to core. use INT6_
+
+	IPEND_count,			// must be last (used in loops)
+	IPEND_min	= IPEND2	// min IPEND (used in loops)
+};
+
+typedef struct INTC_s
+{
+	struct INT_s	i [IPEND_count] ;// use i[IPEND?] = INT?_
+	u32		nmips ;		// use NMIPS_
+} volatile *INT_t ;
+
+enum
+{
+	INT2_timer0_b			= 0,
+	INT2_timer0_m			= 0x00000001,
+	INT2_timer1_b			= 1,
+	INT2_timer1_m			= 0x00000002,
+	INT2_timer2_b			= 2,
+	INT2_timer2_m			= 0x00000004,
+	INT2_refresh_b			= 3,
+	INT2_refresh_m			= 0x00000008,
+	INT2_watchdogTimeout_b		= 4,
+	INT2_watchdogTimeout_m		= 0x00000010,
+	INT2_undecodedCpuWrite_b	= 5,
+	INT2_undecodedCpuWrite_m	= 0x00000020,
+	INT2_undecodedCpuRead_b		= 6,
+	INT2_undecodedCpuRead_m		= 0x00000040,
+	INT2_undecodedPciWrite_b	= 7,
+	INT2_undecodedPciWrite_m	= 0x00000080,
+	INT2_undecodedPciRead_b		= 8,
+	INT2_undecodedPciRead_m		= 0x00000100,
+	INT2_undecodedDmaWrite_b	= 9,
+	INT2_undecodedDmaWrite_m	= 0x00000200,
+	INT2_undecodedDmaRead_b		= 10,
+	INT2_undecodedDmaRead_m		= 0x00000400,
+	INT2_ipBusSlaveAckError_b	= 11,
+	INT2_ipBusSlaveAckError_m	= 0x00000800,
+
+	INT3_dmaChannel0_b		= 0,
+	INT3_dmaChannel0_m		= 0x00000001,
+	INT3_dmaChannel1_b		= 1,
+	INT3_dmaChannel1_m		= 0x00000002,
+	INT3_dmaChannel2_b		= 2,
+	INT3_dmaChannel2_m		= 0x00000004,
+	INT3_dmaChannel3_b		= 3,
+	INT3_dmaChannel3_m		= 0x00000008,
+	INT3_dmaChannel4_b		= 4,
+	INT3_dmaChannel4_m		= 0x00000010,
+	INT3_dmaChannel5_b		= 5,
+	INT3_dmaChannel5_m		= 0x00000020,
+
+	INT5_uartGeneral0_b		= 0,
+	INT5_uartGeneral0_m		= 0x00000001,
+	INT5_uartTxrdy0_b		= 1,
+	INT5_uartTxrdy0_m		= 0x00000002,
+	INT5_uartRxrdy0_b		= 2,
+	INT5_uartRxrdy0_m		= 0x00000004,
+	INT5_pci_b			= 3,
+	INT5_pci_m			= 0x00000008,
+	INT5_pciDecoupled_b		= 4,
+	INT5_pciDecoupled_m		= 0x00000010,
+	INT5_spi_b			= 5,
+	INT5_spi_m			= 0x00000020,
+	INT5_deviceDecoupled_b		= 6,
+	INT5_deviceDecoupled_m		= 0x00000040,
+	INT5_eth0Ovr_b			= 9,
+	INT5_eth0Ovr_m			= 0x00000200,
+	INT5_eth0Und_b			= 10,
+	INT5_eth0Und_m			= 0x00000400,
+	INT5_eth0Pfd_b			= 11,
+	INT5_eth0Pfd_m			= 0x00000800,
+	INT5_nvram_b			= 12,
+	INT5_nvram_m			= 0x00001000,
+
+	INT6_gpio0_b			= 0,
+	INT6_gpio0_m			= 0x00000001,
+	INT6_gpio1_b			= 1,
+	INT6_gpio1_m			= 0x00000002,
+	INT6_gpio2_b			= 2,
+	INT6_gpio2_m			= 0x00000004,
+	INT6_gpio3_b			= 3,
+	INT6_gpio3_m			= 0x00000008,
+	INT6_gpio4_b			= 4,
+	INT6_gpio4_m			= 0x00000010,
+	INT6_gpio5_b			= 5,
+	INT6_gpio5_m			= 0x00000020,
+	INT6_gpio6_b			= 6,
+	INT6_gpio6_m			= 0x00000040,
+	INT6_gpio7_b			= 7,
+	INT6_gpio7_m			= 0x00000080,
+	INT6_gpio8_b			= 8,
+	INT6_gpio8_m			= 0x00000100,
+	INT6_gpio9_b			= 9,
+	INT6_gpio9_m			= 0x00000200,
+	INT6_gpio10_b			= 10,
+	INT6_gpio10_m			= 0x00000400,
+	INT6_gpio11_b			= 11,
+	INT6_gpio11_m			= 0x00000800,
+	INT6_gpio12_b			= 12,
+	INT6_gpio12_m			= 0x00001000,
+	INT6_gpio13_b			= 13,
+	INT6_gpio13_m			= 0x00002000,
+
+	NMIPS_gpio_b			= 0,
+	NMIPS_gpio_m			= 0x00000001,
+} ;
+
+#endif	// __IDT_INT_H__
+
+
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,104 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   IP Arbiter register definitions
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_IPARB_H__
+#define __IDT_IPARB_H__
+
+enum
+{
+	IPARB0_PhysicalAddress	= 0x18048000,
+	IPARB_PhysicalAddress	= IPARB0_PhysicalAddress,	// Default
+
+	IPARB0_VirtualAddress	= 0xB8048000,
+	IPARB_VirtualAddress	= IPARB0_VirtualAddress,	// Default
+} ;
+
+enum
+{
+	IPABMXC_ethernet0Receive	= 0,
+	IPABMXC_ethernet0Transmit	= 1,
+	IPABMXC_memoryToHoldFifo	= 2,
+	IPABMXC_holdFifoToMemory	= 3,
+	IPABMXC_pciToMemory		= 4,
+	IPABMXC_memoryToPci		= 5,
+	IPABMXC_pciTarget		= 6,
+	IPABMXC_pciTargetStart		= 7,
+	IPABMXC_cpuToIpBus		= 8,
+
+	IPABMXC_Count,				// Must be last in list !
+	IPABMXC_Min			= IPABMXC_ethernet0Receive,
+
+	IPAPXC_PriorityCount	= 4,		// 3-highest, 0-lowest.
+} ;
+
+typedef struct
+{
+	u32	ipapc [IPAPXC_PriorityCount] ;	// ipapc[IPAPXC_] = IPAPC_
+	u32	ipabmc [IPABMXC_Count] ;	// ipabmc[IPABMXC_] = IPABMC_
+	u32	ipac ;				// use IPAC_
+	u32	ipaitcc;			// use IPAITCC_
+	u32	ipaspare ;
+} volatile * IPARB_t ;
+
+enum
+{
+	IPAC_dp_b			= 0,
+	IPAC_dp_m			= 0x00000001,
+	IPAC_dep_b			= 1,
+	IPAC_dep_m			= 0x00000002,
+	IPAC_drm_b			= 2,
+	IPAC_drm_m			= 0x00000004,
+	IPAC_dwm_b			= 3,
+	IPAC_dwm_m			= 0x00000008,
+	IPAC_msk_b			= 4,
+	IPAC_msk_m			= 0x00000010,
+
+	IPAPC_ptc_b			= 0,
+	IPAPC_ptc_m			= 0x00003fff,
+	IPAPC_mf_b			= 14,
+	IPAPC_mf_m			= 0x00004000,
+	IPAPC_cptc_b			= 16,
+	IPAPC_cptc_m			= 0x3fff0000,
+
+	IPAITCC_itcc			= 0,
+	IPAITCC_itcc,			= 0x000001ff,
+
+	IPABMC_mtc_b			= 0,
+	IPABMC_mtc_m			= 0x00000fff,
+	IPABMC_p_b			= 12,
+	IPABMC_p_m			= 0x00003000,
+	IPABMC_msk_b			= 14,
+	IPABMC_msk_m			= 0x00004000,
+	IPABMC_cmtc_b			= 16,
+	IPABMC_cmtc_m			= 0x0fff0000,
+};
+
+#endif	// __IDT_IPARB_H__
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_pci.h idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_pci.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_pci.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_pci.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,688 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   PCI register definitio
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_PCI_H__
+#define __IDT_PCI_H__
+
+enum
+{
+	PCI0_PhysicalAddress	= 0x18080000,
+	PCI_PhysicalAddress	= PCI0_PhysicalAddress,
+
+	PCI0_VirtualAddress	= 0xB8080000,
+	PCI_VirtualAddress	= PCI0_VirtualAddress,
+} ;
+
+enum
+{
+	PCI_LbaCount	= 4,		// Local base addresses.
+} ;
+
+typedef struct
+{
+	u32	a ;		// Address.
+	u32	c ;		// Control.
+	u32	m ;		// mapping.
+} PCI_Map_s ;
+
+typedef struct
+{
+	u32		pcic ;
+	u32		pcis ;
+	u32		pcism ;
+	u32		pcicfga ;
+	u32		pcicfgd ;
+	PCI_Map_s	pcilba [PCI_LbaCount] ;
+	u32		pcidac ;
+	u32		pcidas ;
+	u32		pcidasm ;
+	u32		pcidad ;
+	u32		pcidma8c ;
+	u32		pcidma9c ;
+	u32		pcitc ;
+} volatile *PCI_t ;
+
+// PCI messaging unit.
+enum
+{
+	PCIM_Count	= 2,
+} ;
+typedef struct
+{
+	u32		pciim [PCIM_Count] ;
+	u32		pciom [PCIM_Count] ;
+	u32		pciid ;
+	u32		pciiic ;
+	u32		pciiim ;
+	u32		pciiod ;
+	u32		pciioic ;
+	u32		pciioim ;
+} volatile *PCIM_t ;
+
+/*******************************************************************************
+ *
+ * PCI Control Register
+ *
+ ******************************************************************************/
+enum
+{
+	PCIC_en_b	= 0,
+	PCIC_en_m	= 0x00000001,
+	PCIC_tnr_b	= 1,
+	PCIC_tnr_m	= 0x00000002,
+	PCIC_sce_b	= 2,
+	PCIC_sce_m	= 0x00000004,
+	PCIC_ien_b	= 3,
+	PCIC_ien_m	= 0x00000008,
+	PCIC_aaa_b	= 4,
+	PCIC_aaa_m	= 0x00000010,
+	PCIC_eap_b	= 5,
+	PCIC_eap_m	= 0x00000020,
+	PCIC_pcim_b	= 6,
+	PCIC_pcim_m	= 0x000001c0,
+		PCIC_pcim_disabled_v	= 0,
+		PCIC_pcim_tnr_v 	= 1,	// Satellite - target not ready
+		PCIC_pcim_suspend_v	= 2,	// Satellite - suspended CPU.
+		PCIC_pcim_extern_v	= 3,	// Host - external arbiter.
+		PCIC_pcim_fixed_v	= 4,	// Host - fixed priority arb.
+		PCIC_pcim_roundrobin_v	= 5,	// Host - round robin priority.
+		PCIC_pcim_reserved6_v	= 6,
+		PCIC_pcim_reserved7_v	= 7,
+	PCIC_igm_b	= 9,
+	PCIC_igm_m	= 0x00000200,
+} ;
+
+/*******************************************************************************
+ *
+ * PCI Status Register
+ *
+ ******************************************************************************/
+enum {
+	PCIS_eed_b	= 0,
+	PCIS_eed_m	= 0x00000001,
+	PCIS_wr_b	= 1,
+	PCIS_wr_m	= 0x00000002,
+	PCIS_nmi_b	= 2,
+	PCIS_nmi_m	= 0x00000004,
+	PCIS_ii_b	= 3,
+	PCIS_ii_m	= 0x00000008,
+	PCIS_cwe_b	= 4,
+	PCIS_cwe_m	= 0x00000010,
+	PCIS_cre_b	= 5,
+	PCIS_cre_m	= 0x00000020,
+	PCIS_mdpe_b	= 6,
+	PCIS_mdpe_m	= 0x00000040,
+	PCIS_sta_b	= 7,
+	PCIS_sta_m	= 0x00000080,
+	PCIS_rta_b	= 8,
+	PCIS_rta_m	= 0x00000100,
+	PCIS_rma_b	= 9,
+	PCIS_rma_m	= 0x00000200,
+	PCIS_sse_b	= 10,
+	PCIS_sse_m	= 0x00000400,
+	PCIS_ose_b	= 11,
+	PCIS_ose_m	= 0x00000800,
+	PCIS_pe_b	= 12,
+	PCIS_pe_m	= 0x00001000,
+	PCIS_tae_b	= 13,
+	PCIS_tae_m	= 0x00002000,
+	PCIS_rle_b	= 14,
+	PCIS_rle_m	= 0x00004000,
+	PCIS_bme_b	= 15,
+	PCIS_bme_m	= 0x00008000,
+	PCIS_prd_b	= 16,
+	PCIS_prd_m	= 0x00010000,
+	PCIS_rip_b	= 17,
+	PCIS_rip_m	= 0x00020000,
+} ;
+
+/*******************************************************************************
+ *
+ * PCI Status Mask Register
+ *
+ ******************************************************************************/
+enum {
+	PCISM_eed_b		= 0,
+	PCISM_eed_m		= 0x00000001,
+	PCISM_wr_b		= 1,
+	PCISM_wr_m		= 0x00000002,
+	PCISM_nmi_b		= 2,
+	PCISM_nmi_m		= 0x00000004,
+	PCISM_ii_b		= 3,
+	PCISM_ii_m		= 0x00000008,
+	PCISM_cwe_b		= 4,
+	PCISM_cwe_m		= 0x00000010,
+	PCISM_cre_b		= 5,
+	PCISM_cre_m		= 0x00000020,
+	PCISM_mdpe_b		= 6,
+	PCISM_mdpe_m		= 0x00000040,
+	PCISM_sta_b		= 7,
+	PCISM_sta_m		= 0x00000080,
+	PCISM_rta_b		= 8,
+	PCISM_rta_m		= 0x00000100,
+	PCISM_rma_b		= 9,
+	PCISM_rma_m		= 0x00000200,
+	PCISM_sse_b		= 10,
+	PCISM_sse_m		= 0x00000400,
+	PCISM_ose_b		= 11,
+	PCISM_ose_m		= 0x00000800,
+	PCISM_pe_b		= 12,
+	PCISM_pe_m		= 0x00001000,
+	PCISM_tae_b		= 13,
+	PCISM_tae_m		= 0x00002000,
+	PCISM_rle_b		= 14,
+	PCISM_rle_m		= 0x00004000,
+	PCISM_bme_b		= 15,
+	PCISM_bme_m		= 0x00008000,
+	PCISM_prd_b		= 16,
+	PCISM_prd_m		= 0x00010000,
+	PCISM_rip_b		= 17,
+	PCISM_rip_m		= 0x00020000,
+} ;
+
+/*******************************************************************************
+ *
+ * PCI Configuration Address Register
+ *
+ ******************************************************************************/
+enum {
+	PCICFGA_reg_b		= 2,
+	PCICFGA_reg_m		= 0x000000fc,
+		PCICFGA_reg_id_v	= 0x00>>2, //use PCFGID_
+		PCICFGA_reg_04_v	= 0x04>>2, //use PCFG04_
+		PCICFGA_reg_08_v	= 0x08>>2, //use PCFG08_
+		PCICFGA_reg_0C_v	= 0x0C>>2, //use PCFG0C_
+		PCICFGA_reg_pba0_v	= 0x10>>2, //use PCIPBA_
+		PCICFGA_reg_pba1_v	= 0x14>>2, //use PCIPBA_
+		PCICFGA_reg_pba2_v	= 0x18>>2, //use PCIPBA_
+		PCICFGA_reg_pba3_v	= 0x1c>>2, //use PCIPBA_
+		PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
+		PCICFGA_reg_3C_v	= 0x3C>>2, //use PCFG3C_
+		PCICFGA_reg_pba0c_v	= 0x44>>2, //use PCIPBAC_
+		PCICFGA_reg_pba0m_v	= 0x48>>2,
+		PCICFGA_reg_pba1c_v	= 0x4c>>2, //use PCIPBAC_
+		PCICFGA_reg_pba1m_v	= 0x50>>2,
+		PCICFGA_reg_pba2c_v	= 0x54>>2, //use PCIPBAC_
+		PCICFGA_reg_pba2m_v	= 0x58>>2,
+		PCICFGA_reg_pba3c_v	= 0x5c>>2, //use PCIPBAC_
+		PCICFGA_reg_pba3m_v	= 0x60>>2,
+		PCICFGA_reg_pmgt_v	= 0x64>>2,
+	PCICFGA_func_b		= 8,
+	PCICFGA_func_m		= 0x00000700,
+	PCICFGA_dev_b		= 11,
+	PCICFGA_dev_m		= 0x0000f800,
+		PCICFGA_dev_internal_v	= 0,
+	PCICFGA_bus_b		= 16,
+	PCICFGA_bus_m		= 0x00ff0000,
+		PCICFGA_bus_type0_v	= 0,	//local bus
+	PCICFGA_en_b		= 31,		// read only
+	PCICFGA_en_m		= 0x80000000,
+} ;
+
+enum {
+	PCFGID_vendor_b 	= 0,
+	PCFGID_vendor_m 	= 0x0000ffff,
+		PCFGID_vendor_IDT_v		= 0x111d,
+	PCFGID_device_b 	= 16,
+	PCFGID_device_m 	= 0xffff0000,
+		PCFGID_device_Korinade_v	= 0x0214,
+
+	PCFG04_command_ioena_b		= 1,
+	PCFG04_command_ioena_m		= 0x00000001,
+	PCFG04_command_memena_b 	= 2,
+	PCFG04_command_memena_m 	= 0x00000002,
+	PCFG04_command_bmena_b		= 3,
+	PCFG04_command_bmena_m		= 0x00000004,
+	PCFG04_command_mwinv_b		= 5,
+	PCFG04_command_mwinv_m		= 0x00000010,
+	PCFG04_command_parena_b 	= 7,
+	PCFG04_command_parena_m 	= 0x00000040,
+	PCFG04_command_serrena_b	= 9,
+	PCFG04_command_serrena_m	= 0x00000100,
+	PCFG04_command_fastbbena_b	= 10,
+	PCFG04_command_fastbbena_m	= 0x00000200,
+	PCFG04_status_b 		= 16,
+	PCFG04_status_m 		= 0xffff0000,
+	PCFG04_status_66MHz_b		= 21,	// 66 MHz enable
+	PCFG04_status_66MHz_m		= 0x00200000,
+	PCFG04_status_fbb_b		= 23,
+	PCFG04_status_fbb_m		= 0x00800000,
+	PCFG04_status_mdpe_b		= 24,
+	PCFG04_status_mdpe_m		= 0x01000000,
+	PCFG04_status_dst_b		= 25,
+	PCFG04_status_dst_m		= 0x06000000,
+	PCFG04_status_sta_b		= 27,
+	PCFG04_status_sta_m		= 0x08000000,
+	PCFG04_status_rta_b		= 28,
+	PCFG04_status_rta_m		= 0x10000000,
+	PCFG04_status_rma_b		= 29,
+	PCFG04_status_rma_m		= 0x20000000,
+	PCFG04_status_sse_b		= 30,
+	PCFG04_status_sse_m		= 0x40000000,
+	PCFG04_status_pe_b		= 31,
+	PCFG04_status_pe_m		= 0x40000000,
+
+	PCFG08_revId_b			= 0,
+	PCFG08_revId_m			= 0x000000ff,
+	PCFG08_classCode_b		= 0,
+	PCFG08_classCode_m		= 0xffffff00,
+		PCFG08_classCode_bridge_v	= 06,
+		PCFG08_classCode_proc_v 	= 0x0b3000, // processor-MIPS
+	PCFG0C_cacheline_b		= 0,
+	PCFG0C_cacheline_m		= 0x000000ff,
+	PCFG0C_masterLatency_b		= 8,
+	PCFG0C_masterLatency_m		= 0x0000ff00,
+	PCFG0C_headerType_b		= 16,
+	PCFG0C_headerType_m		= 0x00ff0000,
+	PCFG0C_bist_b			= 24,
+	PCFG0C_bist_m			= 0xff000000,
+
+	PCIPBA_msi_b			= 0,
+	PCIPBA_msi_m			= 0x00000001,
+	PCIPBA_p_b			= 3,
+	PCIPBA_p_m			= 0x00000004,
+	PCIPBA_baddr_b			= 8,
+	PCIPBA_baddr_m			= 0xffffff00,
+
+	PCFGSS_vendorId_b		= 0,
+	PCFGSS_vendorId_m		= 0x0000ffff,
+	PCFGSS_id_b			= 16,
+	PCFGSS_id_m			= 0xffff0000,
+
+	PCFG3C_interruptLine_b		= 0,
+	PCFG3C_interruptLine_m		= 0x000000ff,
+	PCFG3C_interruptPin_b		= 8,
+	PCFG3C_interruptPin_m		= 0x0000ff00,
+	PCFG3C_minGrant_b		= 16,
+	PCFG3C_minGrant_m		= 0x00ff0000,
+	PCFG3C_maxLat_b 		= 24,
+	PCFG3C_maxLat_m 		= 0xff000000,
+
+	PCIPBAC_msi_b			= 0,
+	PCIPBAC_msi_m			= 0x00000001,
+	PCIPBAC_p_b			= 1,
+	PCIPBAC_p_m			= 0x00000002,
+	PCIPBAC_size_b			= 2,
+	PCIPBAC_size_m			= 0x0000007c,
+	PCIPBAC_sb_b			= 7,
+	PCIPBAC_sb_m			= 0x00000080,
+	PCIPBAC_pp_b			= 8,
+	PCIPBAC_pp_m			= 0x00000100,
+	PCIPBAC_mr_b			= 9,
+	PCIPBAC_mr_m			= 0x00000600,
+		PCIPBAC_mr_read_v	=0,	//no prefetching
+		PCIPBAC_mr_readLine_v	=1,
+		PCIPBAC_mr_readMult_v	=2,
+	PCIPBAC_mrl_b			= 11,
+	PCIPBAC_mrl_m			= 0x00000800,
+	PCIPBAC_mrm_b			= 12,
+	PCIPBAC_mrm_m			= 0x00001000,
+	PCIPBAC_trp_b			= 13,
+	PCIPBAC_trp_m			= 0x00002000,
+
+	PCFG40_trdyTimeout_b		= 0,
+	PCFG40_trdyTimeout_m		= 0x000000ff,
+	PCFG40_retryLim_b		= 8,
+	PCFG40_retryLim_m		= 0x0000ff00,
+};
+
+/*******************************************************************************
+ *
+ * PCI Local Base Address [0|1|2|3] Register
+ *
+ ******************************************************************************/
+enum {
+	PCILBA_baddr_b		= 0,		// In PCI_t -> pcilba [] .a
+	PCILBA_baddr_m		= 0xffffff00,
+} ;
+/*******************************************************************************
+ *
+ * PCI Local Base Address Control Register
+ *
+ ******************************************************************************/
+enum {
+	PCILBAC_msi_b		= 0,		// In pPci->pcilba[i].c
+	PCILBAC_msi_m		= 0x00000001,
+		PCILBAC_msi_mem_v	= 0,
+		PCILBAC_msi_io_v	= 1,
+	PCILBAC_size_b		= 2,	// In pPci->pcilba[i].c
+	PCILBAC_size_m		= 0x0000007c,
+	PCILBAC_sb_b		= 7,	// In pPci->pcilba[i].c
+	PCILBAC_sb_m		= 0x00000080,
+	PCILBAC_rt_b		= 8,	// In pPci->pcilba[i].c
+	PCILBAC_rt_m		= 0x00000100,
+		PCILBAC_rt_noprefetch_v = 0, // mem read
+		PCILBAC_rt_prefetch_v	= 1, // mem readline
+} ;
+
+/*******************************************************************************
+ *
+ * PCI Local Base Address [0|1|2|3] Mapping Register
+ *
+ ******************************************************************************/
+enum {
+	PCILBAM_maddr_b 	= 8,
+	PCILBAM_maddr_m 	= 0xffffff00,
+} ;
+
+/*******************************************************************************
+ *
+ * PCI Decoupled Access Control Register
+ *
+ ******************************************************************************/
+enum {
+	PCIDAC_den_b		= 0,
+	PCIDAC_den_m		= 0x00000001,
+} ;
+
+/*******************************************************************************
+ *
+ * PCI Decoupled Access Status Register
+ *
+ ******************************************************************************/
+enum {
+	PCIDAS_d_b	= 0,
+	PCIDAS_d_m	= 0x00000001,
+	PCIDAS_b_b	= 1,
+	PCIDAS_b_m	= 0x00000002,
+	PCIDAS_e_b	= 2,
+	PCIDAS_e_m	= 0x00000004,
+	PCIDAS_ofe_b	= 3,
+	PCIDAS_ofe_m	= 0x00000008,
+	PCIDAS_off_b	= 4,
+	PCIDAS_off_m	= 0x00000010,
+	PCIDAS_ife_b	= 5,
+	PCIDAS_ife_m	= 0x00000020,
+	PCIDAS_iff_b	= 6,
+	PCIDAS_iff_m	= 0x00000040,
+} ;
+
+/*******************************************************************************
+ *
+ * PCI DMA Channel 8 Configuration Register
+ *
+ ******************************************************************************/
+enum
+{
+	PCIDMA8C_mbs_b	= 0,		// Maximum Burst Size.
+	PCIDMA8C_mbs_m	= 0x00000fff,	// { pcidma8c }
+	PCIDMA8C_our_b	= 12,		// Optimize Unaligned Burst Reads.
+	PCIDMA8C_our_m	= 0x00001000,	// { pcidma8c }
+} ;
+
+/*******************************************************************************
+ *
+ * PCI DMA Channel 9 Configuration Register
+ *
+ ******************************************************************************/
+enum
+{
+	PCIDMA9C_mbs_b	= 0,		// Maximum Burst Size.
+	PCIDMA9C_mbs_m	= 0x00000fff, // { pcidma9c }
+} ;
+
+/*******************************************************************************
+ *
+ * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
+ *
+ ******************************************************************************/
+enum {
+	PCIDMAD_pt_b		= 22,		// in DEVCMD field (descriptor)
+	PCIDMAD_pt_m		= 0x00c00000,	// preferred transaction field
+		// These are for reads (DMA channel 8)
+		PCIDMAD_devcmd_mr_v	= 0,	//memory read
+		PCIDMAD_devcmd_mrl_v	= 1,	//memory read line
+		PCIDMAD_devcmd_mrm_v	= 2,	//memory read multiple
+		PCIDMAD_devcmd_ior_v	= 3,	//I/O read
+		// These are for writes (DMA channel 9)
+		PCIDMAD_devcmd_mw_v	= 0,	//memory write
+		PCIDMAD_devcmd_mwi_v	= 1,	//memory write invalidate
+		PCIDMAD_devcmd_iow_v	= 3,	//I/O write
+
+	// Swap byte field applies to both DMA channel 8 and 9
+	PCIDMAD_sb_b		= 24,		// in DEVCMD field (descriptor)
+	PCIDMAD_sb_m		= 0x01000000,	// swap byte field
+} ;
+
+
+/*******************************************************************************
+ *
+ * PCI Target Control Register
+ *
+ ******************************************************************************/
+enum
+{
+	PCITC_rtimer_b		= 0,		// In PCITC_t -> pcitc
+	PCITC_rtimer_m		= 0x000000ff,
+	PCITC_dtimer_b		= 8,		// In PCITC_t -> pcitc
+	PCITC_dtimer_m		= 0x0000ff00,
+	PCITC_rdr_b		= 18,		// In PCITC_t -> pcitc
+	PCITC_rdr_m		= 0x00040000,
+	PCITC_ddt_b		= 19,		// In PCITC_t -> pcitc
+	PCITC_ddt_m		= 0x00080000,
+} ;
+/*******************************************************************************
+ *
+ * PCI messaging unit [applies to both inbound and outbound registers ]
+ *
+ ******************************************************************************/
+enum
+{
+	PCIM_m0_b	= 0,		// In PCIM_t -> {pci{iic,iim,ioic,ioim}}
+	PCIM_m0_m	= 0x00000001,	// inbound or outbound message 0
+	PCIM_m1_b	= 1,		// In PCIM_t -> {pci{iic,iim,ioic,ioim}}
+	PCIM_m1_m	= 0x00000002,	// inbound or outbound message 1
+	PCIM_db_b	= 2,		// In PCIM_t -> {pci{iic,iim,ioic,ioim}}
+	PCIM_db_m	= 0x00000004,	// inbound or outbound doorbell
+};
+
+
+
+
+
+
+#define PCI_MSG_VirtualAddress	     0xB8088010
+#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
+#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
+
+#define PCIM_SHFT		0x6
+#define PCIM_BIT_LEN		0x7
+#define PCIM_H_EA		0x3
+#define PCIM_H_IA_FIX		0x4
+#define PCIM_H_IA_RR		0x5
+#if 0
+#define PCI_ADDR_START		0x13000000
+#endif
+
+#define PCI_ADDR_START		0x50000000
+
+#define CPUTOPCI_MEM_WIN	0x02000000
+#define CPUTOPCI_IO_WIN		0x00100000
+#define PCILBA_SIZE_SHFT	2
+#define PCILBA_SIZE_MASK	0x1F
+#define SIZE_256MB		0x1C
+#define SIZE_128MB		0x1B
+#define SIZE_64MB               0x1A
+#define SIZE_32MB		0x19
+#define SIZE_16MB               0x18
+#define SIZE_4MB		0x16
+#define SIZE_2MB		0x15
+#define SIZE_1MB		0x14
+#define KORINA_CONFIG0_ADDR	0x80000000
+#define KORINA_CONFIG1_ADDR	0x80000004
+#define KORINA_CONFIG2_ADDR	0x80000008
+#define KORINA_CONFIG3_ADDR	0x8000000C
+#define KORINA_CONFIG4_ADDR	0x80000010
+#define KORINA_CONFIG5_ADDR	0x80000014
+#define KORINA_CONFIG6_ADDR	0x80000018
+#define KORINA_CONFIG7_ADDR	0x8000001C
+#define KORINA_CONFIG8_ADDR	0x80000020
+#define KORINA_CONFIG9_ADDR	0x80000024
+#define KORINA_CONFIG10_ADDR	0x80000028
+#define KORINA_CONFIG11_ADDR	0x8000002C
+#define KORINA_CONFIG12_ADDR	0x80000030
+#define KORINA_CONFIG13_ADDR	0x80000034
+#define KORINA_CONFIG14_ADDR	0x80000038
+#define KORINA_CONFIG15_ADDR	0x8000003C
+#define KORINA_CONFIG16_ADDR	0x80000040
+#define KORINA_CONFIG17_ADDR	0x80000044
+#define KORINA_CONFIG18_ADDR	0x80000048
+#define KORINA_CONFIG19_ADDR	0x8000004C
+#define KORINA_CONFIG20_ADDR	0x80000050
+#define KORINA_CONFIG21_ADDR	0x80000054
+#define KORINA_CONFIG22_ADDR	0x80000058
+#define KORINA_CONFIG23_ADDR	0x8000005C
+#define KORINA_CONFIG24_ADDR	0x80000060
+#define KORINA_CONFIG25_ADDR	0x80000064
+#define KORINA_CMD 		(PCFG04_command_ioena_m | \
+				 PCFG04_command_memena_m | \
+				 PCFG04_command_bmena_m | \
+				 PCFG04_command_mwinv_m | \
+				 PCFG04_command_parena_m | \
+				 PCFG04_command_serrena_m )
+
+#define KORINA_STAT		(PCFG04_status_mdpe_m | \
+				 PCFG04_status_sta_m  | \
+				 PCFG04_status_rta_m  | \
+				 PCFG04_status_rma_m  | \
+				 PCFG04_status_sse_m  | \
+				 PCFG04_status_pe_m)
+
+#define KORINA_CNFG1		((KORINA_STAT<<16)|KORINA_CMD)
+
+#define KORINA_REVID		0
+#define KORINA_CLASS_CODE	0
+#define KORINA_CNFG2		((KORINA_CLASS_CODE<<8) | \
+				  KORINA_REVID)
+
+#define KORINA_CACHE_LINE_SIZE	4
+#define KORINA_MASTER_LAT	0x3c
+#define KORINA_HEADER_TYPE	0
+#define KORINA_BIST		0
+
+#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
+		      (KORINA_HEADER_TYPE<<16) | \
+		      (KORINA_MASTER_LAT<<8) | \
+		      KORINA_CACHE_LINE_SIZE )
+
+#define KORINA_BAR0	0x00000008 /* 128 MB Memory */
+#define KORINA_BAR1	0x18800001 /* 1 MB IO */
+#define KORINA_BAR2	0x18000001 /* 2 MB IO window for Korina
+					internal Registers */
+#define KORINA_BAR3	0x48000008 /* Spare 128 MB Memory */
+
+#define KORINA_CNFG4	KORINA_BAR0
+#define KORINA_CNFG5    KORINA_BAR1
+#define KORINA_CNFG6 	KORINA_BAR2
+#define KORINA_CNFG7	KORINA_BAR3
+
+#define KORINA_SUBSYS_VENDOR_ID 0x011d
+#define KORINA_SUBSYSTEM_ID	0x0214
+#define KORINA_CNFG8		0
+#define KORINA_CNFG9		0
+#define KORINA_CNFG10		0
+#define KORINA_CNFG11 	((KORINA_SUBSYS_VENDOR_ID<<16) | \
+			  KORINA_SUBSYSTEM_ID)
+#define KORINA_INT_LINE		1
+#define KORINA_INT_PIN		1
+#define KORINA_MIN_GNT		8
+#define KORINA_MAX_LAT		0x38
+#define KORINA_CNFG12		0
+#define KORINA_CNFG13 		0
+#define KORINA_CNFG14		0
+#define KORINA_CNFG15	((KORINA_MAX_LAT<<24) | \
+			 (KORINA_MIN_GNT<<16) | \
+			 (KORINA_INT_PIN<<8)  | \
+			  KORINA_INT_LINE)
+#define	KORINA_RETRY_LIMIT	0x80
+#define KORINA_TRDY_LIMIT	0x80
+#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
+			KORINA_TRDY_LIMIT)
+#define PCI_PBAxC_R		0x0
+#define PCI_PBAxC_RL		0x1
+#define PCI_PBAxC_RM		0x2
+#define SIZE_SHFT		2
+
+#if defined(__MIPSEB__)
+#define KORINA_PBA0C	( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
+			  ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
+			  PCIPBAC_pp_m | \
+			  (SIZE_128MB<<SIZE_SHFT) | \
+			   PCIPBAC_p_m)
+#else
+#define KORINA_PBA0C	( PCIPBAC_mrl_m | \
+			  ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
+			  PCIPBAC_pp_m | \
+			  (SIZE_128MB<<SIZE_SHFT) | \
+			   PCIPBAC_p_m)
+#endif
+#define KORINA_CNFG17	KORINA_PBA0C
+#define KORINA_PBA0M	0x0
+#define KORINA_CNFG18	KORINA_PBA0M
+
+#if defined(__MIPSEB__)
+#define KORINA_PBA1C	((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
+			  PCIPBAC_msi_m)
+#else
+#define KORINA_PBA1C	((SIZE_1MB<<SIZE_SHFT) | \
+			  PCIPBAC_msi_m)
+#endif
+#define KORINA_CNFG19	KORINA_PBA1C
+#define KORINA_PBA1M	0x0
+#define KORINA_CNFG20	KORINA_PBA1M
+
+#if defined(__MIPSEB__)
+#define KORINA_PBA2C	((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
+			  PCIPBAC_msi_m)
+#else
+#define KORINA_PBA2C	((SIZE_2MB<<SIZE_SHFT) | \
+			  PCIPBAC_msi_m)
+#endif
+#define KORINA_CNFG21	KORINA_PBA2C
+#define KORINA_PBA2M	0x18000000
+#define KORINA_CNFG22	KORINA_PBA2M
+#define KORINA_PBA3C	0
+#define KORINA_CNFG23	KORINA_PBA3C
+#define KORINA_PBA3M	0
+#define KORINA_CNFG24	KORINA_PBA3M
+
+
+
+#define	PCITC_DTIMER_VAL	8
+#define PCITC_RTIMER_VAL	0x10
+
+
+
+
+#endif	// __IDT_PCI_H__
+
+
+
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_rst.h idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_rst.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_rst.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_rst.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,112 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Reset register definitions.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_RST_H__
+#define __IDT_RST_H__
+
+enum
+{
+	RST0_PhysicalAddress	= 0x18000000,
+	RST_PhysicalAddress	= RST0_PhysicalAddress,		// Default
+
+	RST0_VirtualAddress	= 0xb8000000,
+	RST_VirtualAddress	= RST0_VirtualAddress,		// Default
+} ;
+
+typedef struct RST_s
+{
+	u32	filler [0x0006] ;
+	u32	sysid ;
+	u32	filler2 [0x2000-8] ;		// Pad out to offset 0x8000
+	u32	reset ;
+	u32	bcv ;
+	u32	cea ;
+} volatile * RST_t ;
+
+enum
+{
+	SYSID_rev_b		= 0,
+	SYSID_rev_m		= 0x000000ff,
+	SYSID_imp_b		= 8,
+	SYSID_imp_m		= 0x000fff00,
+	SYSID_vendor_b		= 8,
+	SYSID_vendor_m		= 0xfff00000,
+
+	BCV_pll_b		= 0,
+	BCV_pll_m		= 0x0000000f,
+		BCV_pll_PLLBypass_v	= 0x0,	// PCLK=1*CLK.
+		BCV_pll_Mul3_v		= 0x1,	// PCLK=3*CLK.
+		BCV_pll_Mul4_v		= 0x2,	// PCLK=4*CLK.
+		BCV_pll_SlowMul5_v	= 0x3,	// PCLK=5*CLK.
+		BCV_pll_Mul5_v		= 0x4,	// PCLK=5*CLK.
+		BCV_pll_SlowMul6_v	= 0x5,	// PCLK=6*CLK.
+		BCV_pll_Mul6_v		= 0x6,	// PCLK=6*CLK.
+		BCV_pll_Mul8_v		= 0x7,	// PCLK=8*CLK.
+		BCV_pll_Mul10_v		= 0x8,	// PCLK=10*CLK.
+	        BCV_pll_Res9_v	        = 0x9,
+		BCV_pll_Res10_v	        = 0xa,
+		BCV_pll_Res11_v	        = 0xb,
+		BCV_pll_Res12_v	        = 0xc,
+		BCV_pll_Res13_v		= 0xd,
+		BCV_pll_Res14_v		= 0xe,
+		BCV_pll_Res15_v		= 0xf,
+	BCV_clkDiv_b		= 4,
+	BCV_clkDiv_m		= 0x00000030,
+		BCV_clkDiv_Div1_v	= 0x0,
+		BCV_clkDiv_Div2_v	= 0x1,
+		BCV_clkDiv_Div4_v	= 0x2,
+		BCV_clkDiv_Res3_v	= 0x3,
+	BCV_bigEndian_b		= 6,
+	BCV_bigEndian_m		= 0x00000040,
+	BCV_resetFast_b		= 7,
+	BCV_resetFast_m		= 0x00000080,
+	BCV_pciMode_b		= 8,
+	BCV_pciMode_m		= 0x00000700,
+		BCV_pciMode_disabled_v	= 0,	// PCI is disabled.
+		BCV_pciMode_tnr_v	= 1,	// satellite Target Not Ready.
+		BCV_pciMode_suspended_v	= 2,	// satellite with suspended CPU.
+		BCV_pciMode_external_v	= 3,	// host, external arbiter.
+		BCV_pciMode_fixed_v	= 4,	// host, fixed priority arbiter.
+		BCV_pciMode_roundRobin_v= 5,	// host, round robin arbiter.
+		BCV_pciMode_res6_v	= 6,
+		BCV_pciMode_res7_v	= 7,
+	BCV_watchDisable_b	= 11,
+	BCV_watchDisable_m	= 0x00000800,
+	BCV_res12_b		= 12,
+	BCV_res12_m		= 0x00001000,
+	BCV_res13_b		= 13,
+	BCV_res13_m		= 0x00002000,
+	BCV_res14_b		= 14,
+	BCV_res14_m		= 0x00004000,
+	BCV_res15_b		= 15,
+	BCV_res15_m		= 0x00008000,
+} ;
+#endif	// __IDT_RST_H__
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_spi.h idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_spi.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_spi.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_spi.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,113 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Serial Peripheral Interface register definitions.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_SPI_H__
+#define __IDT_SPI_H__
+
+enum
+{
+	SPI0_PhysicalAddress	= 0x18070000,
+	SPI_PhysicalAddress	= SPI0_PhysicalAddress,
+
+	SPI0_VirtualAddress	= 0xB8070000,
+	SPI_VirtualAddress	= SPI0_VirtualAddress,
+} ;
+
+typedef struct
+{
+	u32 spcp ;	// prescalar. 0=off, * spiClk = sysClk/(2*(spcp+1)*SPR)
+	u32 spc ;	// spi control reg use SPC_
+	u32 sps ;	// spi status reg use SPS_
+	u32 spd ;	// spi data reg use SPD_
+	u32 siofunc ;	// serial IO function use SIOFUNC_
+	u32 siocfg ;	// serial IO config use SIOCFG_
+	u32 siod;	// serial IO data use SIOD_
+} volatile *SPI_t ;
+
+enum
+{
+	SPCP_div_b	 = 0,	       
+	SPCP_div_m	 = 0x000000ff,
+	SPC_spr_b	= 0,	       
+	SPC_spr_m	= 0x00000003,
+	     SPC_spr_div2_v  = 0,
+	     SPC_spr_div4_v  = 1,
+	     SPC_spr_div16_v = 2,
+	     SPC_spr_div32_v = 3,
+	SPC_cpha_b	= 2,	       
+	SPC_cpha_m	= 0x00000004,
+	SPC_cpol_b	= 3,	       
+	SPC_cpol_m	= 0x00000008,
+	SPC_mstr_b	= 4,	       
+	SPC_mstr_m	= 0x00000010,
+	SPC_spe_b	= 6,	       
+	SPC_spe_m	= 0x00000040,
+	SPC_spie_b	= 7,	       
+	SPC_spie_m	= 0x00000080,
+
+	SPS_modf_b	= 4,	       
+	SPS_modf_m	= 0x00000010,
+	SPS_wcol_b	= 6,	       
+	SPS_wcol_m	= 0x00000040,
+	SPS_spif_b	= 7,	       
+	SPS_spif_m	= 0x00000070,
+
+	SPD_data_b	= 0,	       
+	SPD_data_m	= 0x000000ff,
+
+	SIOFUNC_sdo_b	    = 0,	   
+	SIOFUNC_sdo_m	    = 0x00000001,
+	SIOFUNC_sdi_b	    = 1,	   
+	SIOFUNC_sdi_m	    = 0x00000002,
+	SIOFUNC_sck_b	    = 2,	   
+	SIOFUNC_sck_m	    = 0x00000004,
+	SIOFUNC_pci_b	    = 3,	   
+	SIOFUNC_pci_m	    = 0x00000008,
+	
+	SIOCFG_sdo_b	   = 0, 	   
+	SIOCFG_sdo_m	   = 0x00000001,
+	SIOCFG_sdi_b	   = 1, 	   
+	SIOCFG_sdi_m	   = 0x00000002,
+	SIOCFG_sck_b	   = 2, 	   
+	SIOCFG_sck_m	   = 0x00000004,
+	SIOCFG_pci_b	   = 3, 	   
+	SIOCFG_pci_m	   = 0x00000008,
+	
+	SIOD_sdo_b	 = 0,		 
+	SIOD_sdo_m	 = 0x00000001,
+	SIOD_sdi_b	 = 1,		 
+	SIOD_sdi_m	 = 0x00000002,
+	SIOD_sck_b	 = 2,		 
+	SIOD_sck_m	 = 0x00000004,
+	SIOD_pci_b	 = 3,		 
+	SIOD_pci_m	 = 0x00000008,
+} ;
+#endif	// __IDT_SPI_H__
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_timer.h idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_timer.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_timer.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_timer.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,84 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Definitions for timer registers
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_TIM_H__
+#define __IDT_TIM_H__
+
+enum
+{
+	TIM0_PhysicalAddress	= 0x18028000,
+	TIM_PhysicalAddress	= TIM0_PhysicalAddress,		// Default
+
+	TIM0_VirtualAddress	= 0xb8028000,
+	TIM_VirtualAddress	= TIM0_VirtualAddress,		// Default
+} ;
+
+enum
+{
+	TIM_Count = 3,
+} ;
+
+struct TIM_CNTR_s
+{
+  u32 count ;
+  u32 compare ;
+  u32 ctc ;	//use CTC_
+} ;
+
+typedef struct TIM_s
+{
+  struct TIM_CNTR_s	tim [TIM_Count] ;
+  u32			rcount ;	//use RCOUNT_
+  u32			rcompare ;	//use RCOMPARE_
+  u32			rtc ;		//use RTC_
+} volatile * TIM_t ;
+
+enum
+{
+  CTC_en_b	= 0,		
+  CTC_en_m	= 0x00000001,
+  CTC_to_b	= 1,		 
+  CTC_to_m	= 0x00000002,
+  
+  RCOUNT_count_b		= 0,	     
+  RCOUNT_count_m		= 0x0000ffff,
+  RCOMPARE_compare_b	= 0,	   
+  RCOMPARE_compare_m	= 0x0000ffff,
+  RTC_ce_b		= 0,		
+  RTC_ce_m		= 0x00000001,
+  RTC_to_b		= 1,		
+  RTC_to_m		= 0x00000002,
+  RTC_rqe_b		= 2,		
+  RTC_rqe_m		= 0x00000004,
+  
+} ;
+#endif	// __IDT_TIM_H__
+
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_uart.h idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_uart.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32434/rc32434_uart.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32434/rc32434_uart.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,182 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   UART register definitions
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_UART_H__
+#define __IDT_UART_H__
+
+enum
+{
+	UART0_PhysicalAddress	= 0x18058000,
+	UART_PhysicalAddress	= UART0_PhysicalAddress,	// Default
+
+	UART0_VirtualAddress	= 0xb8058000,
+	UART_VirtualAddress	= UART0_VirtualAddress,		// Default
+} ;
+
+/*
+ * Register definitions are in bytes so we can handle endian problems.
+ */
+
+typedef struct UART_s
+{
+	union
+	{
+		u32 const	uartrb ;	// 0x00 - DLAB=0, read.
+		u32		uartth ;	// 0x00 - DLAB=0, write.
+		u32		uartdll ;	// 0x00 - DLAB=1, read/write.
+	} ;
+
+	union
+	{
+		u32		uartie ;	// 0x04 - DLAB=0, read/write.
+		u32		uartdlh ;	// 0x04 - DLAB=1, read/write.
+	} ;
+	union
+	{
+		u32 const	uartii ;	// 0x08 - DLAB=0, read.
+		u32		uartfc ;	// 0x08 - DLAB=0, write.
+	} ;
+
+	u32		uartlc ;		// 0x0c
+	u32		uartmc ;		// 0x10
+	u32		uartls ;		// 0x14
+	u32		uartms ;		// 0x18
+	u32		uarts ;			// 0x1c
+} volatile *UART_t ;
+
+// Reset registers.
+typedef u32	volatile *UARTRR_t ;
+
+enum
+{
+	UARTIE_rda_b	= 0,
+	UARTIE_rda_m	= 0x00000001,
+	UARTIE_the_b	= 1,
+	UARTIE_the_m	= 0x00000002,
+	UARTIE_rls_b	= 2,
+	UARTIE_rls_m	= 0x00000004,
+	UARTIE_ems_b	= 3,
+	UARTIE_ems_m	= 0x00000008,
+
+	UARTII_pi_b	= 0,
+	UARTII_pi_m	= 0x00000001,
+	UARTII_iid_b	= 1,
+	UARTII_iid_m	= 0x0000000e,
+		UARTII_iid_ms_v		= 0,	// Modem stat-CTS,DSR,RI or DCD.
+		UARTII_iid_thre_v	= 1,	// Trans. Holding Reg. empty.
+		UARTII_iid_rda_v	= 2,	// Receive data available
+		UARTII_iid_rls_v	= 3,	// Overrun, parity, etc, error.
+		UARTII_iid_res4_v	= 4,	// reserved.
+		UARTII_iid_res5_v	= 5,	// reserved.
+		UARTII_iid_cto_v	= 6,	// Character timeout.
+		UARTII_iid_res7_v	= 7,	// reserved.
+
+	UARTFC_en_b	= 0,
+	UARTFC_en_m	= 0x00000001,
+	UARTFC_rr_b	= 1,
+	UARTFC_rr_m	= 0x00000002,
+	UARTFC_tr_b	= 2,
+	UARTFC_tr_m	= 0x00000004,
+	UARTFC_dms_b	= 3,
+	UARTFC_dms_m	= 0x00000008,
+	UARTFC_rt_b	= 6,
+	UARTFC_rt_m	= 0x000000c0,
+		UARTFC_rt_1Byte_v	= 0,
+		UARTFC_rt_4Byte_v	= 1,
+		UARTFC_rt_8Byte_v	= 2,
+		UARTFC_rt_14Byte_v	= 3,
+
+	UARTLC_wls_b	= 0,
+	UARTLC_wls_m	= 0x00000003,
+		UARTLC_wls_5Bits_v	= 0,
+		UARTLC_wls_6Bits_v	= 1,
+		UARTLC_wls_7Bits_v	= 2,
+		UARTLC_wls_8Bits_v	= 3,
+	UARTLC_stb_b	= 2,
+	UARTLC_stb_m	= 0x00000004,
+	UARTLC_pen_b	= 3,
+	UARTLC_pen_m	= 0x00000008,
+	UARTLC_eps_b	= 4,
+	UARTLC_eps_m	= 0x00000010,
+	UARTLC_sp_b	= 5,
+	UARTLC_sp_m	= 0x00000020,
+	UARTLC_sb_b	= 6,
+	UARTLC_sb_m	= 0x00000040,
+	UARTLC_dlab_b	= 7,
+	UARTLC_dlab_m	= 0x00000080,
+
+	UARTMC_dtr_b	= 0,
+	UARTMC_dtr_m	= 0x00000001,
+	UARTMC_rts_b	= 1,
+	UARTMC_rts_m	= 0x00000002,
+	UARTMC_o1_b	= 2,
+	UARTMC_o1_m	= 0x00000004,
+	UARTMC_o2_b	= 3,
+	UARTMC_o2_m	= 0x00000008,
+	UARTMC_lp_b	= 4,
+	UARTMC_lp_m	= 0x00000010,
+
+	UARTLS_dr_b	= 0,
+	UARTLS_dr_m	= 0x00000001,
+	UARTLS_oe_b	= 1,
+	UARTLS_oe_m	= 0x00000002,
+	UARTLS_pe_b	= 2,
+	UARTLS_pe_m	= 0x00000004,
+	UARTLS_fe_b	= 3,
+	UARTLS_fe_m	= 0x00000008,
+	UARTLS_bi_b	= 4,
+	UARTLS_bi_m	= 0x00000010,
+	UARTLS_thr_b	= 5,
+	UARTLS_thr_m	= 0x00000020,
+	UARTLS_te_b	= 6,
+	UARTLS_te_m	= 0x00000040,
+	UARTLS_rfe_b	= 7,
+	UARTLS_rfe_m	= 0x00000080,
+
+	UARTMS_dcts_b	= 0,
+	UARTMS_dcts_m	= 0x00000001,
+	UARTMS_ddsr_b	= 1,
+	UARTMS_ddsr_m	= 0x00000002,
+	UARTMS_teri_b	= 2,
+	UARTMS_teri_m	= 0x00000004,
+	UARTMS_ddcd_b	= 3,
+	UARTMS_ddcd_m	= 0x00000008,
+	UARTMS_cts_b	= 4,
+	UARTMS_cts_m	= 0x00000010,
+	UARTMS_dsr_b	= 5,
+	UARTMS_dsr_m	= 0x00000020,
+	UARTMS_ri_b	= 6,
+	UARTMS_ri_m	= 0x00000040,
+	UARTMS_dcd_b	= 7,
+	UARTMS_dcd_m	= 0x00000080,
+} ;
+
+#endif	// __IDT_UART_H__
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32438/rc32438_dma.h idtlinux/include/asm-mips/idt-boards/rc32438/rc32438_dma.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32438/rc32438_dma.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32438/rc32438_dma.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,224 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Register definitions for  IDT RC32438 DMA.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+#ifndef __IDT_RC32438_DMA_H__
+#define __IDT_RC32438_DMA_H__
+enum
+{
+	DMA0_PhysicalAddress	= 0x18040000,
+	DMA_PhysicalAddress	= DMA0_PhysicalAddress,		// Default
+
+	DMA0_VirtualAddress	= 0xb8040000,
+	DMA_VirtualAddress	= DMA0_VirtualAddress,		// Default
+} ;
+
+/*
+ * DMA descriptor (in physical memory).
+ */
+
+typedef struct DMAD_s
+{
+	u32			control ;	// Control. use DMAD_*
+	u32			ca ;		// Current Address.
+	u32			devcs ; 	// Device control and status.
+	u32			link ;		// Next descriptor in chain.
+} volatile *DMAD_t ;
+
+enum
+{
+	DMAD_size		= sizeof (struct DMAD_s),
+	DMAD_count_b		= 0,		// in DMAD_t -> control
+	DMAD_count_m		= 0x0003ffff,	// in DMAD_t -> control
+	DMAD_ds_b		= 20,		// in DMAD_t -> control
+	DMAD_ds_m		= 0x00300000,	// in DMAD_t -> control
+		DMAD_ds_extToMem0_v	= 0,
+		DMAD_ds_memToExt0_v	= 1,
+		DMAD_ds_extToMem1_v	= 0,
+		DMAD_ds_memToExt1_v	= 1,
+		DMAD_ds_ethRcv0_v	= 0,
+		DMAD_ds_ethXmt0_v	= 0,
+		DMAD_ds_ethRcv1_v	= 0,
+		DMAD_ds_ethXmt2_v	= 0,
+		DMAD_ds_memToFifo_v	= 0,
+		DMAD_ds_fifoToMem_v	= 0,
+		DMAD_ds_rng_de_v	   = 1,//randomNumberGenerator on LC/DE
+		DMAD_ds_pciToMem_v	= 0,
+		DMAD_ds_memToPci_v	= 0,
+		DMAD_ds_securityInput_v = 0,
+		DMAD_ds_securityOutput_v = 0,
+		DMAD_ds_rng_se_v	= 0,//randomNumberGenerator on SE
+	
+	DMAD_devcmd_b		= 22,		// in DMAD_t -> control
+	DMAD_devcmd_m		= 0x01c00000,	// in DMAD_t -> control
+		DMAD_devcmd_byte_v	= 0,	//memory-to-memory
+		DMAD_devcmd_halfword_v	= 1,	//memory-to-memory
+		DMAD_devcmd_word_v	= 2,	//memory-to-memory
+		DMAD_devcmd_2words_v	= 3,	//memory-to-memory
+		DMAD_devcmd_4words_v	= 4,	//memory-to-memory
+		DMAD_devcmd_6words_v	= 5,	//memory-to-memory
+		DMAD_devcmd_8words_v	= 6,	//memory-to-memory
+		DMAD_devcmd_16words_v	= 7,	//memory-to-memory
+	DMAD_cof_b		= 25,		// chain on finished
+	DMAD_cof_m		= 0x02000000,	// 
+	DMAD_cod_b		= 26,		// chain on done
+	DMAD_cod_m		= 0x04000000,	// 
+	DMAD_iof_b		= 27,		// interrupt on finished
+	DMAD_iof_m		= 0x08000000,	// 
+	DMAD_iod_b		= 28,		// interrupt on done
+	DMAD_iod_m		= 0x10000000,	// 
+	DMAD_t_b		= 29,		// terminated
+	DMAD_t_m		= 0x20000000,	// 
+	DMAD_d_b		= 30,		// done
+	DMAD_d_m		= 0x40000000,	// 
+	DMAD_f_b		= 31,		// finished
+	DMAD_f_m		= 0x80000000,	// 
+} ;
+
+/*
+ * DMA register (within Internal Register Map).
+ */
+
+struct DMA_Chan_s
+{
+	u32		dmac ;		// Control.
+	u32		dmas ;		// Status.	
+	u32		dmasm ; 	// Mask.
+	u32		dmadptr ;	// Descriptor pointer.
+	u32		dmandptr ;	// Next descriptor pointer.
+};
+
+typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
+
+//DMA_Channels	  use DMACH_count instead
+
+enum
+{
+	DMAC_run_b	= 0,		// 
+	DMAC_run_m	= 0x00000001,	// 
+	DMAC_dm_b	= 1,		// done mask
+	DMAC_dm_m	= 0x00000002,	// 
+	DMAC_mode_b	= 2,		// 
+	DMAC_mode_m	= 0x0000000c,	// 
+		DMAC_mode_auto_v	= 0,
+		DMAC_mode_burst_v	= 1,
+		DMAC_mode_transfer_v	= 2, //usually used
+		DMAC_mode_reserved_v	= 3,
+	DMAC_a_b	= 4,		// 
+	DMAC_a_m	= 0x00000010,	// 
+
+	DMAS_f_b	= 0,		// finished (sticky) 
+	DMAS_f_m	= 0x00000001,	//		     
+	DMAS_d_b	= 1,		// done (sticky)     
+	DMAS_d_m	= 0x00000002,	//		     
+	DMAS_c_b	= 2,		// chain (sticky)    
+	DMAS_c_m	= 0x00000004,	//		     
+	DMAS_e_b	= 3,		// error (sticky)    
+	DMAS_e_m	= 0x00000008,	//		     
+	DMAS_h_b	= 4,		// halt (sticky)     
+	DMAS_h_m	= 0x00000010,	//		     
+
+	DMASM_f_b	= 0,		// finished (1=mask)
+	DMASM_f_m	= 0x00000001,	// 
+	DMASM_d_b	= 1,		// done (1=mask)
+	DMASM_d_m	= 0x00000002,	// 
+	DMASM_c_b	= 2,		// chain (1=mask)
+	DMASM_c_m	= 0x00000004,	// 
+	DMASM_e_b	= 3,		// error (1=mask)
+	DMASM_e_m	= 0x00000008,	// 
+	DMASM_h_b	= 4,		// halt (1=mask)
+	DMASM_h_m	= 0x00000010,	// 
+} ;
+
+/*
+ * DMA channel definitions
+ */
+
+enum
+{
+	DMACH_extToMem0 = 0,
+	DMACH_memToExt0 = 0,
+	DMACH_extToMem1 = 1,
+	DMACH_memToExt1 = 1,
+	DMACH_ethRcv0 = 2,
+	DMACH_ethXmt0 = 3,
+	DMACH_ethRcv1 = 4,
+	DMACH_ethXmt2 = 5,
+	DMACH_memToFifo = 6,
+	DMACH_fifoToMem = 7,
+	DMACH_rng_de = 7,//randomNumberGenerator on LC/DE
+	DMACH_pciToMem = 8,
+	DMACH_memToPci = 9,
+	DMACH_securityInput = 10,
+	DMACH_securityOutput = 11,
+	DMACH_rng_se = 12, //randomNumberGenerator on SE
+	
+	DMACH_count //must be last
+};
+
+
+typedef struct DMAC_s
+{
+	struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
+} volatile *DMA_t ;
+
+
+/*
+ * External DMA parameters
+*/
+
+enum
+{
+	DMADEVCMD_ts_b	= 0,		// ts field in devcmd
+	DMADEVCMD_ts_m	= 0x00000007,	// ts field in devcmd
+		DMADEVCMD_ts_byte_v	= 0,
+		DMADEVCMD_ts_halfword_v	= 1,
+		DMADEVCMD_ts_word_v	= 2,
+		DMADEVCMD_ts_2word_v	= 3,
+		DMADEVCMD_ts_4word_v	= 4,
+		DMADEVCMD_ts_6word_v	= 5,
+		DMADEVCMD_ts_8word_v	= 6,
+		DMADEVCMD_ts_16word_v	= 7
+};
+
+
+#if 1	// aws - Compatibility.
+#	define	EXTDMA_ts_b		DMADEVCMD_ts_b
+#	define	EXTDMA_ts_m		DMADEVCMD_ts_m
+#	define	EXTDMA_ts_byte_v	DMADEVCMD_ts_byte_v
+#	define	EXTDMA_ts_halfword_v	DMADEVCMD_ts_halfword_v
+#	define	EXTDMA_ts_word_v	DMADEVCMD_ts_word_v
+#	define	EXTDMA_ts_2word_v	DMADEVCMD_ts_2word_v
+#	define	EXTDMA_ts_4word_v	DMADEVCMD_ts_4word_v
+#	define	EXTDMA_ts_6word_v	DMADEVCMD_ts_6word_v
+#	define	EXTDMA_ts_8word_v	DMADEVCMD_ts_8word_v
+#	define	EXTDMA_ts_16word_v	DMADEVCMD_ts_16word_v
+#endif	// aws - Compatibility.
+
+#endif //__IDT_RC32438_DMA_H__
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h idtlinux/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,76 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   DMA operations for IDT RC32438.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_RC32438_DMA_V_H__
+#define __IDT_RC32438_DMA_V_H__
+#include  <asm/idt-boards/rc32438/rc32438_dma.h> 
+
+#define DMA_CHAN_OFFSET  0x14
+#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
+#define DMA_COUNT(count)   \
+  ((count) & DMAD_count_m)
+
+#define DMA_HALT_TIMEOUT 500
+
+
+static inline int rc32438_halt_dma(DMA_Chan_t ch)
+{
+	int timeout=1;
+	if (rc32438_readl(&ch->dmac) & DMAC_run_m) {
+		rc32438_writel(0, &ch->dmac); 
+		
+		for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
+			if (rc32438_readl(&ch->dmas) & DMAS_h_m) {
+				rc32438_writel(0, &ch->dmas);  
+				break;
+			}
+		}
+
+	}
+	
+	return timeout ? 0 : 1;
+}
+
+
+
+
+static inline void rc32438_start_dma(DMA_Chan_t ch, u32 dma_addr)
+{
+	rc32438_writel(0, &ch->dmandptr); 
+	rc32438_writel(dma_addr, &ch->dmadptr);
+}
+
+static inline void rc32438_chain_dma(DMA_Chan_t ch, u32 dma_addr)
+{
+	rc32438_writel(dma_addr, &ch->dmandptr);
+}
+#endif //__IDT_RC32438_DMA_V_H__
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32438/rc32438_eth.h idtlinux/include/asm-mips/idt-boards/rc32438/rc32438_eth.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32438/rc32438_eth.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32438/rc32438_eth.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,321 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Definitions for IDT EB438 ethernet
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_RC32438_ETH_H__
+#define __IDT_RC32438_ETH_H__
+enum
+{
+	ETH0_PhysicalAddress	= 0x18058000,
+	ETH_PhysicalAddress	= ETH0_PhysicalAddress,		// Default
+
+	ETH0_VirtualAddress	= 0xb8058000,
+	ETH_VirtualAddress	= ETH0_VirtualAddress,		// Default
+	ETH1_PhysicalAddress	= 0x18060000,
+	ETH1_VirtualAddress	= 0xb8060000,			// Default
+} ;
+
+typedef struct
+{
+	u32 ethintfc		;
+	u32 ethfifott		;
+	u32 etharc		;
+	u32 ethhash0		;
+	u32 ethhash1		;
+	u32 ethu0 [4]		;	// Reserved.	
+	u32 ethpfs		;
+	u32 ethmcp		;
+	u32 eth_u1 [10]		;	// Reserved.
+	u32 ethspare		;
+	u32 eth_u2 [42]		;	// Reserved. 
+	u32 ethsal0		;
+	u32 ethsah0		;
+	u32 ethsal1		;
+	u32 ethsah1		;
+	u32 ethsal2		;
+	u32 ethsah2		;
+	u32 ethsal3		;
+	u32 ethsah3		;
+	u32 ethrbc		;
+	u32 ethrpc		;
+	u32 ethrupc		;
+	u32 ethrfc		;
+	u32 ethtbc		;
+	u32 ethgpf		;
+	u32 eth_u9 [50]		;	// Reserved.	
+	u32 ethmac1		;
+	u32 ethmac2		;
+	u32 ethipgt		;
+	u32 ethipgr		;
+	u32 ethclrt		;
+	u32 ethmaxf		;
+	u32 eth_u10		;	// Reserved.	
+	u32 ethmtest		;
+	u32 miimcfg		;
+	u32 miimcmd		;
+	u32 miimaddr		;
+	u32 miimwtd		;
+	u32 miimrdd		;
+	u32 miimind		;
+	u32 eth_u11		;	// Reserved.
+	u32 eth_u12		;	// Reserved.
+	u32 ethcfsa0		;
+	u32 ethcfsa1		;
+	u32 ethcfsa2		;
+} volatile *ETH_t;
+
+enum
+{
+	ETHINTFC_en_b		= 0,
+	ETHINTFC_en_m		= 0x00000001,
+	ETHINTFC_its_b		= 1,
+	ETHINTFC_its_m		= 0x00000002,
+	ETHINTFC_rip_b		= 2,
+	ETHINTFC_rip_m		= 0x00000004,
+	ETHINTFC_jam_b		= 3,
+	ETHINTFC_jam_m		= 0x00000008,
+	ETHINTFC_ovr_b		= 4,
+	ETHINTFC_ovr_m		= 0x00000010,
+	ETHINTFC_und_b		= 5,
+	ETHINTFC_und_m		= 0x00000020,
+
+	ETHFIFOTT_tth_b		= 0,
+	ETHFIFOTT_tth_m		= 0x0000007f,
+
+	ETHARC_pro_b		= 0,
+	ETHARC_pro_m		= 0x00000001,
+	ETHARC_am_b		= 1,
+	ETHARC_am_m		= 0x00000002,
+	ETHARC_afm_b		= 2,
+	ETHARC_afm_m		= 0x00000004,
+	ETHARC_ab_b		= 3,
+	ETHARC_ab_m		= 0x00000008,
+
+	ETHSAL_byte5_b		= 0,
+	ETHSAL_byte5_m		= 0x000000ff,
+	ETHSAL_byte4_b		= 8,
+	ETHSAL_byte4_m		= 0x0000ff00,
+	ETHSAL_byte3_b		= 16,
+	ETHSAL_byte3_m		= 0x00ff0000,
+	ETHSAL_byte2_b		= 24,
+	ETHSAL_byte2_m		= 0xff000000,
+
+	ETHSAH_byte1_b		= 0,
+	ETHSAH_byte1_m		= 0x000000ff,
+	ETHSAH_byte0_b		= 8,
+	ETHSAH_byte0_m		= 0x0000ff00,
+	
+	ETHGPF_ptv_b		= 0,
+	ETHGPF_ptv_m		= 0x0000ffff,
+
+	ETHPFS_pfd_b		= 0,
+	ETHPFS_pfd_m		= 0x00000001,
+
+	ETHCFSA0_cfsa4_b	= 0,
+	ETHCFSA0_cfsa4_m	= 0x000000ff,
+	ETHCFSA0_cfsa5_b	= 8,
+	ETHCFSA0_cfsa5_m	= 0x0000ff00,
+
+	ETHCFSA1_cfsa2_b	= 0,
+	ETHCFSA1_cfsa2_m	= 0x000000ff,
+	ETHCFSA1_cfsa3_b	= 8,
+	ETHCFSA1_cfsa3_m	= 0x0000ff00,
+
+	ETHCFSA2_cfsa0_b	= 0,
+	ETHCFSA2_cfsa0_m	= 0x000000ff,
+	ETHCFSA2_cfsa1_b	= 8,
+	ETHCFSA2_cfsa1_m	= 0x0000ff00,
+
+	ETHMAC1_re_b		= 0,
+	ETHMAC1_re_m		= 0x00000001,
+	ETHMAC1_paf_b		= 1,
+	ETHMAC1_paf_m		= 0x00000002,
+	ETHMAC1_rfc_b		= 2,
+	ETHMAC1_rfc_m		= 0x00000004,
+	ETHMAC1_tfc_b		= 3,
+	ETHMAC1_tfc_m		= 0x00000008,
+	ETHMAC1_lb_b		= 4,
+	ETHMAC1_lb_m		= 0x00000010,
+	ETHMAC1_mr_b		= 31,
+	ETHMAC1_mr_m		= 0x80000000,
+
+	ETHMAC2_fd_b		= 0,
+	ETHMAC2_fd_m		= 0x00000001,
+	ETHMAC2_flc_b		= 1,
+	ETHMAC2_flc_m		= 0x00000002,
+	ETHMAC2_hfe_b		= 2,
+	ETHMAC2_hfe_m		= 0x00000004,
+	ETHMAC2_dc_b		= 3,
+	ETHMAC2_dc_m		= 0x00000008,
+	ETHMAC2_cen_b		= 4,
+	ETHMAC2_cen_m		= 0x00000010,
+	ETHMAC2_pe_b		= 5,
+	ETHMAC2_pe_m		= 0x00000020,
+	ETHMAC2_vpe_b		= 6,
+	ETHMAC2_vpe_m		= 0x00000040,
+	ETHMAC2_ape_b		= 7,
+	ETHMAC2_ape_m		= 0x00000080,
+	ETHMAC2_ppe_b		= 8,
+	ETHMAC2_ppe_m		= 0x00000100,
+	ETHMAC2_lpe_b		= 9,
+	ETHMAC2_lpe_m		= 0x00000200,
+	ETHMAC2_nb_b		= 12,
+	ETHMAC2_nb_m		= 0x00001000,
+	ETHMAC2_bp_b		= 13,
+	ETHMAC2_bp_m		= 0x00002000,
+	ETHMAC2_ed_b		= 14,
+	ETHMAC2_ed_m		= 0x00004000,
+
+	ETHIPGT_ipgt_b		= 0,
+	ETHIPGT_ipgt_m		= 0x0000007f,
+
+	ETHIPGR_ipgr2_b		= 0,
+	ETHIPGR_ipgr2_m		= 0x0000007f,
+	ETHIPGR_ipgr1_b		= 8,
+	ETHIPGR_ipgr1_m		= 0x00007f00,
+
+	ETHCLRT_maxret_b	= 0,
+	ETHCLRT_maxret_m	= 0x0000000f,
+	ETHCLRT_colwin_b	= 8,
+	ETHCLRT_colwin_m	= 0x00003f00,
+
+	ETHMAXF_maxf_b		= 0,
+	ETHMAXF_maxf_m		= 0x0000ffff,
+
+	ETHMTEST_tb_b		= 2,
+	ETHMTEST_tb_m		= 0x00000004,
+
+	ETHMCP_div_b		= 0,
+	ETHMCP_div_m		= 0x000000ff,
+	
+	MIIMCFG_rsv_b		= 0,
+	MIIMCFG_rsv_m		= 0x0000000c,
+
+	MIIMCMD_rd_b		= 0,
+	MIIMCMD_rd_m		= 0x00000001,
+	MIIMCMD_scn_b		= 1,
+	MIIMCMD_scn_m		= 0x00000002,
+
+	MIIMADDR_regaddr_b	= 0,
+	MIIMADDR_regaddr_m	= 0x0000001f,
+	MIIMADDR_phyaddr_b	= 8,
+	MIIMADDR_phyaddr_m	= 0x00001f00,
+
+	MIIMWTD_wdata_b		= 0,
+	MIIMWTD_wdata_m		= 0x0000ffff,
+
+	MIIMRDD_rdata_b		= 0,
+	MIIMRDD_rdata_m		= 0x0000ffff,
+
+	MIIMIND_bsy_b		= 0,
+	MIIMIND_bsy_m		= 0x00000001,
+	MIIMIND_scn_b		= 1,
+	MIIMIND_scn_m		= 0x00000002,
+	MIIMIND_nv_b		= 2,
+	MIIMIND_nv_m		= 0x00000004,
+
+} ;
+
+/*
+ * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
+ */
+enum
+{
+	ETHRX_fd_b		= 0,
+	ETHRX_fd_m		= 0x00000001,
+	ETHRX_ld_b		= 1,
+	ETHRX_ld_m		= 0x00000002,
+	ETHRX_rok_b		= 2,
+	ETHRX_rok_m		= 0x00000004,
+	ETHRX_fm_b		= 3,
+	ETHRX_fm_m		= 0x00000008,
+	ETHRX_mp_b		= 4,
+	ETHRX_mp_m		= 0x00000010,
+	ETHRX_bp_b		= 5,
+	ETHRX_bp_m		= 0x00000020,
+	ETHRX_vlt_b		= 6,
+	ETHRX_vlt_m		= 0x00000040,
+	ETHRX_cf_b		= 7,
+	ETHRX_cf_m		= 0x00000080,
+	ETHRX_ovr_b		= 8,
+	ETHRX_ovr_m		= 0x00000100,
+	ETHRX_crc_b		= 9,
+	ETHRX_crc_m		= 0x00000200,
+	ETHRX_cv_b		= 10,
+	ETHRX_cv_m		= 0x00000400,
+	ETHRX_db_b		= 11,
+	ETHRX_db_m		= 0x00000800,
+	ETHRX_le_b		= 12,
+	ETHRX_le_m		= 0x00001000,
+	ETHRX_lor_b		= 13,
+	ETHRX_lor_m		= 0x00002000,
+	ETHRX_ces_b		= 14,
+	ETHRX_ces_m		= 0x00004000,
+	ETHRX_length_b		= 16,
+	ETHRX_length_m		= 0xffff0000,
+
+	ETHTX_fd_b		= 0,
+	ETHTX_fd_m		= 0x00000001,
+	ETHTX_ld_b		= 1,
+	ETHTX_ld_m		= 0x00000002,
+	ETHTX_oen_b		= 2,
+	ETHTX_oen_m		= 0x00000004,
+	ETHTX_pen_b		= 3,
+	ETHTX_pen_m		= 0x00000008,
+	ETHTX_cen_b		= 4,
+	ETHTX_cen_m		= 0x00000010,
+	ETHTX_hen_b		= 5,
+	ETHTX_hen_m		= 0x00000020,
+	ETHTX_tok_b		= 6,
+	ETHTX_tok_m		= 0x00000040,
+	ETHTX_mp_b		= 7,
+	ETHTX_mp_m		= 0x00000080,
+	ETHTX_bp_b		= 8,
+	ETHTX_bp_m		= 0x00000100,
+	ETHTX_und_b		= 9,
+	ETHTX_und_m		= 0x00000200,
+	ETHTX_of_b		= 10,
+	ETHTX_of_m		= 0x00000400,
+	ETHTX_ed_b		= 11,
+	ETHTX_ed_m		= 0x00000800,
+	ETHTX_ec_b		= 12,
+	ETHTX_ec_m		= 0x00001000,
+	ETHTX_lc_b		= 13,
+	ETHTX_lc_m		= 0x00002000,
+	ETHTX_td_b		= 14,
+	ETHTX_td_m		= 0x00004000,
+	ETHTX_crc_b		= 15,
+	ETHTX_crc_m		= 0x00008000,
+	ETHTX_le_b		= 16,
+	ETHTX_le_m		= 0x00010000,
+	ETHTX_cc_b		= 17,
+	ETHTX_cc_m		= 0x001E0000,
+} ;
+#endif //__IDT_RC32438_ETH_H__
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h idtlinux/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,64 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   macros for IDT EB438 ethernet
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_RC32438_ETH_V_H__
+#define __IDT_RC32438_ETH_V_H__
+#include  <asm/idt-boards/rc32438/rc32438_eth.h> 
+
+#define IS_TX_TOK(X)         (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b )   /* Transmit Okay    */
+#define IS_TX_MP(X)          (((X) & (1<<ETHTX_mp_b))  >> ETHTX_mp_b )    /* Multicast        */
+#define IS_TX_BP(X)          (((X) & (1<<ETHTX_bp_b))  >> ETHTX_bp_b )    /* Broadcast        */
+#define IS_TX_UND_ERR(X)     (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b )   /* Transmit FIFO Underflow */
+#define IS_TX_OF_ERR(X)      (((X) & (1<<ETHTX_of_b))  >> ETHTX_of_b )    /* Oversized frame  */
+#define IS_TX_ED_ERR(X)      (((X) & (1<<ETHTX_ed_b))  >> ETHTX_ed_b )    /* Excessive deferral  */
+#define IS_TX_EC_ERR(X)      (((X) & (1<<ETHTX_ec_b))  >> ETHTX_ec_b)     /* Excessive collisions  */
+#define IS_TX_LC_ERR(X)      (((X) & (1<<ETHTX_lc_b))  >> ETHTX_lc_b )    /* Late Collision   */
+#define IS_TX_TD_ERR(X)      (((X) & (1<<ETHTX_td_b))  >> ETHTX_td_b )    /* Transmit deferred*/
+#define IS_TX_CRC_ERR(X)     (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b )   /* CRC Error        */
+#define IS_TX_LE_ERR(X)      (((X) & (1<<ETHTX_le_b))  >>  ETHTX_le_b )    /* Length Error     */
+
+#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b)  /* Collision Count  */
+
+#define IS_RCV_ROK(X)        (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b)    /* Receive Okay     */
+#define IS_RCV_FM(X)         (((X) & (1<<ETHRX_fm_b))  >> ETHRX_fm_b)     /* Is Filter Match  */
+#define IS_RCV_MP(X)         (((X) & (1<<ETHRX_mp_b))  >> ETHRX_mp_b)     /* Is it MP         */
+#define IS_RCV_BP(X)         (((X) & (1<<ETHRX_bp_b))  >> ETHRX_bp_b)     /* Is it BP         */
+#define IS_RCV_VLT(X)        (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b)    /* VLAN Tag Detect  */
+#define IS_RCV_CF(X)         (((X) & (1<<ETHRX_cf_b))  >> ETHRX_cf_b)     /* Control Frame    */
+#define IS_RCV_OVR_ERR(X)    (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b)    /* Receive Overflow */
+#define IS_RCV_CRC_ERR(X)    (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b)    /* CRC Error        */
+#define IS_RCV_CV_ERR(X)     (((X) & (1<<ETHRX_cv_b))  >> ETHRX_cv_b)     /* Code Violation   */
+#define IS_RCV_DB_ERR(X)     (((X) & (1<<ETHRX_db_b))  >> ETHRX_db_b)     /* Dribble Bits     */
+#define IS_RCV_LE_ERR(X)     (((X) & (1<<ETHRX_le_b))  >> ETHRX_le_b)     /* Length error     */
+#define IS_RCV_LOR_ERR(X)    (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b)    /* Length Out of Range */
+#define IS_RCV_CES_ERR(X)    (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b)  /* Preamble error   */
+#define RCVPKT_LENGTH(X)     (((X) & ETHRX_length_m) >> ETHRX_length_b)   /* Length of the received packet */
+
+#endif //__IDT_RC32438_ETH_V_H__
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h idtlinux/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,249 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Definitions for IDT RC32438 GPIO.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+#ifndef __IDT_RC32438_GPIO_H__
+#define __IDT_RC32438_GPIO_H__ 
+enum
+{
+	GPIO0_PhysicalAddress	= 0x18048000,
+	GPIO_PhysicalAddress	= GPIO0_PhysicalAddress,	// Default
+
+	GPIO0_VirtualAddress	= 0xb8048000,
+	GPIO_VirtualAddress	= GPIO0_VirtualAddress,		// Default
+} ;
+
+typedef struct
+{
+	u32   gpiofunc;   /* GPIO Function Register
+			   * gpiofunc[x]==0 bit = gpio
+			   * func[x]==1  bit = altfunc
+			   */
+	u32   gpiocfg;	  /* GPIO Configuration Register
+			   * gpiocfg[x]==0 bit = input
+			   * gpiocfg[x]==1 bit = output
+			   */
+	u32   gpiod;	  /* GPIO Data Register
+			   * gpiod[x] read/write gpio pinX status
+			   */
+	u32   gpioilevel; /* GPIO Interrupt Status Register
+			   * interrupt level (see gpioistat)
+			   */
+	u32   gpioistat;  /* Gpio Interrupt Status Register
+			   * istat[x] = (gpiod[x] == level[x])
+			   * cleared in ISR (STICKY bits)
+			   */
+	u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
+} volatile * GPIO_t ;
+
+typedef enum
+{
+	GPIO_gpio_v		= 0,		// gpiofunc use pin as GPIO.
+	GPIO_alt_v		= 1,		// gpiofunc use pin as alt.
+	GPIO_input_v		= 0,		// gpiocfg use pin as input.
+	GPIO_output_v		= 1,		// gpiocfg use pin as output.
+	GPIO_pin0_b		= 0,
+	GPIO_pin0_m		= 0x00000001,
+	GPIO_pin1_b		= 1,
+	GPIO_pin1_m		= 0x00000002,
+	GPIO_pin2_b		= 2,
+	GPIO_pin2_m		= 0x00000004,
+	GPIO_pin3_b		= 3,
+	GPIO_pin3_m		= 0x00000008,
+	GPIO_pin4_b		= 4,
+	GPIO_pin4_m		= 0x00000010,
+	GPIO_pin5_b		= 5,
+	GPIO_pin5_m		= 0x00000020,
+	GPIO_pin6_b		= 6,
+	GPIO_pin6_m		= 0x00000040,
+	GPIO_pin7_b		= 7,
+	GPIO_pin7_m		= 0x00000080,
+	GPIO_pin8_b		= 8,
+	GPIO_pin8_m		= 0x00000100,
+	GPIO_pin9_b		= 9,
+	GPIO_pin9_m		= 0x00000200,
+	GPIO_pin10_b		= 10,
+	GPIO_pin10_m		= 0x00000400,
+	GPIO_pin11_b		= 11,
+	GPIO_pin11_m		= 0x00000800,
+	GPIO_pin12_b		= 12,
+	GPIO_pin12_m		= 0x00001000,
+	GPIO_pin13_b		= 13,
+	GPIO_pin13_m		= 0x00002000,
+	GPIO_pin14_b		= 14,
+	GPIO_pin14_m		= 0x00004000,
+	GPIO_pin15_b		= 15,
+	GPIO_pin15_m		= 0x00008000,
+	GPIO_pin16_b		= 16,
+	GPIO_pin16_m		= 0x00010000,
+	GPIO_pin17_b		= 17,
+	GPIO_pin17_m		= 0x00020000,
+	GPIO_pin18_b		= 18,
+	GPIO_pin18_m		= 0x00040000,
+	GPIO_pin19_b		= 19,
+	GPIO_pin19_m		= 0x00080000,
+	GPIO_pin20_b		= 20,
+	GPIO_pin20_m		= 0x00100000,
+	GPIO_pin21_b		= 21,
+	GPIO_pin21_m		= 0x00200000,
+	GPIO_pin22_b		= 22,
+	GPIO_pin22_m		= 0x00400000,
+	GPIO_pin23_b		= 23,
+	GPIO_pin23_m		= 0x00800000,
+	GPIO_pin24_b		= 24,
+	GPIO_pin24_m		= 0x01000000,
+	GPIO_pin25_b		= 25,
+	GPIO_pin25_m		= 0x02000000,
+	GPIO_pin26_b		= 26,
+	GPIO_pin26_m		= 0x04000000,
+	GPIO_pin27_b		= 27,
+	GPIO_pin27_m		= 0x08000000,
+	GPIO_pin28_b		= 28,
+	GPIO_pin28_m		= 0x10000000,
+	GPIO_pin29_b		= 29,
+	GPIO_pin29_m		= 0x20000000,
+	GPIO_pin30_b		= 30,
+	GPIO_pin30_m		= 0x40000000,
+	GPIO_pin31_b		= 31,
+	GPIO_pin31_m		= 0x80000000,
+
+// Alternate function pins.  Corrsponding gpiofunc bit set to GPIO_alt_v.
+
+	GPIO_u0sout_b		= GPIO_pin0_b,		// UART 0 serial out.
+	GPIO_u0sout_m		= GPIO_pin0_m,
+		GPIO_u0sout_cfg_v	= GPIO_output_v,
+	GPIO_u0sinp_b	= GPIO_pin1_b,			// UART 0 serial in.
+	GPIO_u0sinp_m	= GPIO_pin1_m,
+		GPIO_u0sinp_cfg_v	= GPIO_input_v,
+	GPIO_u0rin_b	= GPIO_pin2_b,			// UART 0 ring indic.
+	GPIO_u0rin_m	= GPIO_pin2_m,
+		GPIO_u0rin_cfg_v	= GPIO_input_v,
+	GPIO_u0dcdn_b	= GPIO_pin3_b,			// UART 0 data carr.det.
+	GPIO_u0dcdn_m	= GPIO_pin3_m,
+		GPIO_u0dcdn_cfg_v	= GPIO_input_v,
+	GPIO_u0dtrn_b	= GPIO_pin4_b,			// UART 0 data term rdy.
+	GPIO_u0dtrn_m	= GPIO_pin4_m,
+		GPIO_u0dtrn_cfg_v	= GPIO_output_v,
+	GPIO_u0dsrn_b	= GPIO_pin5_b,			// UART 0 data set rdy.
+	GPIO_u0dsrn_m	= GPIO_pin5_m,
+		GPIO_u0dsrn_cfg_v	= GPIO_input_v,
+	GPIO_u0rtsn_b	= GPIO_pin6_b,			// UART 0 req. to send.
+	GPIO_u0rtsn_m	= GPIO_pin6_m,
+		GPIO_u0rtsn_cfg_v	= GPIO_output_v,
+	GPIO_u0ctsn_b	= GPIO_pin7_b,			// UART 0 clear to send.
+	GPIO_u0ctsn_m	= GPIO_pin7_m,
+		GPIO_u0ctsn_cfg_v	= GPIO_input_v,
+
+	GPIO_u1sout_b		= GPIO_pin8_b,		// UART 1 serial out.
+	GPIO_u1sout_m		= GPIO_pin8_m,
+		GPIO_u1sout_cfg_v	= GPIO_output_v,
+	GPIO_u1sinp_b		= GPIO_pin9_b,		// UART 1 serial in.
+	GPIO_u1sinp_m		= GPIO_pin9_m,
+		GPIO_u1sinp_cfg_v	= GPIO_input_v,
+	GPIO_u1dtrn_b		= GPIO_pin10_b, 	// UART 1 data term rdy.
+	GPIO_u1dtrn_m		= GPIO_pin10_m,
+		GPIO_u1dtrn_cfg_v	= GPIO_output_v,
+	GPIO_u1dsrn_b		= GPIO_pin11_b, 	// UART 1 data set rdy.
+	GPIO_u1dsrn_m		= GPIO_pin11_m,
+		GPIO_u1dsrn_cfg_v	= GPIO_input_v,
+	GPIO_u1rtsn_b		= GPIO_pin12_b, 	// UART 1 req. to send.
+	GPIO_u1rtsn_m		= GPIO_pin12_m,
+		GPIO_u1rtsn_cfg_v	= GPIO_output_v,
+	GPIO_u1ctsn_b		= GPIO_pin13_b, 	// UART 1 clear to send.
+	GPIO_u1ctsn_m		= GPIO_pin13_m,
+		GPIO_u1ctsn_cfg_v	= GPIO_input_v,
+
+	GPIO_dmareqn0_b 	= GPIO_pin14_b, 	// Ext. DMA 0 request
+	GPIO_dmareqn0_m 	= GPIO_pin14_m,
+		GPIO_dmareqn0_cfg_v	= GPIO_input_v,
+
+	GPIO_dmareqn1_b 	= GPIO_pin15_b, 	// Ext. DMA 1 request
+	GPIO_dmareqn1_m 	= GPIO_pin15_m,
+		GPIO_dmareqn1_cfg_v	= GPIO_input_v,
+
+	GPIO_dmadonen0_b	= GPIO_pin16_b, 	// Ext. DMA 0 done
+	GPIO_dmadonen0_m	= GPIO_pin16_m,
+		GPIO_dmadonen0_cfg_v	= GPIO_input_v,
+
+	GPIO_dmadonen1_b	= GPIO_pin17_b, 	// Ext. DMA 1 done
+	GPIO_dmadonen1_m	= GPIO_pin17_m,
+		GPIO_dmadonen1_cfg_v	= GPIO_input_v,
+
+	GPIO_dmafinn0_b 	= GPIO_pin18_b, 	// Ext. DMA 0 finished
+	GPIO_dmafinn0_m 	= GPIO_pin18_m,
+		GPIO_dmafinn0_cfg_v	= GPIO_output_v,
+
+	GPIO_dmafinn1_b 	= GPIO_pin19_b, 	// Ext. DMA 1 finished
+	GPIO_dmafinn1_m 	= GPIO_pin19_m,
+		GPIO_dmafinn1_cfg_v	= GPIO_output_v,
+
+	GPIO_maddr22_b		= GPIO_pin20_b, 	// M&P bus bit 22.
+	GPIO_maddr22_m		= GPIO_pin20_m,
+		GPIO_maddr22_cfg_v	= GPIO_output_v,
+
+	GPIO_maddr23_b		= GPIO_pin21_b, 	// M&P bus bit 23.
+	GPIO_maddr23_m		= GPIO_pin21_m,
+		GPIO_maddr23_cfg_v	= GPIO_output_v,
+
+	GPIO_maddr24_b		= GPIO_pin22_b, 	// M&P bus bit 24.
+	GPIO_maddr24_m		= GPIO_pin22_m,
+		GPIO_maddr24_cfg_v	= GPIO_output_v,
+
+	GPIO_maddr25_b		= GPIO_pin23_b, 	// M&P bus bit 25.
+	GPIO_maddr25_m		= GPIO_pin23_m,
+		GPIO_maddr25_cfg_v	= GPIO_output_v,
+
+	GPIO_afspare6_b 	= GPIO_pin24_b, 	// reserved.
+	GPIO_afspare6_m 	= GPIO_pin24_m,
+		GPIO_afspare6_cfg_v	= GPIO_input_v,
+	GPIO_afspare5_b 	= GPIO_pin25_b, 	// reserved.
+	GPIO_afspare5_m 	= GPIO_pin25_m,
+		GPIO_afspare5_cfg_v	= GPIO_input_v,
+	GPIO_afspare4_b 	= GPIO_pin26_b, 	// reserved.
+	GPIO_afspare4_m 	= GPIO_pin26_m,
+		GPIO_afspare4_cfg_v	= GPIO_input_v,
+	GPIO_afspare3_b 	= GPIO_pin27_b, 	// reserved.
+	GPIO_afspare3_m 	= GPIO_pin27_m,
+		GPIO_afspare3_cfg_v	= GPIO_input_v,
+	GPIO_afspare2_b 	= GPIO_pin28_b, 	// reserved.
+	GPIO_afspare2_m 	= GPIO_pin28_m,
+		GPIO_afspare2_cfg_v	= GPIO_input_v,
+	GPIO_afspare1_b 	= GPIO_pin29_b, 	// reserved.
+	GPIO_afspare1_m 	= GPIO_pin29_m,
+		GPIO_afspare1_cfg_v	= GPIO_input_v,
+
+	GPIO_pcimuintn_b	= GPIO_pin30_b, 	// PCI messaging int.
+	GPIO_pcimuintn_m	= GPIO_pin30_m,
+		GPIO_pcimuintn_cfg_v	= GPIO_output_v,
+
+	GPIO_rngclk_b		= GPIO_pin31_b, 	// RNG external clock
+	GPIO_rngclk_m		= GPIO_pin31_m,
+		GPIO_rncclk_cfg_v	= GPIO_input_v,
+} GPIO_DEFS_t;
+
+#endif //__IDT_RC32438_GPIO_H__
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32438/rc32438.h idtlinux/include/asm-mips/idt-boards/rc32438/rc32438.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32438/rc32438.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32438/rc32438.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,144 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Definitions for IDT RC32438 CPU.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_RC32438_H__
+#define  __IDT_RC32438_H__
+#include <linux/config.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <asm/idt-boards/rc32438/rc32438_timer.h>
+
+#define RC32438_REG_BASE   0x18000000
+
+#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
+#define idttimer     ((volatile TIM_t)  TIM0_VirtualAddress)
+#define gpio	  ((volatile GPIO_t) GPIO0_VirtualAddress)
+
+#define IDT_CLOCK_MULT 2
+#define MIPS_CPU_TIMER_IRQ 7
+/* Interrupt Controller */
+#define IC_GROUP0_PEND     (RC32438_REG_BASE + 0x38000)
+#define IC_GROUP0_MASK     (RC32438_REG_BASE + 0x38008)
+#define IC_GROUP_OFFSET    0x0C
+#define RTC_BASE           0xAC0801FF0
+
+#define NUM_INTR_GROUPS    5
+/* 16550 UARTs */
+
+#define GROUP0_IRQ_BASE 8		/* GRP2 IRQ numbers start here */
+#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
+#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
+#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32)	/* GRP5 IRQ numbers start here */
+#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
+
+#ifdef __MIPSEB__
+#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50003)
+#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50023)
+#else
+#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50000)
+#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50020)
+#endif
+
+#define RC32438_UART0_IRQ  GROUP3_IRQ_BASE + 0
+#define RC32438_UART1_IRQ  GROUP3_IRQ_BASE + 3
+
+#define RC32438_NR_IRQS  (GROUP4_IRQ_BASE + 32)
+
+
+
+/* cpu pipeline flush */
+static inline void rc32438_sync(void)
+{
+        __asm__ volatile ("sync");
+}
+
+static inline void rc32438_sync_udelay(int us)
+{
+        __asm__ volatile ("sync");
+        udelay(us);
+}
+
+static inline void rc32438_sync_delay(int ms)
+{
+        __asm__ volatile ("sync");
+        mdelay(ms);
+}
+
+/*
+ * Macros to access internal RC32438 registers. No byte
+ * swapping should be done when accessing the internal
+ * registers.
+ */
+
+#define rc32438_readb __raw_readb
+#define rc32438_readw __raw_readw
+#define rc32438_readl __raw_readl
+
+#define rc32438_writeb __raw_writeb
+#define rc32438_writew __raw_writew
+#define rc32438_writel __raw_writel
+
+/*
+ * C access to CLZ and CLO instructions
+ * (count leading zeroes/ones).
+ */
+static inline int rc32438_clz(unsigned long val)
+{
+	int ret;
+        __asm__ volatile (
+		".set\tnoreorder\n\t"
+		".set\tnoat\n\t"
+		".set\tmips32\n\t"
+		"clz\t%0,%1\n\t"
+                ".set\tmips0\n\t"
+                ".set\tat\n\t"
+                ".set\treorder"
+                : "=r" (ret)
+		: "r" (val));
+
+	return ret;
+}
+static inline int rc32438_clo(unsigned long val)
+{
+	int ret;
+        __asm__ volatile (
+		".set\tnoreorder\n\t"
+		".set\tnoat\n\t"
+		".set\tmips32\n\t"
+		"clo\t%0,%1\n\t"
+                ".set\tmips0\n\t"
+                ".set\tat\n\t"
+                ".set\treorder"
+                : "=r" (ret)
+		: "r" (val));
+
+	return ret;
+}
+#endif //__IDT_RC32438_H__
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32438/rc32438_pci.h idtlinux/include/asm-mips/idt-boards/rc32438/rc32438_pci.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32438/rc32438_pci.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32438/rc32438_pci.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,502 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Definitions for IDT RC32438 PCI.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+enum
+{
+	PCI0_PhysicalAddress	= 0x18080000,
+	PCI_PhysicalAddress	= PCI0_PhysicalAddress,
+
+	PCI0_VirtualAddress	= 0xb8080000,
+	PCI_VirtualAddress	= PCI0_VirtualAddress,
+} ;
+
+enum
+{
+	PCI_LbaCount	= 4,		// Local base addresses.
+} ;
+
+typedef struct
+{
+	u32	a ;		// Address.
+	u32	c ;		// Control.
+	u32	m ;		// mapping.
+} PCI_Map_s ;
+
+typedef struct
+{
+	u32		pcic ;
+	u32		pcis ;
+	u32		pcism ;
+	u32		pcicfga ;
+	u32		pcicfgd ;
+	PCI_Map_s	pcilba [PCI_LbaCount] ;
+	u32		pcidac ;
+	u32		pcidas ;
+	u32		pcidasm ;
+	u32		pcidad ;
+	u32		pcidma8c ;
+	u32		pcidma9c ;
+	u32		pcitc ;
+} volatile *PCI_t ;
+
+// PCI messaging unit.
+enum
+{
+	PCIM_Count	= 2,
+} ;
+typedef struct
+{
+	u32		pciim [PCIM_Count] ;
+	u32		pciom [PCIM_Count] ;
+	u32		pciid ;
+	u32		pciiic ;
+	u32		pciiim ;
+	u32		pciiod ;
+	u32		pciioic ;
+	u32		pciioim ;
+} volatile *PCIM_t ;
+
+/*******************************************************************************
+ *
+ * PCI Control Register
+ *
+ ******************************************************************************/
+enum
+{
+	PCIC_en_b	= 0,
+	PCIC_en_m	= 0x00000001,
+	PCIC_tnr_b	= 1,
+	PCIC_tnr_m	= 0x00000002,
+	PCIC_sce_b	= 2,
+	PCIC_sce_m	= 0x00000004,
+	PCIC_ien_b	= 3,
+	PCIC_ien_m	= 0x00000008,
+	PCIC_aaa_b	= 4,
+	PCIC_aaa_m	= 0x00000010,
+	PCIC_eap_b	= 5,
+	PCIC_eap_m	= 0x00000020,
+	PCIC_pcim_b	= 6,
+	PCIC_pcim_m	= 0x000001c0,
+		PCIC_pcim_disabled_v	= 0,
+		PCIC_pcim_tnr_v 	= 1,	// Satellite - target not ready
+		PCIC_pcim_suspend_v	= 2,	// Satellite - suspended CPU.
+		PCIC_pcim_extern_v	= 3,	// Host - external arbiter.
+		PCIC_pcim_fixed_v	= 4,	// Host - fixed priority arb.
+		PCIC_pcim_roundrobin_v	= 5,	// Host - round robin priority.
+		PCIC_pcim_reserved6_v	= 6,
+		PCIC_pcim_reserved7_v	= 7,
+	PCIC_igm_b	= 9,
+	PCIC_igm_m	= 0x00000200,
+} ;
+
+/*******************************************************************************
+ *
+ * PCI Status Register
+ *
+ ******************************************************************************/
+enum {
+	PCIS_eed_b	= 0,
+	PCIS_eed_m	= 0x00000001,
+	PCIS_wr_b	= 1,
+	PCIS_wr_m	= 0x00000002,
+	PCIS_nmi_b	= 2,
+	PCIS_nmi_m	= 0x00000004,
+	PCIS_ii_b	= 3,
+	PCIS_ii_m	= 0x00000008,
+	PCIS_cwe_b	= 4,
+	PCIS_cwe_m	= 0x00000010,
+	PCIS_cre_b	= 5,
+	PCIS_cre_m	= 0x00000020,
+	PCIS_mdpe_b	= 6,
+	PCIS_mdpe_m	= 0x00000040,
+	PCIS_sta_b	= 7,
+	PCIS_sta_m	= 0x00000080,
+	PCIS_rta_b	= 8,
+	PCIS_rta_m	= 0x00000100,
+	PCIS_rma_b	= 9,
+	PCIS_rma_m	= 0x00000200,
+	PCIS_sse_b	= 10,
+	PCIS_sse_m	= 0x00000400,
+	PCIS_ose_b	= 11,
+	PCIS_ose_m	= 0x00000800,
+	PCIS_pe_b	= 12,
+	PCIS_pe_m	= 0x00001000,
+	PCIS_tae_b	= 13,
+	PCIS_tae_m	= 0x00002000,
+	PCIS_rle_b	= 14,
+	PCIS_rle_m	= 0x00004000,
+	PCIS_bme_b	= 15,
+	PCIS_bme_m	= 0x00008000,
+	PCIS_prd_b	= 16,
+	PCIS_prd_m	= 0x00010000,
+	PCIS_rip_b	= 17,
+	PCIS_rip_m	= 0x00020000,
+} ;
+
+/*******************************************************************************
+ *
+ * PCI Status Mask Register
+ *
+ ******************************************************************************/
+enum {
+	PCISM_eed_b		= 0,
+	PCISM_eed_m		= 0x00000001,
+	PCISM_wr_b		= 1,
+	PCISM_wr_m		= 0x00000002,
+	PCISM_nmi_b		= 2,
+	PCISM_nmi_m		= 0x00000004,
+	PCISM_ii_b		= 3,
+	PCISM_ii_m		= 0x00000008,
+	PCISM_cwe_b		= 4,
+	PCISM_cwe_m		= 0x00000010,
+	PCISM_cre_b		= 5,
+	PCISM_cre_m		= 0x00000020,
+	PCISM_mdpe_b		= 6,
+	PCISM_mdpe_m		= 0x00000040,
+	PCISM_sta_b		= 7,
+	PCISM_sta_m		= 0x00000080,
+	PCISM_rta_b		= 8,
+	PCISM_rta_m		= 0x00000100,
+	PCISM_rma_b		= 9,
+	PCISM_rma_m		= 0x00000200,
+	PCISM_sse_b		= 10,
+	PCISM_sse_m		= 0x00000400,
+	PCISM_ose_b		= 11,
+	PCISM_ose_m		= 0x00000800,
+	PCISM_pe_b		= 12,
+	PCISM_pe_m		= 0x00001000,
+	PCISM_tae_b		= 13,
+	PCISM_tae_m		= 0x00002000,
+	PCISM_rle_b		= 14,
+	PCISM_rle_m		= 0x00004000,
+	PCISM_bme_b		= 15,
+	PCISM_bme_m		= 0x00008000,
+	PCISM_prd_b		= 16,
+	PCISM_prd_m		= 0x00010000,
+	PCISM_rip_b		= 17,
+	PCISM_rip_m		= 0x00020000,
+} ;
+
+/*******************************************************************************
+ *
+ * PCI Configuration Address Register
+ *
+ ******************************************************************************/
+enum {
+	PCICFGA_reg_b		= 2,
+	PCICFGA_reg_m		= 0x000000fc,
+		PCICFGA_reg_id_v	= 0x00>>2, //use PCFGID_
+		PCICFGA_reg_04_v	= 0x04>>2, //use PCFG04_
+		PCICFGA_reg_08_v	= 0x08>>2, //use PCFG08_
+		PCICFGA_reg_0C_v	= 0x0C>>2, //use PCFG0C_
+		PCICFGA_reg_pba0_v	= 0x10>>2, //use PCIPBA_
+		PCICFGA_reg_pba1_v	= 0x14>>2, //use PCIPBA_
+		PCICFGA_reg_pba2_v	= 0x18>>2, //use PCIPBA_
+		PCICFGA_reg_pba3_v	= 0x1c>>2, //use PCIPBA_
+		PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
+		PCICFGA_reg_3C_v	= 0x3C>>2, //use PCFG3C_
+		PCICFGA_reg_pba0c_v	= 0x44>>2, //use PCIPBAC_
+		PCICFGA_reg_pba0m_v	= 0x48>>2,
+		PCICFGA_reg_pba1c_v	= 0x4c>>2, //use PCIPBAC_
+		PCICFGA_reg_pba1m_v	= 0x50>>2,
+		PCICFGA_reg_pba2c_v	= 0x54>>2, //use PCIPBAC_
+		PCICFGA_reg_pba2m_v	= 0x58>>2,
+		PCICFGA_reg_pba3c_v	= 0x5c>>2, //use PCIPBAC_
+		PCICFGA_reg_pba3m_v	= 0x60>>2,
+		PCICFGA_reg_pmgt_v	= 0x64>>2,
+	PCICFGA_func_b		= 8,
+	PCICFGA_func_m		= 0x00000700,
+	PCICFGA_dev_b		= 11,
+	PCICFGA_dev_m		= 0x0000f800,
+		PCICFGA_dev_internal_v	= 0,
+	PCICFGA_bus_b		= 16,
+	PCICFGA_bus_m		= 0x00ff0000,
+		PCICFGA_bus_type0_v	= 0,	//local bus
+	PCICFGA_en_b		= 31,		// read only
+	PCICFGA_en_m		= 0x80000000,
+} ;
+
+enum {
+	PCFGID_vendor_b 	= 0,
+	PCFGID_vendor_m 	= 0x0000ffff,
+		PCFGID_vendor_IDT_v		= 0x111d,
+	PCFGID_device_b 	= 16,
+	PCFGID_device_m 	= 0xffff0000,
+		PCFGID_device_Acaciade_v	= 0x0207,
+
+	PCFG04_command_ioena_b		= 1,
+	PCFG04_command_ioena_m		= 0x00000001,
+	PCFG04_command_memena_b 	= 2,
+	PCFG04_command_memena_m 	= 0x00000002,
+	PCFG04_command_bmena_b		= 3,
+	PCFG04_command_bmena_m		= 0x00000004,
+	PCFG04_command_mwinv_b		= 5,
+	PCFG04_command_mwinv_m		= 0x00000010,
+	PCFG04_command_parena_b 	= 7,
+	PCFG04_command_parena_m 	= 0x00000040,
+	PCFG04_command_serrena_b	= 9,
+	PCFG04_command_serrena_m	= 0x00000100,
+	PCFG04_command_fastbbena_b	= 10,
+	PCFG04_command_fastbbena_m	= 0x00000200,
+	PCFG04_status_b 		= 16,
+	PCFG04_status_m 		= 0xffff0000,
+	PCFG04_status_66MHz_b		= 21,	// 66 MHz enable
+	PCFG04_status_66MHz_m		= 0x00200000,
+	PCFG04_status_fbb_b		= 23,
+	PCFG04_status_fbb_m		= 0x00800000,
+	PCFG04_status_mdpe_b		= 24,
+	PCFG04_status_mdpe_m		= 0x01000000,
+	PCFG04_status_dst_b		= 25,
+	PCFG04_status_dst_m		= 0x06000000,
+	PCFG04_status_sta_b		= 27,
+	PCFG04_status_sta_m		= 0x08000000,
+	PCFG04_status_rta_b		= 28,
+	PCFG04_status_rta_m		= 0x10000000,
+	PCFG04_status_rma_b		= 29,
+	PCFG04_status_rma_m		= 0x20000000,
+	PCFG04_status_sse_b		= 30,
+	PCFG04_status_sse_m		= 0x40000000,
+	PCFG04_status_pe_b		= 31,
+	PCFG04_status_pe_m		= 0x40000000,
+
+	PCFG08_revId_b			= 0,
+	PCFG08_revId_m			= 0x000000ff,
+	PCFG08_classCode_b		= 0,
+	PCFG08_classCode_m		= 0xffffff00,
+		PCFG08_classCode_bridge_v	= 06,
+		PCFG08_classCode_proc_v 	= 0x0b3000, // processor-MIPS
+	PCFG0C_cacheline_b		= 0,
+	PCFG0C_cacheline_m		= 0x000000ff,
+	PCFG0C_masterLatency_b		= 8,
+	PCFG0C_masterLatency_m		= 0x0000ff00,
+	PCFG0C_headerType_b		= 16,
+	PCFG0C_headerType_m		= 0x00ff0000,
+	PCFG0C_bist_b			= 24,
+	PCFG0C_bist_m			= 0xff000000,
+
+	PCIPBA_msi_b			= 0,
+	PCIPBA_msi_m			= 0x00000001,
+	PCIPBA_p_b			= 3,
+	PCIPBA_p_m			= 0x00000004,
+	PCIPBA_baddr_b			= 8,
+	PCIPBA_baddr_m			= 0xffffff00,
+
+	PCFGSS_vendorId_b		= 0,
+	PCFGSS_vendorId_m		= 0x0000ffff,
+	PCFGSS_id_b			= 16,
+	PCFGSS_id_m			= 0xffff0000,
+
+	PCFG3C_interruptLine_b		= 0,
+	PCFG3C_interruptLine_m		= 0x000000ff,
+	PCFG3C_interruptPin_b		= 8,
+	PCFG3C_interruptPin_m		= 0x0000ff00,
+	PCFG3C_minGrant_b		= 16,
+	PCFG3C_minGrant_m		= 0x00ff0000,
+	PCFG3C_maxLat_b 		= 24,
+	PCFG3C_maxLat_m 		= 0xff000000,
+
+	PCIPBAC_msi_b			= 0,
+	PCIPBAC_msi_m			= 0x00000001,
+	PCIPBAC_p_b			= 1,
+	PCIPBAC_p_m			= 0x00000002,
+	PCIPBAC_size_b			= 2,
+	PCIPBAC_size_m			= 0x0000007c,
+	PCIPBAC_sb_b			= 7,
+	PCIPBAC_sb_m			= 0x00000080,
+	PCIPBAC_pp_b			= 8,
+	PCIPBAC_pp_m			= 0x00000100,
+	PCIPBAC_mr_b			= 9,
+	PCIPBAC_mr_m			= 0x00000600,
+		PCIPBAC_mr_read_v	=0,	//no prefetching
+		PCIPBAC_mr_readLine_v	=1,
+		PCIPBAC_mr_readMult_v	=2,
+	PCIPBAC_mrl_b			= 11,
+	PCIPBAC_mrl_m			= 0x00000800,
+	PCIPBAC_mrm_b			= 12,
+	PCIPBAC_mrm_m			= 0x00001000,
+	PCIPBAC_trp_b			= 13,
+	PCIPBAC_trp_m			= 0x00002000,
+
+	PCFG40_trdyTimeout_b		= 0,
+	PCFG40_trdyTimeout_m		= 0x000000ff,
+	PCFG40_retryLim_b		= 8,
+	PCFG40_retryLim_m		= 0x0000ff00,
+};
+
+/*******************************************************************************
+ *
+ * PCI Local Base Address [0|1|2|3] Register
+ *
+ ******************************************************************************/
+enum {
+	PCILBA_baddr_b		= 0,		// In PCI_t -> pcilba [] .a
+	PCILBA_baddr_m		= 0xffffff00,
+} ;
+/*******************************************************************************
+ *
+ * PCI Local Base Address Control Register
+ *
+ ******************************************************************************/
+enum {
+	PCILBAC_msi_b		= 0,		// In pPci->pcilba[i].c
+	PCILBAC_msi_m		= 0x00000001,
+		PCILBAC_msi_mem_v	= 0,
+		PCILBAC_msi_io_v	= 1,
+	PCILBAC_size_b		= 2,	// In pPci->pcilba[i].c
+	PCILBAC_size_m		= 0x0000007c,
+	PCILBAC_sb_b		= 7,	// In pPci->pcilba[i].c
+	PCILBAC_sb_m		= 0x00000080,
+	PCILBAC_rt_b		= 8,	// In pPci->pcilba[i].c
+	PCILBAC_rt_m		= 0x00000100,
+		PCILBAC_rt_noprefetch_v = 0, // mem read
+		PCILBAC_rt_prefetch_v	= 1, // mem readline
+} ;
+
+/*******************************************************************************
+ *
+ * PCI Local Base Address [0|1|2|3] Mapping Register
+ *
+ ******************************************************************************/
+enum {
+	PCILBAM_maddr_b 	= 8,
+	PCILBAM_maddr_m 	= 0xffffff00,
+} ;
+
+/*******************************************************************************
+ *
+ * PCI Decoupled Access Control Register
+ *
+ ******************************************************************************/
+enum {
+	PCIDAC_den_b		= 0,
+	PCIDAC_den_m		= 0x00000001,
+} ;
+
+/*******************************************************************************
+ *
+ * PCI Decoupled Access Status Register
+ *
+ ******************************************************************************/
+enum {
+	PCIDAS_d_b	= 0,
+	PCIDAS_d_m	= 0x00000001,
+	PCIDAS_b_b	= 1,
+	PCIDAS_b_m	= 0x00000002,
+	PCIDAS_e_b	= 2,
+	PCIDAS_e_m	= 0x00000004,
+	PCIDAS_ofe_b	= 3,
+	PCIDAS_ofe_m	= 0x00000008,
+	PCIDAS_off_b	= 4,
+	PCIDAS_off_m	= 0x00000010,
+	PCIDAS_ife_b	= 5,
+	PCIDAS_ife_m	= 0x00000020,
+	PCIDAS_iff_b	= 6,
+	PCIDAS_iff_m	= 0x00000040,
+} ;
+
+/*******************************************************************************
+ *
+ * PCI DMA Channel 8 Configuration Register
+ *
+ ******************************************************************************/
+enum
+{
+	PCIDMA8C_mbs_b	= 0,		// Maximum Burst Size.
+	PCIDMA8C_mbs_m	= 0x00000fff,	// { pcidma8c }
+	PCIDMA8C_our_b	= 12,		// Optimize Unaligned Burst Reads.
+	PCIDMA8C_our_m	= 0x00001000,	// { pcidma8c }
+} ;
+
+/*******************************************************************************
+ *
+ * PCI DMA Channel 9 Configuration Register
+ *
+ ******************************************************************************/
+enum
+{
+	PCIDMA9C_mbs_b	= 0,		// Maximum Burst Size.
+	PCIDMA9C_mbs_m	= 0x00000fff, // { pcidma9c }
+} ;
+
+/*******************************************************************************
+ *
+ * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
+ *
+ ******************************************************************************/
+enum {
+	PCIDMAD_pt_b		= 22,		// in DEVCMD field (descriptor)
+	PCIDMAD_pt_m		= 0x00c00000,	// preferred transaction field
+		// These are for reads (DMA channel 8)
+		PCIDMAD_devcmd_mr_v	= 0,	//memory read
+		PCIDMAD_devcmd_mrl_v	= 1,	//memory read line
+		PCIDMAD_devcmd_mrm_v	= 2,	//memory read multiple
+		PCIDMAD_devcmd_ior_v	= 3,	//I/O read
+		// These are for writes (DMA channel 9)
+		PCIDMAD_devcmd_mw_v	= 0,	//memory write
+		PCIDMAD_devcmd_mwi_v	= 1,	//memory write invalidate
+		PCIDMAD_devcmd_iow_v	= 3,	//I/O write
+
+	// Swap byte field applies to both DMA channel 8 and 9
+	PCIDMAD_sb_b		= 24,		// in DEVCMD field (descriptor)
+	PCIDMAD_sb_m		= 0x01000000,	// swap byte field
+} ;
+
+
+/*******************************************************************************
+ *
+ * PCI Target Control Register
+ *
+ ******************************************************************************/
+enum
+{
+	PCITC_rtimer_b		= 0,		// In PCITC_t -> pcitc
+	PCITC_rtimer_m		= 0x000000ff,
+	PCITC_dtimer_b		= 8,		// In PCITC_t -> pcitc
+	PCITC_dtimer_m		= 0x0000ff00,
+	PCITC_rdr_b		= 18,		// In PCITC_t -> pcitc
+	PCITC_rdr_m		= 0x00040000,
+	PCITC_ddt_b		= 19,		// In PCITC_t -> pcitc
+	PCITC_ddt_m		= 0x00080000,
+} ;
+/*******************************************************************************
+ *
+ * PCI messaging unit [applies to both inbound and outbound registers ]
+ *
+ ******************************************************************************/
+enum
+{
+	PCIM_m0_b	= 0,		// In PCIM_t -> {pci{iic,iim,ioic,ioim}}
+	PCIM_m0_m	= 0x00000001,	// inbound or outbound message 0
+	PCIM_m1_b	= 1,		// In PCIM_t -> {pci{iic,iim,ioic,ioim}}
+	PCIM_m1_m	= 0x00000002,	// inbound or outbound message 1
+	PCIM_db_b	= 2,		// In PCIM_t -> {pci{iic,iim,ioic,ioim}}
+	PCIM_db_m	= 0x00000004,	// inbound or outbound doorbell
+};
+
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h idtlinux/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,183 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   Definitions for IDT RC32438 PCI setup.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#define PCI_MSG_VirtualAddress	     0xB8088010
+#define rc32438_pci ((volatile PCI_t) PCI0_VirtualAddress)
+#define rc32438_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
+
+#define PCIM_SHFT		0x6
+#define PCIM_BIT_LEN		0x7
+#define PCIM_H_EA		0x3
+#define PCIM_H_IA_FIX		0x4
+#define PCIM_H_IA_RR		0x5
+
+#define PCI_ADDR_START		0x50000000
+
+#define CPUTOPCI_MEM_WIN	0x02000000
+#define CPUTOPCI_IO_WIN		0x00100000
+#define PCILBA_SIZE_SHFT	2
+#define PCILBA_SIZE_MASK	0x1F
+#define SIZE_256MB		0x1C
+#define SIZE_128MB		0x1B
+#define SIZE_64MB               0x1A
+#define SIZE_32MB		0x19
+#define SIZE_16MB               0x18
+#define SIZE_4MB		0x16
+#define SIZE_2MB		0x15
+#define SIZE_1MB		0x14
+#define ACACIA_CONFIG0_ADDR	0x80000000
+#define ACACIA_CONFIG1_ADDR	0x80000004
+#define ACACIA_CONFIG2_ADDR	0x80000008
+#define ACACIA_CONFIG3_ADDR	0x8000000C
+#define ACACIA_CONFIG4_ADDR	0x80000010
+#define ACACIA_CONFIG5_ADDR	0x80000014
+#define ACACIA_CONFIG6_ADDR	0x80000018
+#define ACACIA_CONFIG7_ADDR	0x8000001C
+#define ACACIA_CONFIG8_ADDR	0x80000020
+#define ACACIA_CONFIG9_ADDR	0x80000024
+#define ACACIA_CONFIG10_ADDR	0x80000028
+#define ACACIA_CONFIG11_ADDR	0x8000002C
+#define ACACIA_CONFIG12_ADDR	0x80000030
+#define ACACIA_CONFIG13_ADDR	0x80000034
+#define ACACIA_CONFIG14_ADDR	0x80000038
+#define ACACIA_CONFIG15_ADDR	0x8000003C
+#define ACACIA_CONFIG16_ADDR	0x80000040
+#define ACACIA_CONFIG17_ADDR	0x80000044
+#define ACACIA_CONFIG18_ADDR	0x80000048
+#define ACACIA_CONFIG19_ADDR	0x8000004C
+#define ACACIA_CONFIG20_ADDR	0x80000050
+#define ACACIA_CONFIG21_ADDR	0x80000054
+#define ACACIA_CONFIG22_ADDR	0x80000058
+#define ACACIA_CONFIG23_ADDR	0x8000005C
+#define ACACIA_CONFIG24_ADDR	0x80000060
+#define ACACIA_CONFIG25_ADDR	0x80000064
+#define ACACIA_CMD 		(PCFG04_command_ioena_m | \
+				 PCFG04_command_memena_m | \
+				 PCFG04_command_bmena_m | \
+				 PCFG04_command_mwinv_m | \
+				 PCFG04_command_parena_m | \
+				 PCFG04_command_serrena_m )
+
+#define ACACIA_STAT		(PCFG04_status_mdpe_m | \
+				 PCFG04_status_sta_m  | \
+				 PCFG04_status_rta_m  | \
+				 PCFG04_status_rma_m  | \
+				 PCFG04_status_sse_m  | \
+				 PCFG04_status_pe_m)
+
+#define ACACIA_CNFG1		((ACACIA_STAT<<16)|ACACIA_CMD)
+
+#define ACACIA_REVID		0
+#define ACACIA_CLASS_CODE	0
+#define ACACIA_CNFG2		((ACACIA_CLASS_CODE<<8) | \
+				  ACACIA_REVID)
+
+#define ACACIA_CACHE_LINE_SIZE	4
+#define ACACIA_MASTER_LAT	0x3c
+#define ACACIA_HEADER_TYPE	0
+#define ACACIA_BIST		0
+
+#define ACACIA_CNFG3 ((ACACIA_BIST << 24) | \
+		      (ACACIA_HEADER_TYPE<<16) | \
+		      (ACACIA_MASTER_LAT<<8) | \
+		      ACACIA_CACHE_LINE_SIZE )
+
+#define ACACIA_BAR0	0x00000008 /* 128 MB Memory */
+#define ACACIA_BAR1	0x18800001 /* 1 MB IO */
+#define ACACIA_BAR2	0x18000001 /* 2 MB IO window for Acacia
+					internal Registers */
+#define ACACIA_BAR3	0x48000008 /* Spare 128 MB Memory */
+
+#define ACACIA_CNFG4	ACACIA_BAR0
+#define ACACIA_CNFG5    ACACIA_BAR1
+#define ACACIA_CNFG6 	ACACIA_BAR2
+#define ACACIA_CNFG7	ACACIA_BAR3
+
+#define ACACIA_SUBSYS_VENDOR_ID 0
+#define ACACIA_SUBSYSTEM_ID	0
+#define ACACIA_CNFG8		0
+#define ACACIA_CNFG9		0
+#define ACACIA_CNFG10		0
+#define ACACIA_CNFG11 	((ACACIA_SUBSYS_VENDOR_ID<<16) | \
+			  ACACIA_SUBSYSTEM_ID)
+#define ACACIA_INT_LINE		1
+#define ACACIA_INT_PIN		1
+#define ACACIA_MIN_GNT		8
+#define ACACIA_MAX_LAT		0x38
+#define ACACIA_CNFG12		0
+#define ACACIA_CNFG13 		0
+#define ACACIA_CNFG14		0
+#define ACACIA_CNFG15	((ACACIA_MAX_LAT<<24) | \
+			 (ACACIA_MIN_GNT<<16) | \
+			 (ACACIA_INT_PIN<<8)  | \
+			  ACACIA_INT_LINE)
+#define	ACACIA_RETRY_LIMIT	0x80
+#define ACACIA_TRDY_LIMIT	0x80
+#define ACACIA_CNFG16 ((ACACIA_RETRY_LIMIT<<8) | \
+			ACACIA_TRDY_LIMIT)
+#define PCI_PBAxC_R		0x0
+#define PCI_PBAxC_RL		0x1
+#define PCI_PBAxC_RM		0x2
+#define SIZE_SHFT		2
+
+#define ACACIA_PBA0C	( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
+			  ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
+			  PCIPBAC_pp_m | \
+			  (SIZE_128MB<<SIZE_SHFT) | \
+			   PCIPBAC_p_m)
+
+#define ACACIA_CNFG17	ACACIA_PBA0C
+#define ACACIA_PBA0M	0x0
+#define ACACIA_CNFG18	ACACIA_PBA0M
+
+#define ACACIA_PBA1C	((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
+			  PCIPBAC_msi_m)
+
+#define ACACIA_CNFG19	ACACIA_PBA1C
+#define ACACIA_PBA1M	0x0
+#define ACACIA_CNFG20	ACACIA_PBA1M
+
+#define ACACIA_PBA2C	((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
+			  PCIPBAC_msi_m)
+
+#define ACACIA_CNFG21	ACACIA_PBA2C
+#define ACACIA_PBA2M	0x18000000
+#define ACACIA_CNFG22	ACACIA_PBA2M
+#define ACACIA_PBA3C	0
+#define ACACIA_CNFG23	ACACIA_PBA3C
+#define ACACIA_PBA3M	0
+#define ACACIA_CNFG24	ACACIA_PBA3M
+
+
+
+#define	PCITC_DTIMER_VAL	8
+#define PCITC_RTIMER_VAL	0x10
+
diff -uNr linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32438/rc32438_timer.h idtlinux/include/asm-mips/idt-boards/rc32438/rc32438_timer.h
--- linux-2.6.16-rc5/include/asm-mips/idt-boards/rc32438/rc32438_timer.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/idt-boards/rc32438/rc32438_timer.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,83 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *    Timer register definition IDT RC32438 CPU.
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+ 
+#ifndef __IDT_RC32438_TIM_H__
+#define __IDT_RC32438_TIM_H__
+
+enum
+{
+	TIM0_PhysicalAddress	= 0x18028000,
+	TIM_PhysicalAddress	= TIM0_PhysicalAddress,		// Default
+
+	TIM0_VirtualAddress	= 0xb8028000,
+	TIM_VirtualAddress	= TIM0_VirtualAddress,		// Default
+} ;
+
+enum
+{
+	TIM_Count = 3,
+} ;
+
+struct TIM_CNTR_s
+{
+	u32 count ;
+	u32 compare ;
+	u32 ctc ;	//use CTC_
+} ;
+
+typedef struct TIM_s
+{
+	struct TIM_CNTR_s	tim [TIM_Count] ;
+	u32			rcount ;	//use RCOUNT_
+	u32			rcompare ;	//use RCOMPARE_
+	u32			rtc ;		//use RTC_
+} volatile * TIM_t ;
+
+enum
+{
+	CTC_en_b	= 0,		
+	CTC_en_m	= 0x00000001,
+	CTC_to_b	= 1,		 
+	CTC_to_m	= 0x00000002,
+
+	RCOUNT_count_b		= 0,	     
+	RCOUNT_count_m		= 0x0000ffff,
+	RCOMPARE_compare_b	= 0,	   
+	RCOMPARE_compare_m	= 0x0000ffff,
+	RTC_ce_b		= 0,		
+	RTC_ce_m		= 0x00000001,
+	RTC_to_b		= 1,		
+	RTC_to_m		= 0x00000002,
+	RTC_rqe_b		= 2,		
+	RTC_rqe_m		= 0x00000004,
+				 
+} ;
+#endif	//__IDT_RC32438_TIM_H__
+
diff -uNr linux-2.6.16-rc5/include/asm-mips/mach-idt/irq.h idtlinux/include/asm-mips/mach-idt/irq.h
--- linux-2.6.16-rc5/include/asm-mips/mach-idt/irq.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/mach-idt/irq.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,60 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   NR_IRQS for IDT boards
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ **************************************************************************
+ */
+
+#ifndef __ASM_MACH_IDT_IRQ_H__
+#define __ASM_MACH_IDT_IRQ_H__
+#include <linux/config.h>
+
+#ifdef CONFIG_IDT_EB365
+#include <asm/idt-boards/rc32300/rc32365.h>
+#define NR_IRQS RC32365_NR_IRQS
+#endif
+
+#ifdef CONFIG_IDT_EB434
+#include <asm/idt-boards/rc32434/rc32434.h>
+#define NR_IRQS RC32434_NR_IRQS
+#endif
+
+#ifdef CONFIG_IDT_EB438
+#include <asm/idt-boards/rc32438/rc32438.h>
+#define NR_IRQS RC32438_NR_IRQS
+#endif
+
+#ifdef CONFIG_IDT_S334
+#include <asm/idt-boards/rc32300/rc32334.h>
+#define NR_IRQS RC32334_NR_IRQS
+#endif
+
+#ifdef CONFIG_IDT_EB355
+#include <asm/idt-boards/rc32300/rc32355.h>
+#define NR_IRQS RC32355_NR_IRQS
+#endif
+
+#endif //__ASM_MACH_IDT_IRQ_H__
diff -uNr linux-2.6.16-rc5/include/asm-mips/mach-idt/param.h idtlinux/include/asm-mips/mach-idt/param.h
--- linux-2.6.16-rc5/include/asm-mips/mach-idt/param.h	1969-12-31 16:00:00.000000000 -0800
+++ idtlinux/include/asm-mips/mach-idt/param.h	2006-03-09 16:26:31.000000000 -0800
@@ -0,0 +1,41 @@
+/**************************************************************************
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   HZ for IDT boards
+ *
+ *  Copyright 2006 IDT Inc. (rischelp@idt.com)
+ *         
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef __ASM_MACH_IDT_PARAM_H
+#define __ASM_MACH_IDT_PARAM_H
+#include <linux/config.h>
+#ifdef CONFIG_IDT_EB438
+#define HZ		1000
+#else
+#define HZ		100
+#endif
+
+#endif /* __ASM_MACH_IDT_PARAM_H */
diff -uNr linux-2.6.16-rc5/include/asm-mips/module.h idtlinux/include/asm-mips/module.h
--- linux-2.6.16-rc5/include/asm-mips/module.h	2006-02-27 02:56:56.000000000 -0800
+++ idtlinux/include/asm-mips/module.h	2006-03-09 16:26:31.000000000 -0800
@@ -113,6 +113,8 @@
 #define MODULE_PROC_FAMILY "RM9000 "
 #elif defined CONFIG_CPU_SB1
 #define MODULE_PROC_FAMILY "SB1 "
+#elif defined CONFIG_CPU_RC32300
+#define MODULE_PROC_FAMILY "R4X00"
 #else
 #error MODULE_PROC_FAMILY undefined for your processor configuration
 #endif
diff -uNr linux-2.6.16-rc5/include/asm-mips/serial.h idtlinux/include/asm-mips/serial.h
--- linux-2.6.16-rc5/include/asm-mips/serial.h	2006-02-27 02:56:56.000000000 -0800
+++ idtlinux/include/asm-mips/serial.h	2006-03-09 16:26:31.000000000 -0800
@@ -238,6 +238,14 @@
 #define IP32_SERIAL_PORT_DEFNS
 #endif /* CONFIG_SGI_IP32 */
 
+#if defined(CONFIG_IDT_EB438) || defined(CONFIG_IDT_EB365) || defined(CONFIG_IDT_EB434) || defined(CONFIG_IDT_S334) || defined(CONFIG_IDT_EB355)
+#define IDT_SERIAL_PORT_DEFNS \
+        {},{},
+#else
+#define IDT_SERIAL_PORT_DEFNS
+#endif
+
+
 #define SERIAL_PORT_DFNS				\
 	DDB5477_SERIAL_PORT_DEFNS			\
 	EV96100_SERIAL_PORT_DEFNS			\
diff -uNr linux-2.6.16-rc5/MAINTAINERS idtlinux/MAINTAINERS
--- linux-2.6.16-rc5/MAINTAINERS	2006-02-27 02:56:56.000000000 -0800
+++ idtlinux/MAINTAINERS	2006-03-09 16:26:34.000000000 -0800
@@ -1232,6 +1232,13 @@
 L:	linux-kernel@vger.kernel.org
 S:	Maintained
 
+IDT INTERPRISE INTEGRATED COMMUNICATION PROCESSOR SUPPORT
+P:      Rakesh Tiwari
+M:      rischelp@idt.com
+L:	rischelp@idt.com
+W:	http://www.idt.com/?catID=58532
+S:	Supported
+
 IDE/ATAPI TAPE DRIVERS
 P:	Gadi Oxman
 M:	Gadi Oxman <gadio@netvision.net.il>

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH] IDT Interprise Processor Support for Linux  2.6.x
  2006-03-10  1:08 [PATCH] IDT Interprise Processor Support for Linux 2.6.x Tiwari, Rakesh
@ 2006-03-10  5:15 ` Robin H. Johnson
  2006-03-10  9:37   ` P. Christeas
  2006-03-10 17:45 ` Chris Wedgwood
  1 sibling, 1 reply; 6+ messages in thread
From: Robin H. Johnson @ 2006-03-10  5:15 UTC (permalink / raw)
  To: linux-mips

[-- Attachment #1: Type: text/plain, Size: 818 bytes --]

On Thu, Mar 09, 2006 at 05:08:49PM -0800, Tiwari, Rakesh wrote:
> The attached patch adds support for the IDT Interprise series of processor 
> based on the MIPS 4KC and Cronus (RC32300) core.
I'm not Ralf, but I gave your patch a quick once-over anyway for the
hell of it.

I see a lot of duplicated code, esp in arch/mips/idt-boards and the
network drivers.

Is it possible to have a kernel capable of booting on all IDT boards?
Could such a kernel detect what board it's actually running on - or
enough elements of the board configuration to provide more generic
drivers?

-- 
Robin Hugh Johnson
E-Mail     : robbat2@orbis-terrarum.net
Home Page  : http://www.orbis-terrarum.net/?l=people.robbat2
ICQ#       : 30269588 or 41961639
GnuPG FP   : 11AC BA4F 4778 E3F6 E4ED  F38E B27B 944E 3488 4E85

[-- Attachment #2: Type: application/pgp-signature, Size: 241 bytes --]

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH] IDT Interprise Processor Support for Linux  2.6.x
  2006-03-10  5:15 ` Robin H. Johnson
@ 2006-03-10  9:37   ` P. Christeas
  0 siblings, 0 replies; 6+ messages in thread
From: P. Christeas @ 2006-03-10  9:37 UTC (permalink / raw)
  To: Robin H. Johnson; +Cc: linux-mips

On Friday 10 March 2006 7:15 am, Robin H. Johnson wrote:
> I'm not Ralf, but I gave your patch a quick once-over anyway for the
> hell of it.
>
> I see a lot of duplicated code, esp in arch/mips/idt-boards and the
> network drivers.
>
> Is it possible to have a kernel capable of booting on all IDT boards?
> Could such a kernel detect what board it's actually running on - or
> enough elements of the board configuration to provide more generic
> drivers?

Without going into details of the code or the hardware, I would advise against 
that. linux/arch follows that principle: separate the platform-specific code.
Even if the code is similar, it is better to separate it. Especially for such 
processors (like IDT's), which suggest that the system is embedded. We don't 
want an all-capable kernel, but the smallest one that can cover the hardware.

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH] IDT Interprise Processor Support for Linux  2.6.x
  2006-03-10  1:08 [PATCH] IDT Interprise Processor Support for Linux 2.6.x Tiwari, Rakesh
  2006-03-10  5:15 ` Robin H. Johnson
@ 2006-03-10 17:45 ` Chris Wedgwood
  1 sibling, 0 replies; 6+ messages in thread
From: Chris Wedgwood @ 2006-03-10 17:45 UTC (permalink / raw)
  To: Tiwari, Rakesh; +Cc: 'Ralf Baechle', linux-mips

Additional comments:

  * Firstly, it's really great to see this!

  * A single 1.6MB patch is far from ideal, please try to break it
    into a series of smaller logically separate patches.  It's hard to
    comment on a giant patch.  Perhaps something like:
      - a patch for each CPU
      - a patch for each driver
      - a patch for each platform/eval-board
    and see what you have left. Each patch should have a suitable
    description.  Also put "Signed-off-by:" lines on your patches.

  * You shouldn't be removing .gitignore :-)

  * The Ethernet drivers should probably go jeff@garzik.org and cc
    netdev@vger.kernel.org

  * The code contains unreferenced functions?  Without even looking
    hard I can see rc32434_mii_handler is declared and not used for
    example.

  * It might be that some of the CPU-level code should be platform
    level.  For example having two UARTs is a feature of the EB434 not
    the rc32434 so EB434_UART1_IRQ is misplaced I would argue.

  * Some init code should probably be declared __init and similar

  * There is quite a bit of extraneous white-space that could be
    cleaned up and some minor indentation cleanups to match what is
    elsewhere in the kernel.

Sorry this is a little vague and 'hand-wavy', if you post smaller
logically complete patches I think you'll get better feedback where
people can comment more easily.  Ideally inline to the email if you
can, m$ lookout/$exchange as that just makes a mess, if you have to
use that then attach them as you did.

^ permalink raw reply	[flat|nested] 6+ messages in thread

* RE: [PATCH] IDT Interprise Processor Support for Linux  2.6.x
@ 2006-03-10 18:20 Tiwari, Rakesh
  0 siblings, 0 replies; 6+ messages in thread
From: Tiwari, Rakesh @ 2006-03-10 18:20 UTC (permalink / raw)
  To: 'Robin H. Johnson', linux-mips

[-- Attachment #1: Type: text/plain, Size: 1703 bytes --]

Hi Robin,

Thanks for reviewing the patch. 

I like your idea of having a single kernel which can boot on any board
and also agree with you that code duplication is not a good thing.

However, based on our customer's feedback so far, we prefer to keep it
separate
for each board, so that code doesn't get to messy or people don't have to
look at unwanted code. 

Also since IDT's processors are SoC's and do undergo various rev's for the
chips,
in which certain feature (hardware) are fixed/removed/added. In this case
having
a separate directory (at the cost of code duplication) is easier to
maintain.

Regards
Rakesh

-----Original Message-----
From: linux-mips-bounce@linux-mips.org
[mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Robin H. Johnson
Sent: Thursday, March 09, 2006 9:15 PM
To: linux-mips@linux-mips.org
Subject: Re: [PATCH] IDT Interprise Processor Support for Linux 2.6.x

On Thu, Mar 09, 2006 at 05:08:49PM -0800, Tiwari, Rakesh wrote:
> The attached patch adds support for the IDT Interprise series of 
> processor
> based on the MIPS 4KC and Cronus (RC32300) core.
I'm not Ralf, but I gave your patch a quick once-over anyway for the hell of
it.

I see a lot of duplicated code, esp in arch/mips/idt-boards and the network
drivers.

Is it possible to have a kernel capable of booting on all IDT boards? Could
such a kernel detect what board it's actually running on - or enough
elements of the board configuration to provide more generic drivers?

-- 
Robin Hugh Johnson
E-Mail     : robbat2@orbis-terrarum.net
Home Page  : http://www.orbis-terrarum.net/?l=people.robbat2
ICQ#       : 30269588 or 41961639
GnuPG FP   : 11AC BA4F 4778 E3F6 E4ED  F38E B27B 944E 3488 4E85

[-- Attachment #2: Type: text/html, Size: 3074 bytes --]

^ permalink raw reply	[flat|nested] 6+ messages in thread

* RE: [PATCH] IDT Interprise Processor Support for Linux  2.6.x
@ 2006-03-13 21:06 Tiwari, Rakesh
  0 siblings, 0 replies; 6+ messages in thread
From: Tiwari, Rakesh @ 2006-03-13 21:06 UTC (permalink / raw)
  To: 'Chris Wedgwood', Tiwari, Rakesh
  Cc: 'Ralf Baechle', linux-mips

[-- Attachment #1: Type: text/plain, Size: 2796 bytes --]

Hi Chris,

Appreciate your feedback.
Please see my comments below, inline prefixed by [rkt]

Look forward for additional comments/suggestions, if any.

Thanks
Rakesh


-----Original Message-----
From: Chris Wedgwood [mailto:cw@f00f.org <mailto:cw@f00f.org> ] 
Sent: Friday, March 10, 2006 9:46 AM
To: Tiwari, Rakesh
Cc: 'Ralf Baechle'; linux-mips@linux-mips.org
Subject: Re: [PATCH] IDT Interprise Processor Support for Linux 2.6.x


Additional comments:

  * Firstly, it's really great to see this!

  * A single 1.6MB patch is far from ideal, please try to break it
    into a series of smaller logically separate patches.  It's hard to
    comment on a giant patch.  Perhaps something like:
      - a patch for each CPU
      - a patch for each driver
      - a patch for each platform/eval-board
    and see what you have left. Each patch should have a suitable
    description.  Also put "Signed-off-by:" lines on your patches.

    [rkt] Agreed, 1.6MB is a huge patch. I will try to break it down into
          multiple patches (ard 5) based on platform/eval board and will
          send it out soon.

  * You shouldn't be removing .gitignore :-)

    [rkt] I think these are still there.
 	
  * The Ethernet drivers should probably go jeff@garzik.org and cc
    netdev@vger.kernel.org

    [rkt] The Ethernet interface/driver is integral to each processor
    and dependent upon other system header files, unlike a regular NIC.
    I can try posting the patches (probably sub-patch) to Jeff and netdev,
    in order to get feedback on the driver.

	
  * The code contains unreferenced functions?  Without even looking
    hard I can see rc32434_mii_handler is declared and not used for
    example.

    [rkt] Chris you hit the bulls eye. This is the only function which
    I missed out... Will clean it up.
	
  * It might be that some of the CPU-level code should be platform
    level.  For example having two UARTs is a feature of the EB434 not
    the rc32434 so EB434_UART1_IRQ is misplaced I would argue.

    [rkt] Since all the IDT's processors are primarily SoC's, the UARTS are
     part of the processor. In case on rc32434 there is only 1 UART. However
     rc32438 has 2 UARTS

 	
  * Some init code should probably be declared __init and similar

  * There is quite a bit of extraneous white-space that could be
    cleaned up and some minor indentation cleanups to match what is
    elsewhere in the kernel.

   [rkt] Will try to clean up as much as possible...

Sorry this is a little vague and 'hand-wavy', if you post smaller logically
complete patches I think you'll get better feedback where people can comment
more easily.  Ideally inline to the email if you can, m$ lookout/$exchange
as that just makes a mess, if you have to use that then attach them as you
did.

[-- Attachment #2: Type: text/html, Size: 6295 bytes --]

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2006-03-13 20:58 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2006-03-10  1:08 [PATCH] IDT Interprise Processor Support for Linux 2.6.x Tiwari, Rakesh
2006-03-10  5:15 ` Robin H. Johnson
2006-03-10  9:37   ` P. Christeas
2006-03-10 17:45 ` Chris Wedgwood
  -- strict thread matches above, loose matches on Subject: below --
2006-03-10 18:20 Tiwari, Rakesh
2006-03-13 21:06 Tiwari, Rakesh

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox