From: Thiemo Seufer <ths@networkno.de>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Subject: Re: [PATCH] fix interrupt handling for R2 CPUs
Date: Tue, 16 May 2006 18:55:08 +0100 [thread overview]
Message-ID: <20060516175508.GH11370@networkno.de> (raw)
In-Reply-To: <20060516174848.GA30064@linux-mips.org>
Ralf Baechle wrote:
> On Mon, May 15, 2006 at 06:27:47PM +0100, Thiemo Seufer wrote:
>
> > a) only the low bit is used for status flags if CONFIG_CPU_MIPSR2,
> > consistent with the use of di/ei.
> >
> > b) the ERL/EXL bits get cleared as well.
>
> Does this patch make a difference for you anywhere?
It fixes a MIPS32R2-compiled qemu kernel for me which broke when the
new bitfield instructions were added.
Thiemo
prev parent reply other threads:[~2006-05-16 17:55 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-05-15 17:27 [PATCH] fix interrupt handling for R2 CPUs Thiemo Seufer
2006-05-16 17:48 ` Ralf Baechle
2006-05-16 17:55 ` Thiemo Seufer [this message]
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