Re: [PATCH] fix cache coherency issues

[Ralf Baechle <ralf@linux-mips.org>]

On Thu, Aug 24, 2006 at 08:38:38PM +0900, Atsushi Nemoto wrote:
> Date:	Thu, 24 Aug 2006 20:38:38 +0900 (JST)
> To:	ralf@linux-mips.org
> Cc:	nigel@mips.com, linux-mips@linux-mips.org
> Subject: Re: [PATCH] fix cache coherency issues
> From:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
> Content-Type: Text/Plain; charset=us-ascii
> 
> On Thu, 24 Aug 2006 12:15:15 +0100, Ralf Baechle <ralf@linux-mips.org> wrote:
> > Your patch also still contains copy_user_page().  The only user of it used
> > to be copy_user_highpage() so after our rewrite it can go away.  I've
> > already applied both fixes to my working version of the patch.
> 
> Yes, it is intentional.  I keep copy_user_page() just because it is
> described in cachetlb.txt and exported.
> 
> Of course we can remove it.  I do not care :-) Also I wondered we
> should export copy_user_highpage() or not ...
> 
> > Your patch only maps the source page.  I'm trying to map the destination
> > page also and I'm hitting a few issues with it.
> 
> If you wanted to map the destination, you must writeback the dcache
> via kernel mapping first.  The dcache can contain dirty data for the
> page by previous usage.  And if the page was executable, we must flush
> the destination page after copy_page() (via coherent mapping) anyway
> for I/D coherency.
> 
> So now I think mapping the destination is not worth to do.

I figured it was worth a try.  It means the process will start running with
a hot copy of the COW page instead of a cold copy and I can use hit
invalidates instead of hit wbinv on the kernel address of the to page.

Lmbenching now, stay tuned ...

  Ralf