How to emulate lw/sw instruction by lb/sb instruction

How to emulate lw/sw instruction by lb/sb instruction

[william_lei]

Dear all
      Could someone tell me how to modify GCC as titled?because we have met
problem while porting some middleware,which will generate some lw/sw
instruction to unaligned address,so I would modify GCC to not generate
lw/sw instructions for this pieces code.
Regards
William Lei

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Re: How to emulate lw/sw instruction by lb/sb instruction

[Florian Fainelli]

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Hi William,

As far as I know, there is the nonmips project [1] which is providing a 
toolchain for mips clones such as the Lexra 5280 we can find in Realtek 865x 
SoC for instance. This SoC does not have lw/sw instruction set.

The Realtek 8181 project also provide a patch to emulate those instructions by 
the kernel, see [2].

Hope this helps !

[1] http://nonmips.sourceforge.net/
[2] http://rtl8181.sourceforge.net/


Le lundi 25 septembre 2006 02:41, william_lei@ali.com.tw a écrit :
> Dear all
>       Could someone tell me how to modify GCC as titled?because we have met
> problem while porting some middleware,which will generate some lw/sw
> instruction to unaligned address,so I would modify GCC to not generate
> lw/sw instructions for this pieces code.
> Regards
> William Lei
>
> ************* Email Confidentiality Notice ********************
>
> The information contained in this e-mail message (including any
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Re: How to emulate lw/sw instruction by lb/sb instruction

[Ulrich Eckhardt]

On Monday 25 September 2006 02:41, william_lei@ali.com.tw wrote:
> Could someone tell me how to modify GCC as titled?because we have met
> problem while porting some middleware,which will generate some lw/sw
> instruction to unaligned address,so I would modify GCC to not generate
> lw/sw instructions for this pieces code.

I'm not exactly sure what problem you are facing but if I understand you 
correctly and you have code that simply does misaligned accesses, you would 
be better off fixing the code. The reason is that such unaligned accesses 
would have to be emulated with bytewise access and combining/dissecting the 
values accordingly, which hurts performance (processing and cache). Even when 
run on x86 (where such accesses don't cause bus errors) this would be the 
better choice, because even there these are emulated in hardware and only 
cause hidden performance losses.

Other than that, I would rather filter the output of GCC, i.e. use -S (or what 
it was) to generate assembler code and then replace the lw/sw instructions 
via your $FAVOURITE_TEXTPROCESSING_TOOL in the affected files. Most other 
software isn't that broken and would only suffer from such changes.

Thinking about it, I believe there is also a way (some __attribute__) to tell 
GCC that some pointer is not aligned and it will then output suitable code 
for unaligned accesses. This requires changes to the generated sourcecode 
though, but would be a rather clean solution because it would work on other 
platforms, too.

Just wondering, what middleware are you talking about?

Uli


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Re: How to emulate lw/sw instruction by lb/sb instruction

[Ralf Baechle]

On Mon, Sep 25, 2006 at 08:41:53AM +0800, william_lei@ali.com.tw wrote:

> Dear all
>       Could someone tell me how to modify GCC as titled?because we have met
> problem while porting some middleware,which will generate some lw/sw
> instruction to unaligned address,so I would modify GCC to not generate
> lw/sw instructions for this pieces code.

You can use gcc's __attribute__((packed)) to define a data structure
that does not have any alignment gaps in it.  Gcc will then use unaligned
loads and stores to access this structure.  This however is a kludge, for
best performance you should redefine the data structures your code is
working to avoid such missalignment.

Otoh if the miss-alignment case is rare only then you may actually be
better off by relying on the kernel's handling of this case.

  Ralf

Re: How to emulate lw/sw instruction by lb/sb instruction

[william_lei]

Dear Kevin
      Because there are some aligned instruction will load/store from/to
unaligned base address in some module,such as "lw t0,56(sp)  ##sp is odd
address"
that's why I want some special version GCC can avoid generating load/store
4 bytes opcode,then I can use this "GCC" to compile specified module and
linked with others,it will avoid unnecessary exception processing when
these instruction to be invoked and come up with best performance for me.
Regards
William Lei


|---------+---------------------------->
|         |           "Kevin D.        |
|         |           Kissell"         |
|         |           <kevink@mips.com>|
|         |                            |
|         |                            |
|         |           2006-09-25 16:42 |
|---------+---------------------------->
  >------------------------------------------------------------------------------------------------------------------------------|
  |                                                                                                                              |
  |       To:       <linux-mips@linux-mips.org>, <william_lei@ali.com.tw>                                                        |
  |       cc:                                                                                                                    |
  |       Subject:  Re: How to emulate lw/sw instruction by lb/sb instruction                                                    |
  >------------------------------------------------------------------------------------------------------------------------------|





The MIPS Linux kernel is capable of handling unalgined loads and
stores in emulation.  This is less efficient than synthesizing the word
access out of byte or left/right load/store operations in-line, but it's
only done when there really is an unaligned access, whereas forcing
the compiler to synthesize *all* loads/stores adds that overhead
even when the addresses are actually aligned.

            Regards,

            Kevin K.

----- Original Message -----
From: <william_lei@ali.com.tw>
To: <linux-mips@linux-mips.org>
Sent: Monday, September 25, 2006 2:41 AM
Subject: How to emulate lw/sw instruction by lb/sb instruction


> Dear all
>       Could someone tell me how to modify GCC as titled?because we have
met
> problem while porting some middleware,which will generate some lw/sw
> instruction to unaligned address,so I would modify GCC to not generate
> lw/sw instructions for this pieces code.
> Regards
> William Lei
>
> ************* Email Confidentiality Notice ********************
>
> The information contained in this e-mail message (including any
> attachments) may be confidential, proprietary, privileged, or otherwise
> exempt from disclosure under applicable laws. It is intended to be
conveyed
> only to the designated recipient(s). Any use, dissemination,
distribution,
> printing, retaining or copying of this e-mail (including its attachments)
> by unintended recipient(s) is strictly prohibited and may be unlawful. If
> you are not an intended recipient of this e-mail, or believe that you
have
> received this e-mail in error, please notify the sender immediately (by
> replying to this e-mail), delete any and all copies of this e-mail
> (including any attachments) from your system, and do not disclose the
> content of this e-mail to any other person. Thank you!
>
>
>
>

Re: How to emulate lw/sw instruction by lb/sb instruction

[Maciej W. Rozycki]

On Mon, 25 Sep 2006, william_lei@ali.com.tw wrote:

>       Because there are some aligned instruction will load/store from/to
> unaligned base address in some module,such as "lw t0,56(sp)  ##sp is odd
> address"

 Hmm, the stack at an odd address -- somebody must be in the hard joking 
mood...

  Maciej

Re: How to emulate lw/sw instruction by lb/sb instruction

[Jim Wilson]

On Mon, 2006-09-25 at 18:35 +0800, william_lei@ali.com.tw wrote:
>       Because there are some aligned instruction will load/store from/to
> unaligned base address in some module,such as "lw t0,56(sp)  ##sp is odd
> address"

You are better off fixing your code.  SP must always be aligned to an 8
byte boundary minimum, 16 bytes for the New ABIs.

Changing gcc would be difficult, and it isn't even clear if such a
change can be made to work.  If it is possible, the resulting code will
likely be so bad as to be nearly useless.
-- 
Jim Wilson, GNU Tools Support, http://www.specifix.com