From: Ralf Baechle <ralf@linux-mips.org>
To: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Cc: linux-mips <linux-mips@linux-mips.org>
Subject: Re: [PATCH][MIPS] merge GT64111 PCI routines and GT64120 PCI_0 routines
Date: Wed, 14 Mar 2007 13:45:12 +0000 [thread overview]
Message-ID: <20070314134511.GA24290@linux-mips.org> (raw)
In-Reply-To: <20070314215126.72d21e96.yoichi_yuasa@tripeaks.co.jp>
On Wed, Mar 14, 2007 at 09:51:26PM +0900, Yoichi Yuasa wrote:
> This patch has merged GT64111 PCI routines and GT64120 PCI_0 routines.
> GT64111 PCI is almost the same as GT64120's PCI_0.
> This patch don't change GT64120 PCI routines.
>
> This patch tested on Cobalt Qube2.
>
> Please queue for 2.6.22.
Will do.
This sort of cleanup is something I meant to do for a long time. We have
other fairly similar chips such as the GT-64240 used in the Ocelot G and
the GT-64340 used in the Ocelot 3 which both are supported by
arch/mips/pci/ops-marvell.c. There are many other PCI busses which are
virtually identical.
Thanks,
Ralf
next prev parent reply other threads:[~2007-03-14 13:47 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-03-14 12:51 [PATCH][MIPS] merge GT64111 PCI routines and GT64120 PCI_0 routines Yoichi Yuasa
2007-03-14 13:45 ` Ralf Baechle [this message]
2007-03-16 7:31 ` Yoichi Yuasa
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