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From: Ralf Baechle <ralf@linux-mips.org>
To: yshi <yang.shi@windriver.com>
Cc: linux-mips@linux-mips.org
Subject: Re: [PATCH] malta4kec hang in calibrate_delay fix
Date: Tue, 4 Sep 2007 13:44:45 +0100	[thread overview]
Message-ID: <20070904124444.GB23736@linux-mips.org> (raw)
In-Reply-To: <46DD1CD1.5040306@windriver.com>

On Tue, Sep 04, 2007 at 04:52:33PM +0800, yshi wrote:

> perfmon2 patch changed timer interrupt handler of malta board.
> When kernel handles timer interrupt, interrupt handler will read 30 bit
> of cause register. If this bit is zero, timer interrupt handler will
> exit, won't really handle interrupt. Because Malta 4kec board's core
> revision is CoreFPGA-3, this core's cause register doesn't implement 30
> bit, so kernel always read zero from this bit. This will cause kernel
> hang in calibrate_delay.

You seem to have defined cpu_has_mips_r2 as 1 in your cpu_features_override.h
file.  Classic cut'n'paste error I'd guess :-)

  Ralf

  parent reply	other threads:[~2007-09-04 12:44 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2007-09-04  8:52 [PATCH] malta4kec hang in calibrate_delay fix yshi
2007-09-04 10:03 ` Kevin D. Kissell
2007-09-04 10:03   ` Kevin D. Kissell
2007-09-04 10:32   ` yshi
2007-09-04 11:21     ` Kevin D. Kissell
2007-09-04 11:21       ` Kevin D. Kissell
2007-09-04 11:33       ` Thomas Bogendoerfer
2007-09-04 11:47         ` Kevin D. Kissell
2007-09-04 11:47           ` Kevin D. Kissell
2007-09-04 11:55       ` Thiemo Seufer
2007-09-04 12:04         ` Nigel Stephens
2007-09-04 12:19           ` Kevin D. Kissell
2007-09-04 12:19             ` Kevin D. Kissell
2007-09-04 12:42             ` Thiemo Seufer
2007-09-04 12:44 ` Ralf Baechle [this message]
2007-09-05  5:51   ` yshi
2007-09-05 10:49     ` Chris Dearman

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