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From: "Kevin D. Kissell" <kevink@mips.com>
To: "Thomas Bogendoerfer" <tsbogend@alpha.franken.de>
Cc: "yshi" <yang.shi@windriver.com>, <linux-mips@linux-mips.org>
Subject: Re: [PATCH] malta4kec hang in calibrate_delay fix
Date: Tue, 4 Sep 2007 13:47:53 +0200	[thread overview]
Message-ID: <009201c7eee9$6ea3d5d0$10eca8c0@grendel> (raw)
In-Reply-To: 20070904113325.GA6904@alpha.franken.de

> > In that case, your core is a 4Kc and not a 4KEc.  The "r2" value in the
> 
> does that mean all 4KEc must support MIPS32R2 ? TI claims to use
> an 4KEc core for their AR7/UR8 SoCs, but they only support MIPS32R1.

There are two main differences between the 4K and the 4KE:  Write-back
caches and MIPS32R2.  I honestly don't know if it's possible to synthesise
a 4KE so as to inhibit the MIPS32R2 features, but it would be a surprising
thing to do.  I have no idea what TI actually does, but I could imagine,
hypothetically, a customer who had done a design based around the original
4K, and who upgraded it to the 4KE, deciding not to upgrade their chip-level
testing to cover the Release 2 features, and therefore not wanting to guarantee
them for their customers.  These things happen.  But, again, I have no idea what
TI actually does.  I *do* know that the 4KE is a Release 2 part.

            Regards,

            Kevin K.

WARNING: multiple messages have this Message-ID (diff)
From: "Kevin D. Kissell" <kevink@mips.com>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: yshi <yang.shi@windriver.com>, linux-mips@linux-mips.org
Subject: Re: [PATCH] malta4kec hang in calibrate_delay fix
Date: Tue, 4 Sep 2007 13:47:53 +0200	[thread overview]
Message-ID: <009201c7eee9$6ea3d5d0$10eca8c0@grendel> (raw)
Message-ID: <20070904114753.mwTIj8MGwYISjr395bCjH8Wmh_pnowpxBjoo2se5jpA@z> (raw)
In-Reply-To: 20070904113325.GA6904@alpha.franken.de

> > In that case, your core is a 4Kc and not a 4KEc.  The "r2" value in the
> 
> does that mean all 4KEc must support MIPS32R2 ? TI claims to use
> an 4KEc core for their AR7/UR8 SoCs, but they only support MIPS32R1.

There are two main differences between the 4K and the 4KE:  Write-back
caches and MIPS32R2.  I honestly don't know if it's possible to synthesise
a 4KE so as to inhibit the MIPS32R2 features, but it would be a surprising
thing to do.  I have no idea what TI actually does, but I could imagine,
hypothetically, a customer who had done a design based around the original
4K, and who upgraded it to the 4KE, deciding not to upgrade their chip-level
testing to cover the Release 2 features, and therefore not wanting to guarantee
them for their customers.  These things happen.  But, again, I have no idea what
TI actually does.  I *do* know that the 4KE is a Release 2 part.

            Regards,

            Kevin K.

  reply	other threads:[~2007-09-04 11:55 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2007-09-04  8:52 [PATCH] malta4kec hang in calibrate_delay fix yshi
2007-09-04 10:03 ` Kevin D. Kissell
2007-09-04 10:03   ` Kevin D. Kissell
2007-09-04 10:32   ` yshi
2007-09-04 11:21     ` Kevin D. Kissell
2007-09-04 11:21       ` Kevin D. Kissell
2007-09-04 11:33       ` Thomas Bogendoerfer
2007-09-04 11:47         ` Kevin D. Kissell [this message]
2007-09-04 11:47           ` Kevin D. Kissell
2007-09-04 11:55       ` Thiemo Seufer
2007-09-04 12:04         ` Nigel Stephens
2007-09-04 12:19           ` Kevin D. Kissell
2007-09-04 12:19             ` Kevin D. Kissell
2007-09-04 12:42             ` Thiemo Seufer
2007-09-04 12:44 ` Ralf Baechle
2007-09-05  5:51   ` yshi
2007-09-05 10:49     ` Chris Dearman

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