GCC 3.4.5 and mftc0

GCC 3.4.5 and mftc0

[Mikael Starvik]

mftc0() is implemented as
 
 .word ...
  move %0, $1

With at least gcc 3.4.5 the move is implemented as an addu %0, $1, $0.
But in the MIPS sumulator this fails and %0 gets the value 0xffffffff.
Implementing this as a or %0, $1, $0 instead gives the expected result.

Any suggestions where the problem is and what the correct solution is?

After fixing this my next problem is that IPIs doesn't reach all TCs
correctly (it seams like the code doesn't detect IXMT status correctly,
but I am still investigating). It is likely that it is caused by
something similar to the problem above.

Regards
/Mikael

GCC 3.4.5 and mftc0

[Mikael Starvik]

mftc0() is implemented as
 
 .word ...
  move %0, $1

With at least gcc 3.4.5 the move is implemented as an addu %0, $1, $0.
But in the MIPS sumulator this fails and %0 gets the value 0xffffffff.
Implementing this as a or %0, $1, $0 instead gives the expected result.

Any suggestions where the problem is and what the correct solution is?

After fixing this my next problem is that IPIs doesn't reach all TCs
correctly (it seams like the code doesn't detect IXMT status correctly,
but I am still investigating). It is likely that it is caused by
something similar to the problem above.

Regards
/Mikael

Re: GCC 3.4.5 and mftc0

[Ralf Baechle]

On Fri, Dec 14, 2007 at 10:49:40AM +0100, Mikael Starvik wrote:

> mftc0() is implemented as
>  
>  .word ...
>   move %0, $1
> 
> With at least gcc 3.4.5 the move is implemented as an addu %0, $1, $0.
> But in the MIPS sumulator this fails and %0 gets the value 0xffffffff.
> Implementing this as a or %0, $1, $0 instead gives the expected result.

I wonder what "sumulator" you're using ...

Addu is a perfectly fine implementation of move for 32-bit code.  It's not
for 64-bit code but that's beside the point here.  The or method is also
correct but historically the add instruction has been prefered, also
because some processor - the R4300 afair - processes arithmetic instructions
(add, sub that is not mul / div) faster than logic operations.

> Any suggestions where the problem is and what the correct solution is?

Fix the sumulator.

> After fixing this my next problem is that IPIs doesn't reach all TCs
> correctly (it seams like the code doesn't detect IXMT status correctly,
> but I am still investigating). It is likely that it is caused by
> something similar to the problem above.

The code certainly works on real silicon, so the cause must be something
local to your environment.

Cheers,

  Ralf

RE: GCC 3.4.5 and mftc0

[Mikael Starvik]

Thanks!

and sorry for the spelling of simulator.

/Mikael

-----Original Message-----
From: Ralf Baechle [mailto:ralf@linux-mips.org] 
Sent: Friday, December 14, 2007 5:26 PM
To: Mikael Starvik
Cc: linux-mips@linux-mips.org
Subject: Re: GCC 3.4.5 and mftc0


On Fri, Dec 14, 2007 at 10:49:40AM +0100, Mikael Starvik wrote:

> mftc0() is implemented as
>  
>  .word ...
>   move %0, $1
> 
> With at least gcc 3.4.5 the move is implemented as an addu %0, $1, $0.
> But in the MIPS sumulator this fails and %0 gets the value 0xffffffff.
> Implementing this as a or %0, $1, $0 instead gives the expected result.

I wonder what "sumulator" you're using ...

Addu is a perfectly fine implementation of move for 32-bit code.  It's not
for 64-bit code but that's beside the point here.  The or method is also
correct but historically the add instruction has been prefered, also
because some processor - the R4300 afair - processes arithmetic instructions
(add, sub that is not mul / div) faster than logic operations.

> Any suggestions where the problem is and what the correct solution is?

Fix the sumulator.

> After fixing this my next problem is that IPIs doesn't reach all TCs
> correctly (it seams like the code doesn't detect IXMT status correctly,
> but I am still investigating). It is likely that it is caused by
> something similar to the problem above.

The code certainly works on real silicon, so the cause must be something
local to your environment.

Cheers,

  Ralf

RE: GCC 3.4.5 and mftc0

[Mikael Starvik]

Thanks!

and sorry for the spelling of simulator.

/Mikael

-----Original Message-----
From: Ralf Baechle [mailto:ralf@linux-mips.org] 
Sent: Friday, December 14, 2007 5:26 PM
To: Mikael Starvik
Cc: linux-mips@linux-mips.org
Subject: Re: GCC 3.4.5 and mftc0


On Fri, Dec 14, 2007 at 10:49:40AM +0100, Mikael Starvik wrote:

> mftc0() is implemented as
>  
>  .word ...
>   move %0, $1
> 
> With at least gcc 3.4.5 the move is implemented as an addu %0, $1, $0.
> But in the MIPS sumulator this fails and %0 gets the value 0xffffffff.
> Implementing this as a or %0, $1, $0 instead gives the expected result.

I wonder what "sumulator" you're using ...

Addu is a perfectly fine implementation of move for 32-bit code.  It's not
for 64-bit code but that's beside the point here.  The or method is also
correct but historically the add instruction has been prefered, also
because some processor - the R4300 afair - processes arithmetic instructions
(add, sub that is not mul / div) faster than logic operations.

> Any suggestions where the problem is and what the correct solution is?

Fix the sumulator.

> After fixing this my next problem is that IPIs doesn't reach all TCs
> correctly (it seams like the code doesn't detect IXMT status correctly,
> but I am still investigating). It is likely that it is caused by
> something similar to the problem above.

The code certainly works on real silicon, so the cause must be something
local to your environment.

Cheers,

  Ralf