[PATCH] IP22: Fix crashes due to wrong L1_CACHE_BYTES

[PATCH] IP22: Fix crashes due to wrong L1_CACHE_BYTES

[Thomas Bogendoerfer]

The introduction of a real dma cache invalidate makes it important
to have a correct cache line size, otherwise the kernel will gives
out two memory segment, which might share one cache line. The R4400
Indy/Indigo2 CPU modules are using a second level cache line size
of 128 bytes, so MIPS_L1_CACHE_SHIFT needs to be bumped up to 7 for
IP22.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e5a7c5d..24c5dee 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1006,7 +1006,7 @@ config BOOT_ELF32
 config MIPS_L1_CACHE_SHIFT
 	int
 	default "4" if MACH_DECSTATION
-	default "7" if SGI_IP27 || SGI_IP28 || SNI_RM
+	default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM
 	default "4" if PMC_MSP4200_EVAL
 	default "5"
 

Re: [PATCH] IP22: Fix crashes due to wrong L1_CACHE_BYTES

[Ralf Baechle]

On Fri, Jun 27, 2008 at 11:52:26PM +0200, Thomas Bogendoerfer wrote:

> The introduction of a real dma cache invalidate makes it important
> to have a correct cache line size, otherwise the kernel will gives
> out two memory segment, which might share one cache line. The R4400
> Indy/Indigo2 CPU modules are using a second level cache line size
> of 128 bytes, so MIPS_L1_CACHE_SHIFT needs to be bumped up to 7 for
> IP22.

Thanks, applied.

I also think this missconfiguration is worth an additional runtime
check; the consequence of that kind of bug are subtle and painful to
debug.

  Ralf