Re: [PATCH 26/30] loongson: flush irq write operation

[Ralf Baechle <ralf@linux-mips.org>]

On Tue, May 19, 2009 at 10:37:17AM +0800, yanh wrote:

> > The semantic of inX() / outX() is defined by the x86 architecture which
> > forbids posting I/O port writes.  In short I think this one is papering
> > over a bug in the outX() implementation.
> Yes, the outX should do a delayed write, however it does not. 
> So our solution is making a read to flush the write.

Do you actually need all the inb() you added to get things to work or is

diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index 01c0885..42d75d7 100644
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -177,10 +177,12 @@ handle_real_irq:
 		outb(cached_slave_mask, PIC_SLAVE_IMR);
 		outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
 		outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
+		inb(PIC_MASTER_CMD);
 	} else {
 		inb(PIC_MASTER_IMR);	/* DUMMY - (do we need this?) */
 		outb(cached_master_mask, PIC_MASTER_IMR);
 		outb(0x60+irq, PIC_MASTER_CMD);	/* 'Specific EOI to master */
+		inb(PIC_MASTER_CMD);
 	}
 	smtc_im_ack_irq(irq);
 	spin_unlock_irqrestore(&i8259A_lock, flags);

sufficient to solve the problem?

  Ralf