From: Ralf Baechle <ralf@linux-mips.org>
To: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips <linux-mips@linux-mips.org>
Subject: Re: [PATCH 0/6] MIPS Read Inhibit/eXecute Inhibit support (v2).
Date: Thu, 11 Feb 2010 00:56:49 +0100 [thread overview]
Message-ID: <20100210235649.GA7975@linux-mips.org> (raw)
In-Reply-To: <4B733C71.8030304@caviumnetworks.com>
On Wed, Feb 10, 2010 at 03:08:33PM -0800, David Daney wrote:
> This patch set adds execute and read inhibit support. By default glibc
> based tool chains will create mappings for data areas of a program and
> shared libraries with PROT_EXEC cleared. With this patch applied, a
> SIGSEGV is correctly sent if an attempt is made to execute from data
> areas.
>
> The first three patch just make a few tweaks in preperation for the
> main body of the patch in 4/6. The last two turn on the feature for
> some Octeon CPUs.
>
> I will reply with the six patches.
>
> David Daney (6):
> MIPS: Use 64-bit stores to c0_entrylo on 64-bit kernels.
> MIPS: Add accessor functions and bit definitions for c0_PageGrain
> MIPS: Add TLBR and ROTR to uasm.
> MIPS: Implement Read Inhibit/eXecute Inhibit
> MIPS: Give Octeon+ CPUs their own cputype.
> MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUs
Hangs on IP27 after
[...]
Calibrating delay loop... 178.17 BogoMIPS (lpj=89088)
Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
Ralf
next prev parent reply other threads:[~2010-02-10 23:56 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-02-10 23:08 [PATCH 0/6] MIPS Read Inhibit/eXecute Inhibit support (v2) David Daney
2010-02-10 23:12 ` [PATCH 1/6] MIPS: Use 64-bit stores to c0_entrylo on 64-bit kernels David Daney
2010-02-10 23:12 ` [PATCH 2/6] MIPS: Add accessor functions and bit definitions for c0_PageGrain David Daney
2010-02-10 23:12 ` [PATCH 3/6] MIPS: Add TLBR and ROTR to uasm David Daney
2010-02-10 23:12 ` [PATCH 4/6] MIPS: Implement Read Inhibit/eXecute Inhibit David Daney
2010-02-14 20:16 ` Manuel Lauss
2010-02-15 1:17 ` David Daney
2010-02-15 2:08 ` David Daney
2010-02-15 17:34 ` Manuel Lauss
2010-02-15 17:38 ` David Daney
2010-02-10 23:12 ` [PATCH 5/6] MIPS: Give Octeon+ CPUs their own cputype David Daney
2010-02-10 23:12 ` [PATCH 6/6] MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUs David Daney
2010-02-10 23:56 ` Ralf Baechle [this message]
2010-02-11 0:53 ` [PATCH 0/6] MIPS Read Inhibit/eXecute Inhibit support (v2) David Daney
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20100210235649.GA7975@linux-mips.org \
--to=ralf@linux-mips.org \
--cc=ddaney@caviumnetworks.com \
--cc=linux-mips@linux-mips.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox