From: David Daney <david.s.daney@gmail.com>
To: Manuel Lauss <manuel.lauss@googlemail.com>
Cc: David Daney <ddaney@caviumnetworks.com>,
linux-mips@linux-mips.org, ralf@linux-mips.org
Subject: Re: [PATCH 4/6] MIPS: Implement Read Inhibit/eXecute Inhibit
Date: Sun, 14 Feb 2010 18:08:23 -0800 [thread overview]
Message-ID: <4B78AC97.8030404@gmail.com> (raw)
In-Reply-To: <4B78A0C1.1070509@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 3260 bytes --]
On 02/14/2010 05:17 PM, David Daney wrote:
> On 02/14/2010 12:16 PM, Manuel Lauss wrote:
>> Hi David,
>>
>> this patch breaks my Alchemy builds:
>>
>> Using /mnt/data/_home/mano/db1200/kernel/linux-2.6.git as source for
>> kernel
>> GEN /mnt/data/_home/mano/db1200/kernel/kbuild-linux-2.6.git/Makefile
>> CHK include/linux/version.h
>> CHK include/generated/utsrelease.h
>> UPD include/generated/utsrelease.h
>> CC arch/mips/kernel/asm-offsets.s
>> In file included from
>> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/io.h:25,
>>
>> from
>> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/page.h:46,
>>
>> from
>> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/include/linux/mm_types.h:15,
>>
>> from
>> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/include/linux/sched.h:63,
>>
>> from
>> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/kernel/asm-offsets.c:13:
>>
>> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:
>>
>> In function 'pte_to_entrylo':
>> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:146:
>>
>> error: '_PAGE_NO_READ_SHIFT' undeclared (first use in this function)
>> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:146:
>>
>> error: (Each undeclared identifier is reported only once
>> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:146:
>>
>> error: for each function it appears in.)
>> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:155:
>>
>> error: '_PAGE_GLOBAL_SHIFT' undeclared (first use in this function)
>> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:156:
>>
>> error: '_PAGE_NO_EXEC' undeclared (first use in this function)
>> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:156:
>>
>> error: '_PAGE_NO_READ' undeclared (first use in this function)
>> In file included from
>> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/include/linux/mm.h:39,
>> from
>> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/kernel/asm-offsets.c:14:
>>
>> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable.h:
>>
>> In function 'pte_modify':
>> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable.h:351:
>>
>> error: '_PFN_MASK' undeclared (first use in this function)
>> make[2]: *** [arch/mips/kernel/asm-offsets.s] Error 1
>> make[1]: *** [prepare0] Error 2
>> make: *** [sub-make] Error 2
> Whoops! I will endeavor to fix this.
Try the attached patch, it allows me to build an au1000 kernel. But
since I don't have harware, I cannot test it.
I started with pb1500_defconfig, but had to disable au1000_eth.c:
drivers/net/au1000_eth.c: In function ‘au1000_probe’:
drivers/net/au1000_eth.c:1009: error: implicit declaration of function
‘DECLARE_MAC_BUF’
drivers/net/au1000_eth.c:1009: error: ‘ethaddr’ undeclared (first use in
this function)
drivers/net/au1000_eth.c:1009: error: (Each undeclared identifier is
reported only once
drivers/net/au1000_eth.c:1009: error: for each function it appears in.)
David Daney.
[-- Attachment #2: dd.patch --]
[-- Type: text/plain, Size: 1740 bytes --]
MIPS: Fix RIXI patch for au1000 processors.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/include/asm/pgtable-bits.h | 20 +++++++++++++++-----
1 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index a2e646f..47ca734 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -66,7 +66,6 @@
#define _PAGE_SILENT_WRITE (1<<10)
#define _CACHE_UNCACHED (1<<11)
#define _CACHE_MASK (1<<11)
-#define _PFN_SHIFT PAGE_SHIFT
#else /* 'Normal' r4K case */
/*
@@ -129,10 +128,22 @@
#define _CACHE_MASK (7 << _CACHE_SHIFT)
#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
-#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1))
#endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */
+#ifndef _PFN_SHIFT
+#define _PFN_SHIFT PAGE_SHIFT
+#endif
+#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1))
+
+#ifndef _PAGE_NO_READ
+#define _PAGE_NO_READ ({BUG(); 0; })
+#define _PAGE_NO_READ_SHIFT ({BUG(); 0; })
+#endif
+#ifndef _PAGE_NO_EXEC
+#define _PAGE_NO_EXEC ({BUG(); 0; })
+#endif
+
#ifndef __ASSEMBLY__
/*
* pte_to_entrylo converts a page table entry (PTE) into a Mips
@@ -152,11 +163,10 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
* followed by a ROTR 2. Luckily in the fast path
* this is done in assembly
*/
- return (pte_val >> _PAGE_GLOBAL_SHIFT) |
+ return (pte_val >> ilog2(_PAGE_GLOBAL)) |
((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
}
-
- return pte_val >> _PAGE_GLOBAL_SHIFT;
+ return pte_val >> ilog2(_PAGE_GLOBAL);
}
#endif
next prev parent reply other threads:[~2010-02-15 2:08 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-02-10 23:08 [PATCH 0/6] MIPS Read Inhibit/eXecute Inhibit support (v2) David Daney
2010-02-10 23:12 ` [PATCH 1/6] MIPS: Use 64-bit stores to c0_entrylo on 64-bit kernels David Daney
2010-02-10 23:12 ` [PATCH 2/6] MIPS: Add accessor functions and bit definitions for c0_PageGrain David Daney
2010-02-10 23:12 ` [PATCH 3/6] MIPS: Add TLBR and ROTR to uasm David Daney
2010-02-10 23:12 ` [PATCH 4/6] MIPS: Implement Read Inhibit/eXecute Inhibit David Daney
2010-02-14 20:16 ` Manuel Lauss
2010-02-15 1:17 ` David Daney
2010-02-15 2:08 ` David Daney [this message]
2010-02-15 17:34 ` Manuel Lauss
2010-02-15 17:38 ` David Daney
2010-02-10 23:12 ` [PATCH 5/6] MIPS: Give Octeon+ CPUs their own cputype David Daney
2010-02-10 23:12 ` [PATCH 6/6] MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUs David Daney
2010-02-10 23:56 ` [PATCH 0/6] MIPS Read Inhibit/eXecute Inhibit support (v2) Ralf Baechle
2010-02-11 0:53 ` David Daney
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=4B78AC97.8030404@gmail.com \
--to=david.s.daney@gmail.com \
--cc=ddaney@caviumnetworks.com \
--cc=linux-mips@linux-mips.org \
--cc=manuel.lauss@googlemail.com \
--cc=ralf@linux-mips.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox