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* How is interrupt handling on MIPS SMP?
@ 2010-08-28  7:18 Adam Jiang
  2010-08-28 16:02 ` wu zhangjin
  0 siblings, 1 reply; 3+ messages in thread
From: Adam Jiang @ 2010-08-28  7:18 UTC (permalink / raw)
  To: linux-mips

How dose interrupt be handled on SMP build on MIPS architecture? Does
mips-linux support SMP?

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: How is interrupt handling on MIPS SMP?
  2010-08-28  7:18 How is interrupt handling on MIPS SMP? Adam Jiang
@ 2010-08-28 16:02 ` wu zhangjin
  2010-08-29  6:57   ` Adam Jiang
  0 siblings, 1 reply; 3+ messages in thread
From: wu zhangjin @ 2010-08-28 16:02 UTC (permalink / raw)
  To: linux-mips

Hi, Adam

On 8/28/10, Adam Jiang <jiang.adam@gmail.com> wrote:
> How dose interrupt be handled on SMP build on MIPS architecture? Does
> mips-linux support SMP?
>

$ grep SYS_SUPPORTS_SMP -ur arch/mips/Kconfig | egrep -v "config|depend" | wc -l
6

You can get more information from the book "See MIPS Run Linux" version 2.

Regards,
Wu Zhangjin

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: How is interrupt handling on MIPS SMP?
  2010-08-28 16:02 ` wu zhangjin
@ 2010-08-29  6:57   ` Adam Jiang
  0 siblings, 0 replies; 3+ messages in thread
From: Adam Jiang @ 2010-08-29  6:57 UTC (permalink / raw)
  To: wu zhangjin; +Cc: linux-mips

> Hi, Adam
> 
> On 8/28/10, Adam Jiang <jiang.adam@gmail.com> wrote:
> > How dose interrupt be handled on SMP build on MIPS architecture? Does
> > mips-linux support SMP?
> >
> 
> $ grep SYS_SUPPORTS_SMP -ur arch/mips/Kconfig | egrep -v "config|depend" | wc -l
> 6
> 
> You can get more information from the book "See MIPS Run Linux" version 2.

Thank you, Wu. I'd like to read the book ASAP.

I have gotten a general image how multi-APIC system distribute IRQs to
each CPU on x86 architecture. For misp, is there a mechanism to do the
same thing?

Another question is about the comments in file

arch/mips/kernel/irq_cpu.c

it is said "8 interrupt sources" things could not be applied to SMP.
What dose this mean? How is MIPS CPU interrupts handled? Could I get a
general information from MIPS programmer manual?

Best regards,
/Adam

> 
> Regards,
> Wu Zhangjin
> 

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2010-08-29  6:55 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2010-08-28  7:18 How is interrupt handling on MIPS SMP? Adam Jiang
2010-08-28 16:02 ` wu zhangjin
2010-08-29  6:57   ` Adam Jiang

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