* Re: Problem About Vectored interrupt [not found] <AANLkTinhM4PUmLbWeAyavf-JPM1Xpu9pJVkXDq4c-f0C@mail.gmail.com> @ 2010-12-27 14:00 ` Dennis.Yxun [not found] ` <A7DEA48C84FD0B48AAAE33F328C02014033DADEC@BBY1EXM11.pmc_nt.nt.pmc-sierra.bc.ca> 0 siblings, 1 reply; 4+ messages in thread From: Dennis.Yxun @ 2010-12-27 14:00 UTC (permalink / raw) To: linux-mips [-- Attachment #1.1: Type: text/plain, Size: 1149 bytes --] HI: Here is my patch which hacked set_vi_srs_handler, with this I could successfully bring timer(compare/counter), But I still not reach the root problem, Could someone shine some lights on me. Thanks Dennis On Mon, Dec 27, 2010 at 4:40 PM, Dennis.Yxun <dennis.yxun@gmail.com> wrote: > HI ALL: > I'm try to porting kernel-2.6.36 to one mips24kc board, seems it can't > bind vectored irq 7 to timer interrupt. > The hardware wired IP7 to timer interrupt (CP0 compare/counter interrupt) > I implemented my own time.c, use set_vi_handler to map > cp0_compare_irq(value: 7) to mips_timer_dispatch, > but weird problem, it didn't successfully map to mips_timer_dispatch, but > print out "Caught unexpected vectored interrupt." > which means it still use " static asmlinkage void do_default_vi(void)" [1] > > My question is : why first call to "set_vi_srs_handler" successfully > mapped to vectored irq7 [2] > but later is fail[3], see my attached file, bad_kernel.txt > > Dennis > > > [1] arch/mips/kernel/traps.c 1339 > [2] arch/mips/kernel/traps.c 1436, when addr == NULL > [3] my attached file time.c get_c0_compare_int > > [-- Attachment #1.2: Type: text/html, Size: 1545 bytes --] [-- Attachment #2: mips_timer.patch --] [-- Type: text/x-patch, Size: 862 bytes --] diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index e971043..ead8750 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1377,6 +1377,11 @@ static asmlinkage void do_default_vi(void) panic("Caught unexpected vectored interrupt."); } +static asmlinkage void mips_timer_dispatch(void) +{ + do_IRQ(7); +} + static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) { unsigned long handler; @@ -1388,7 +1393,14 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) BUG_ON(!cpu_has_veic && !cpu_has_vint); if (addr == NULL) { - handler = (unsigned long) do_default_vi; + switch(n) { + case 7: + handler = (unsigned long) mips_timer_dispatch; + break; + default: + handler = (unsigned long) do_default_vi; + break; + } srs = 0; } else handler = (unsigned long) addr; ^ permalink raw reply related [flat|nested] 4+ messages in thread
[parent not found: <A7DEA48C84FD0B48AAAE33F328C02014033DADEC@BBY1EXM11.pmc_nt.nt.pmc-sierra.bc.ca>]
[parent not found: <AANLkTikWUehOmyD6Nk3Abz=u7FEb8NMtX2-N4r5HHuY9@mail.gmail.com>]
* Re: Problem About Vectored interrupt [not found] ` <AANLkTikWUehOmyD6Nk3Abz=u7FEb8NMtX2-N4r5HHuY9@mail.gmail.com> @ 2011-03-19 0:42 ` Dennis.Yxun 2011-03-19 17:22 ` Ralf Baechle 0 siblings, 1 reply; 4+ messages in thread From: Dennis.Yxun @ 2011-03-19 0:42 UTC (permalink / raw) To: linux-mips; +Cc: Anoop P.A. [-- Attachment #1: Type: text/plain, Size: 3744 bytes --] HI ALL: Again, found that when come to set vect irq 7, do additional data flush fix my problem, here is the patch diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index e971043..850ce58 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1451,6 +1451,9 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); w = (u32 *)(b + ori_offset); *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); + /* FIXME: need flash data cache, for timer irq */ + if (n == 7) + flush_data_cache_page((unsigned int)b); local_flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); } Dennis On Mon, Dec 27, 2010 at 11:56 PM, Dennis.Yxun <dennis.yxun@gmail.com> wrote: > HI Annop: > Thanks for your reply. > Actually, I think I've already done those two point > you mentioned here. > I checked my .config file, it include > CONFIG_CEVT_R4K_LIB=y > CONFIG_CEVT_R4K=y > CONFIG_CSRC_R4K_LIB=y > CONFIG_CSRC_R4K=y > > for the get_c0_compare_int > I've already implemented, see my attached time.c > > unsigned int __cpuinit get_c0_compare_int(void) > { > if (cpu_has_vint) > set_vi_handler(cp0_compare_irq, mips_timer_dispatch0); > > mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; > > return mips_cpu_timer_irq; > } > > c0_compare_irq = 7 > and MIPS_CPU_IRQ_BASE = 0 > so mips_cpu_timer_irq = 7 > > should be the same as your mail > > Dennis > > > On Mon, Dec 27, 2010 at 11:20 PM, Anoop P.A. <Anoop_P.A@pmc-sierra.com>wrote: > >> Hi Dennis, >> >> You may not have to do this ugly hack. Since your cpu is 24kc you should >> be able to re-use r4k timer library. Select r4k timer from your Kconfig >> [code] >> select CEVT_R4K >> select CSRC_R4K >> >> To point your timer interrupt you can add get_c0_compare_int function to >> your platform init code >> >> [code] >> >> unsigned int __cpuinit get_c0_compare_int(void) >> { >> return 7; >> } >> >> Thanks >> Anoop >> >> >> ________________________________ >> >> From: linux-mips-bounce@linux-mips.org on behalf of Dennis.Yxun >> Sent: Mon 12/27/2010 7:30 PM >> To: linux-mips@linux-mips.org >> Subject: Re: Problem About Vectored interrupt >> >> >> HI: >> Here is my patch which hacked set_vi_srs_handler, with this I could >> successfully bring timer(compare/counter), >> But I still not reach the root problem, >> Could someone shine some lights on me. >> Thanks >> >> Dennis >> >> >> On Mon, Dec 27, 2010 at 4:40 PM, Dennis.Yxun <dennis.yxun@gmail.com> >> wrote: >> >> >> HI ALL: >> I'm try to porting kernel-2.6.36 to one mips24kc board, seems >> it can't bind vectored irq 7 to timer interrupt. >> The hardware wired IP7 to timer interrupt (CP0 compare/counter >> interrupt) >> I implemented my own time.c, use set_vi_handler to map >> cp0_compare_irq(value: 7) to mips_timer_dispatch, >> but weird problem, it didn't successfully map to >> mips_timer_dispatch, but print out "Caught unexpected vectored interrupt." >> which means it still use " static asmlinkage void >> do_default_vi(void)" [1] >> >> My question is : why first call to "set_vi_srs_handler" >> successfully mapped to vectored irq7 [2] >> but later is fail[3], see my attached file, bad_kernel.txt >> >> Dennis >> >> >> [1] arch/mips/kernel/traps.c 1339 >> [2] arch/mips/kernel/traps.c 1436, when addr == NULL >> [3] my attached file time.c get_c0_compare_int >> >> >> >> >> > [-- Attachment #2: Type: text/html, Size: 5442 bytes --] ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: Problem About Vectored interrupt 2011-03-19 0:42 ` Dennis.Yxun @ 2011-03-19 17:22 ` Ralf Baechle 2011-03-22 2:02 ` Dennis.Yxun 0 siblings, 1 reply; 4+ messages in thread From: Ralf Baechle @ 2011-03-19 17:22 UTC (permalink / raw) To: Dennis.Yxun; +Cc: linux-mips, Anoop P.A. On Sat, Mar 19, 2011 at 08:42:17AM +0800, Dennis.Yxun wrote: > HI ALL: > Again, found that when come to set vect irq 7, do additional data flush > fix my problem, here is the patch > > diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c > index e971043..850ce58 100644 > --- a/arch/mips/kernel/traps.c > +++ b/arch/mips/kernel/traps.c > @@ -1451,6 +1451,9 @@ static void *set_vi_srs_handler(int n, vi_handler_t > addr, int srs) > *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); > w = (u32 *)(b + ori_offset); > *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); > + /* FIXME: need flash data cache, for timer irq */ > + if (n == 7) > + flush_data_cache_page((unsigned int)b); > local_flush_icache_range((unsigned long)b, > (unsigned long)(b+handler_len)); The call local_flush_icache_range should already flushes the cache and there should be no reason why a 2nd range makes it any better - or why it would only be needed for irq 7 - and the timer isn't necessarily always irq 7. What is your hardware platform and processor? Ralf ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Problem About Vectored interrupt 2011-03-19 17:22 ` Ralf Baechle @ 2011-03-22 2:02 ` Dennis.Yxun 0 siblings, 0 replies; 4+ messages in thread From: Dennis.Yxun @ 2011-03-22 2:02 UTC (permalink / raw) To: Ralf Baechle; +Cc: linux-mips [-- Attachment #1: Type: text/plain, Size: 1774 bytes --] HI Ralf: It's still a hack here, but that's solve my problem. The Compare/Count timer interrupt here is connect to irq7 here, which means interrupt occurs hardware will set CAUSE TI bit to 7. The hardware, it's a integrated SOC platform shipped with mips24kc processor, Still no public document released yet. What's could explain that flush_data_cache_page fix the problem? Cache misconfiguration? Thanks Dennis On Sun, Mar 20, 2011 at 1:22 AM, Ralf Baechle <ralf@linux-mips.org> wrote: > On Sat, Mar 19, 2011 at 08:42:17AM +0800, Dennis.Yxun wrote: > > > HI ALL: > > Again, found that when come to set vect irq 7, do additional data flush > > fix my problem, here is the patch > > > > diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c > > index e971043..850ce58 100644 > > --- a/arch/mips/kernel/traps.c > > +++ b/arch/mips/kernel/traps.c > > @@ -1451,6 +1451,9 @@ static void *set_vi_srs_handler(int n, vi_handler_t > > addr, int srs) > > *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); > > w = (u32 *)(b + ori_offset); > > *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); > > + /* FIXME: need flash data cache, for timer irq */ > > + if (n == 7) > > + flush_data_cache_page((unsigned int)b); > > local_flush_icache_range((unsigned long)b, > > (unsigned long)(b+handler_len)); > > The call local_flush_icache_range should already flushes the cache and > there should be no reason why a 2nd range makes it any better - or why > it would only be needed for irq 7 - and the timer isn't necessarily > always irq 7. > > What is your hardware platform and processor? > > Ralf > > [-- Attachment #2: Type: text/html, Size: 2370 bytes --] ^ permalink raw reply [flat|nested] 4+ messages in thread
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2010-12-27 14:00 ` Problem About Vectored interrupt Dennis.Yxun
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