From: Thomas Gleixner <tglx@linutronix.de>
To: linux-mips@linux-mips.org
Cc: Ralf Baechle <ralf@linux-mips.org>, Lars-Peter Clausen <lars@metafoo.de>
Subject: [patch 09/38] MIPS: JZ4740: Convert to new irq functions
Date: Wed, 23 Mar 2011 21:08:53 -0000 [thread overview]
Message-ID: <20110323210535.431706586@linutronix.de> (raw)
In-Reply-To: 20110323210437.398062704@linutronix.de
[-- Attachment #1: 1-2-MIPS-JZ4740-Convert-to-new-irq-functions.patch --]
[-- Type: text/plain, Size: 8471 bytes --]
Convert the JZ4740 intc and gpio irq chips to use newstyle irq functions.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
arch/mips/jz4740/gpio.c | 93 ++++++++++++++++++++++++-----------------------
arch/mips/jz4740/gpio.c | 93 ++++++++++++++++++++++++------------------------
arch/mips/jz4740/irq.c | 32 ++++++++++------
2 files changed, 67 insertions(+), 58 deletions(-)
Index: linux-mips-next/arch/mips/jz4740/gpio.c
===================================================================
--- linux-mips-next.orig/arch/mips/jz4740/gpio.c
+++ linux-mips-next/arch/mips/jz4740/gpio.c
@@ -102,9 +102,9 @@ static inline struct jz_gpio_chip *gpio_
return container_of(gpio_chip, struct jz_gpio_chip, gpio_chip);
}
-static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(unsigned int irq)
+static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(struct irq_data *data)
{
- return get_irq_chip_data(irq);
+ return irq_data_get_irq_chip_data(data);
}
static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg)
@@ -325,62 +325,63 @@ static void jz_gpio_irq_demux_handler(un
generic_handle_irq(gpio_irq);
};
-static inline void jz_gpio_set_irq_bit(unsigned int irq, unsigned int reg)
+static inline void jz_gpio_set_irq_bit(struct irq_data *data, unsigned int reg)
{
- struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
- writel(IRQ_TO_BIT(irq), chip->base + reg);
+ struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
+ writel(IRQ_TO_BIT(data->irq), chip->base + reg);
}
-static void jz_gpio_irq_mask(unsigned int irq)
+static void jz_gpio_irq_mask(struct irq_data *data)
{
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_SET);
+ jz_gpio_set_irq_bit(data, JZ_REG_GPIO_MASK_SET);
};
-static void jz_gpio_irq_unmask(unsigned int irq)
+static void jz_gpio_irq_unmask(struct irq_data *data)
{
- struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
+ struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
- jz_gpio_check_trigger_both(chip, irq);
+ jz_gpio_check_trigger_both(chip, data->irq);
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_CLEAR);
+ jz_gpio_set_irq_bit(data, JZ_REG_GPIO_MASK_CLEAR);
};
/* TODO: Check if function is gpio */
-static unsigned int jz_gpio_irq_startup(unsigned int irq)
+static unsigned int jz_gpio_irq_startup(struct irq_data *data)
{
- struct irq_desc *desc = irq_to_desc(irq);
+ struct irq_desc *desc = irq_to_desc(data->irq);
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_SET);
+ jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_SET);
desc->status &= ~IRQ_MASKED;
- jz_gpio_irq_unmask(irq);
+ jz_gpio_irq_unmask(data);
return 0;
}
-static void jz_gpio_irq_shutdown(unsigned int irq)
+static void jz_gpio_irq_shutdown(struct irq_data *data)
{
- struct irq_desc *desc = irq_to_desc(irq);
+ struct irq_desc *desc = irq_to_desc(data->irq);
- jz_gpio_irq_mask(irq);
+ jz_gpio_irq_mask(data);
desc->status |= IRQ_MASKED;
/* Set direction to input */
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_CLEAR);
+ jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
+ jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_CLEAR);
}
-static void jz_gpio_irq_ack(unsigned int irq)
+static void jz_gpio_irq_ack(struct irq_data *data)
{
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_FLAG_CLEAR);
+ jz_gpio_set_irq_bit(data, JZ_REG_GPIO_FLAG_CLEAR);
};
-static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
+static int jz_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
{
- struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
- struct irq_desc *desc = irq_to_desc(irq);
+ struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
+ struct irq_desc *desc = irq_to_desc(data->irq);
+ unsigned int irq = data->irq;
- jz_gpio_irq_mask(irq);
+ jz_gpio_irq_mask(data);
if (flow_type == IRQ_TYPE_EDGE_BOTH) {
uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN);
@@ -395,39 +396,39 @@ static int jz_gpio_irq_set_type(unsigned
switch (flow_type) {
case IRQ_TYPE_EDGE_RISING:
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET);
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET);
+ jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
+ jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
break;
case IRQ_TYPE_EDGE_FALLING:
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET);
+ jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
+ jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
break;
case IRQ_TYPE_LEVEL_HIGH:
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET);
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR);
+ jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
+ jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
break;
case IRQ_TYPE_LEVEL_LOW:
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
- jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR);
+ jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
+ jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
break;
default:
return -EINVAL;
}
if (!(desc->status & IRQ_MASKED))
- jz_gpio_irq_unmask(irq);
+ jz_gpio_irq_unmask(data);
return 0;
}
-static int jz_gpio_irq_set_wake(unsigned int irq, unsigned int on)
+static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
{
- struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
+ struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
spin_lock(&chip->lock);
if (on)
- chip->wakeup |= IRQ_TO_BIT(irq);
+ chip->wakeup |= IRQ_TO_BIT(data->irq);
else
- chip->wakeup &= ~IRQ_TO_BIT(irq);
+ chip->wakeup &= ~IRQ_TO_BIT(data->irq);
spin_unlock(&chip->lock);
set_irq_wake(chip->irq, on);
@@ -454,13 +455,13 @@ static struct lock_class_key gpio_lock_c
}, \
.irq_chip = { \
.name = "GPIO Bank " # _bank, \
- .mask = jz_gpio_irq_mask, \
- .unmask = jz_gpio_irq_unmask, \
- .ack = jz_gpio_irq_ack, \
- .startup = jz_gpio_irq_startup, \
- .shutdown = jz_gpio_irq_shutdown, \
- .set_type = jz_gpio_irq_set_type, \
- .set_wake = jz_gpio_irq_set_wake, \
+ .irq_mask = jz_gpio_irq_mask, \
+ .irq_unmask = jz_gpio_irq_unmask, \
+ .irq_ack = jz_gpio_irq_ack, \
+ .irq_startup = jz_gpio_irq_startup, \
+ .irq_shutdown = jz_gpio_irq_shutdown, \
+ .irq_set_type = jz_gpio_irq_set_type, \
+ .irq_set_wake = jz_gpio_irq_set_wake, \
}, \
}
Index: linux-mips-next/arch/mips/jz4740/irq.c
===================================================================
--- linux-mips-next.orig/arch/mips/jz4740/irq.c
+++ linux-mips-next/arch/mips/jz4740/irq.c
@@ -43,32 +43,37 @@ static uint32_t jz_intc_saved;
#define IRQ_BIT(x) BIT((x) - JZ4740_IRQ_BASE)
-static void intc_irq_unmask(unsigned int irq)
+static inline unsigned long intc_irq_bit(struct irq_data *data)
{
- writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
+ return (unsigned long)irq_data_get_irq_chip_data(data);
}
-static void intc_irq_mask(unsigned int irq)
+static void intc_irq_unmask(struct irq_data *data)
{
- writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK);
+ writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
}
-static int intc_irq_set_wake(unsigned int irq, unsigned int on)
+static void intc_irq_mask(struct irq_data *data)
+{
+ writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_SET_MASK);
+}
+
+static int intc_irq_set_wake(struct irq_data *data, unsigned int on)
{
if (on)
- jz_intc_wakeup |= IRQ_BIT(irq);
+ jz_intc_wakeup |= intc_irq_bit(data);
else
- jz_intc_wakeup &= ~IRQ_BIT(irq);
+ jz_intc_wakeup &= ~intc_irq_bit(data);
return 0;
}
static struct irq_chip intc_irq_type = {
.name = "INTC",
- .mask = intc_irq_mask,
- .mask_ack = intc_irq_mask,
- .unmask = intc_irq_unmask,
- .set_wake = intc_irq_set_wake,
+ .irq_mask = intc_irq_mask,
+ .irq_mask_ack = intc_irq_mask,
+ .irq_unmask = intc_irq_unmask,
+ .irq_set_wake = intc_irq_set_wake,
};
static irqreturn_t jz4740_cascade(int irq, void *data)
@@ -95,8 +100,11 @@ void __init arch_init_irq(void)
jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14);
+ /* Mask all irqs */
+ writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK);
+
for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) {
- intc_irq_mask(i);
+ set_irq_chip_data(i, (void *)IRQ_BIT(i));
set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
}
next prev parent reply other threads:[~2011-03-23 21:12 UTC|newest]
Thread overview: 97+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-03-23 21:08 [patch 00/38] mips: irq chip overhaul and cleanup Thomas Gleixner
2011-03-23 21:08 ` [patch 01/38] mips; Convert alchemy to new irq chip functions Thomas Gleixner
2011-03-24 7:41 ` Manuel Lauss
2011-03-24 8:14 ` Thomas Gleixner
2011-03-24 14:06 ` Ralf Baechle
2011-03-23 21:08 ` [patch 02/38] mips: ar7: Convert to new irq_chip functions Thomas Gleixner
2011-03-24 14:09 ` Ralf Baechle
2011-03-23 21:08 ` [patch 04/38] mips: bcm63xx: " Thomas Gleixner
2011-03-24 14:10 ` Ralf Baechle
2011-03-23 21:08 ` [patch 03/38] mips: ath79: " Thomas Gleixner
2011-03-24 14:07 ` Ralf Baechle
2011-03-23 21:08 ` [patch 05/38] mips: cavium-octeon: " Thomas Gleixner
2011-03-23 21:31 ` David Daney
2011-03-24 14:12 ` Ralf Baechle
2011-03-23 21:08 ` [patch 06/38] mips: dec: " Thomas Gleixner
2011-03-24 14:18 ` Ralf Baechle
2011-03-24 15:21 ` Maciej W. Rozycki
2011-03-24 16:16 ` Thomas Gleixner
2011-03-24 18:14 ` Maciej W. Rozycki
2011-03-24 19:29 ` Thomas Gleixner
2011-03-25 0:33 ` Maciej W. Rozycki
2011-03-29 12:56 ` Atsushi Nemoto
2011-03-29 13:20 ` Maciej W. Rozycki
2011-03-23 21:08 ` [patch 07/38] mips: emma: " Thomas Gleixner
2011-03-24 14:18 ` Ralf Baechle
2011-03-23 21:08 ` [patch 08/38] mips: jazz: " Thomas Gleixner
2011-03-24 14:19 ` Ralf Baechle
2011-03-23 21:08 ` Thomas Gleixner [this message]
2011-03-24 14:20 ` [patch 09/38] MIPS: JZ4740: Convert to new irq functions Ralf Baechle
2011-03-23 21:08 ` [patch 10/38] MIPS: JZ4740: GPIO: Use shared irq chip for all gpios Thomas Gleixner
2011-03-24 12:15 ` Sergei Shtylyov
2011-03-24 12:59 ` Thomas Gleixner
2011-03-24 14:28 ` Ralf Baechle
2011-03-23 21:08 ` [patch 11/38] mips: jz4740: Cleanup the mechanical irq_chip conversion Thomas Gleixner
2011-03-24 14:29 ` Ralf Baechle
2011-03-23 21:08 ` [patch 12/38] misp: lasat: Convert to new irq_chip functions Thomas Gleixner
2011-03-24 14:31 ` Ralf Baechle
2011-03-23 21:08 ` [patch 13/38] mips: i8259: " Thomas Gleixner
2011-03-24 14:32 ` Ralf Baechle
2011-03-23 21:08 ` [patch 14/38] mips: gic: " Thomas Gleixner
2011-03-24 12:22 ` Sergei Shtylyov
2011-03-24 14:34 ` Ralf Baechle
2011-03-23 21:08 ` [patch 16/38] mips: msc01: " Thomas Gleixner
2011-03-24 14:35 ` Ralf Baechle
2011-03-23 21:08 ` [patch 15/38] mips: gt641: " Thomas Gleixner
2011-03-24 14:34 ` Ralf Baechle
2011-03-23 21:09 ` [patch 17/38] mips: rm7000: " Thomas Gleixner
2011-03-24 14:35 ` Ralf Baechle
2011-03-23 21:09 ` [patch 18/38] mips: rm9000: " Thomas Gleixner
2011-03-24 14:36 ` Ralf Baechle
2011-03-23 21:09 ` [patch 20/38] mips: txx9: Convert core " Thomas Gleixner
2011-03-24 14:39 ` Ralf Baechle
2011-03-23 21:09 ` [patch 19/38] misp: irq_cpu: Convert " Thomas Gleixner
2011-03-24 12:28 ` Sergei Shtylyov
2011-03-24 14:37 ` Ralf Baechle
2011-03-23 21:09 ` [patch 21/38] mips: smtc: Use irq_data in smtc_forward_irq() Thomas Gleixner
2011-03-24 14:40 ` Ralf Baechle
2011-03-23 21:09 ` [patch 22/38] mips: smtc: Cleanup the hook mess and use irq_data Thomas Gleixner
2011-03-24 14:40 ` Ralf Baechle
2011-03-23 21:09 ` [patch 23/38] mips: Use generic show_interrupts() Thomas Gleixner
2011-03-24 14:41 ` Ralf Baechle
2011-03-23 21:09 ` [patch 25/38] mips: pmc-sierra: Convert to new irq_chip functions Thomas Gleixner
2011-03-24 14:44 ` Ralf Baechle
2011-03-23 21:09 ` [patch 24/38] mips: loongson: " Thomas Gleixner
2011-03-24 14:43 ` Ralf Baechle
2011-03-23 21:09 ` [patch 26/38] mips: pnx83xx: " Thomas Gleixner
2011-03-24 14:44 ` Ralf Baechle
2011-03-23 21:09 ` [patch 28/38] mips: powertv: " Thomas Gleixner
2011-03-24 14:47 ` Ralf Baechle
2011-03-23 21:09 ` [patch 27/38] mips: pnx855: " Thomas Gleixner
2011-03-24 12:32 ` Sergei Shtylyov
2011-03-24 14:45 ` Ralf Baechle
2011-03-23 21:09 ` [patch 29/38] mips: rb532: " Thomas Gleixner
2011-03-24 14:53 ` Ralf Baechle
2011-03-23 21:09 ` [patch 30/38] mips: sgi-ip22: " Thomas Gleixner
2011-03-24 14:49 ` Ralf Baechle
2011-03-23 21:09 ` [patch 31/38] mips: sgi-ip27: " Thomas Gleixner
2011-03-24 14:50 ` Ralf Baechle
2011-03-23 21:09 ` [patch 32/38] mips: sgi32: " Thomas Gleixner
2011-03-24 14:50 ` Ralf Baechle
2011-03-23 21:09 ` [patch 33/38] mips: sybyte: " Thomas Gleixner
2011-03-24 14:51 ` Ralf Baechle
2011-03-23 21:09 ` [patch 34/38] mips: sni: " Thomas Gleixner
2011-03-24 14:52 ` Ralf Baechle
2011-03-23 21:09 ` [patch 35/38] mips: txx9: " Thomas Gleixner
2011-03-24 14:53 ` Ralf Baechle
2011-03-23 21:09 ` [patch 36/38] mips: vr41: " Thomas Gleixner
2011-03-24 12:36 ` Sergei Shtylyov
2011-03-24 14:55 ` Ralf Baechle
2011-03-23 21:09 ` [patch 37/38] mips: vr41xx: Cleanup the direct access to irq_desc[] Thomas Gleixner
2011-03-24 12:44 ` Sergei Shtylyov
2011-03-24 13:00 ` Thomas Gleixner
2011-03-24 13:56 ` Sergei Shtylyov
2011-03-24 14:21 ` Thomas Gleixner
2011-03-24 15:12 ` Ralf Baechle
2011-03-23 21:09 ` [patch 38/38] mips: Select GENERIC_HARDIRQS_NO_DEPRECATED Thomas Gleixner
2011-03-24 14:15 ` Ralf Baechle
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