* [PATCH 06/12] MIPS: Netlogic: XLP CPU support.
@ 2011-10-23 13:40 Jayachandran C
2011-10-23 13:40 ` Jayachandran C
0 siblings, 1 reply; 5+ messages in thread
From: Jayachandran C @ 2011-10-23 13:40 UTC (permalink / raw)
To: ralf, linux-mips
Add support for Netlogic's XLP MIPS SoC. This patch adds:
* XLP processor ID in cpu_probe.c and asm/cpu.h
* XLP case to asm/module.h
* CPU_XLP case to mm/tlbex.c
* minor change to r4k cache handling to ignore XLP secondary cache
* XLP cpu overrides to mach-netlogic/cpu-feature-overrides.h
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
---
arch/mips/include/asm/cpu.h | 3 ++-
.../asm/mach-netlogic/cpu-feature-overrides.h | 18 ++++++++++++++----
arch/mips/include/asm/module.h | 2 ++
arch/mips/kernel/cpu-probe.c | 19 ++++++++++++++++---
arch/mips/mm/c-r4k.c | 3 +++
5 files changed, 37 insertions(+), 8 deletions(-)
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 5f95a4b..4bcb668b 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -167,6 +167,7 @@
#define PRID_IMP_NETLOGIC_XLS408B 0x4e00
#define PRID_IMP_NETLOGIC_XLS404B 0x4f00
+#define PRID_IMP_NETLOGIC_XLP832 0x1000
/*
* Definitions for 7:0 on legacy processors
*/
@@ -260,7 +261,7 @@ enum cpu_type_enum {
*/
CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
- CPU_XLR,
+ CPU_XLR, CPU_XLP,
CPU_LAST
};
diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
index 3780743..d193fb6 100644
--- a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
@@ -24,23 +24,33 @@
#define cpu_has_llsc 1
#define cpu_has_vtag_icache 0
-#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 1
#define cpu_has_dsp 0
#define cpu_has_mipsmt 0
-#define cpu_has_userlocal 0
#define cpu_icache_snoops_remote_store 1
#define cpu_has_64bits 1
#define cpu_has_mips32r1 1
-#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 1
-#define cpu_has_mips64r2 0
#define cpu_has_inclusive_pcaches 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
+#if defined(CONFIG_CPU_XLR)
+#define cpu_has_userlocal 0
+#define cpu_has_dc_aliases 0
+#define cpu_has_mips32r2 0
+#define cpu_has_mips64r2 0
+#elif defined(CONFIG_CPU_XLP)
+#define cpu_has_userlocal 1
+#define cpu_has_mips32r2 1
+#define cpu_has_mips64r2 1
+#define cpu_has_dc_aliases 1
+#else
+#error "Unknown Netlogic CPU"
+#endif
+
#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index bc01a02..2278e34 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -120,6 +120,8 @@ search_module_dbetables(unsigned long addr)
#define MODULE_PROC_FAMILY "OCTEON "
#elif defined CONFIG_CPU_XLR
#define MODULE_PROC_FAMILY "XLR "
+#elif defined CONFIG_CPU_XLP
+#define MODULE_PROC_FAMILY "XLP "
#else
#error MODULE_PROC_FAMILY undefined for your processor configuration
#endif
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 664bc13..501d302 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -191,6 +191,7 @@ void __init check_wait(void)
case CPU_CAVIUM_OCTEON2:
case CPU_JZRISC:
case CPU_XLR:
+ case CPU_XLP:
cpu_wait = r4k_wait;
break;
@@ -1020,6 +1021,11 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
MIPS_CPU_LLSC);
switch (c->processor_id & 0xff00) {
+ case PRID_IMP_NETLOGIC_XLP832:
+ c->cputype = CPU_XLP;
+ __cpu_name[cpu] = "Netlogic XLP";
+ break;
+
case PRID_IMP_NETLOGIC_XLR732:
case PRID_IMP_NETLOGIC_XLR716:
case PRID_IMP_NETLOGIC_XLR532:
@@ -1050,14 +1056,21 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
break;
default:
- printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n",
+ pr_info("Unknown Netlogic chip id [%02x]!\n",
c->processor_id);
c->cputype = CPU_XLR;
break;
}
- c->isa_level = MIPS_CPU_ISA_M64R1;
- c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
+ if (c->cputype == CPU_XLP) {
+ c->isa_level = MIPS_CPU_ISA_M64R2;
+ c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
+ /* This will be updated again after all threads are woken up */
+ c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
+ } else {
+ c->isa_level = MIPS_CPU_ISA_M64R1;
+ c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
+ }
}
#ifdef CONFIG_64BIT
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index a79fe9a..4f9eb0b 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1235,6 +1235,9 @@ static void __cpuinit setup_scache(void)
loongson2_sc_init();
return;
#endif
+ case CPU_XLP:
+ /* don't need to worry about L2, fully coherent */
+ return;
default:
if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
--
1.7.4.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 06/12] MIPS: Netlogic: XLP CPU support.
2011-10-23 13:40 [PATCH 06/12] MIPS: Netlogic: XLP CPU support Jayachandran C
@ 2011-10-23 13:40 ` Jayachandran C
0 siblings, 0 replies; 5+ messages in thread
From: Jayachandran C @ 2011-10-23 13:40 UTC (permalink / raw)
To: ralf, linux-mips
Add support for Netlogic's XLP MIPS SoC. This patch adds:
* XLP processor ID in cpu_probe.c and asm/cpu.h
* XLP case to asm/module.h
* CPU_XLP case to mm/tlbex.c
* minor change to r4k cache handling to ignore XLP secondary cache
* XLP cpu overrides to mach-netlogic/cpu-feature-overrides.h
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
---
arch/mips/include/asm/cpu.h | 3 ++-
.../asm/mach-netlogic/cpu-feature-overrides.h | 18 ++++++++++++++----
arch/mips/include/asm/module.h | 2 ++
arch/mips/kernel/cpu-probe.c | 19 ++++++++++++++++---
arch/mips/mm/c-r4k.c | 3 +++
5 files changed, 37 insertions(+), 8 deletions(-)
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 5f95a4b..4bcb668b 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -167,6 +167,7 @@
#define PRID_IMP_NETLOGIC_XLS408B 0x4e00
#define PRID_IMP_NETLOGIC_XLS404B 0x4f00
+#define PRID_IMP_NETLOGIC_XLP832 0x1000
/*
* Definitions for 7:0 on legacy processors
*/
@@ -260,7 +261,7 @@ enum cpu_type_enum {
*/
CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
- CPU_XLR,
+ CPU_XLR, CPU_XLP,
CPU_LAST
};
diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
index 3780743..d193fb6 100644
--- a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
@@ -24,23 +24,33 @@
#define cpu_has_llsc 1
#define cpu_has_vtag_icache 0
-#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 1
#define cpu_has_dsp 0
#define cpu_has_mipsmt 0
-#define cpu_has_userlocal 0
#define cpu_icache_snoops_remote_store 1
#define cpu_has_64bits 1
#define cpu_has_mips32r1 1
-#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 1
-#define cpu_has_mips64r2 0
#define cpu_has_inclusive_pcaches 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
+#if defined(CONFIG_CPU_XLR)
+#define cpu_has_userlocal 0
+#define cpu_has_dc_aliases 0
+#define cpu_has_mips32r2 0
+#define cpu_has_mips64r2 0
+#elif defined(CONFIG_CPU_XLP)
+#define cpu_has_userlocal 1
+#define cpu_has_mips32r2 1
+#define cpu_has_mips64r2 1
+#define cpu_has_dc_aliases 1
+#else
+#error "Unknown Netlogic CPU"
+#endif
+
#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index bc01a02..2278e34 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -120,6 +120,8 @@ search_module_dbetables(unsigned long addr)
#define MODULE_PROC_FAMILY "OCTEON "
#elif defined CONFIG_CPU_XLR
#define MODULE_PROC_FAMILY "XLR "
+#elif defined CONFIG_CPU_XLP
+#define MODULE_PROC_FAMILY "XLP "
#else
#error MODULE_PROC_FAMILY undefined for your processor configuration
#endif
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 664bc13..501d302 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -191,6 +191,7 @@ void __init check_wait(void)
case CPU_CAVIUM_OCTEON2:
case CPU_JZRISC:
case CPU_XLR:
+ case CPU_XLP:
cpu_wait = r4k_wait;
break;
@@ -1020,6 +1021,11 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
MIPS_CPU_LLSC);
switch (c->processor_id & 0xff00) {
+ case PRID_IMP_NETLOGIC_XLP832:
+ c->cputype = CPU_XLP;
+ __cpu_name[cpu] = "Netlogic XLP";
+ break;
+
case PRID_IMP_NETLOGIC_XLR732:
case PRID_IMP_NETLOGIC_XLR716:
case PRID_IMP_NETLOGIC_XLR532:
@@ -1050,14 +1056,21 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
break;
default:
- printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n",
+ pr_info("Unknown Netlogic chip id [%02x]!\n",
c->processor_id);
c->cputype = CPU_XLR;
break;
}
- c->isa_level = MIPS_CPU_ISA_M64R1;
- c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
+ if (c->cputype == CPU_XLP) {
+ c->isa_level = MIPS_CPU_ISA_M64R2;
+ c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
+ /* This will be updated again after all threads are woken up */
+ c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
+ } else {
+ c->isa_level = MIPS_CPU_ISA_M64R1;
+ c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
+ }
}
#ifdef CONFIG_64BIT
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index a79fe9a..4f9eb0b 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1235,6 +1235,9 @@ static void __cpuinit setup_scache(void)
loongson2_sc_init();
return;
#endif
+ case CPU_XLP:
+ /* don't need to worry about L2, fully coherent */
+ return;
default:
if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
--
1.7.4.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 00/12] MIPS: Support for Netlogic XLP processors
@ 2011-11-11 11:37 Jayachandran C
2011-11-11 11:39 ` [PATCH 06/12] MIPS: Netlogic: XLP CPU support Jayachandran C
0 siblings, 1 reply; 5+ messages in thread
From: Jayachandran C @ 2011-11-11 11:37 UTC (permalink / raw)
To: linux-mips, ralf
[Here's is the patchset again, it has been re-based on top of the
ralf/upstream-sfr.git and few conflicts there have been resolved.]
This patchset adds support for Netlogic's XLP processor family.
The first few patches are to update XLR and move common files to a new
netlogic/common directory.
As always, comments and suggestions welcome. More details on the chip at
http://www.netlogicmicro.com/Products/ProductBriefs/MultiCore/XLP832.htm
Changes from version:
- merge smp wakeup code of XLR and XLP
- common support for booting with 1/2/4 threads per core
- Add supprt for XLP 3xx processors
- mark netlogic chips SMT capable
Hillf Danton (1):
MIPS: Netlogic: Mark Netlogic chips as SMT capable
Jayachandran C (11):
MIPS: Netlogic: Style fixes for Platform
MIPS: Netlogic: Use CPU_XLR instead of NLM_XLR
MIPS: Netlogic: No need to set -Werror in mips/xlr
MIPS: Netlogic: Move code common with XLP to common/
MIPS: Netlogic: Update default config
MIPS: Netlogic: XLP CPU support.
MIPS: Netlogic: Add XLP platform files for XLP SoC
MIPS: Netlogic: Add XLP makefiles and config
MIPS: Netlogic: Add default XLP config.
MIPS: Netlogic: Merge some of XLR/XLP wakup code
MIPS: Netlogic: Add support for XLP 3XX cores
arch/mips/Kconfig | 44 ++-
arch/mips/configs/nlm_xlp_defconfig | 570 ++++++++++++++++++++
arch/mips/configs/nlm_xlr_defconfig | 16 +-
arch/mips/include/asm/cpu.h | 5 +-
.../asm/mach-netlogic/cpu-feature-overrides.h | 18 +-
arch/mips/include/asm/module.h | 2 +
arch/mips/include/asm/netlogic/common.h | 76 +++
arch/mips/include/asm/netlogic/haldefs.h | 163 ++++++
arch/mips/include/asm/netlogic/xlp-hal/bridge.h | 187 +++++++
.../mips/include/asm/netlogic/xlp-hal/cpucontrol.h | 83 +++
arch/mips/include/asm/netlogic/xlp-hal/iomap.h | 153 ++++++
arch/mips/include/asm/netlogic/xlp-hal/pic.h | 411 ++++++++++++++
arch/mips/include/asm/netlogic/xlp-hal/sys.h | 129 +++++
arch/mips/include/asm/netlogic/xlp-hal/uart.h | 191 +++++++
arch/mips/include/asm/netlogic/xlp-hal/xlp.h | 51 ++
arch/mips/include/asm/netlogic/xlr/iomap.h | 22 -
arch/mips/include/asm/netlogic/xlr/pic.h | 69 ++-
arch/mips/include/asm/netlogic/xlr/xlr.h | 13 +-
arch/mips/kernel/Makefile | 1 +
arch/mips/kernel/cpu-probe.c | 20 +-
arch/mips/lib/Makefile | 1 +
arch/mips/mm/Makefile | 1 +
arch/mips/mm/c-r4k.c | 3 +
arch/mips/netlogic/Kconfig | 3 -
arch/mips/netlogic/Makefile | 3 +
arch/mips/netlogic/Platform | 13 +-
arch/mips/netlogic/common/Makefile | 3 +
arch/mips/netlogic/common/earlycons.c | 60 ++
arch/mips/netlogic/common/irq.c | 238 ++++++++
arch/mips/netlogic/common/smp.c | 270 +++++++++
arch/mips/netlogic/common/smpboot.S | 272 ++++++++++
arch/mips/netlogic/common/time.c | 51 ++
arch/mips/netlogic/xlp/Makefile | 2 +
arch/mips/netlogic/xlp/nlm_hal.c | 111 ++++
arch/mips/netlogic/xlp/platform.c | 108 ++++
arch/mips/netlogic/xlp/setup.c | 105 ++++
arch/mips/netlogic/xlp/wakeup.c | 102 ++++
arch/mips/netlogic/xlr/Makefile | 7 +-
arch/mips/netlogic/xlr/irq.c | 305 -----------
arch/mips/netlogic/xlr/platform.c | 31 +-
arch/mips/netlogic/xlr/setup.c | 31 +-
arch/mips/netlogic/xlr/smp.c | 220 --------
arch/mips/netlogic/xlr/smpboot.S | 100 ----
arch/mips/netlogic/xlr/time.c | 51 --
arch/mips/netlogic/xlr/wakeup.c | 68 +++
arch/mips/netlogic/xlr/xlr_console.c | 46 --
arch/mips/pci/Makefile | 2 +-
arch/mips/pci/pci-xlr.c | 77 +++
48 files changed, 3679 insertions(+), 829 deletions(-)
create mode 100644 arch/mips/configs/nlm_xlp_defconfig
create mode 100644 arch/mips/include/asm/netlogic/common.h
create mode 100644 arch/mips/include/asm/netlogic/haldefs.h
create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/bridge.h
create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/iomap.h
create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/pic.h
create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/sys.h
create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/uart.h
create mode 100644 arch/mips/include/asm/netlogic/xlp-hal/xlp.h
create mode 100644 arch/mips/netlogic/Makefile
create mode 100644 arch/mips/netlogic/common/Makefile
create mode 100644 arch/mips/netlogic/common/earlycons.c
create mode 100644 arch/mips/netlogic/common/irq.c
create mode 100644 arch/mips/netlogic/common/smp.c
create mode 100644 arch/mips/netlogic/common/smpboot.S
create mode 100644 arch/mips/netlogic/common/time.c
create mode 100644 arch/mips/netlogic/xlp/Makefile
create mode 100644 arch/mips/netlogic/xlp/nlm_hal.c
create mode 100644 arch/mips/netlogic/xlp/platform.c
create mode 100644 arch/mips/netlogic/xlp/setup.c
create mode 100644 arch/mips/netlogic/xlp/wakeup.c
delete mode 100644 arch/mips/netlogic/xlr/irq.c
delete mode 100644 arch/mips/netlogic/xlr/smp.c
delete mode 100644 arch/mips/netlogic/xlr/smpboot.S
delete mode 100644 arch/mips/netlogic/xlr/time.c
create mode 100644 arch/mips/netlogic/xlr/wakeup.c
delete mode 100644 arch/mips/netlogic/xlr/xlr_console.c
--
1.7.5.4
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 06/12] MIPS: Netlogic: XLP CPU support.
2011-11-11 11:37 [PATCH 00/12] MIPS: Support for Netlogic XLP processors Jayachandran C
@ 2011-11-11 11:39 ` Jayachandran C
2011-11-11 11:39 ` Jayachandran C
2011-11-16 0:47 ` Ralf Baechle
0 siblings, 2 replies; 5+ messages in thread
From: Jayachandran C @ 2011-11-11 11:39 UTC (permalink / raw)
To: linux-mips, ralf
Add support for Netlogic's XLP MIPS SoC. This patch adds:
* XLP processor ID in cpu_probe.c and asm/cpu.h
* XLP case to asm/module.h
* CPU_XLP case to mm/tlbex.c
* minor change to r4k cache handling to ignore XLP secondary cache
* XLP cpu overrides to mach-netlogic/cpu-feature-overrides.h
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
---
arch/mips/include/asm/cpu.h | 3 ++-
.../asm/mach-netlogic/cpu-feature-overrides.h | 18 ++++++++++++++----
arch/mips/include/asm/module.h | 2 ++
arch/mips/kernel/cpu-probe.c | 19 ++++++++++++++++---
arch/mips/mm/c-r4k.c | 3 +++
5 files changed, 37 insertions(+), 8 deletions(-)
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 79e4a0d..54e35ad 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -171,6 +171,7 @@
#define PRID_IMP_NETLOGIC_XLS404B 0x4f00
#define PRID_IMP_NETLOGIC_AU13XX 0x8000
+#define PRID_IMP_NETLOGIC_XLP832 0x1000
/*
* Definitions for 7:0 on legacy processors
*/
@@ -264,7 +265,7 @@ enum cpu_type_enum {
*/
CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
- CPU_XLR,
+ CPU_XLR, CPU_XLP,
CPU_LAST
};
diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
index 3780743..d193fb6 100644
--- a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
@@ -24,23 +24,33 @@
#define cpu_has_llsc 1
#define cpu_has_vtag_icache 0
-#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 1
#define cpu_has_dsp 0
#define cpu_has_mipsmt 0
-#define cpu_has_userlocal 0
#define cpu_icache_snoops_remote_store 1
#define cpu_has_64bits 1
#define cpu_has_mips32r1 1
-#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 1
-#define cpu_has_mips64r2 0
#define cpu_has_inclusive_pcaches 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
+#if defined(CONFIG_CPU_XLR)
+#define cpu_has_userlocal 0
+#define cpu_has_dc_aliases 0
+#define cpu_has_mips32r2 0
+#define cpu_has_mips64r2 0
+#elif defined(CONFIG_CPU_XLP)
+#define cpu_has_userlocal 1
+#define cpu_has_mips32r2 1
+#define cpu_has_mips64r2 1
+#define cpu_has_dc_aliases 1
+#else
+#error "Unknown Netlogic CPU"
+#endif
+
#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index bc01a02..2278e34 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -120,6 +120,8 @@ search_module_dbetables(unsigned long addr)
#define MODULE_PROC_FAMILY "OCTEON "
#elif defined CONFIG_CPU_XLR
#define MODULE_PROC_FAMILY "XLR "
+#elif defined CONFIG_CPU_XLP
+#define MODULE_PROC_FAMILY "XLP "
#else
#error MODULE_PROC_FAMILY undefined for your processor configuration
#endif
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index ee6eab6..906e916 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -192,6 +192,7 @@ void __init check_wait(void)
case CPU_CAVIUM_OCTEON2:
case CPU_JZRISC:
case CPU_XLR:
+ case CPU_XLP:
cpu_wait = r4k_wait;
break;
@@ -1031,6 +1032,11 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
MIPS_CPU_LLSC);
switch (c->processor_id & 0xff00) {
+ case PRID_IMP_NETLOGIC_XLP832:
+ c->cputype = CPU_XLP;
+ __cpu_name[cpu] = "Netlogic XLP";
+ break;
+
case PRID_IMP_NETLOGIC_XLR732:
case PRID_IMP_NETLOGIC_XLR716:
case PRID_IMP_NETLOGIC_XLR532:
@@ -1061,14 +1067,21 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
break;
default:
- printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n",
+ pr_info("Unknown Netlogic chip id [%02x]!\n",
c->processor_id);
c->cputype = CPU_XLR;
break;
}
- c->isa_level = MIPS_CPU_ISA_M64R1;
- c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
+ if (c->cputype == CPU_XLP) {
+ c->isa_level = MIPS_CPU_ISA_M64R2;
+ c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
+ /* This will be updated again after all threads are woken up */
+ c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
+ } else {
+ c->isa_level = MIPS_CPU_ISA_M64R1;
+ c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
+ }
}
#ifdef CONFIG_64BIT
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index a79fe9a..4f9eb0b 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1235,6 +1235,9 @@ static void __cpuinit setup_scache(void)
loongson2_sc_init();
return;
#endif
+ case CPU_XLP:
+ /* don't need to worry about L2, fully coherent */
+ return;
default:
if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
--
1.7.5.4
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 06/12] MIPS: Netlogic: XLP CPU support.
2011-11-11 11:39 ` [PATCH 06/12] MIPS: Netlogic: XLP CPU support Jayachandran C
@ 2011-11-11 11:39 ` Jayachandran C
2011-11-16 0:47 ` Ralf Baechle
1 sibling, 0 replies; 5+ messages in thread
From: Jayachandran C @ 2011-11-11 11:39 UTC (permalink / raw)
To: linux-mips, ralf
Add support for Netlogic's XLP MIPS SoC. This patch adds:
* XLP processor ID in cpu_probe.c and asm/cpu.h
* XLP case to asm/module.h
* CPU_XLP case to mm/tlbex.c
* minor change to r4k cache handling to ignore XLP secondary cache
* XLP cpu overrides to mach-netlogic/cpu-feature-overrides.h
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
---
arch/mips/include/asm/cpu.h | 3 ++-
.../asm/mach-netlogic/cpu-feature-overrides.h | 18 ++++++++++++++----
arch/mips/include/asm/module.h | 2 ++
arch/mips/kernel/cpu-probe.c | 19 ++++++++++++++++---
arch/mips/mm/c-r4k.c | 3 +++
5 files changed, 37 insertions(+), 8 deletions(-)
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 79e4a0d..54e35ad 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -171,6 +171,7 @@
#define PRID_IMP_NETLOGIC_XLS404B 0x4f00
#define PRID_IMP_NETLOGIC_AU13XX 0x8000
+#define PRID_IMP_NETLOGIC_XLP832 0x1000
/*
* Definitions for 7:0 on legacy processors
*/
@@ -264,7 +265,7 @@ enum cpu_type_enum {
*/
CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
- CPU_XLR,
+ CPU_XLR, CPU_XLP,
CPU_LAST
};
diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
index 3780743..d193fb6 100644
--- a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
@@ -24,23 +24,33 @@
#define cpu_has_llsc 1
#define cpu_has_vtag_icache 0
-#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 1
#define cpu_has_dsp 0
#define cpu_has_mipsmt 0
-#define cpu_has_userlocal 0
#define cpu_icache_snoops_remote_store 1
#define cpu_has_64bits 1
#define cpu_has_mips32r1 1
-#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 1
-#define cpu_has_mips64r2 0
#define cpu_has_inclusive_pcaches 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
+#if defined(CONFIG_CPU_XLR)
+#define cpu_has_userlocal 0
+#define cpu_has_dc_aliases 0
+#define cpu_has_mips32r2 0
+#define cpu_has_mips64r2 0
+#elif defined(CONFIG_CPU_XLP)
+#define cpu_has_userlocal 1
+#define cpu_has_mips32r2 1
+#define cpu_has_mips64r2 1
+#define cpu_has_dc_aliases 1
+#else
+#error "Unknown Netlogic CPU"
+#endif
+
#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index bc01a02..2278e34 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -120,6 +120,8 @@ search_module_dbetables(unsigned long addr)
#define MODULE_PROC_FAMILY "OCTEON "
#elif defined CONFIG_CPU_XLR
#define MODULE_PROC_FAMILY "XLR "
+#elif defined CONFIG_CPU_XLP
+#define MODULE_PROC_FAMILY "XLP "
#else
#error MODULE_PROC_FAMILY undefined for your processor configuration
#endif
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index ee6eab6..906e916 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -192,6 +192,7 @@ void __init check_wait(void)
case CPU_CAVIUM_OCTEON2:
case CPU_JZRISC:
case CPU_XLR:
+ case CPU_XLP:
cpu_wait = r4k_wait;
break;
@@ -1031,6 +1032,11 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
MIPS_CPU_LLSC);
switch (c->processor_id & 0xff00) {
+ case PRID_IMP_NETLOGIC_XLP832:
+ c->cputype = CPU_XLP;
+ __cpu_name[cpu] = "Netlogic XLP";
+ break;
+
case PRID_IMP_NETLOGIC_XLR732:
case PRID_IMP_NETLOGIC_XLR716:
case PRID_IMP_NETLOGIC_XLR532:
@@ -1061,14 +1067,21 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
break;
default:
- printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n",
+ pr_info("Unknown Netlogic chip id [%02x]!\n",
c->processor_id);
c->cputype = CPU_XLR;
break;
}
- c->isa_level = MIPS_CPU_ISA_M64R1;
- c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
+ if (c->cputype == CPU_XLP) {
+ c->isa_level = MIPS_CPU_ISA_M64R2;
+ c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
+ /* This will be updated again after all threads are woken up */
+ c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
+ } else {
+ c->isa_level = MIPS_CPU_ISA_M64R1;
+ c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
+ }
}
#ifdef CONFIG_64BIT
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index a79fe9a..4f9eb0b 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1235,6 +1235,9 @@ static void __cpuinit setup_scache(void)
loongson2_sc_init();
return;
#endif
+ case CPU_XLP:
+ /* don't need to worry about L2, fully coherent */
+ return;
default:
if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
--
1.7.5.4
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 06/12] MIPS: Netlogic: XLP CPU support.
2011-11-11 11:39 ` [PATCH 06/12] MIPS: Netlogic: XLP CPU support Jayachandran C
2011-11-11 11:39 ` Jayachandran C
@ 2011-11-16 0:47 ` Ralf Baechle
1 sibling, 0 replies; 5+ messages in thread
From: Ralf Baechle @ 2011-11-16 0:47 UTC (permalink / raw)
To: Jayachandran C; +Cc: linux-mips
Queued for 3.3. Thanks,
Ralf
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2011-11-16 0:48 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2011-10-23 13:40 [PATCH 06/12] MIPS: Netlogic: XLP CPU support Jayachandran C
2011-10-23 13:40 ` Jayachandran C
-- strict thread matches above, loose matches on Subject: below --
2011-11-11 11:37 [PATCH 00/12] MIPS: Support for Netlogic XLP processors Jayachandran C
2011-11-11 11:39 ` [PATCH 06/12] MIPS: Netlogic: XLP CPU support Jayachandran C
2011-11-11 11:39 ` Jayachandran C
2011-11-16 0:47 ` Ralf Baechle
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