[PATCH] MIPS: remove port limit in ioport_map

[PATCH] MIPS: remove port limit in ioport_map

[Manuel Lauss]

Alchemy PCMCIA IO lies outside the 32bit address space and needs to
be ioremapped to be accessible.  The resulting address is
then fed as IO-port base to all PCMCIA client drivers attached
to a particular socket.  pata_pcmcia does devm_ioport_map() on
the port address, which returns errors because MIPS' ioport_map()
implementation rejects incoming port addresses which are not
within the 0..64k window.  Other embedded architectures don't
bother with a check like this;  this patch brings MIPS in line
and in turn makes pata_pcmcia work on all my Alchemy systems
(and doesn't break PCI).

Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
---
 arch/mips/lib/iomap.c |    3 ---
 1 files changed, 0 insertions(+), 3 deletions(-)

diff --git a/arch/mips/lib/iomap.c b/arch/mips/lib/iomap.c
index e3acb2d..5139fa6 100644
--- a/arch/mips/lib/iomap.c
+++ b/arch/mips/lib/iomap.c
@@ -210,9 +210,6 @@ static void __iomem *ioport_map_legacy(unsigned long port, unsigned int nr)
 
 void __iomem *ioport_map(unsigned long port, unsigned int nr)
 {
-	if (port > PIO_MASK)
-		return NULL;
-
 	return ioport_map_legacy(port, nr);
 }
 
-- 
1.7.7.1

Re: [PATCH] MIPS: remove port limit in ioport_map

[Ralf Baechle]

On Fri, Nov 04, 2011 at 03:49:51PM +0100, Manuel Lauss wrote:

> Alchemy PCMCIA IO lies outside the 32bit address space and needs to
> be ioremapped to be accessible.  The resulting address is
> then fed as IO-port base to all PCMCIA client drivers attached
> to a particular socket.  pata_pcmcia does devm_ioport_map() on
> the port address, which returns errors because MIPS' ioport_map()
> implementation rejects incoming port addresses which are not
> within the 0..64k window.  Other embedded architectures don't
> bother with a check like this;  this patch brings MIPS in line
> and in turn makes pata_pcmcia work on all my Alchemy systems
> (and doesn't break PCI).

The reason for this had something to do with multiple PCI busses with
devices using I/O ports but I forgot what it was :).  Need to think about
this one.

  Ralf