[PATCH 1/3] MIPS: Alchemy: db1200: improve PB1200 detection.

[PATCH 1/3] MIPS: Alchemy: db1200: improve PB1200 detection.

[Manuel Lauss]

The PB1200 has the CPLD located at an address which on the DB1200 is
RAM;  reading the Board-ID sometimes results in a PB1200 being detected
instead (especially during reboots after long uptimes).
On the other hand, the address of the DB1200's CPLD is hosting Flash
chips on the PB1200.  Test for the DB1200 first and additionally do a
quick write-test to the hexleds register to make sure we're writing
to the CPLD.

Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
---
Applies on top of the other patches queued for 3.3

 arch/mips/alchemy/devboards/db1200.c |   30 ++++++++++++++++++++++--------
 1 files changed, 22 insertions(+), 8 deletions(-)

diff --git a/arch/mips/alchemy/devboards/db1200.c b/arch/mips/alchemy/devboards/db1200.c
index 1181241..6721991 100644
--- a/arch/mips/alchemy/devboards/db1200.c
+++ b/arch/mips/alchemy/devboards/db1200.c
@@ -66,19 +66,33 @@ static int __init detect_board(void)
 {
 	int bid;
 
-	/* try the PB1200 first */
+	/* try the DB1200 first */
+	bcsr_init(DB1200_BCSR_PHYS_ADDR,
+		  DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
+	if (BCSR_WHOAMI_DB1200 == BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
+		unsigned short t = bcsr_read(BCSR_HEXLEDS);
+		bcsr_write(BCSR_HEXLEDS, ~t);
+		if (bcsr_read(BCSR_HEXLEDS) != t) {
+			bcsr_write(BCSR_HEXLEDS, t);
+			return 0;
+		}
+	}
+
+	/* okay, try the PB1200 then */
 	bcsr_init(PB1200_BCSR_PHYS_ADDR,
 		  PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
 	bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
 	if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
-	    (bid == BCSR_WHOAMI_PB1200_DDR2))
-		return 0;
+	    (bid == BCSR_WHOAMI_PB1200_DDR2)) {
+		unsigned short t = bcsr_read(BCSR_HEXLEDS);
+		bcsr_write(BCSR_HEXLEDS, ~t);
+		if (bcsr_read(BCSR_HEXLEDS) != t) {
+			bcsr_write(BCSR_HEXLEDS, t);
+			return 0;
+		}
+	}
 
-	/* okay, try the DB1200 then */
-	bcsr_init(DB1200_BCSR_PHYS_ADDR,
-		  DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
-	bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
-	return bid == BCSR_WHOAMI_DB1200 ? 0 : 1;
+	return 1;	/* it's neither */
 }
 
 void __init board_setup(void)
-- 
1.7.8.rc1

[PATCH 2/3] MIPS: Alchemy: update cpu-feature-overrides

[Manuel Lauss]

Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
---
 .../asm/mach-au1x00/cpu-feature-overrides.h        |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
index d5df0ca..3f741af 100644
--- a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
@@ -13,12 +13,14 @@
 #define cpu_has_4k_cache		1
 #define cpu_has_tx39_cache		0
 #define cpu_has_fpu			0
+#define cpu_has_32fpr			0
 #define cpu_has_counter			1
 #define cpu_has_watch			1
 #define cpu_has_divec			1
 #define cpu_has_vce			0
 #define cpu_has_cache_cdex_p		0
 #define cpu_has_cache_cdex_s		0
+#define cpu_has_prefetch		1
 #define cpu_has_mcheck			1
 #define cpu_has_ejtag			1
 #define cpu_has_llsc			1
@@ -29,6 +31,7 @@
 #define cpu_has_vtag_icache		0
 #define cpu_has_dc_aliases		0
 #define cpu_has_ic_fills_f_dc		1
+#define cpu_has_pindexed_dcache		0
 #define cpu_has_mips32r1		1
 #define cpu_has_mips32r2		0
 #define cpu_has_mips64r1		0
-- 
1.7.8.rc1

[PATCH 3/3] MIPS: Alchemy: fix PCI PM

[Manuel Lauss]

Move PCI Controller PM to syscore_ops since the platform_driver PM methods
are called way too late on resume and far too early on suspend (after and
before PCI device resume/suspend).
This also allows to simplify wired entry management a bit.

Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
---
 arch/mips/pci/pci-alchemy.c |  137 +++++++++++++++++++++----------------------
 1 files changed, 67 insertions(+), 70 deletions(-)

diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c
index b5ce041..b5eddf5 100644
--- a/arch/mips/pci/pci-alchemy.c
+++ b/arch/mips/pci/pci-alchemy.c
@@ -13,6 +13,7 @@
 #include <linux/platform_device.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/syscore_ops.h>
 #include <linux/vmalloc.h>
 
 #include <asm/mach-au1x00/au1000.h>
@@ -41,6 +42,12 @@ struct alchemy_pci_context {
 	int (*board_pci_idsel)(unsigned int devsel, int assert);
 };
 
+/* for syscore_ops. There's only one PCI controller on Alchemy chips, so this
+ * should suffice for now.
+ */
+static struct alchemy_pci_context *__alchemy_pci_ctx;
+
+
 /* IO/MEM resources for PCI. Keep the memres in sync with __fixup_bigphys_addr
  * in arch/mips/alchemy/common/setup.c
  */
@@ -99,18 +106,6 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
 		return -1;
 	}
 
-	/* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired
-	 * on resume, clearing our wired entry.  Unfortunately the ->resume()
-	 * callback is called way way way too late (and ->suspend() too early)
-	 * to have them destroy and recreate it.  Instead just test if c0_wired
-	 * is now lower than the index we retrieved before suspending and then
-	 * recreate the entry if necessary.  Of course this is totally bonkers
-	 * and breaks as soon as someone else adds another wired entry somewhere
-	 * else.  Anyone have any ideas how to handle this better?
-	 */
-	if (unlikely(read_c0_wired() < ctx->wired_entry))
-		alchemy_pci_wired_entry(ctx);
-
 	local_irq_save(flags);
 	r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff;
 	r |= PCI_STATCMD_STATUS(0x2000);
@@ -304,6 +299,62 @@ static int alchemy_pci_def_idsel(unsigned int devsel, int assert)
 	return 1;	/* success */
 }
 
+/* save PCI controller register contents. */
+static int alchemy_pci_suspend(void)
+{
+	struct alchemy_pci_context *ctx = __alchemy_pci_ctx;
+	if (!ctx)
+		return 0;
+
+	ctx->pm[0]  = __raw_readl(ctx->regs + PCI_REG_CMEM);
+	ctx->pm[1]  = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff;
+	ctx->pm[2]  = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH);
+	ctx->pm[3]  = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID);
+	ctx->pm[4]  = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID);
+	ctx->pm[5]  = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV);
+	ctx->pm[6]  = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL);
+	ctx->pm[7]  = __raw_readl(ctx->regs + PCI_REG_ID);
+	ctx->pm[8]  = __raw_readl(ctx->regs + PCI_REG_CLASSREV);
+	ctx->pm[9]  = __raw_readl(ctx->regs + PCI_REG_PARAM);
+	ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR);
+	ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT);
+
+	return 0;
+}
+
+static void alchemy_pci_resume(void)
+{
+	struct alchemy_pci_context *ctx = __alchemy_pci_ctx;
+	if (!ctx)
+		return;
+
+	__raw_writel(ctx->pm[0],  ctx->regs + PCI_REG_CMEM);
+	__raw_writel(ctx->pm[2],  ctx->regs + PCI_REG_B2BMASK_CCH);
+	__raw_writel(ctx->pm[3],  ctx->regs + PCI_REG_B2BBASE0_VID);
+	__raw_writel(ctx->pm[4],  ctx->regs + PCI_REG_B2BBASE1_SID);
+	__raw_writel(ctx->pm[5],  ctx->regs + PCI_REG_MWMASK_DEV);
+	__raw_writel(ctx->pm[6],  ctx->regs + PCI_REG_MWBASE_REV_CCL);
+	__raw_writel(ctx->pm[7],  ctx->regs + PCI_REG_ID);
+	__raw_writel(ctx->pm[8],  ctx->regs + PCI_REG_CLASSREV);
+	__raw_writel(ctx->pm[9],  ctx->regs + PCI_REG_PARAM);
+	__raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR);
+	__raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT);
+	wmb();
+	__raw_writel(ctx->pm[1],  ctx->regs + PCI_REG_CONFIG);
+	wmb();
+
+	/* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired
+	 * on resume, making it necessary to recreate it as soon as possible.
+	 */
+	ctx->wired_entry = 8191;	/* impossibly high value */
+	alchemy_pci_wired_entry(ctx);	/* install it */
+}
+
+static struct syscore_ops alchemy_pci_pmops = {
+	.suspend	= alchemy_pci_suspend,
+	.resume		= alchemy_pci_resume,
+};
+
 static int __devinit alchemy_pci_probe(struct platform_device *pdev)
 {
 	struct alchemy_pci_platdata *pd = pdev->dev.platform_data;
@@ -396,7 +447,8 @@ static int __devinit alchemy_pci_probe(struct platform_device *pdev)
 		ret = -ENOMEM;
 		goto out4;
 	}
-	ctx->wired_entry = 8192;	/* impossibly high value */
+	ctx->wired_entry = 8191;	/* impossibly high value */
+	alchemy_pci_wired_entry(ctx);	/* install it */
 
 	set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base);
 
@@ -408,7 +460,9 @@ static int __devinit alchemy_pci_probe(struct platform_device *pdev)
 	__raw_writel(val, ctx->regs + PCI_REG_CONFIG);
 	wmb();
 
+	__alchemy_pci_ctx = ctx;
 	platform_set_drvdata(pdev, ctx);
+	register_syscore_ops(&alchemy_pci_pmops);
 	register_pci_controller(&ctx->alchemy_pci_ctrl);
 
 	return 0;
@@ -425,68 +479,11 @@ out:
 	return ret;
 }
 
-
-#ifdef CONFIG_PM
-/* save PCI controller register contents. */
-static int alchemy_pci_suspend(struct device *dev)
-{
-	struct alchemy_pci_context *ctx = dev_get_drvdata(dev);
-
-	ctx->pm[0]  = __raw_readl(ctx->regs + PCI_REG_CMEM);
-	ctx->pm[1]  = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff;
-	ctx->pm[2]  = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH);
-	ctx->pm[3]  = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID);
-	ctx->pm[4]  = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID);
-	ctx->pm[5]  = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV);
-	ctx->pm[6]  = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL);
-	ctx->pm[7]  = __raw_readl(ctx->regs + PCI_REG_ID);
-	ctx->pm[8]  = __raw_readl(ctx->regs + PCI_REG_CLASSREV);
-	ctx->pm[9]  = __raw_readl(ctx->regs + PCI_REG_PARAM);
-	ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR);
-	ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT);
-
-	return 0;
-}
-
-static int alchemy_pci_resume(struct device *dev)
-{
-	struct alchemy_pci_context *ctx = dev_get_drvdata(dev);
-
-	__raw_writel(ctx->pm[0],  ctx->regs + PCI_REG_CMEM);
-	__raw_writel(ctx->pm[2],  ctx->regs + PCI_REG_B2BMASK_CCH);
-	__raw_writel(ctx->pm[3],  ctx->regs + PCI_REG_B2BBASE0_VID);
-	__raw_writel(ctx->pm[4],  ctx->regs + PCI_REG_B2BBASE1_SID);
-	__raw_writel(ctx->pm[5],  ctx->regs + PCI_REG_MWMASK_DEV);
-	__raw_writel(ctx->pm[6],  ctx->regs + PCI_REG_MWBASE_REV_CCL);
-	__raw_writel(ctx->pm[7],  ctx->regs + PCI_REG_ID);
-	__raw_writel(ctx->pm[8],  ctx->regs + PCI_REG_CLASSREV);
-	__raw_writel(ctx->pm[9],  ctx->regs + PCI_REG_PARAM);
-	__raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR);
-	__raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT);
-	wmb();
-	__raw_writel(ctx->pm[1],  ctx->regs + PCI_REG_CONFIG);
-	wmb();
-
-	return 0;
-}
-
-static const struct dev_pm_ops alchemy_pci_pmops = {
-	.suspend	= alchemy_pci_suspend,
-	.resume		= alchemy_pci_resume,
-};
-
-#define ALCHEMY_PCICTL_PM	(&alchemy_pci_pmops)
-
-#else
-#define ALCHEMY_PCICTL_PM	NULL
-#endif
-
 static struct platform_driver alchemy_pcictl_driver = {
 	.probe		= alchemy_pci_probe,
 	.driver	= {
 		.name	= "alchemy-pci",
 		.owner	= THIS_MODULE,
-		.pm	= ALCHEMY_PCICTL_PM,
 	},
 };
 
-- 
1.7.8.rc1

Re: [PATCH 1/3] MIPS: Alchemy: db1200: improve PB1200 detection.

[Ralf Baechle]

Queued for 3.3.  Thanks,

  Ralf

Re: [PATCH 2/3] MIPS: Alchemy: update cpu-feature-overrides

[Ralf Baechle]

Queued for 3.3.  Thanks,

  Ralf

Re: [PATCH 3/3] MIPS: Alchemy: fix PCI PM

[Ralf Baechle]

Applied.  Thanks,

  Ralf

Re: [PATCH 1/3] MIPS: Alchemy: db1200: improve PB1200 detection.

[Sergei Shtylyov]

Hello.

On 16-11-2011 19:42, Manuel Lauss wrote:

> The PB1200 has the CPLD located at an address which on the DB1200 is
> RAM;  reading the Board-ID sometimes results in a PB1200 being detected
> instead (especially during reboots after long uptimes).
> On the other hand, the address of the DB1200's CPLD is hosting Flash
> chips on the PB1200.  Test for the DB1200 first and additionally do a
> quick write-test to the hexleds register to make sure we're writing
> to the CPLD.

> Signed-off-by: Manuel Lauss<manuel.lauss@googlemail.com>
> ---
> Applies on top of the other patches queued for 3.3

>   arch/mips/alchemy/devboards/db1200.c |   30 ++++++++++++++++++++++--------
>   1 files changed, 22 insertions(+), 8 deletions(-)

> diff --git a/arch/mips/alchemy/devboards/db1200.c b/arch/mips/alchemy/devboards/db1200.c
> index 1181241..6721991 100644
> --- a/arch/mips/alchemy/devboards/db1200.c
> +++ b/arch/mips/alchemy/devboards/db1200.c
> @@ -66,19 +66,33 @@ static int __init detect_board(void)
>   {
>   	int bid;
>
> -	/* try the PB1200 first */
> +	/* try the DB1200 first */
> +	bcsr_init(DB1200_BCSR_PHYS_ADDR,
> +		  DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
> +	if (BCSR_WHOAMI_DB1200 == BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
> +		unsigned short t = bcsr_read(BCSR_HEXLEDS);
> +		bcsr_write(BCSR_HEXLEDS, ~t);
> +		if (bcsr_read(BCSR_HEXLEDS) != t) {
> +			bcsr_write(BCSR_HEXLEDS, t);
> +			return 0;
> +		}
> +	}
> +
> +	/* okay, try the PB1200 then */
>   	bcsr_init(PB1200_BCSR_PHYS_ADDR,
>   		  PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
>   	bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
>   	if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
> -	    (bid == BCSR_WHOAMI_PB1200_DDR2))
> -		return 0;
> +	    (bid == BCSR_WHOAMI_PB1200_DDR2)) {
> +		unsigned short t = bcsr_read(BCSR_HEXLEDS);
> +		bcsr_write(BCSR_HEXLEDS, ~t);
> +		if (bcsr_read(BCSR_HEXLEDS) != t) {
> +			bcsr_write(BCSR_HEXLEDS, t);
> +			return 0;
> +		}

    Isn't it worth putting the repetitive code into a subroutine?

WBR, Sergei

Re: [PATCH 1/3] MIPS: Alchemy: db1200: improve PB1200 detection.

[Manuel Lauss]

On Thu, Nov 17, 2011 at 12:48 PM, Sergei Shtylyov <sshtylyov@mvista.com> wrote:
> Hello.

>> diff --git a/arch/mips/alchemy/devboards/db1200.c
>> b/arch/mips/alchemy/devboards/db1200.c
>> index 1181241..6721991 100644
>> --- a/arch/mips/alchemy/devboards/db1200.c
>> +++ b/arch/mips/alchemy/devboards/db1200.c
>> @@ -66,19 +66,33 @@ static int __init detect_board(void)
>>  {
>>        int bid;
>>
>> -       /* try the PB1200 first */
>> +       /* try the DB1200 first */
>> +       bcsr_init(DB1200_BCSR_PHYS_ADDR,
>> +                 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
>> +       if (BCSR_WHOAMI_DB1200 ==
>> BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
>> +               unsigned short t = bcsr_read(BCSR_HEXLEDS);
>> +               bcsr_write(BCSR_HEXLEDS, ~t);
>> +               if (bcsr_read(BCSR_HEXLEDS) != t) {
>> +                       bcsr_write(BCSR_HEXLEDS, t);
>> +                       return 0;
>> +               }
>> +       }
>> +
>> +       /* okay, try the PB1200 then */
>>        bcsr_init(PB1200_BCSR_PHYS_ADDR,
>>                  PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
>>        bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
>>        if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
>> -           (bid == BCSR_WHOAMI_PB1200_DDR2))
>> -               return 0;
>> +           (bid == BCSR_WHOAMI_PB1200_DDR2)) {
>> +               unsigned short t = bcsr_read(BCSR_HEXLEDS);
>> +               bcsr_write(BCSR_HEXLEDS, ~t);
>> +               if (bcsr_read(BCSR_HEXLEDS) != t) {
>> +                       bcsr_write(BCSR_HEXLEDS, t);
>> +                       return 0;
>> +               }
>
>   Isn't it worth putting the repetitive code into a subroutine?

If another Au1200-based reference board with similar hw design crops
up, maybe.   The lines saved now however seemed not worth the effort.

Manuel