* [PATCH] MIPS:CMP Fix physical core number calculation logic
@ 2012-10-11 16:48 jerin jacob
2012-10-18 9:45 ` Ralf Baechle
0 siblings, 1 reply; 2+ messages in thread
From: jerin jacob @ 2012-10-11 16:48 UTC (permalink / raw)
To: ralf; +Cc: jerin jacob, linux-mips
CPUNum Field in EBase register is 10bit wide, so after 1 bit right shift, mask
value should be 0x1ff
Signed-off-by: jerin jacob <jerinjacobk@gmail.com>
---
arch/mips/kernel/smp-cmp.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c
index afc379c..06cd0c6 100644
--- a/arch/mips/kernel/smp-cmp.c
+++ b/arch/mips/kernel/smp-cmp.c
@@ -97,7 +97,7 @@ static void cmp_init_secondary(void)
/* Enable per-cpu interrupts: platform specific */
- c->core = (read_c0_ebase() >> 1) & 0xff;
+ c->core = (read_c0_ebase() >> 1) & 0x1ff;
#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE;
#endif
--
1.7.6.5
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] MIPS:CMP Fix physical core number calculation logic
2012-10-11 16:48 [PATCH] MIPS:CMP Fix physical core number calculation logic jerin jacob
@ 2012-10-18 9:45 ` Ralf Baechle
0 siblings, 0 replies; 2+ messages in thread
From: Ralf Baechle @ 2012-10-18 9:45 UTC (permalink / raw)
To: jerin jacob; +Cc: linux-mips
On Thu, Oct 11, 2012 at 10:18:51PM +0530, jerin jacob wrote:
> CPUNum Field in EBase register is 10bit wide, so after 1 bit right shift, mask
> value should be 0x1ff
Fortunately nobody has a CMP with more than 256 cores yet :-)
Applied. Thanks,
Ralf
^ permalink raw reply [flat|nested] 2+ messages in thread
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