* [PATCH] MIPS: VR4133: add LL/SC support
@ 2013-02-21 6:38 Yoichi Yuasa
2013-03-12 12:59 ` Ralf Baechle
0 siblings, 1 reply; 2+ messages in thread
From: Yoichi Yuasa @ 2013-02-21 6:38 UTC (permalink / raw)
To: ralf; +Cc: yuasa, linux-mips
Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org>
---
arch/mips/kernel/cpu-probe.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 9f31334..44c5aad 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -547,6 +547,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
c->tlbsize = 48;
break;
case PRID_IMP_VR41XX:
+ c->isa_level = MIPS_CPU_ISA_III;
+ c->options = R4K_OPTS;
+ c->tlbsize = 32;
switch (c->processor_id & 0xf0) {
case PRID_REV_VR4111:
c->cputype = CPU_VR4111;
@@ -571,6 +574,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "NEC VR4131";
} else {
c->cputype = CPU_VR4133;
+ c->options |= MIPS_CPU_LLSC;
__cpu_name[cpu] = "NEC VR4133";
}
break;
@@ -580,9 +584,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "NEC Vr41xx";
break;
}
- c->isa_level = MIPS_CPU_ISA_III;
- c->options = R4K_OPTS;
- c->tlbsize = 32;
break;
case PRID_IMP_R4300:
c->cputype = CPU_R4300;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] MIPS: VR4133: add LL/SC support
2013-02-21 6:38 [PATCH] MIPS: VR4133: add LL/SC support Yoichi Yuasa
@ 2013-03-12 12:59 ` Ralf Baechle
0 siblings, 0 replies; 2+ messages in thread
From: Ralf Baechle @ 2013-03-12 12:59 UTC (permalink / raw)
To: Yoichi Yuasa; +Cc: linux-mips
On Thu, Feb 21, 2013 at 03:38:19PM +0900, Yoichi Yuasa wrote:
Patch is looking good, applied. Thanks, Yoichi-San!
I noticed that there's no <asm/mach-vr41xx/cpu-feature-overrides.h> file,
so all CPU features will always be runtime tested. This is going to be
rather slow and bloated. You could also use this to specifically define
cpu_has_llsc to 0/1 for those platforms that are known to have not have/
have ll/sc instructions.
Ralf
^ permalink raw reply [flat|nested] 2+ messages in thread
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