From: Ralf Baechle <ralf@linux-mips.org>
To: David Daney <ddaney.cavm@gmail.com>
Cc: linux-mips@linux-mips.org, David Daney <david.daney@cavium.com>
Subject: Re: [PATCH 0/5] MIPS: Add support for OCTEON III based SoCs.
Date: Tue, 30 Jul 2013 18:11:11 +0200 [thread overview]
Message-ID: <20130730161111.GA6010@linux-mips.org> (raw)
In-Reply-To: <1375135624-30950-1-git-send-email-ddaney.cavm@gmail.com>
On Mon, Jul 29, 2013 at 03:06:59PM -0700, David Daney wrote:
> From: David Daney <david.daney@cavium.com>
>
> These patches add minimal support for SoCs in the OCTEON III family.
> In many respects, they are similar to OCTEON II, but with larger cache
> and FPU. FPU support comes later...
Thanks, entire series applied.
Ralf
prev parent reply other threads:[~2013-07-30 16:11 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-29 22:06 [PATCH 0/5] MIPS: Add support for OCTEON III based SoCs David Daney
2013-07-29 22:07 ` [PATCH 1/5] MIPS: Add CPU identifiers for more OCTEON family members David Daney
2013-07-29 22:07 ` [PATCH 2/5] MIPS: Probe for new OCTEON CPU/SoC types David Daney
2013-07-29 22:07 ` [PATCH 3/5] MIPS: Use r4k_wait for OCTEON3 CPUs David Daney
2013-07-29 22:07 ` [PATCH 4/5] MIPS: Generate OCTEON3 TLB handlers with the same features as OCTEON2 David Daney
2013-07-29 22:07 ` David Daney
2013-07-29 22:07 ` [PATCH 5/5] MIPS: OCTEON: Set L1 cache parameters for OCTEON3 CPUs David Daney
2013-07-30 16:11 ` Ralf Baechle [this message]
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