[PATCH 0/5] MIPS: Add support for OCTEON III based SoCs.

[PATCH 0/5] MIPS: Add support for OCTEON III based SoCs.

[David Daney]

From: David Daney <david.daney@cavium.com>

These patches add minimal support for SoCs in the OCTEON III family.
In many respects, they are similar to OCTEON II, but with larger cache
and FPU.  FPU support comes later...

David Daney (5):
  MIPS: Add CPU identifiers for more OCTEON family members.
  MIPS: Probe for new OCTEON CPU/SoC types.
  MIPS: Use r4k_wait for OCTEON3 CPUs.
  MIPS: Generate OCTEON3 TLB handlers with the same features as
    OCTEON2.
  MIPS: OCTEON: Set L1 cache parameters for OCTEON3 CPUs.

 arch/mips/include/asm/cpu.h  |  5 ++++-
 arch/mips/kernel/cpu-probe.c |  7 +++++++
 arch/mips/kernel/idle.c      |  1 +
 arch/mips/mm/c-octeon.c      | 14 ++++++++++++++
 arch/mips/mm/tlbex.c         |  2 ++
 5 files changed, 28 insertions(+), 1 deletion(-)

-- 
1.7.11.7

[PATCH 1/5] MIPS: Add CPU identifiers for more OCTEON family members.

[David Daney]

From: David Daney <david.daney@cavium.com>

Needed to support new SOCs.

Signed-off-by: David Daney <david.daney@cavium.com>
---
 arch/mips/include/asm/cpu.h | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 632bbe5..c198615 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -141,6 +141,9 @@
 #define PRID_IMP_CAVIUM_CN68XX 0x9100
 #define PRID_IMP_CAVIUM_CN66XX 0x9200
 #define PRID_IMP_CAVIUM_CN61XX 0x9300
+#define PRID_IMP_CAVIUM_CNF71XX 0x9400
+#define PRID_IMP_CAVIUM_CN78XX 0x9500
+#define PRID_IMP_CAVIUM_CN70XX 0x9600
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
@@ -272,7 +275,7 @@ enum cpu_type_enum {
 	 */
 	CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
 	CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
-	CPU_XLR, CPU_XLP,
+	CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,
 
 	CPU_LAST
 };
-- 
1.7.11.7

[PATCH 2/5] MIPS: Probe for new OCTEON CPU/SoC types.

[David Daney]

From: David Daney <david.daney@cavium.com>

Add probing for CNF71XX, CN78XX and CN70XX.

Signed-off-by: David Daney <david.daney@cavium.com>
---
 arch/mips/kernel/cpu-probe.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 4c6167a..8e8feb8 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -852,10 +852,17 @@ platform:
 	case PRID_IMP_CAVIUM_CN63XX:
 	case PRID_IMP_CAVIUM_CN66XX:
 	case PRID_IMP_CAVIUM_CN68XX:
+	case PRID_IMP_CAVIUM_CNF71XX:
 		c->cputype = CPU_CAVIUM_OCTEON2;
 		__cpu_name[cpu] = "Cavium Octeon II";
 		set_elf_platform(cpu, "octeon2");
 		break;
+	case PRID_IMP_CAVIUM_CN70XX:
+	case PRID_IMP_CAVIUM_CN78XX:
+		c->cputype = CPU_CAVIUM_OCTEON3;
+		__cpu_name[cpu] = "Cavium Octeon III";
+		set_elf_platform(cpu, "octeon3");
+		break;
 	default:
 		printk(KERN_INFO "Unknown Octeon chip!\n");
 		c->cputype = CPU_UNKNOWN;
-- 
1.7.11.7

[PATCH 3/5] MIPS: Use r4k_wait for OCTEON3 CPUs.

[David Daney]

From: David Daney <david.daney@cavium.com>

Signed-off-by: David Daney <david.daney@cavium.com>
---
 arch/mips/kernel/idle.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 0c655de..42f8875 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -166,6 +166,7 @@ void __init check_wait(void)
 	case CPU_CAVIUM_OCTEON:
 	case CPU_CAVIUM_OCTEON_PLUS:
 	case CPU_CAVIUM_OCTEON2:
+	case CPU_CAVIUM_OCTEON3:
 	case CPU_JZRISC:
 	case CPU_LOONGSON1:
 	case CPU_XLR:
-- 
1.7.11.7

[PATCH 4/5] MIPS: Generate OCTEON3 TLB handlers with the same features as OCTEON2.

[David Daney]

From: David Daney <david.daney@cavium.com>

From the point of view of the TLB Exception handlers, OCTEON3 and
OCTEON2 need the same code.

Signed-off-by: David Daney <david.daney@cavium.com>
---
 arch/mips/mm/tlbex.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 556cb48..821b451 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -85,6 +85,7 @@ static int use_bbit_insns(void)
 	case CPU_CAVIUM_OCTEON:
 	case CPU_CAVIUM_OCTEON_PLUS:
 	case CPU_CAVIUM_OCTEON2:
+	case CPU_CAVIUM_OCTEON3:
 		return 1;
 	default:
 		return 0;
@@ -95,6 +96,7 @@ static int use_lwx_insns(void)
 {
 	switch (current_cpu_type()) {
 	case CPU_CAVIUM_OCTEON2:
+	case CPU_CAVIUM_OCTEON3:
 		return 1;
 	default:
 		return 0;
-- 
1.7.11.7

[PATCH 4/5] MIPS: Generate OCTEON3 TLB handlers with the same features as OCTEON2.

[David Daney]

From: David Daney <david.daney@cavium.com>

[PATCH 5/5] MIPS: OCTEON: Set L1 cache parameters for OCTEON3 CPUs.

[David Daney]

From: David Daney <david.daney@cavium.com>

Signed-off-by: David Daney <david.daney@cavium.com>
---
 arch/mips/mm/c-octeon.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index a0bcdbb..729e770 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -224,6 +224,20 @@ static void probe_octeon(void)
 		c->options |= MIPS_CPU_PREFETCH;
 		break;
 
+	case CPU_CAVIUM_OCTEON3:
+		c->icache.linesz = 128;
+		c->icache.sets = 16;
+		c->icache.ways = 39;
+		c->icache.flags |= MIPS_CACHE_VTAG;
+		icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
+
+		c->dcache.linesz = 128;
+		c->dcache.ways = 32;
+		c->dcache.sets = 8;
+		dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
+		c->options |= MIPS_CPU_PREFETCH;
+		break;
+
 	default:
 		panic("Unsupported Cavium Networks CPU type");
 		break;
-- 
1.7.11.7

Re: [PATCH 0/5] MIPS: Add support for OCTEON III based SoCs.

[Ralf Baechle]

On Mon, Jul 29, 2013 at 03:06:59PM -0700, David Daney wrote:

> From: David Daney <david.daney@cavium.com>
> 
> These patches add minimal support for SoCs in the OCTEON III family.
> In many respects, they are similar to OCTEON II, but with larger cache
> and FPU.  FPU support comes later...

Thanks, entire series applied.

  Ralf