Re: [PATCH 1/2] MIPS: c-r4k: Sync icache when it fills from dcache

[James Hogan <james.hogan@imgtec.com>]

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Hi Joshua,

On Fri, Jan 22, 2016 at 08:05:58AM -0500, Joshua Kinard wrote:
> On 01/22/2016 07:19, James Hogan wrote:
> > On Fri, Jan 22, 2016 at 01:06:14PM +0100, Manuel Lauss wrote:
> >> Hi James,
> [snip]
> > 
> > Thanks Manuel.
> > 
> > FWIW, attached is the test program I mentioned, which hits the first
> > part of this patch (flush_cache_range) via mprotect(2) and checks if
> > icache seems to have been flushed (tested on mips64r6, but should be
> > portable).
> 
> Here's the output on my Octane, R14000 CPU (mips4):
> 
> # ./mprotect
> Initial mprotect SUCCESS
> Looped { mprotect RW, modify, mprotect RX, test } SUCCESS
> 
> This is without your patch applied.  That look good?

Yep, that looks good.

> I'm assuming this CPU is too old to be affected.  I can test with your
> patch after the blizzard is over later this weekend.

Unless you set MIPS_CACHE_IC_F_DC for your core (only ALCHEMY does,
until patch 2 adds I6400 to the list), then cpu_has_ic_fills_f_dc == 0
and everything should already work, as evidenced by the successful
result.

Thanks
James

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