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From: Paul Burton <paul.burton@imgtec.com>
To: Florian Fainelli <f.fainelli@gmail.com>
Cc: <linux-mips@linux-mips.org>, Ralf Baechle <ralf@linux-mips.org>,
	"James Hogan" <james.hogan@imgtec.com>,
	Joshua Kinard <kumba@gentoo.org>,
	"Paul Gortmaker" <paul.gortmaker@windriver.com>,
	<linux-kernel@vger.kernel.org>,
	"Maciej W. Rozycki" <macro@codesourcery.com>,
	Markos Chandras <markos.chandras@imgtec.com>,
	"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Subject: Re: [PATCH 1/2] MIPS: Add barriers between dcache & icache flushes
Date: Tue, 1 Mar 2016 02:27:39 +0000	[thread overview]
Message-ID: <20160301022738.GB12741@NP-P-BURTON> (raw)
In-Reply-To: <56CBA181.8070606@gmail.com>

On Mon, Feb 22, 2016 at 04:02:09PM -0800, Florian Fainelli wrote:
> On 22/02/16 10:09, Paul Burton wrote:
> > Index-based cache operations may be arbitrarily reordered by out of
> > order CPUs. Thus code which writes back the dcache & then invalidates
> > the icache using indexed cache ops must include a barrier between
> > operating on the 2 caches in order to prevent the scenario in which:
> > 
> >   - icache invalidation occurs.
> > 
> >   - icache fetch occurs, due to speculation.
> > 
> >   - dcache writeback occurs.
> > 
> > If the above were allowed to happen then the icache would contain stale
> > data. Forcing the dcache writeback to complete before the icache
> > invalidation avoids this.
> 
> Is that also true for CPUs with have cpu_has_ic_fills_dc?

Hi Florian,

Good question. I imagine not, but probably need to think some more & ask
some questions.

Thanks,
    Paul

WARNING: multiple messages have this Message-ID (diff)
From: Paul Burton <paul.burton@imgtec.com>
To: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org, Ralf Baechle <ralf@linux-mips.org>,
	James Hogan <james.hogan@imgtec.com>,
	Joshua Kinard <kumba@gentoo.org>,
	Paul Gortmaker <paul.gortmaker@windriver.com>,
	linux-kernel@vger.kernel.org,
	"Maciej W. Rozycki" <macro@codesourcery.com>,
	Markos Chandras <markos.chandras@imgtec.com>,
	"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Subject: Re: [PATCH 1/2] MIPS: Add barriers between dcache & icache flushes
Date: Tue, 1 Mar 2016 02:27:39 +0000	[thread overview]
Message-ID: <20160301022738.GB12741@NP-P-BURTON> (raw)
Message-ID: <20160301022739.A8P2s8FB6NFC3uMqOO5vOWBwvk62rSV90zMl6ypQ5j0@z> (raw)
In-Reply-To: <56CBA181.8070606@gmail.com>

On Mon, Feb 22, 2016 at 04:02:09PM -0800, Florian Fainelli wrote:
> On 22/02/16 10:09, Paul Burton wrote:
> > Index-based cache operations may be arbitrarily reordered by out of
> > order CPUs. Thus code which writes back the dcache & then invalidates
> > the icache using indexed cache ops must include a barrier between
> > operating on the 2 caches in order to prevent the scenario in which:
> > 
> >   - icache invalidation occurs.
> > 
> >   - icache fetch occurs, due to speculation.
> > 
> >   - dcache writeback occurs.
> > 
> > If the above were allowed to happen then the icache would contain stale
> > data. Forcing the dcache writeback to complete before the icache
> > invalidation avoids this.
> 
> Is that also true for CPUs with have cpu_has_ic_fills_dc?

Hi Florian,

Good question. I imagine not, but probably need to think some more & ask
some questions.

Thanks,
    Paul

  reply	other threads:[~2016-03-01  2:27 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-02-22 18:09 [PATCH 1/2] MIPS: Add barriers between dcache & icache flushes Paul Burton
2016-02-22 18:09 ` Paul Burton
2016-02-22 18:09 ` [PATCH 2/2] MIPS: Flush highmem pages from dcache in __flush_icache_page Paul Burton
2016-02-22 18:09   ` Paul Burton
2016-02-24  8:02   ` Lars Persson
2016-02-24  8:02     ` Lars Persson
2016-02-22 23:39 ` [PATCH 1/2] MIPS: Add barriers between dcache & icache flushes Joshua Kinard
2016-03-01  2:23   ` Paul Burton
2016-03-01  2:23     ` Paul Burton
2016-02-23  0:02 ` Florian Fainelli
2016-03-01  2:27   ` Paul Burton [this message]
2016-03-01  2:27     ` Paul Burton
2023-03-06 10:28 ` Sven Eckelmann

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